WO2018008422A1 - Inductor with esd protection function - Google Patents

Inductor with esd protection function Download PDF

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Publication number
WO2018008422A1
WO2018008422A1 PCT/JP2017/023067 JP2017023067W WO2018008422A1 WO 2018008422 A1 WO2018008422 A1 WO 2018008422A1 JP 2017023067 W JP2017023067 W JP 2017023067W WO 2018008422 A1 WO2018008422 A1 WO 2018008422A1
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WO
WIPO (PCT)
Prior art keywords
electrode
inductor
coil
esd protection
main surface
Prior art date
Application number
PCT/JP2017/023067
Other languages
French (fr)
Japanese (ja)
Inventor
宣夫 坂井
Original Assignee
株式会社村田製作所
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Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201790000576.5U priority Critical patent/CN208143194U/en
Publication of WO2018008422A1 publication Critical patent/WO2018008422A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/29—Terminals; Tapping arrangements for signal inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks

Definitions

  • the present invention relates to an inductor having an ESD protection function, and more particularly to an inductor with an ESD protection function including an inductor and a diode.
  • the ESD protection circuit is a circuit for escaping ESD to the ground or the like and protecting the electronic circuit in the subsequent stage from ESD, and is disposed, for example, between the signal line and the ground (ground).
  • Patent Document 1 discloses an electronic device in which a filter circuit having an ESD protection function is provided in the vicinity of an antenna terminal for ESD protection.
  • An object of the present invention is to provide an inductor with an ESD protection function capable of reducing a required mounting area and suppressing variation in electrical characteristics.
  • the inductor with an ESD protection function of the present invention is A base material having a first main surface which is a mounting surface; a coil formed on the base material; a first input / output electrode formed on the first main surface and connected to a first end of the coil; A second input / output electrode formed on the first main surface and connected to a second end of the coil; a ground electrode formed on the first main surface; and a first connection electrode connected to the coil; A LGA type chip inductor having a second connection electrode connected to the ground electrode; A diode having a semiconductor substrate, a diode that functions as an ESD protection element, formed on the semiconductor substrate, and a first terminal electrode and a second terminal electrode that are respectively connected to a first end and a second end of the diode Chips, With The diode chip is mounted on the LGA type chip inductor, The first terminal electrode and the second terminal electrode of the diode chip are connected to the first connection electrode and the second connection electrode of the LGA chip inductor, respectively.
  • the mounting area required for the circuit configuration can be reduced as compared with the case where the inductor chip and the diode chip, which are discrete components, are mounted on a mounting substrate or the like. Further, with this configuration, the wiring length between the diode and the coil can be shortened as compared with the case where the discrete component is mounted on a mounting board or the like. Therefore, the conductor resistance and parasitic inductance in the wiring between the diode and the coil are reduced, the ESD suppression voltage is low, and an inductor with an ESD protection function with high response can be realized.
  • the base material has a second main surface facing the first main surface, and the first connection electrode and the second connection electrode are formed on the second main surface.
  • the diode chip is preferably mounted on the second main surface of the base material. With this configuration, it is possible to reduce the mounting area (especially, the area on the plane) of the inductor with an ESD protection function as compared with the case where the diode chip is mounted on the end face or the like of the base material.
  • the diode chip overlaps the coil in a plan view of the first main surface and the second main surface.
  • the distance between the diode chip and the coil on the plane is shorter than the structure in which the diode chip does not overlap the coil when the first main surface and the second main surface are viewed in plan.
  • the wiring length between the two is further shortened. Therefore, the conductor resistance and parasitic inductance in the wiring between the diode and the coil can be further reduced.
  • the base material may be a laminate of a plurality of insulating base material layers.
  • a low-pass filter may be configured by an inductance component of the LGA chip inductor and a capacitance component of the diode.
  • a first interlayer connection conductor formed on the base material is provided, and the first connection electrode is connected to the coil via the first interlayer connection conductor. It may be connected.
  • the base material is a magnetic member, and includes a routing conductor formed on an outer surface of the base material, and the ground electrode is interposed through the routing conductor. It is preferable to be connected to the second connection electrode.
  • an inductor with an ESD protection function that can reduce a required mounting area and suppress fluctuations in electrical characteristics.
  • FIG. 1A is a perspective view of an inductor 101 with an ESD protection function according to the first embodiment
  • FIG. 1B is a perspective view of an LGA type chip inductor 1.
  • 2A is a front view of the inductor 101 with an ESD protection function
  • FIG. 2B is a plan view of the inductor 101 with an ESD protection function.
  • 3A is a plan view of the LGA type chip inductor 1
  • FIG. 3B is a cross-sectional view taken along line AA in FIG. 2A
  • FIG. 3C is a bottom view of the LGA type chip inductor 1.
  • FIG. FIG. FIG. 4 is a perspective view showing conductors and electrodes included in the LGA type chip inductor 1.
  • FIG. 5A is a bottom view of the diode chip 2
  • FIG. 5B is a longitudinal sectional view of the diode chip 2.
  • FIG. 6 is a circuit diagram of the inductor 101 with an ESD protection function.
  • FIG. 7A is a perspective view of the inductor 102 with an ESD protection function according to the second embodiment
  • FIG. 7B is a front view of the inductor 102 with an ESD protection function.
  • 8A is a plan view of the LGA type chip inductor 1A
  • FIG. 8B is a cross-sectional view taken along the line BB in FIG. 7B
  • FIG. 8C is a bottom view of the LGA type chip inductor 1A.
  • FIG. 9 is a perspective view showing conductors and electrodes of the LGA type chip inductor 1A.
  • FIG. 10 is a circuit diagram of the inductor 102 with an ESD protection function.
  • FIG. 11A is a perspective view of the inductor 103 with an ESD protection function according to the third embodiment, and FIG. 11B is a front view of the inductor 103 with an ESD protection function.
  • 12A is a plan view of the LGA type chip inductor 1B
  • FIG. 12B is a cross-sectional view taken along the line CC in FIG. 11B
  • FIG. 12C is a bottom view of the LGA type chip inductor 1B.
  • FIG. 13 is a perspective view showing conductors and electrodes of the LGA type chip inductor 1B.
  • FIG. 14 is a circuit diagram of the inductor 103 with an ESD protection function.
  • FIG. 15 is a perspective view of the inductor 104 with an ESD protection function according to the fourth embodiment.
  • FIG. 16A is a perspective view of an LGA type chip inductor 1C
  • FIG. 16B is a perspective view showing conductors and electrodes of the LGA type chip inductor 1C.
  • FIG. 17 is a circuit diagram of the inductor 104 with an ESD protection function.
  • FIG. 1A is a perspective view of an inductor 101 with an ESD protection function according to the first embodiment
  • FIG. 1B is a perspective view of an LGA type chip inductor 1.
  • 2A is a front view of the inductor 101 with an ESD protection function
  • FIG. 2B is a plan view of the inductor 101 with an ESD protection function.
  • the first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are indicated by broken lines.
  • the coil 31, the conductor 41, and the interlayer connection conductors V1, V2, and V5 are indicated by broken lines.
  • the inductor 101 with an ESD protection function includes an LGA chip inductor 1 and a diode chip 2 mounted on the LGA chip inductor 1.
  • the “LGA type chip inductor” in the present invention is an electrode for mounting on a mounting substrate or the like (“first input / output electrode” described in detail later) only on the mounting surface (“first main surface of the base material described in detail later”). , Second input / output electrode and ground electrode "), and a chip inductor having no mounting electrodes on the end face and the top face.
  • FIG. 3A is a plan view of the LGA type chip inductor 1
  • FIG. 3B is a cross-sectional view taken along line AA in FIG. 2A
  • FIG. 3C is a bottom view of the LGA type chip inductor 1.
  • FIG. FIG. 4 is a perspective view showing conductors and electrodes included in the LGA type chip inductor 1.
  • the LGA type chip inductor 1 includes a base material 10, a coil 31 formed inside the base material 10, a conductor 41, a first input / output electrode P1, a second input / output electrode P2, a ground electrode GP, a first connection electrode CP1, A second connection electrode CP2 and interlayer connection conductors V1, V2, V3, V4, and V5 are provided.
  • the base material 10 is a rectangular parallelepiped insulator flat plate having a first main surface VS1 and a second main surface VS2 facing each other and having a longitudinal direction coinciding with the X-axis direction. Both the first main surface VS1 and the second main surface VS2 are surfaces orthogonal to the Z-axis direction and parallel to the XY plane.
  • the substrate 10 according to this embodiment is a laminate of a plurality of insulating substrate layers.
  • the first main surface VS1 of the base material 10 is a mounting surface on a mounting substrate or the like.
  • the base material 10 is a dielectric ceramic such as, for example, low temperature co-fired ceramics (LTCC: Low Temperature Co-fired Ceramics).
  • the coil 31 is a two-turn spiral conductor formed inside the substrate 10 and has a winding axis in the thickness direction (Z-axis direction).
  • the coil 31 is a conductor pattern made of Cu paste or the like formed on an insulating base material layer constituting the base material 10, for example.
  • the number of turns of the coil 31 is not limited to more than 2 turns, and may be 1 turn or 3 turns or more.
  • the conductor 41 is an L-shaped conductor formed inside the base material 10.
  • the conductor 41 is a conductor pattern made of Cu paste or the like formed on, for example, an insulating base layer (an insulating base layer different from the insulating base layer on which the coil 31 is formed).
  • the first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are conductors formed on the first main surface VS1 of the base material 10.
  • the first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are rectangular conductors whose longitudinal direction coincides with the Y-axis direction.
  • the second input / output electrode P2, the ground electrode GP, and the first input / output electrode They are arranged in the X-axis direction in the order of P1.
  • the first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are conductor patterns such as Cu paste, for example.
  • the first connection electrode CP1 and the second connection electrode CP2 are rectangular conductors formed on the second main surface VS2 of the base material 10.
  • the first connection electrode CP1 and the second connection electrode CP2 are arranged near the center of the second main surface VS2 in the X-axis direction and arranged in the Y-axis direction.
  • the first connection electrode CP1 and the second connection electrode CP2 are conductor patterns such as Cu paste, for example.
  • Interlayer connection conductors V1, V2, V3, V4, and V5 are columnar conductors formed inside the substrate 10.
  • the interlayer connection conductors V1, V2, V3, V4, and V5 are, for example, via conductors or through holes that are formed by filling a through hole that penetrates the base material 10 in the thickness direction (Z-axis direction) with a conductive paste.
  • the interlayer connection conductors V4 and V5 correspond to the “first interlayer connection conductor” in the present invention.
  • the first input / output electrode P1 is connected to the first end E1 of the coil 31 via the interlayer connection conductor V1.
  • the second input / output electrode P2 is connected to the second end of the coil 31 through the conductor 41 and the interlayer connection conductors V2 and V5.
  • the first connection electrode CP1 is connected to the second end E2 of the coil 31 through the conductor 41 and the interlayer connection conductors V4 and V5.
  • the second connection electrode CP2 is connected to the ground electrode GP via the interlayer connection conductor V3.
  • FIG. 5A is a bottom view of the diode chip 2
  • FIG. 5B is a vertical cross-sectional view of the diode chip 2.
  • the diode chip 2 includes a semiconductor substrate 20, a diode (described later in detail) formed on the semiconductor substrate 20, a first terminal electrode EP1, and a second terminal electrode EP2.
  • the semiconductor substrate 20 is a rectangular parallelepiped semiconductor substrate having an element formation surface S1 and having a longitudinal direction coinciding with the Y-axis direction.
  • the semiconductor substrate 20 is, for example, a Si substrate.
  • a semiconductor element portion 21 is formed in a region of the semiconductor substrate 20 on the element formation surface S1 side.
  • an n-type semiconductor layer (n-type well) having a predetermined depth is formed on the element formation surface S 1 side of the semiconductor substrate 20, and two p-type semiconductor portions are formed in the n-type semiconductor. Are formed apart from each other.
  • the two p-type semiconductor portions are exposed on the element formation surface S1.
  • the portions where the two p-type semiconductor portions are exposed on the element formation surface S1 are the first end and the second end of the diode formed on the semiconductor element portion 21 (semiconductor substrate 20).
  • this diode chip 2 functions as an ESD protection element.
  • Insulating layers 3 and 4 and electrodes 51 and 52 are formed on the element formation surface S1 of the semiconductor substrate 20.
  • the insulating layer 4 and the insulating layer 3 are formed in this order from the element formation surface S1 side.
  • the electrode 51 is connected to one p-type semiconductor portion exposed on the element formation surface S1. A part of the electrode 51 is exposed to the outside through a hole formed in the insulating layer 3.
  • the electrode 52 is connected to the other p-type semiconductor part exposed on the element formation surface S1. A part of the electrode 52 is exposed to the outside through a hole formed in the insulating layer 3.
  • the electrodes 51 and 52 are, for example, Al films, and the insulating layer 3 is, for example, a SiO 2 film.
  • the portion where the electrode 51 is exposed is the first terminal electrode EP1 of the diode chip 2, and the portion where the electrode 52 is exposed is the second terminal electrode EP2 of the diode chip 2.
  • the first terminal electrode EP1 and the second terminal electrode EP2 are formed on the element formation surface S1 of the semiconductor substrate 20, and the first end and the second end of the diode formed on the semiconductor element portion 21 (semiconductor substrate 20). Connected to each end.
  • the exposed surfaces of the electrode 51 and the electrode 52 may be plated.
  • Au plating based on Ni can be used.
  • the diode chip 2 is mounted on the second main surface VS2 of the base 10 so that the second main surface VS2 of the base 10 and the element formation surface S1 of the semiconductor substrate 20 face each other. Is done. Thereby, the first terminal electrode EP1 and the second terminal electrode EP2 of the diode chip 2 are connected to the first connection electrode CP1 and the second connection electrode CP2 of the LGA type chip inductor 1, respectively.
  • the diode chip 2 overlaps the coil 31 when the first main surface VS1 and the second main surface VS2 are viewed in plan (viewed from the Z-axis direction).
  • FIG. 6 is a circuit diagram of the inductor 101 with an ESD protection function.
  • the coil 31 is represented by a coil L1
  • the Zener diode formed on the semiconductor substrate 20 shown in FIG. 5B is represented by a diode D1.
  • the inductor 101 with ESD protection function includes a coil L1 connected between the first input / output electrode P1 and the second input / output electrode P2, and the second input / output electrode P2 and the ground electrode GP.
  • a diode D1 is connected between them.
  • the first input / output electrode P1 is connected to the first end of the coil L1
  • the second input / output electrode P2 is connected to the second end of the coil L1.
  • the second input / output electrode P2 is connected to the first end of the diode via the first connection electrode CP1 and the first terminal electrode EP1.
  • the ground electrode GP is connected to the second end of the diode D1 through the second connection electrode CP2 and the second terminal electrode EP2.
  • the ground electrode GP is connected to the ground.
  • the ground electrode GP is connected to the ground.
  • a low-pass filter is constituted by the inductance component (coil L1) of the LGA type chip inductor 1 and the capacitance component of the diode D1.
  • the inductor 101 with an ESD protection function according to this embodiment has the following effects.
  • the inductor 101 with an ESD protection function has a structure in which the diode chip 2 is mounted on the LGA type chip inductor 1. Therefore, the mounting area required for the circuit configuration can be reduced as compared with the case where the inductor chip and the diode chip, which are discrete components, are mounted on a mounting substrate or the like. Further, with this configuration, the wiring length between the diode and the coil can be shortened as compared with the case where the discrete component is mounted on a mounting board or the like. Therefore, the conductor resistance and parasitic inductance in the wiring between the diode and the coil are reduced, the ESD suppression voltage is low, and an inductor with an ESD protection function with high response can be realized.
  • the diode chip 2 is mounted on the second main surface VS2 of the substrate 10.
  • the mounting area (especially, the area on the XY plane) of the inductor 101 with an ESD protection function can be reduced as compared with the case where the diode chip 2 is mounted on the end face or the like of the substrate 10.
  • the diode chip 2 overlaps the coil 31 as viewed from the Z-axis direction.
  • the distance between the diode chip 2 and the coil 31 on the plane (XY plane) is shorter than the structure in which the diode chip 2 does not overlap the coil 31 when viewed from the Z-axis direction.
  • the wiring length between the two is further shortened. Therefore, the conductor resistance and parasitic inductance in the wiring between the diode and the coil can be further reduced.
  • the inductor 101 with an ESD protection function is manufactured by, for example, the following processes (1) to (5).
  • a base material 10 on which V4 and V5 are formed is prepared.
  • the base material 10 is obtained by laminating a plurality of insulating base material layers on which coils 31 and the like and interlayer connection conductors are formed and press-bonding, and then firing at a temperature of 800 ° C. or higher.
  • the insulating base layer before firing is a green sheet such as non-magnetic ferrite such as low temperature co-fired ceramics (LTCC).
  • a paste-like conductive bonding material is printed on the first connection electrode CP1 and the second connection electrode CP2 of the substrate 10.
  • solder is used as the conductive bonding material
  • a solder paste is printed on the first connection electrode CP1 and the second connection electrode CP2 formed on the second main surface VS2 of the substrate 10.
  • the diode chip 2 is prepared, and the diode chip 2 is disposed on the substrate 10. Specifically, the first terminal electrode EP1 and the second terminal electrode EP2 of the diode chip 2 are respectively opposed to the first connection electrode CP1 and the second connection electrode CP2 formed on the second main surface VS2 of the base material 10. Thus, the diode chip 2 is disposed on the second main surface VS2 by the mounter.
  • the first terminal electrode EP1 and the second terminal electrode EP2 may be preliminarily printed with a solder paste and semi-cured.
  • connection electrode CP1 and the first terminal electrode EP1 are connected by a conductive bonding material
  • second connection electrode CP2 and the second terminal electrode EP2 are connected by a conductive bonding material.
  • Second Embodiment the structure and circuit of the coil formed in a base material show an example different from 1st Embodiment.
  • FIG. 7A is a perspective view of the inductor 102 with an ESD protection function according to the second embodiment
  • FIG. 7B is a front view of the inductor 102 with an ESD protection function.
  • the coil 32 and the interlayer connection conductors V1, V2, and V3 are indicated by broken lines for easy understanding of the structure.
  • the inductor 102 with an ESD protection function includes an LGA chip inductor 1A and a diode chip 2 mounted on the LGA chip inductor 1A.
  • the inductor 102 with ESD protection function is the same as the inductor 101 with ESD protection function according to the first embodiment except for the structure of the LGA chip inductor 1A.
  • a different part from the inductor 101 with an ESD protection function which concerns on 1st Embodiment is demonstrated.
  • FIG. 8A is a plan view of the LGA type chip inductor 1A
  • FIG. 8B is a cross-sectional view taken along the line BB in FIG. 7B
  • FIG. 8C is a bottom view of the LGA type chip inductor 1A
  • FIG. 9 is a perspective view showing conductors and electrodes of the LGA type chip inductor 1A.
  • the LGA type chip inductor 1A includes a base material 10A, a coil 32 formed inside the base material 10A, a first input / output electrode P1, a second input / output electrode P2, a ground electrode GP, a first connection electrode CP1, and a second connection. It has an electrode CP2 and interlayer connection conductors V1, V2, V3, V4, V5.
  • the base material 10A is a rectangular parallelepiped insulator plate having a first main surface VS1 and a second main surface VS2 facing each other and having a longitudinal direction coinciding with the X-axis direction.
  • the base material 10A according to the present embodiment is a laminate of a plurality of insulating base material layers.
  • the coil 32 is a loop-shaped conductor of about 1 turn formed inside the base material 10 and has a winding axis in the thickness direction (Z-axis direction).
  • the coil 32 includes coils 32A and 32C formed on the insulating base layer, coils 32B formed on the insulating base layer (insulating base layer different from the insulating base layer on which the coils 32A and 32C are formed), and the like. Composed.
  • the coils 32A, 32B, and 32C are connected to each other via an interlayer connection conductor formed on the insulating base material layer.
  • the number of turns of the coil 32 is not limited to about 1 turn, and may be a plurality of turns.
  • the coil 32 is not limited to a loop shape, and may be a helical shape or a spiral shape.
  • the configurations of the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, and the second connection electrode CP2 are substantially the same as those in the first embodiment.
  • the first input / output electrode P1 is connected to the first end E1 of the coil 32 via the interlayer connection conductor V1.
  • the second input / output electrode P2 is connected to the second end E2 of the coil 32 via the interlayer connection conductor V2.
  • the first connection electrode CP1 is connected to a third end E3 formed near the center of the loop of the coil 32 via the interlayer connection conductor V5.
  • the second connection electrode CP2 is connected to the ground electrode GP via the interlayer connection conductor V3.
  • FIG. 10 is a circuit diagram of the inductor 102 with an ESD protection function.
  • the coil 32 is represented by a coil L2
  • the diode chip 2 shown in FIGS. 7A and 7B is represented by a diode D1.
  • the inductor 102 with ESD protection function includes a coil L2 connected between the first input / output electrode P1 and the second input / output electrode P2, and between the center of the coil L2 and the ground electrode GP.
  • This is a circuit to which a diode D1 is connected.
  • the first input / output electrode P1 is connected to the first end of the coil L2, and the second input / output electrode P2 is connected to the second end of the coil L2.
  • the first end of the diode D1 is connected to the center of the coil L2 via the first connection electrode CP1 and the first terminal electrode EP1.
  • the second end of the diode D1 is connected to the ground electrode GP through the second connection electrode CP2 and the second terminal electrode EP2.
  • the ground electrode GP is connected to the ground.
  • the diode D1 is connected to the ground from the center of the coil L2, and a T-type low-pass filter having symmetry with respect to the input and output is configured. That is, an inductor with an ESD protection function having the same characteristics can be realized even if the input / output electrodes (first input / output electrode P1 and second input / output electrode P2) are mounted in reverse.
  • the diode may be connected in the middle of the coil.
  • a circuit in which the diode D1 is connected to the ground from the center of the coil L2 is shown, but the present invention is not limited to this configuration.
  • the diode D1 may be connected between a position other than the center of the coil L2 and the ground.
  • the third embodiment shows an example in which two diode chips are mounted on an LGA type chip inductor.
  • FIG. 11A is a perspective view of the inductor 103 with an ESD protection function according to the third embodiment
  • FIG. 11B is a front view of the inductor 103 with an ESD protection function.
  • the coil 33 and the interlayer connection conductors V1, V2, V3, V4, and V5 are indicated by broken lines.
  • the inductor 103 with an ESD protection function includes an LGA chip inductor 1B and two diode chips 2A and 2B mounted on the LGA chip inductor 1B.
  • the diode chips 2A and 2B are the same as the diode chip 2 shown in the first embodiment. Hereinafter, a different part from the inductor 101 with an ESD protection function which concerns on 1st Embodiment is demonstrated.
  • FIG. 12A is a plan view of the LGA type chip inductor 1B
  • FIG. 12B is a cross-sectional view taken along the line CC in FIG. 11B
  • FIG. 12C is a bottom view of the LGA type chip inductor 1B
  • FIG. FIG. 13 is a perspective view showing conductors and electrodes of the LGA type chip inductor 1B.
  • the LGA type chip inductor 1B includes a base material 10B, a coil 33 formed inside the base material 10B, a first input / output electrode P1, a second input / output electrode P2, a ground electrode GP, first connection electrodes CP1A and CP1B, Two connection electrodes CP2 and interlayer connection conductors V1, V2, V3, V4, and V5 are provided.
  • the base material 10 ⁇ / b> B is a rectangular parallelepiped insulator plate having a first main surface VS ⁇ b> 1 and a second main surface VS ⁇ b> 2 that face each other and whose longitudinal direction coincides with the X-axis direction.
  • the base material 10B according to the present embodiment is a laminate of a plurality of insulating base material layers.
  • the coil 33 is a loop-shaped conductor of about 1 turn formed inside the base material 10B.
  • the coil 33 includes coils 33A and 33C formed on the insulating base layer, coils 33B formed on the insulating base layer (an insulating base layer different from the insulating base layer on which the coils 33A and 33C are formed), and the like. Composed.
  • the coils 33A, 33B, and 33C are connected to each other via an interlayer connection conductor formed on the insulating base material layer. Note that the number of turns of the coil 33 is not limited to about one turn, and may be a plurality of turns.
  • the coil 33 is not limited to a loop shape, and may be a helical shape or a spiral shape.
  • the first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are conductors formed on the first main surface VS1 of the base material 10B.
  • the first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are rectangular conductors whose longitudinal direction coincides with the Y-axis direction.
  • the second input / output electrode P2, the ground electrode GP, and the first input / output electrode They are arranged in the X-axis direction in the order of P1. As shown in FIG. 12C, the width of the ground electrode GP in the X-axis direction is larger than the width of the first input / output electrode P1 and the second input / output electrode P2 in the X-axis direction.
  • the first connection electrodes CP1A and CP1B are rectangular conductors arranged near the first side (the upper side of the base material 10B in FIG. 12C) of the second main surface VS2 of the base material 10B.
  • the first connection electrodes CP1A and CP1B are arranged near the center of the second main surface VS2 in the X-axis direction and aligned in the X-axis direction.
  • the second connection electrode CP2 is a rectangular conductor disposed near the second side (the lower side of the base material 10B in FIG. 12C) of the second main surface VS2 of the base material 10B.
  • the second connection electrode CP2 is disposed in the X-axis direction of the second main surface VS2.
  • the first input / output electrode P1 is connected to the first end E1 of the coil 33 via the interlayer connection conductor V1.
  • the second input / output electrode P2 is connected to the second end E2 of the coil 33 via the interlayer connection conductor V2.
  • the first connection electrode CP1A is connected to the third end E3 of the coil 33 via the interlayer connection conductor V4.
  • the first connection electrode CP1B is connected to the fourth end E4 of the coil 33 via the interlayer connection conductor V5.
  • the second connection electrode CP2 is connected to the ground electrode GP via the interlayer connection conductor V3.
  • the diode chips 2A and 2B are mounted on the second main surface VS2 of the base material 10B so that the second main surface VS2 of the base material 10B and the element formation surface S1 of the semiconductor substrate 20 face each other.
  • the first terminal electrode (EP1) and the second terminal electrode (EP2) of the diode chip 2A are connected to the first connection electrode CP1A and the second connection electrode CP2 of the LGA type chip inductor 1B, respectively.
  • the first terminal electrode (EP1) and the second terminal electrode (EP2) of the diode chip 2B are connected to the first connection electrode CP1B and the second connection electrode CP2 of the LGA type chip inductor 1B, respectively.
  • FIG. 14 is a circuit diagram of the inductor 103 with an ESD protection function.
  • the coil 33 is represented by a coil L3
  • the diodes formed on the semiconductor substrate 20 illustrated in FIGS. 11A and 11B are represented by diodes D1A and D1B.
  • the inductor 103 with ESD protection function includes a coil L3 connected between the first input / output electrode P1 and the second input / output electrode P2, and the first and second ends of the coil L3 and the ground.
  • diodes D1A and D1B are connected to the electrode GP, respectively.
  • the first input / output electrode P1 is connected to the first end of the coil L3, and the second input / output electrode P2 is connected to the second end of the coil L3.
  • the first end of the diode D1A is connected to the first end of the coil L3 via the first connection electrode CP1A and the first terminal electrode EP1.
  • the second end of the diode D1A is connected to the ground electrode GP through the second connection electrode CP2 and the second terminal electrode EP2.
  • the first end of the diode D1B is connected to the second end of the coil L3 via the first connection electrode CP1B and the first terminal electrode EP1.
  • the second end of the diode D1B is connected to the ground electrode GP through the second connection electrode CP2 and the second terminal electrode EP2. As shown in FIG. 14, the ground electrode GP is connected to the ground.
  • This configuration constitutes a low-pass filter in which the diodes D1A and D1B are connected to the ground from both ends of the coil L3. Also, with this configuration, it is possible to obtain an inductor with an ESD protection function having a circuit configuration having a contrast to input / output.
  • a plurality of diode chips may be mounted on the LGA type chip inductor.
  • FIG. 15 is a perspective view of the inductor 104 with an ESD protection function according to the fourth embodiment.
  • the inductor 104 with an ESD protection function includes an LGA chip inductor 1C and a diode chip 2 mounted on the LGA chip inductor 1C.
  • the inductor 102 with the ESD protection function is the same as the inductor 101 with the ESD protection function according to the first embodiment except for the structure of the LGA chip inductor 1C.
  • the inductor 101 with an ESD protection function which concerns on 1st Embodiment is demonstrated.
  • FIG. 16A is a perspective view of an LGA type chip inductor 1C
  • FIG. 16B is a perspective view showing conductors and electrodes of the LGA type chip inductor 1C.
  • the LGA chip inductor 1C includes a base material 10C, a coil 31 formed inside the base material 10C, a first input / output electrode P1, a second input / output electrode P2, a ground electrode GP, a first connection electrode CP1, and a second connection. It has an electrode CP2, interlayer connection conductors V1, V2, V4, V5 and a lead conductor V3P.
  • the base material 10 ⁇ / b> C is a rectangular parallelepiped insulator plate having a first main surface VS ⁇ b> 1 and a second main surface VS ⁇ b> 2 that face each other and whose longitudinal direction matches the X-axis direction.
  • the base material 10C is, for example, a magnetic member (magnetic ferrite), and is a laminate of a plurality of insulating base material layers made of magnetic ferrite.
  • the configuration of the coil 31, the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, the second connection electrode CP2, and the interlayer connection conductors V1, V2, V4, V5 is the first configuration. This is substantially the same as the embodiment.
  • the lead conductor V3P is a semi-cylindrical conductor formed on the outer surface of the base material 10C.
  • the lead conductor V3P is, for example, cut in the thickness direction (Z-axis direction) together with the substrate along a line passing through the center of a cylindrical via conductor or a through hole extending in the thickness direction (Z-axis direction).
  • the first input / output electrode P1 is connected to the first end E1 of the coil 31 via the interlayer connection conductor V1.
  • the second input / output electrode P2 is connected to the second end of the coil 31 through the conductor 41 and the interlayer connection conductors V2 and V5.
  • the first connection electrode CP1 is connected to the second end E2 of the coil 31 through the conductor 41 and the interlayer connection conductors V4 and V5.
  • the second connection electrode CP2 is connected to the ground electrode GP through the lead conductor V3P.
  • the diode chip 2 is mounted on the second main surface VS2 of the substrate 10C.
  • the first terminal electrode (EP1) and the second terminal electrode (EP2) of the diode chip 2 are connected to the first connection electrode CP1 and the second connection electrode CP2 of the LGA type chip inductor 1C, respectively.
  • FIG. 17 is a circuit diagram of the inductor 104 with an ESD protection function.
  • the coil 31 is represented by a coil L1
  • the diode formed on the semiconductor substrate 20 illustrated in FIGS. 16A and 16B is represented by a diode D1.
  • the low-pass filter is configured by the inductance component (coil L1) of the LGA chip inductor 1C and the capacitance component of the diode D1.
  • the inductor 104 with an ESD protection function has the following effects.
  • the base material 10C is a magnetic member.
  • the lead conductor V3P which is a wiring between the diode D1 and the ground electrode GP (ground) shown in FIG. 17, is formed on the outer surface of the base material 10C that is a magnetic member.
  • the parasitic inductor generated in the wiring between the diode D1 and the ground electrode GP is suppressed as compared with the case where the wiring between the diode D1 and the ground electrode GP is formed inside the magnetic body member (base material). it can. Therefore, this configuration improves the ESD protection function (removal function) of the inductor 104 with ESD protection function and the attenuation characteristic of the filter. This effect is particularly remarkable at high frequencies.
  • the semi-cylindrical routing conductor V3P is shown, but the routing conductor is not limited to this configuration.
  • the lead conductor may be a conductor pattern formed on the outer surface of the substrate.
  • planar shape of the base material is a rectangular parallelepiped
  • the present invention is not limited to this configuration.
  • the shape of the base material can be changed as appropriate within the range where the functions and effects of the present invention are exhibited.
  • the planar shape of the substrate may be, for example, a polygon, a circle, an ellipse, an L shape, a crank shape, a T shape, a Y shape, or the like.
  • the base material is a laminated body of a plurality of insulating base material layers is shown, but the present invention is not limited to this configuration.
  • the substrate may be a single layer.
  • the base material is a dielectric ceramic such as low temperature co-fired ceramics (LTCC) or a magnetic ferrite is shown, but the present invention is not limited to this configuration.
  • the base material may be a resin molded body made of, for example, a thermosetting resin.
  • a loop-shaped coil of about 1 turn or a spiral of about 2 turns having a winding axis in the thickness direction (Z-axis direction) is shown, but the present invention is limited to this configuration. It is not a thing.
  • the shape of the coil and the number of turns can be changed as appropriate within the range where the functions and effects of the present invention are exhibited.
  • the coil may be a helical conductor.
  • the winding axis of the coil can be appropriately changed within the range where the operation and effect of the present invention are exhibited, and may be along the X-axis direction or the Y-axis direction.
  • a part or all of a coil may be formed in the end surface (surface) etc. of a base material. .
  • an example of an inductor with an ESD protection function in which a low-pass filter is configured has been described, but the present invention is not limited to this configuration.
  • the circuit configured in the inductor with an ESD protection function can be changed as appropriate.
  • the components mounted on the LGA type chip inductor can be changed by a circuit configured as an inductor with an ESD protection function.
  • a chip capacitor or the like other than the diode chip may be mounted on the LGA type chip inductor.
  • the diode chip is mounted on the second main surface VS2 of the base material.
  • the present invention is not limited to this configuration.
  • the components mounted on the LGA type chip inductor may be formed other than the first main surface VS1 and the second main surface VS2, for example, may be mounted on an end surface or the like.
  • the first connection electrode CP1 and the second connection electrode CP2 may be formed other than the first main surface VS1 and the second main surface VS2.
  • first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, and the second connection electrode CP2 are rectangular conductors. It is not limited to this configuration.
  • the shapes of the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, and the second connection electrode CP2 can be changed as appropriate. Further, the arrangement and number of the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, and the second connection electrode CP2 can be appropriately changed depending on the circuit configuration of the inductor with the ESD protection function. It is.
  • first terminal electrode EP1 and the second terminal electrode EP2 of the diode chip are configured by the conductor pattern formed on the element formation surface S1 of the semiconductor substrate 20 . It is not limited.
  • the first terminal electrode EP1 and the second terminal electrode EP2 may be configured by forming a rewiring layer on the element formation surface S1 of the semiconductor substrate 20.
  • the diode chip is shown as a configuration example in which the first main surface VS1 and the second main surface VS2 of the base material are planarly viewed and overlapped with the coil.
  • the present invention is not limited to this. Absent.
  • the diode chip does not have to overlap the coil in plan view of the first main surface VS1 and the second main surface VS2 of the base material.
  • Base material VS1 First main surface VS2 of base material ... of base material
  • Second main surface GP ground electrode
  • CP1, CP1A, CP1B ... first connection electrode CP2 ... second connection electrodes V1, V2, V3, V4, V5 ... interlayer connection Conductor V3P ... Leading conductor 31, 32, 32A, 32B, 32C, 33, 33A, 33B, 33C ...
  • Coil E1 ...

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Abstract

An inductor (101) with an ESD protection function is provided with an LGA-type chip inductor (1) and a diode chip (2). The LGA-type chip inductor (1) has: a base material (10) having a first main surface (VS1), i.e., a mounting surface; a coil formed in the base material (10); a first input/output electrode (P1) and a second input/output electrode (P2), which are connected to the coil; a ground electrode (GP); a first connecting electrode (CP1) connected to the coil; and a second connecting electrode (CP2) connected to the ground electrode (GP). The first input/output electrode (P1), the second input/output electrode (P2), and the ground conductor (GP) are formed on the first main surface (VS1). The diode chip (2) is mounted on the (LGA)-type chip inductor (1), and the first connecting electrode (CP1) and the second connecting electrode (CP2) of the LGA-type chip inductor (1) are connected to a diode that functions as an ESD protection element.

Description

ＥＳＤ保護機能付きインダクタInductor with ESD protection function
　本発明は、ＥＳＤ保護機能を有するインダクタに関し、特にインダクタとダイオードとを備えるＥＳＤ保護機能付きインダクタに関するものである。 The present invention relates to an inductor having an ESD protection function, and more particularly to an inductor with an ESD protection function including an inductor and a diode.
　従来、ＥＳＤ（Ｅｌｅｃｔｒｏ－Ｓｔａｔｉｃ　Ｄｉｓｃｈａｒｇｅ；静電気放電）による電子機器の損傷や誤作動等を防止するため、各種ＥＳＤ保護回路が利用されている。ＥＳＤ保護回路は、ＥＳＤをグランド等に逃がし、後段の電子回路をＥＳＤから保護するための回路であって、例えば信号線路とグランド（接地）との間に配置される。 Conventionally, various ESD protection circuits have been used to prevent electronic devices from being damaged or malfunctioning due to ESD (Electro-Static Discharge). The ESD protection circuit is a circuit for escaping ESD to the ground or the like and protecting the electronic circuit in the subsequent stage from ESD, and is disposed, for example, between the signal line and the ground (ground).
　例えば、特許文献１には、ＥＳＤ保護対策のため、アンテナ端子の近傍にＥＳＤ保護機能を有するフィルタ回路が設けられた電子機器が開示されている。 For example, Patent Document 1 discloses an electronic device in which a filter circuit having an ESD protection function is provided in the vicinity of an antenna terminal for ESD protection.
特開２００８－５４０５５号公報JP 2008-54055 A
　しかし、特許文献１に示されるようなＥＳＤ保護機能を有する回路を構成するために、複数のディスクリート部品を実装基板上に配置すると、実装面積が大きくなってしまうという問題がある。また、ディスクリート部品を接続するための配線を実装基板に形成するため、配線長が長くなって必要な特性が得られない虞もある。 However, when a plurality of discrete components are arranged on a mounting board in order to configure a circuit having an ESD protection function as disclosed in Patent Document 1, there is a problem that a mounting area becomes large. In addition, since the wiring for connecting the discrete components is formed on the mounting substrate, the wiring length becomes long, and the necessary characteristics may not be obtained.
　本発明の目的は、必要な実装面積の低減を可能とし、且つ、電気的特性の変動を抑制したＥＳＤ保護機能付きインダクタを提供することにある。 An object of the present invention is to provide an inductor with an ESD protection function capable of reducing a required mounting area and suppressing variation in electrical characteristics.
（１）本発明のＥＳＤ保護機能付きインダクタは、
　実装面である第１主面を有する基材と、前記基材に形成されるコイルと、前記第１主面に形成され、前記コイルの第１端に接続される第１入出力電極と、前記第１主面に形成され、前記コイルの第２端に接続される第２入出力電極と、前記第１主面に形成されるグランド電極と、前記コイルに接続される第１接続電極と、前記グランド電極に接続される第２接続電極と、を有するＬＧＡ型チップインダクタと、
　半導体基板と、ＥＳＤ保護素子として機能し、前記半導体基板に形成されるダイオードと、前記ダイオードの第１端および第２端にそれぞれ接続される第１端子電極および第２端子電極と、を有するダイオードチップと、
　を備え、
　前記ダイオードチップは、前記ＬＧＡ型チップインダクタに搭載され、
　前記ダイオードチップの前記第１端子電極および前記第２端子電極は、前記ＬＧＡ型チップインダクタの前記第１接続電極および前記第２接続電極にそれぞれ接続されることを特徴とする。 (1) The inductor with an ESD protection function of the present invention is
A base material having a first main surface which is a mounting surface; a coil formed on the base material; a first input / output electrode formed on the first main surface and connected to a first end of the coil; A second input / output electrode formed on the first main surface and connected to a second end of the coil; a ground electrode formed on the first main surface; and a first connection electrode connected to the coil; A LGA type chip inductor having a second connection electrode connected to the ground electrode;
A diode having a semiconductor substrate, a diode that functions as an ESD protection element, formed on the semiconductor substrate, and a first terminal electrode and a second terminal electrode that are respectively connected to a first end and a second end of the diode Chips,
With
The diode chip is mounted on the LGA type chip inductor,
The first terminal electrode and the second terminal electrode of the diode chip are connected to the first connection electrode and the second connection electrode of the LGA chip inductor, respectively.
　この構成により、ディスクリート部品であるインダクタチップおよびダイオードチップを実装基板等に搭載する場合に比べて、回路構成に必要な実装面積を低減することができる。また、この構成により、ディスクリート部品を実装基板等に搭載する場合に比べて、ダイオードとコイルとの間の配線長を短くできる。そのため、ダイオードとコイルとの間の配線における導体抵抗や寄生インダクタンスが小さくなり、ＥＳＤ抑制電圧が低く、応答性の高いＥＳＤ保護機能付きインダクタを実現できる。 With this configuration, the mounting area required for the circuit configuration can be reduced as compared with the case where the inductor chip and the diode chip, which are discrete components, are mounted on a mounting substrate or the like. Further, with this configuration, the wiring length between the diode and the coil can be shortened as compared with the case where the discrete component is mounted on a mounting board or the like. Therefore, the conductor resistance and parasitic inductance in the wiring between the diode and the coil are reduced, the ESD suppression voltage is low, and an inductor with an ESD protection function with high response can be realized.
（２）上記（１）において、前記基材は、前記第１主面に対向する第２主面を有し、前記第１接続電極および前記第２接続電極は、前記第２主面に形成され、前記ダイオードチップは、前記基材の前記第２主面に搭載されることが好ましい。この構成により、基材の端面等にダイオードチップを搭載した場合と比べて、ＥＳＤ保護機能付きインダクタの実装面積（特に平面上の面積）を低減できる。 (2) In the above (1), the base material has a second main surface facing the first main surface, and the first connection electrode and the second connection electrode are formed on the second main surface. The diode chip is preferably mounted on the second main surface of the base material. With this configuration, it is possible to reduce the mounting area (especially, the area on the plane) of the inductor with an ESD protection function as compared with the case where the diode chip is mounted on the end face or the like of the base material.
（３）上記（２）において、前記ダイオードチップは、前記第１主面および前記第２主面を平面視して、前記コイルに重なることが好ましい。この構成では、第１主面および第２主面を平面視してダイオードチップがコイルに重なっていない構造に比べて、ダイオードチップとコイルとの平面上での距離が短くなるため、ダイオードとコイルとの間の配線長がさらに短くなる。したがって、ダイオードとコイルとの間の配線における導体抵抗や寄生インダクタンスをさらに小さくできる。 (3) In the above (2), it is preferable that the diode chip overlaps the coil in a plan view of the first main surface and the second main surface. In this configuration, the distance between the diode chip and the coil on the plane is shorter than the structure in which the diode chip does not overlap the coil when the first main surface and the second main surface are viewed in plan. The wiring length between the two is further shortened. Therefore, the conductor resistance and parasitic inductance in the wiring between the diode and the coil can be further reduced.
（４）上記（１）から（３）のいずれかにおいて、前記基材は、複数の絶縁基材層の積層体であってもよい。 (4) In any one of (1) to (3), the base material may be a laminate of a plurality of insulating base material layers.
（５）上記（１）から（４）のいずれかにおいて、前記ＬＧＡ型チップインダクタのインダクタンス成分と、前記ダイオードが有する容量成分とでローパスフィルタを構成してもよい。 (5) In any one of the above (1) to (4), a low-pass filter may be configured by an inductance component of the LGA chip inductor and a capacitance component of the diode.
（６）上記（１）から（５）のいずれかにおいて、前記基材に形成される第１層間接続導体を備え、前記第１接続電極は、前記第１層間接続導体を介して前記コイルに接続されていてもよい。 (6) In any one of the above (1) to (5), a first interlayer connection conductor formed on the base material is provided, and the first connection electrode is connected to the coil via the first interlayer connection conductor. It may be connected.
（７）上記（１）から（６）のいずれかにおいて、前記基材は磁性体部材であり、前記基材の外面に形成される引き回し導体を備え、前記グランド電極は、前記引き回し導体を介して前記第２接続電極に接続されることが好ましい。この構成により、ダイオードとグランド電極との間の配線を磁性体部材の内部に形成する場合に比べて、ダイオードとグランド電極との間の配線に生じる寄生インダクタを抑制できる。したがって、ＥＳＤ保護機能付きインダクタのＥＳＤ保護機能（除去機能）やフィルタの減衰特性が向上する。 (7) In any one of the above (1) to (6), the base material is a magnetic member, and includes a routing conductor formed on an outer surface of the base material, and the ground electrode is interposed through the routing conductor. It is preferable to be connected to the second connection electrode. With this configuration, it is possible to suppress the parasitic inductor generated in the wiring between the diode and the ground electrode, compared to the case where the wiring between the diode and the ground electrode is formed inside the magnetic member. Therefore, the ESD protection function (removal function) of the inductor with an ESD protection function and the attenuation characteristic of the filter are improved.
　本発明によれば、必要な実装面積の低減を可能とし、且つ、電気的特性の変動を抑制したＥＳＤ保護機能付きインダクタを実現できる。 According to the present invention, it is possible to realize an inductor with an ESD protection function that can reduce a required mounting area and suppress fluctuations in electrical characteristics.
図１（Ａ）は第１の実施形態に係るＥＳＤ保護機能付きインダクタ１０１の斜視図であり、図１（Ｂ）はＬＧＡ型チップインダクタ１の斜視図である。FIG. 1A is a perspective view of an inductor 101 with an ESD protection function according to the first embodiment, and FIG. 1B is a perspective view of an LGA type chip inductor 1. 図２（Ａ）はＥＳＤ保護機能付きインダクタ１０１の正面図であり、図２（Ｂ）はＥＳＤ保護機能付きインダクタ１０１の平面図である。2A is a front view of the inductor 101 with an ESD protection function, and FIG. 2B is a plan view of the inductor 101 with an ESD protection function. 図３（Ａ）はＬＧＡ型チップインダクタ１の平面図であり、図３（Ｂ）は図２（Ａ）におけるＡ－Ａ断面図であり、図３（Ｃ）はＬＧＡ型チップインダクタ１の底面図である。3A is a plan view of the LGA type chip inductor 1, FIG. 3B is a cross-sectional view taken along line AA in FIG. 2A, and FIG. 3C is a bottom view of the LGA type chip inductor 1. FIG. FIG. 図４は、ＬＧＡ型チップインダクタ１が有する導体および電極を示す斜視図である。FIG. 4 is a perspective view showing conductors and electrodes included in the LGA type chip inductor 1. 図５（Ａ）はダイオードチップ２の底面図であり、図５（Ｂ）はダイオードチップ２の縦断面図である。FIG. 5A is a bottom view of the diode chip 2, and FIG. 5B is a longitudinal sectional view of the diode chip 2. 図６はＥＳＤ保護機能付きインダクタ１０１の回路図である。FIG. 6 is a circuit diagram of the inductor 101 with an ESD protection function. 図７（Ａ）は、第２の実施形態に係るＥＳＤ保護機能付きインダクタ１０２の斜視図であり、図７（Ｂ）はＥＳＤ保護機能付きインダクタ１０２の正面図である。FIG. 7A is a perspective view of the inductor 102 with an ESD protection function according to the second embodiment, and FIG. 7B is a front view of the inductor 102 with an ESD protection function. 図８（Ａ）はＬＧＡ型チップインダクタ１Ａの平面図であり、図８（Ｂ）は図７（Ｂ）におけるＢ－Ｂ断面図であり、図８（Ｃ）はＬＧＡ型チップインダクタ１Ａの底面図である。8A is a plan view of the LGA type chip inductor 1A, FIG. 8B is a cross-sectional view taken along the line BB in FIG. 7B, and FIG. 8C is a bottom view of the LGA type chip inductor 1A. FIG. 図９は、ＬＧＡ型チップインダクタ１Ａが有する導体および電極を示す斜視図である。FIG. 9 is a perspective view showing conductors and electrodes of the LGA type chip inductor 1A. 図１０はＥＳＤ保護機能付きインダクタ１０２の回路図である。FIG. 10 is a circuit diagram of the inductor 102 with an ESD protection function. 図１１（Ａ）は第３の実施形態に係るＥＳＤ保護機能付きインダクタ１０３の斜視図であり、図１１（Ｂ）はＥＳＤ保護機能付きインダクタ１０３の正面図である。FIG. 11A is a perspective view of the inductor 103 with an ESD protection function according to the third embodiment, and FIG. 11B is a front view of the inductor 103 with an ESD protection function. 図１２（Ａ）はＬＧＡ型チップインダクタ１Ｂの平面図であり、図１２（Ｂ）は図１１（Ｂ）におけるＣ－Ｃ断面図であり、図１２（Ｃ）はＬＧＡ型チップインダクタ１Ｂの底面図である。12A is a plan view of the LGA type chip inductor 1B, FIG. 12B is a cross-sectional view taken along the line CC in FIG. 11B, and FIG. 12C is a bottom view of the LGA type chip inductor 1B. FIG. 図１３は、ＬＧＡ型チップインダクタ１Ｂが有する導体および電極を示す斜視図である。FIG. 13 is a perspective view showing conductors and electrodes of the LGA type chip inductor 1B. 図１４はＥＳＤ保護機能付きインダクタ１０３の回路図である。FIG. 14 is a circuit diagram of the inductor 103 with an ESD protection function. 図１５は第４の実施形態に係るＥＳＤ保護機能付きインダクタ１０４の斜視図である。FIG. 15 is a perspective view of the inductor 104 with an ESD protection function according to the fourth embodiment. 図１６（Ａ）はＬＧＡ型チップインダクタ１Ｃの斜視図であり、図１６（Ｂ）はＬＧＡ型チップインダクタ１Ｃが有する導体および電極を示す斜視図である。FIG. 16A is a perspective view of an LGA type chip inductor 1C, and FIG. 16B is a perspective view showing conductors and electrodes of the LGA type chip inductor 1C. 図１７はＥＳＤ保護機能付きインダクタ１０４の回路図である。FIG. 17 is a circuit diagram of the inductor 104 with an ESD protection function.
　以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付している。要点の説明または理解の容易性を考慮して、便宜上実施形態を分けて示すが、異なる実施形態で示した構成の部分的な置換または組み合わせが可能である。第２の実施形態以降では第１の実施形態と共通の事柄についての記述を省略し、異なる点についてのみ説明する。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。 Hereinafter, several specific examples will be given with reference to the drawings to show a plurality of modes for carrying out the present invention. In each figure, the same reference numerals are assigned to the same portions. In consideration of ease of explanation or understanding of the main points, the embodiments are shown separately for convenience, but the components shown in different embodiments can be partially replaced or combined. In the second and subsequent embodiments, description of matters common to the first embodiment is omitted, and only different points will be described. In particular, the same operation effect by the same configuration will not be sequentially described for each embodiment.
　《第１の実施形態》
　図１（Ａ）は第１の実施形態に係るＥＳＤ保護機能付きインダクタ１０１の斜視図であり、図１（Ｂ）はＬＧＡ型チップインダクタ１の斜視図である。図２（Ａ）はＥＳＤ保護機能付きインダクタ１０１の正面図であり、図２（Ｂ）はＥＳＤ保護機能付きインダクタ１０１の平面図である。図１（Ｂ）では、第１入出力電極Ｐ１、第２入出力電極Ｐ２およびグランド電極ＧＰを破線で示している。また、図２（Ａ）および図２（Ｂ）では、コイル３１、導体４１および層間接続導体Ｖ１，Ｖ２，Ｖ５を破線で示している。 << First Embodiment >>
FIG. 1A is a perspective view of an inductor 101 with an ESD protection function according to the first embodiment, and FIG. 1B is a perspective view of an LGA type chip inductor 1. 2A is a front view of the inductor 101 with an ESD protection function, and FIG. 2B is a plan view of the inductor 101 with an ESD protection function. In FIG. 1B, the first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are indicated by broken lines. 2A and 2B, the coil 31, the conductor 41, and the interlayer connection conductors V1, V2, and V5 are indicated by broken lines.
　ＥＳＤ保護機能付きインダクタ１０１は、ＬＧＡ型チップインダクタ１、ＬＧＡ型チップインダクタ１に搭載されるダイオードチップ２を備える。 The inductor 101 with an ESD protection function includes an LGA chip inductor 1 and a diode chip 2 mounted on the LGA chip inductor 1.
　本発明における「ＬＧＡ型チップインダクタ」とは、実装面（後に詳述する「基材の第１主面」）のみに実装基板等への実装用電極（後に詳述する「第１入出力電極、第２入出力電極およびグランド電極」）を備え、端面および天面には実装用電極を備えていないチップインダクタを言う。 The “LGA type chip inductor” in the present invention is an electrode for mounting on a mounting substrate or the like (“first input / output electrode” described in detail later) only on the mounting surface (“first main surface of the base material described in detail later”). , Second input / output electrode and ground electrode "), and a chip inductor having no mounting electrodes on the end face and the top face.
　図３（Ａ）はＬＧＡ型チップインダクタ１の平面図であり、図３（Ｂ）は図２（Ａ）におけるＡ－Ａ断面図であり、図３（Ｃ）はＬＧＡ型チップインダクタ１の底面図である。図４は、ＬＧＡ型チップインダクタ１が有する導体および電極を示す斜視図である。 3A is a plan view of the LGA type chip inductor 1, FIG. 3B is a cross-sectional view taken along line AA in FIG. 2A, and FIG. 3C is a bottom view of the LGA type chip inductor 1. FIG. FIG. FIG. 4 is a perspective view showing conductors and electrodes included in the LGA type chip inductor 1.
　ＬＧＡ型チップインダクタ１は、基材１０、基材１０の内部に形成されるコイル３１、導体４１、第１入出力電極Ｐ１、第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１、第２接続電極ＣＰ２および層間接続導体Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖ５を有する。 The LGA type chip inductor 1 includes a base material 10, a coil 31 formed inside the base material 10, a conductor 41, a first input / output electrode P1, a second input / output electrode P2, a ground electrode GP, a first connection electrode CP1, A second connection electrode CP2 and interlayer connection conductors V1, V2, V3, V4, and V5 are provided.
　基材１０は、互いに対向する第１主面ＶＳ１および第２主面ＶＳ２を有し、長手方向がＸ軸方向に一致する直方体の絶縁体平板である。第１主面ＶＳ１および第２主面ＶＳ２は、ともにＺ軸方向に直交し、ＸＹ平面に平行な面である。本実施形態に係る基材１０は、複数の絶縁基材層の積層体である。基材１０の第１主面ＶＳ１は、実装基板等への実装面である。基材１０は、例えば低温同時焼成セラミックス（ＬＴＣＣ：Ｌｏｗ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｃｏ－ｆｉｒｅｄ　Ｃｅｒａｍｉｃｓ）のような誘電体セラミックである。 The base material 10 is a rectangular parallelepiped insulator flat plate having a first main surface VS1 and a second main surface VS2 facing each other and having a longitudinal direction coinciding with the X-axis direction. Both the first main surface VS1 and the second main surface VS2 are surfaces orthogonal to the Z-axis direction and parallel to the XY plane. The substrate 10 according to this embodiment is a laminate of a plurality of insulating substrate layers. The first main surface VS1 of the base material 10 is a mounting surface on a mounting substrate or the like. The base material 10 is a dielectric ceramic such as, for example, low temperature co-fired ceramics (LTCC: Low Temperature Co-fired Ceramics).
　コイル３１は、基材１０の内部に形成される２ターン強のスパイラル状の導体であり、厚み方向（Ｚ軸方向）に巻回軸を有する。コイル３１は、例えば基材１０を構成する絶縁基材層に形成されたＣｕペースト等による導体パターンである。なお、コイル３１のターン数は２ターン強に限定されず、１ターンであってもよく、３ターン以上であってもよい。 The coil 31 is a two-turn spiral conductor formed inside the substrate 10 and has a winding axis in the thickness direction (Z-axis direction). The coil 31 is a conductor pattern made of Cu paste or the like formed on an insulating base material layer constituting the base material 10, for example. The number of turns of the coil 31 is not limited to more than 2 turns, and may be 1 turn or 3 turns or more.
　導体４１は、基材１０の内部に形成されるＬ字形の導体である。導体４１は、例えば絶縁基材層（コイル３１が形成された絶縁基材層とは異なる絶縁基材層）に形成されたＣｕペースト等による導体パターンである。 The conductor 41 is an L-shaped conductor formed inside the base material 10. The conductor 41 is a conductor pattern made of Cu paste or the like formed on, for example, an insulating base layer (an insulating base layer different from the insulating base layer on which the coil 31 is formed).
　第１入出力電極Ｐ１、第２入出力電極Ｐ２およびグランド電極ＧＰは、基材１０の第１主面ＶＳ１に形成される導体である。第１入出力電極Ｐ１、第２入出力電極Ｐ２およびグランド電極ＧＰは、長手方向がＹ軸方向に一致した矩形の導体であり、第２入出力電極Ｐ２、グランド電極ＧＰ、第１入出力電極Ｐ１の順にＸ軸方向に並べて配置される。第１入出力電極Ｐ１、第２入出力電極Ｐ２およびグランド電極ＧＰは、例えばＣｕペースト等の導体パターンである。 The first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are conductors formed on the first main surface VS1 of the base material 10. The first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are rectangular conductors whose longitudinal direction coincides with the Y-axis direction. The second input / output electrode P2, the ground electrode GP, and the first input / output electrode They are arranged in the X-axis direction in the order of P1. The first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are conductor patterns such as Cu paste, for example.
　第１接続電極ＣＰ１および第２接続電極ＣＰ２は、基材１０の第２主面ＶＳ２に形成される矩形の導体である。第１接続電極ＣＰ１および第２接続電極ＣＰ２は、第２主面ＶＳ２のＸ軸方向の中央付近で、且つ、Ｙ軸方向に並べて配置される。第１接続電極ＣＰ１および第２接続電極ＣＰ２は、例えばＣｕペースト等の導体パターンである。 The first connection electrode CP1 and the second connection electrode CP2 are rectangular conductors formed on the second main surface VS2 of the base material 10. The first connection electrode CP1 and the second connection electrode CP2 are arranged near the center of the second main surface VS2 in the X-axis direction and arranged in the Y-axis direction. The first connection electrode CP1 and the second connection electrode CP2 are conductor patterns such as Cu paste, for example.
　層間接続導体Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖ５は、基材１０の内部に形成される円柱状の導体である。層間接続導体Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖ５は、例えば基材１０を厚み方向（Ｚ軸方向）に貫通する貫通孔に導電性ペーストを充填してなるビア導体やスルーホール等である。本実施形態では、層間接続導体Ｖ４，Ｖ５が本発明における「第１層間接続導体」に相当する。 Interlayer connection conductors V1, V2, V3, V4, and V5 are columnar conductors formed inside the substrate 10. The interlayer connection conductors V1, V2, V3, V4, and V5 are, for example, via conductors or through holes that are formed by filling a through hole that penetrates the base material 10 in the thickness direction (Z-axis direction) with a conductive paste. In the present embodiment, the interlayer connection conductors V4 and V5 correspond to the “first interlayer connection conductor” in the present invention.
　図４に示すように、第１入出力電極Ｐ１は、層間接続導体Ｖ１を介してコイル３１の第１端Ｅ１に接続される。第２入出力電極Ｐ２は、導体４１および層間接続導体Ｖ２，Ｖ５を介して、コイル３１の第２端に接続される。また、第１接続電極ＣＰ１は、導体４１および層間接続導体Ｖ４，Ｖ５を介して、コイル３１の第２端Ｅ２に接続される。また、第２接続電極ＣＰ２は、層間接続導体Ｖ３を介してグランド電極ＧＰに接続される。 As shown in FIG. 4, the first input / output electrode P1 is connected to the first end E1 of the coil 31 via the interlayer connection conductor V1. The second input / output electrode P2 is connected to the second end of the coil 31 through the conductor 41 and the interlayer connection conductors V2 and V5. The first connection electrode CP1 is connected to the second end E2 of the coil 31 through the conductor 41 and the interlayer connection conductors V4 and V5. The second connection electrode CP2 is connected to the ground electrode GP via the interlayer connection conductor V3.
　図５（Ａ）はダイオードチップ２の底面図であり、図５（Ｂ）はダイオードチップ２の縦断面図である。 5A is a bottom view of the diode chip 2, and FIG. 5B is a vertical cross-sectional view of the diode chip 2. FIG.
　ダイオードチップ２は、半導体基板２０、半導体基板２０に形成されるダイオード（後に詳述する。）、第１端子電極ＥＰ１および第２端子電極ＥＰ２を有する。 The diode chip 2 includes a semiconductor substrate 20, a diode (described later in detail) formed on the semiconductor substrate 20, a first terminal electrode EP1, and a second terminal electrode EP2.
　半導体基板２０は、素子形成面Ｓ１を有し、長手方向がＹ軸方向に一致する直方体の半導体基板である。半導体基板２０は例えばＳｉ基板である。 The semiconductor substrate 20 is a rectangular parallelepiped semiconductor substrate having an element formation surface S1 and having a longitudinal direction coinciding with the Y-axis direction. The semiconductor substrate 20 is, for example, a Si substrate.
　図５（Ｂ）に示すように、半導体基板２０の素子形成面Ｓ１側の領域に半導体素子部２１が形成されている。半導体素子部２１には、半導体基板２０の素子形成面Ｓ１側に、所定の深さのｎ型半導体層（ｎ型ウェル）が形成されており、このｎ型半導体内に２つのｐ型半導体部が離間して形成されている。２つのｐ型半導体部は素子形成面Ｓ１に露出している。この２つのｐ型半導体部が素子形成面Ｓ１に露出する部分が、半導体素子部２１（半導体基板２０）に形成されるダイオードの第１端および第２端である。この構成により、アノードがそれぞれ素子形成面Ｓ１に露出し、カソードが互いに接続された２つのｐｎ接合ダイオードはツェナー特性を有し、半導体素子部２１（半導体基板２０）に形成される。そのため、このダイオードチップ２はＥＳＤ保護素子として機能する。 As shown in FIG. 5B, a semiconductor element portion 21 is formed in a region of the semiconductor substrate 20 on the element formation surface S1 side. In the semiconductor element portion 21, an n-type semiconductor layer (n-type well) having a predetermined depth is formed on the element formation surface S 1 side of the semiconductor substrate 20, and two p-type semiconductor portions are formed in the n-type semiconductor. Are formed apart from each other. The two p-type semiconductor portions are exposed on the element formation surface S1. The portions where the two p-type semiconductor portions are exposed on the element formation surface S1 are the first end and the second end of the diode formed on the semiconductor element portion 21 (semiconductor substrate 20). With this configuration, the two pn junction diodes each having the anode exposed to the element formation surface S1 and the cathode connected to each other have zener characteristics and are formed in the semiconductor element portion 21 (semiconductor substrate 20). Therefore, this diode chip 2 functions as an ESD protection element.
　半導体基板２０の素子形成面Ｓ１には、絶縁層３，４および電極５１，５２が形成される。絶縁層４と絶縁層３は、素子形成面Ｓ１側からこの順に形成される。図５（Ｂ）に示すように、電極５１は、素子形成面Ｓ１に露出する一方のｐ型半導体部に接続される。また、電極５１の一部は、絶縁層３に形成された孔から外部に露出する。電極５２は、素子形成面Ｓ１に露出する他方のｐ型半導体部に接続される。また、電極５２の一部は、絶縁層３に形成された孔から外部に露出する。電極５１，５２は例えばＡｌ膜であり、絶縁層３は例えばＳｉＯ２膜である。 Insulating layers 3 and 4 and electrodes 51 and 52 are formed on the element formation surface S1 of the semiconductor substrate 20. The insulating layer 4 and the insulating layer 3 are formed in this order from the element formation surface S1 side. As shown in FIG. 5B, the electrode 51 is connected to one p-type semiconductor portion exposed on the element formation surface S1. A part of the electrode 51 is exposed to the outside through a hole formed in the insulating layer 3. The electrode 52 is connected to the other p-type semiconductor part exposed on the element formation surface S1. A part of the electrode 52 is exposed to the outside through a hole formed in the insulating layer 3. The electrodes 51 and 52 are, for example, Al films, and the insulating layer 3 is, for example, a SiO 2 film.
　この電極５１が露出する部分が、ダイオードチップ２の第１端子電極ＥＰ１であり、電極５２が露出する部分が、ダイオードチップ２の第２端子電極ＥＰ２である。このように、第１端子電極ＥＰ１および第２端子電極ＥＰ２は、半導体基板２０の素子形成面Ｓ１に形成され、半導体素子部２１（半導体基板２０）に形成されるダイオードの第１端および第２端にそれぞれ接続される。 The portion where the electrode 51 is exposed is the first terminal electrode EP1 of the diode chip 2, and the portion where the electrode 52 is exposed is the second terminal electrode EP2 of the diode chip 2. Thus, the first terminal electrode EP1 and the second terminal electrode EP2 are formed on the element formation surface S1 of the semiconductor substrate 20, and the first end and the second end of the diode formed on the semiconductor element portion 21 (semiconductor substrate 20). Connected to each end.
　なお、電極５１および電極５２の露出面（第１端子電極ＥＰ１および第２端子電極ＥＰ２）には、めっき処理が施されていてもよい。例えば、Ｎｉを下地としたＡｕめっき等を用いることができる。 Note that the exposed surfaces of the electrode 51 and the electrode 52 (the first terminal electrode EP1 and the second terminal electrode EP2) may be plated. For example, Au plating based on Ni can be used.
　図２（Ａ）に示すように、基材１０の第２主面ＶＳ２と半導体基板２０の素子形成面Ｓ１とが対向するように、ダイオードチップ２は基材１０の第２主面ＶＳ２に搭載される。これにより、ダイオードチップ２の第１端子電極ＥＰ１および第２端子電極ＥＰ２は、ＬＧＡ型チップインダクタ１の第１接続電極ＣＰ１および第２接続電極ＣＰ２にそれぞれ接続される。 As shown in FIG. 2A, the diode chip 2 is mounted on the second main surface VS2 of the base 10 so that the second main surface VS2 of the base 10 and the element formation surface S1 of the semiconductor substrate 20 face each other. Is done. Thereby, the first terminal electrode EP1 and the second terminal electrode EP2 of the diode chip 2 are connected to the first connection electrode CP1 and the second connection electrode CP2 of the LGA type chip inductor 1, respectively.
　また、図２（Ｂ）に示すように、ダイオードチップ２は、第１主面ＶＳ１および第２主面ＶＳ２を平面視して（Ｚ軸方向から視て）、コイル３１に重なる。 As shown in FIG. 2B, the diode chip 2 overlaps the coil 31 when the first main surface VS1 and the second main surface VS2 are viewed in plan (viewed from the Z-axis direction).
　図６はＥＳＤ保護機能付きインダクタ１０１の回路図である。図６では、コイル３１をコイルＬ１で表し、図５（Ｂ）で示した半導体基板２０に形成されるツェナーダイオードをダイオードＤ１で表している。 FIG. 6 is a circuit diagram of the inductor 101 with an ESD protection function. In FIG. 6, the coil 31 is represented by a coil L1, and the Zener diode formed on the semiconductor substrate 20 shown in FIG. 5B is represented by a diode D1.
　ＥＳＤ保護機能付きインダクタ１０１は、図６に示すように、第１入出力電極Ｐ１と第２入出力電極Ｐ２との間にコイルＬ１が接続され、第２入出力電極Ｐ２とグランド電極ＧＰとの間にダイオードＤ１が接続された回路である。第１入出力電極Ｐ１はコイルＬ１の第１端に接続され、第２入出力電極Ｐ２はコイルＬ１の第２端に接続される。また、第２入出力電極Ｐ２は、第１接続電極ＣＰ１および第１端子電極ＥＰ１を介して、ダイオードの第１端に接続される。グランド電極ＧＰは、第２接続電極ＣＰ２および第２端子電極ＥＰ２を介して、ダイオードＤ１の第２端に接続される。図６に示すように、グランド電極ＧＰはグランドに接続される。図６に示すように、グランド電極ＧＰはグランドに接続される。 As shown in FIG. 6, the inductor 101 with ESD protection function includes a coil L1 connected between the first input / output electrode P1 and the second input / output electrode P2, and the second input / output electrode P2 and the ground electrode GP. In this circuit, a diode D1 is connected between them. The first input / output electrode P1 is connected to the first end of the coil L1, and the second input / output electrode P2 is connected to the second end of the coil L1. The second input / output electrode P2 is connected to the first end of the diode via the first connection electrode CP1 and the first terminal electrode EP1. The ground electrode GP is connected to the second end of the diode D1 through the second connection electrode CP2 and the second terminal electrode EP2. As shown in FIG. 6, the ground electrode GP is connected to the ground. As shown in FIG. 6, the ground electrode GP is connected to the ground.
　本実施形態では、ＬＧＡ型チップインダクタ１のインダクタンス成分（コイルＬ１）と、ダイオードＤ１が有する容量成分とで、ローパスフィルタが構成される。 In this embodiment, a low-pass filter is constituted by the inductance component (coil L1) of the LGA type chip inductor 1 and the capacitance component of the diode D1.
　本実施形態に係るＥＳＤ保護機能付きインダクタ１０１によれば、次のような効果を奏する。 The inductor 101 with an ESD protection function according to this embodiment has the following effects.
（ａ）ＥＳＤ保護機能付きインダクタ１０１は、ダイオードチップ２がＬＧＡ型チップインダクタ１に搭載される構造である。そのため、ディスクリート部品であるインダクタチップおよびダイオードチップを実装基板等に搭載する場合に比べて、回路構成に必要な実装面積を低減することができる。また、この構成により、ディスクリート部品を実装基板等に搭載する場合に比べて、ダイオードとコイルとの間の配線長を短くできる。そのため、ダイオードとコイルとの間の配線における導体抵抗や寄生インダクタンスが小さくなり、ＥＳＤ抑制電圧が低く、応答性の高いＥＳＤ保護機能付きインダクタを実現できる。 (A) The inductor 101 with an ESD protection function has a structure in which the diode chip 2 is mounted on the LGA type chip inductor 1. Therefore, the mounting area required for the circuit configuration can be reduced as compared with the case where the inductor chip and the diode chip, which are discrete components, are mounted on a mounting substrate or the like. Further, with this configuration, the wiring length between the diode and the coil can be shortened as compared with the case where the discrete component is mounted on a mounting board or the like. Therefore, the conductor resistance and parasitic inductance in the wiring between the diode and the coil are reduced, the ESD suppression voltage is low, and an inductor with an ESD protection function with high response can be realized.
（ｂ）また、本実施形態では、ダイオードチップ２が基材１０の第２主面ＶＳ２に搭載される。この構成により、基材１０の端面等にダイオードチップ２を搭載した場合と比べて、ＥＳＤ保護機能付きインダクタ１０１の実装面積（特にＸＹ平面上の面積）を低減できる。 (B) In the present embodiment, the diode chip 2 is mounted on the second main surface VS2 of the substrate 10. With this configuration, the mounting area (especially, the area on the XY plane) of the inductor 101 with an ESD protection function can be reduced as compared with the case where the diode chip 2 is mounted on the end face or the like of the substrate 10.
　さらに、本実施形態では、ダイオードチップ２が、Ｚ軸方向から視て、コイル３１に重なっている。この構成では、Ｚ軸方向から視てダイオードチップ２がコイル３１に重なっていない構造に比べて、ダイオードチップ２とコイル３１との平面（ＸＹ平面）上での距離が短くなるため、ダイオードとコイルとの間の配線長がさらに短くなる。したがって、ダイオードとコイルとの間の配線における導体抵抗や寄生インダクタンスをさらに小さくできる。 Furthermore, in this embodiment, the diode chip 2 overlaps the coil 31 as viewed from the Z-axis direction. In this configuration, the distance between the diode chip 2 and the coil 31 on the plane (XY plane) is shorter than the structure in which the diode chip 2 does not overlap the coil 31 when viewed from the Z-axis direction. The wiring length between the two is further shortened. Therefore, the conductor resistance and parasitic inductance in the wiring between the diode and the coil can be further reduced.
　ＥＳＤ保護機能付きインダクタ１０１は、例えば次の（１）から（５）に述べるような工程で製造する。 The inductor 101 with an ESD protection function is manufactured by, for example, the following processes (1) to (5).
（１）まず、コイル３１、導体４１、第１入出力電極Ｐ１、第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１、第２接続電極ＣＰ２および層間接続導体Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖ５が形成された基材１０を用意する。基材１０は、コイル３１等や層間接続導体を形成した複数の絶縁基材層を積層して圧着後、８００℃以上の温度で焼成して得る。焼成前の絶縁基材層は、例えば低温同時焼成セラミックス（ＬＴＣＣ）のような非磁性体フェライト等のグリーンシートである。 (1) First, the coil 31, the conductor 41, the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, the second connection electrode CP2, and the interlayer connection conductors V1, V2, V3. A base material 10 on which V4 and V5 are formed is prepared. The base material 10 is obtained by laminating a plurality of insulating base material layers on which coils 31 and the like and interlayer connection conductors are formed and press-bonding, and then firing at a temperature of 800 ° C. or higher. The insulating base layer before firing is a green sheet such as non-magnetic ferrite such as low temperature co-fired ceramics (LTCC).
（２）次に、基材１０の第１接続電極ＣＰ１および第２接続電極ＣＰ２にペースト状の導電性接合材を印刷する。導電性接合材にはんだを用いる場合には、基材１０の第２主面ＶＳ２に形成された第１接続電極ＣＰ１および第２接続電極ＣＰ２に、はんだペーストを印刷する。 (2) Next, a paste-like conductive bonding material is printed on the first connection electrode CP1 and the second connection electrode CP2 of the substrate 10. When solder is used as the conductive bonding material, a solder paste is printed on the first connection electrode CP1 and the second connection electrode CP2 formed on the second main surface VS2 of the substrate 10.
（３）次に、ダイオードチップ２を用意し、ダイオードチップ２を基材１０に配置する。具体的には、ダイオードチップ２の第１端子電極ＥＰ１および第２端子電極ＥＰ２が、基材１０の第２主面ＶＳ２に形成された第１接続電極ＣＰ１および第２接続電極ＣＰ２にそれぞれ対向するように、マウンターでダイオードチップ２を第２主面ＶＳ２上に配置する。なお、第１端子電極ＥＰ１および第２端子電極ＥＰ２には、予めはんだペーストを印刷し、半硬化させておいてもよい。 (3) Next, the diode chip 2 is prepared, and the diode chip 2 is disposed on the substrate 10. Specifically, the first terminal electrode EP1 and the second terminal electrode EP2 of the diode chip 2 are respectively opposed to the first connection electrode CP1 and the second connection electrode CP2 formed on the second main surface VS2 of the base material 10. Thus, the diode chip 2 is disposed on the second main surface VS2 by the mounter. The first terminal electrode EP1 and the second terminal electrode EP2 may be preliminarily printed with a solder paste and semi-cured.
（４）次に、リフロープロセスにより、導電性接合材によって第１接続電極ＣＰ１と第１端子電極ＥＰ１と接続し、導電性接合材によって第２接続電極ＣＰ２と第２端子電極ＥＰ２とを接続する。 (4) Next, by a reflow process, the first connection electrode CP1 and the first terminal electrode EP1 are connected by a conductive bonding material, and the second connection electrode CP2 and the second terminal electrode EP2 are connected by a conductive bonding material. .
（５）なお、上記の工程は、複数のＥＳＤ保護機能付きインダクタ１０１が形成された集合基板状態のまま処理される。最後にダイシングを行い、集合基板から個々のＥＳＤ保護機能付きインダクタ１０１単位（個片）に分離する。 (5) In addition, said process is processed with the aggregate substrate state in which the several inductor 101 with an ESD protection function was formed. Finally, dicing is performed to separate each inductor 101 unit with ESD protection function (piece) from the collective substrate.
　《第２の実施形態》
　第２の実施形態では、基材に形成されるコイルの構造および回路が第１の実施形態とは異なる例を示す。 << Second Embodiment >>
In 2nd Embodiment, the structure and circuit of the coil formed in a base material show an example different from 1st Embodiment.
　図７（Ａ）は、第２の実施形態に係るＥＳＤ保護機能付きインダクタ１０２の斜視図であり、図７（Ｂ）はＥＳＤ保護機能付きインダクタ１０２の正面図である。図７（Ｂ）では、構造を解りやすくするため、コイル３２および層間接続導体Ｖ１，Ｖ２，Ｖ３を破線で示している。 7A is a perspective view of the inductor 102 with an ESD protection function according to the second embodiment, and FIG. 7B is a front view of the inductor 102 with an ESD protection function. In FIG. 7B, the coil 32 and the interlayer connection conductors V1, V2, and V3 are indicated by broken lines for easy understanding of the structure.
　ＥＳＤ保護機能付きインダクタ１０２は、ＬＧＡ型チップインダクタ１Ａ、ＬＧＡ型チップインダクタ１Ａに搭載されるダイオードチップ２を備える。 The inductor 102 with an ESD protection function includes an LGA chip inductor 1A and a diode chip 2 mounted on the LGA chip inductor 1A.
　ＥＳＤ保護機能付きインダクタ１０２は、ＬＧＡ型チップインダクタ１Ａの構造が第１の実施形態に係るＥＳＤ保護機能付きインダクタ１０１と異なり、その他は同じである。以下、第１の実施形態に係るＥＳＤ保護機能付きインダクタ１０１と異なる部分について説明する。 The inductor 102 with ESD protection function is the same as the inductor 101 with ESD protection function according to the first embodiment except for the structure of the LGA chip inductor 1A. Hereinafter, a different part from the inductor 101 with an ESD protection function which concerns on 1st Embodiment is demonstrated.
　図８（Ａ）はＬＧＡ型チップインダクタ１Ａの平面図であり、図８（Ｂ）は図７（Ｂ）におけるＢ－Ｂ断面図であり、図８（Ｃ）はＬＧＡ型チップインダクタ１Ａの底面図である。図９は、ＬＧＡ型チップインダクタ１Ａが有する導体および電極を示す斜視図である。 8A is a plan view of the LGA type chip inductor 1A, FIG. 8B is a cross-sectional view taken along the line BB in FIG. 7B, and FIG. 8C is a bottom view of the LGA type chip inductor 1A. FIG. FIG. 9 is a perspective view showing conductors and electrodes of the LGA type chip inductor 1A.
　ＬＧＡ型チップインダクタ１Ａは、基材１０Ａ、基材１０Ａの内部に形成されるコイル３２、第１入出力電極Ｐ１、第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１、第２接続電極ＣＰ２および層間接続導体Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖ５を有する。 The LGA type chip inductor 1A includes a base material 10A, a coil 32 formed inside the base material 10A, a first input / output electrode P1, a second input / output electrode P2, a ground electrode GP, a first connection electrode CP1, and a second connection. It has an electrode CP2 and interlayer connection conductors V1, V2, V3, V4, V5.
　基材１０Ａは、互いに対向する第１主面ＶＳ１および第２主面ＶＳ２を有し、長手方向がＸ軸方向に一致する直方体の絶縁体平板である。本実施形態に係る基材１０Ａは、複数の絶縁基材層の積層体である。 The base material 10A is a rectangular parallelepiped insulator plate having a first main surface VS1 and a second main surface VS2 facing each other and having a longitudinal direction coinciding with the X-axis direction. The base material 10A according to the present embodiment is a laminate of a plurality of insulating base material layers.
　コイル３２は、基材１０の内部に形成される約１ターンのループ状の導体であり、厚み方向（Ｚ軸方向）に巻回軸を有する。コイル３２は、絶縁基材層に形成されるコイル３２Ａ，３２Ｃ、絶縁基材層（コイル３２Ａ，３２Ｃが形成された絶縁基材層とは異なる絶縁基材層）に形成されるコイル３２Ｂ等で構成される。コイル３２Ａ，３２Ｂ，３２Ｃは、絶縁基材層に形成される層間接続導体を介して互いに接続される。なお、コイル３２のターン数は約１ターンに限定されず、複数ターンであってもよい。また、コイル３２はループ状に限定されず、ヘリカル状またはスパイラル状でもよい。 The coil 32 is a loop-shaped conductor of about 1 turn formed inside the base material 10 and has a winding axis in the thickness direction (Z-axis direction). The coil 32 includes coils 32A and 32C formed on the insulating base layer, coils 32B formed on the insulating base layer (insulating base layer different from the insulating base layer on which the coils 32A and 32C are formed), and the like. Composed. The coils 32A, 32B, and 32C are connected to each other via an interlayer connection conductor formed on the insulating base material layer. The number of turns of the coil 32 is not limited to about 1 turn, and may be a plurality of turns. The coil 32 is not limited to a loop shape, and may be a helical shape or a spiral shape.
　第１入出力電極Ｐ１、第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１および第２接続電極ＣＰ２の構成については、第１の実施形態と実質的に同じである。 The configurations of the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, and the second connection electrode CP2 are substantially the same as those in the first embodiment.
　図９に示すように、第１入出力電極Ｐ１は、層間接続導体Ｖ１を介してコイル３２の第１端Ｅ１に接続される。第２入出力電極Ｐ２は、層間接続導体Ｖ２を介して、コイル３２の第２端Ｅ２に接続される。第１接続電極ＣＰ１は、層間接続導体Ｖ５を介して、コイル３２のループの中央付近に形成された第３端Ｅ３に接続される。また、第２接続電極ＣＰ２は、層間接続導体Ｖ３を介してグランド電極ＧＰに接続される。 As shown in FIG. 9, the first input / output electrode P1 is connected to the first end E1 of the coil 32 via the interlayer connection conductor V1. The second input / output electrode P2 is connected to the second end E2 of the coil 32 via the interlayer connection conductor V2. The first connection electrode CP1 is connected to a third end E3 formed near the center of the loop of the coil 32 via the interlayer connection conductor V5. The second connection electrode CP2 is connected to the ground electrode GP via the interlayer connection conductor V3.
　図１０はＥＳＤ保護機能付きインダクタ１０２の回路図である。図１０では、コイル３２をコイルＬ２で表し、図７（Ａ）および図７（Ｂ）で示したダイオードチップ２をダイオードＤ１で表している。 FIG. 10 is a circuit diagram of the inductor 102 with an ESD protection function. In FIG. 10, the coil 32 is represented by a coil L2, and the diode chip 2 shown in FIGS. 7A and 7B is represented by a diode D1.
　ＥＳＤ保護機能付きインダクタ１０２は、図１０に示すように、第１入出力電極Ｐ１と第２入出力電極Ｐ２との間にコイルＬ２が接続され、コイルＬ２の中央とグランド電極ＧＰとの間にダイオードＤ１が接続された回路である。第１入出力電極Ｐ１はコイルＬ２の第１端に接続され、第２入出力電極Ｐ２はコイルＬ２の第２端に接続される。ダイオードＤ１の第１端は、第１接続電極ＣＰ１および第１端子電極ＥＰ１を介して、コイルＬ２の中央に接続される。ダイオードＤ１の第２端は、第２接続電極ＣＰ２および第２端子電極ＥＰ２を介して、グランド電極ＧＰに接続される。図１０に示すように、グランド電極ＧＰはグランドに接続される。 As shown in FIG. 10, the inductor 102 with ESD protection function includes a coil L2 connected between the first input / output electrode P1 and the second input / output electrode P2, and between the center of the coil L2 and the ground electrode GP. This is a circuit to which a diode D1 is connected. The first input / output electrode P1 is connected to the first end of the coil L2, and the second input / output electrode P2 is connected to the second end of the coil L2. The first end of the diode D1 is connected to the center of the coil L2 via the first connection electrode CP1 and the first terminal electrode EP1. The second end of the diode D1 is connected to the ground electrode GP through the second connection electrode CP2 and the second terminal electrode EP2. As shown in FIG. 10, the ground electrode GP is connected to the ground.
　この構成により、コイルＬ２の中央からダイオードＤ１がグランドに接続され、入出力に対して対称性を有するＴ型のローパスフィルタが構成される。すなわち、入出力電極（第１入出力電極Ｐ１および第２入出力電極Ｐ２）を逆に実装しても同じ特性を有するＥＳＤ保護機能付きインダクタを実現できる。 With this configuration, the diode D1 is connected to the ground from the center of the coil L2, and a T-type low-pass filter having symmetry with respect to the input and output is configured. That is, an inductor with an ESD protection function having the same characteristics can be realized even if the input / output electrodes (first input / output electrode P1 and second input / output electrode P2) are mounted in reverse.
　本実施形態で示したように、ダイオードはコイルの途中に接続されていてもよい。なお、本実施形態では、コイルＬ２の中央からダイオードＤ１がグランドに接続された回路を示したが、この構成に限定されるものではない。ダイオードＤ１は、コイルＬ２の中央以外の位置とグランドとの間に接続されていてもよい。 As shown in this embodiment, the diode may be connected in the middle of the coil. In the present embodiment, a circuit in which the diode D1 is connected to the ground from the center of the coil L2 is shown, but the present invention is not limited to this configuration. The diode D1 may be connected between a position other than the center of the coil L2 and the ground.
　《第３の実施形態》
　第３の実施形態では、ＬＧＡ型チップインダクタに２つのダイオードチップを搭載した例を示す。 << Third Embodiment >>
The third embodiment shows an example in which two diode chips are mounted on an LGA type chip inductor.
　図１１（Ａ）は第３の実施形態に係るＥＳＤ保護機能付きインダクタ１０３の斜視図であり、図１１（Ｂ）はＥＳＤ保護機能付きインダクタ１０３の正面図である。図１１（Ｂ）では、コイル３３および層間接続導体Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖ５を破線で示している。 FIG. 11A is a perspective view of the inductor 103 with an ESD protection function according to the third embodiment, and FIG. 11B is a front view of the inductor 103 with an ESD protection function. In FIG. 11B, the coil 33 and the interlayer connection conductors V1, V2, V3, V4, and V5 are indicated by broken lines.
　ＥＳＤ保護機能付きインダクタ１０３は、ＬＧＡ型チップインダクタ１Ｂ、ＬＧＡ型チップインダクタ１Ｂに搭載される２つのダイオードチップ２Ａ，２Ｂを備える。 The inductor 103 with an ESD protection function includes an LGA chip inductor 1B and two diode chips 2A and 2B mounted on the LGA chip inductor 1B.
　ダイオードチップ２Ａ，２Ｂは、第１の実施形態で示したダイオードチップ２と同じものである。以下、第１の実施形態に係るＥＳＤ保護機能付きインダクタ１０１と異なる部分について説明する。 The diode chips 2A and 2B are the same as the diode chip 2 shown in the first embodiment. Hereinafter, a different part from the inductor 101 with an ESD protection function which concerns on 1st Embodiment is demonstrated.
　図１２（Ａ）はＬＧＡ型チップインダクタ１Ｂの平面図であり、図１２（Ｂ）は図１１（Ｂ）におけるＣ－Ｃ断面図であり、図１２（Ｃ）はＬＧＡ型チップインダクタ１Ｂの底面図である。図１３は、ＬＧＡ型チップインダクタ１Ｂが有する導体および電極を示す斜視図である。 12A is a plan view of the LGA type chip inductor 1B, FIG. 12B is a cross-sectional view taken along the line CC in FIG. 11B, and FIG. 12C is a bottom view of the LGA type chip inductor 1B. FIG. FIG. 13 is a perspective view showing conductors and electrodes of the LGA type chip inductor 1B.
　ＬＧＡ型チップインダクタ１Ｂは、基材１０Ｂ、基材１０Ｂの内部に形成されるコイル３３、第１入出力電極Ｐ１、第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１Ａ，ＣＰ１Ｂ、第２接続電極ＣＰ２および層間接続導体Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖ５を有する。 The LGA type chip inductor 1B includes a base material 10B, a coil 33 formed inside the base material 10B, a first input / output electrode P1, a second input / output electrode P2, a ground electrode GP, first connection electrodes CP1A and CP1B, Two connection electrodes CP2 and interlayer connection conductors V1, V2, V3, V4, and V5 are provided.
　基材１０Ｂは、互いに対向する第１主面ＶＳ１および第２主面ＶＳ２を有し、長手方向がＸ軸方向に一致する直方体の絶縁体平板である。本実施形態に係る基材１０Ｂは、複数の絶縁基材層の積層体である。 The base material 10 </ b> B is a rectangular parallelepiped insulator plate having a first main surface VS <b> 1 and a second main surface VS <b> 2 that face each other and whose longitudinal direction coincides with the X-axis direction. The base material 10B according to the present embodiment is a laminate of a plurality of insulating base material layers.
　コイル３３は、基材１０Ｂの内部に形成される約１ターンのループ状の導体である。コイル３３は、絶縁基材層に形成されるコイル３３Ａ，３３Ｃ、絶縁基材層（コイル３３Ａ，３３Ｃが形成された絶縁基材層とは異なる絶縁基材層）に形成されるコイル３３Ｂ等で構成される。コイル３３Ａ，３３Ｂ，３３Ｃは、絶縁基材層に形成される層間接続導体を介して互いに接続される。なお、コイル３３のターン数は約１ターンに限定されず、複数ターンであってもよい。また、コイル３３はループ状に限定されず、ヘリカル状またはスパイラル状でもよい。 The coil 33 is a loop-shaped conductor of about 1 turn formed inside the base material 10B. The coil 33 includes coils 33A and 33C formed on the insulating base layer, coils 33B formed on the insulating base layer (an insulating base layer different from the insulating base layer on which the coils 33A and 33C are formed), and the like. Composed. The coils 33A, 33B, and 33C are connected to each other via an interlayer connection conductor formed on the insulating base material layer. Note that the number of turns of the coil 33 is not limited to about one turn, and may be a plurality of turns. The coil 33 is not limited to a loop shape, and may be a helical shape or a spiral shape.
　第１入出力電極Ｐ１、第２入出力電極Ｐ２およびグランド電極ＧＰは、基材１０Ｂの第１主面ＶＳ１に形成される導体である。第１入出力電極Ｐ１、第２入出力電極Ｐ２およびグランド電極ＧＰは、長手方向がＹ軸方向に一致した矩形の導体であり、第２入出力電極Ｐ２、グランド電極ＧＰ、第１入出力電極Ｐ１の順にＸ軸方向に並べて配置される。図１２（Ｃ）に示すように、グランド電極ＧＰのＸ軸方向の幅は、第１入出力電極Ｐ１および第２入出力電極Ｐ２のＸ軸方向の幅よりも大きい。 The first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are conductors formed on the first main surface VS1 of the base material 10B. The first input / output electrode P1, the second input / output electrode P2, and the ground electrode GP are rectangular conductors whose longitudinal direction coincides with the Y-axis direction. The second input / output electrode P2, the ground electrode GP, and the first input / output electrode They are arranged in the X-axis direction in the order of P1. As shown in FIG. 12C, the width of the ground electrode GP in the X-axis direction is larger than the width of the first input / output electrode P1 and the second input / output electrode P2 in the X-axis direction.
　第１接続電極ＣＰ１Ａ，ＣＰ１Ｂは、基材１０Ｂの第２主面ＶＳ２の第１辺（図１２（Ｃ）における基材１０Ｂの上辺）付近に配置される矩形の導体である。第１接続電極ＣＰ１Ａ，ＣＰ１Ｂは、第２主面ＶＳ２のＸ軸方向の中央付近で、且つ、Ｘ軸方向に並べて配置される。第２接続電極ＣＰ２は、基材１０Ｂの第２主面ＶＳ２の第２辺（図１２（Ｃ）における基材１０Ｂの下辺）付近に配置される矩形の導体である。第２接続電極ＣＰ２は、第２主面ＶＳ２のＸ軸方向に配置される。 The first connection electrodes CP1A and CP1B are rectangular conductors arranged near the first side (the upper side of the base material 10B in FIG. 12C) of the second main surface VS2 of the base material 10B. The first connection electrodes CP1A and CP1B are arranged near the center of the second main surface VS2 in the X-axis direction and aligned in the X-axis direction. The second connection electrode CP2 is a rectangular conductor disposed near the second side (the lower side of the base material 10B in FIG. 12C) of the second main surface VS2 of the base material 10B. The second connection electrode CP2 is disposed in the X-axis direction of the second main surface VS2.
　図１３に示すように、第１入出力電極Ｐ１は、層間接続導体Ｖ１を介してコイル３３の第１端Ｅ１に接続される。第２入出力電極Ｐ２は、層間接続導体Ｖ２を介して、コイル３３の第２端Ｅ２に接続される。第１接続電極ＣＰ１Ａは、層間接続導体Ｖ４を介して、コイル３３の第３端Ｅ３に接続される。第１接続電極ＣＰ１Ｂは、層間接続導体Ｖ５を介して、コイル３３の第４端Ｅ４に接続される。また、第２接続電極ＣＰ２は、層間接続導体Ｖ３を介してグランド電極ＧＰに接続される。 As shown in FIG. 13, the first input / output electrode P1 is connected to the first end E1 of the coil 33 via the interlayer connection conductor V1. The second input / output electrode P2 is connected to the second end E2 of the coil 33 via the interlayer connection conductor V2. The first connection electrode CP1A is connected to the third end E3 of the coil 33 via the interlayer connection conductor V4. The first connection electrode CP1B is connected to the fourth end E4 of the coil 33 via the interlayer connection conductor V5. The second connection electrode CP2 is connected to the ground electrode GP via the interlayer connection conductor V3.
　図１１に示すように、基材１０Ｂの第２主面ＶＳ２と半導体基板２０の素子形成面Ｓ１とが対向するように、ダイオードチップ２Ａ，２Ｂは基材１０Ｂの第２主面ＶＳ２に搭載される。これにより、ダイオードチップ２Ａの第１端子電極（ＥＰ１）および第２端子電極（ＥＰ２）は、ＬＧＡ型チップインダクタ１Ｂの第１接続電極ＣＰ１Ａおよび第２接続電極ＣＰ２にそれぞれ接続される。また、ダイオードチップ２Ｂの第１端子電極（ＥＰ１）および第２端子電極（ＥＰ２）は、ＬＧＡ型チップインダクタ１Ｂの第１接続電極ＣＰ１Ｂおよび第２接続電極ＣＰ２にそれぞれ接続される。 As shown in FIG. 11, the diode chips 2A and 2B are mounted on the second main surface VS2 of the base material 10B so that the second main surface VS2 of the base material 10B and the element formation surface S1 of the semiconductor substrate 20 face each other. The Accordingly, the first terminal electrode (EP1) and the second terminal electrode (EP2) of the diode chip 2A are connected to the first connection electrode CP1A and the second connection electrode CP2 of the LGA type chip inductor 1B, respectively. The first terminal electrode (EP1) and the second terminal electrode (EP2) of the diode chip 2B are connected to the first connection electrode CP1B and the second connection electrode CP2 of the LGA type chip inductor 1B, respectively.
　図１４はＥＳＤ保護機能付きインダクタ１０３の回路図である。図１４では、コイル３３をコイルＬ３で表し、図１１（Ａ）および図１１（Ｂ）で示した半導体基板２０に形成されるダイオードをダイオードＤ１Ａ，Ｄ１Ｂで表している。 FIG. 14 is a circuit diagram of the inductor 103 with an ESD protection function. In FIG. 14, the coil 33 is represented by a coil L3, and the diodes formed on the semiconductor substrate 20 illustrated in FIGS. 11A and 11B are represented by diodes D1A and D1B.
　ＥＳＤ保護機能付きインダクタ１０３は、図１４に示すように、第１入出力電極Ｐ１と第２入出力電極Ｐ２との間にコイルＬ３が接続され、コイルＬ３の第１端および第２端とグランド電極ＧＰとの間にそれぞれダイオードＤ１Ａ，Ｄ１Ｂが接続された回路である。第１入出力電極Ｐ１はコイルＬ３の第１端に接続され、第２入出力電極Ｐ２はコイルＬ３の第２端に接続される。ダイオードＤ１Ａの第１端は、第１接続電極ＣＰ１Ａおよび第１端子電極ＥＰ１を介して、コイルＬ３の第１端に接続される。ダイオードＤ１Ａの第２端は、第２接続電極ＣＰ２および第２端子電極ＥＰ２を介して、グランド電極ＧＰに接続される。ダイオードＤ１Ｂの第１端は、第１接続電極ＣＰ１Ｂおよび第１端子電極ＥＰ１を介して、コイルＬ３の第２端に接続される。ダイオードＤ１Ｂの第２端は、第２接続電極ＣＰ２および第２端子電極ＥＰ２を介して、グランド電極ＧＰに接続される。図１４に示すように、グランド電極ＧＰはグランドに接続される。 As shown in FIG. 14, the inductor 103 with ESD protection function includes a coil L3 connected between the first input / output electrode P1 and the second input / output electrode P2, and the first and second ends of the coil L3 and the ground. In this circuit, diodes D1A and D1B are connected to the electrode GP, respectively. The first input / output electrode P1 is connected to the first end of the coil L3, and the second input / output electrode P2 is connected to the second end of the coil L3. The first end of the diode D1A is connected to the first end of the coil L3 via the first connection electrode CP1A and the first terminal electrode EP1. The second end of the diode D1A is connected to the ground electrode GP through the second connection electrode CP2 and the second terminal electrode EP2. The first end of the diode D1B is connected to the second end of the coil L3 via the first connection electrode CP1B and the first terminal electrode EP1. The second end of the diode D1B is connected to the ground electrode GP through the second connection electrode CP2 and the second terminal electrode EP2. As shown in FIG. 14, the ground electrode GP is connected to the ground.
　この構成により、コイルＬ３の両端からダイオードＤ１Ａ，Ｄ１Ｂがそれぞれグランドに接続されたローパスフィルタが構成される。また、この構成により、入出力に対して対照性を有する回路構成のＥＳＤ保護機能付きインダクタを得ることができる。 This configuration constitutes a low-pass filter in which the diodes D1A and D1B are connected to the ground from both ends of the coil L3. Also, with this configuration, it is possible to obtain an inductor with an ESD protection function having a circuit configuration having a contrast to input / output.
　本実施形態で示したように、ＬＧＡ型チップインダクタに搭載されるダイオードチップの数は複数でもよい。 As shown in the present embodiment, a plurality of diode chips may be mounted on the LGA type chip inductor.
　《第４の実施形態》
　第４の実施形態では、基材が磁性体部材であり、グランド電極と第２接続電極ＣＰ２との間の配線が第１から第３の実施形態とは異なる例を示す。 << Fourth Embodiment >>
In the fourth embodiment, an example is shown in which the base material is a magnetic member, and the wiring between the ground electrode and the second connection electrode CP2 is different from the first to third embodiments.
　図１５は第４の実施形態に係るＥＳＤ保護機能付きインダクタ１０４の斜視図である。 FIG. 15 is a perspective view of the inductor 104 with an ESD protection function according to the fourth embodiment.
　ＥＳＤ保護機能付きインダクタ１０４は、ＬＧＡ型チップインダクタ１Ｃ、ＬＧＡ型チップインダクタ１Ｃに搭載されるダイオードチップ２を備える。 The inductor 104 with an ESD protection function includes an LGA chip inductor 1C and a diode chip 2 mounted on the LGA chip inductor 1C.
　ＥＳＤ保護機能付きインダクタ１０２は、ＬＧＡ型チップインダクタ１Ｃの構造が第１の実施形態に係るＥＳＤ保護機能付きインダクタ１０１と異なり、その他は同じである。以下、第１の実施形態に係るＥＳＤ保護機能付きインダクタ１０１と異なる部分について説明する。 The inductor 102 with the ESD protection function is the same as the inductor 101 with the ESD protection function according to the first embodiment except for the structure of the LGA chip inductor 1C. Hereinafter, a different part from the inductor 101 with an ESD protection function which concerns on 1st Embodiment is demonstrated.
　図１６（Ａ）はＬＧＡ型チップインダクタ１Ｃの斜視図であり、図１６（Ｂ）はＬＧＡ型チップインダクタ１Ｃが有する導体および電極を示す斜視図である。 16A is a perspective view of an LGA type chip inductor 1C, and FIG. 16B is a perspective view showing conductors and electrodes of the LGA type chip inductor 1C.
　ＬＧＡ型チップインダクタ１Ｃは、基材１０Ｃ、基材１０Ｃの内部に形成されるコイル３１、第１入出力電極Ｐ１、第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１、第２接続電極ＣＰ２および層間接続導体Ｖ１，Ｖ２，Ｖ４，Ｖ５および引き回し導体Ｖ３Ｐを有する。 The LGA chip inductor 1C includes a base material 10C, a coil 31 formed inside the base material 10C, a first input / output electrode P1, a second input / output electrode P2, a ground electrode GP, a first connection electrode CP1, and a second connection. It has an electrode CP2, interlayer connection conductors V1, V2, V4, V5 and a lead conductor V3P.
　基材１０Ｃは、互いに対向する第１主面ＶＳ１および第２主面ＶＳ２を有し、長手方向がＸ軸方向に一致する直方体の絶縁体平板である。本実施形態では、基材１０Ｃは例えば磁性体部材（磁性体フェライト）であり、磁性体フェライトからなる複数の絶縁基材層の積層体である。 The base material 10 </ b> C is a rectangular parallelepiped insulator plate having a first main surface VS <b> 1 and a second main surface VS <b> 2 that face each other and whose longitudinal direction matches the X-axis direction. In the present embodiment, the base material 10C is, for example, a magnetic member (magnetic ferrite), and is a laminate of a plurality of insulating base material layers made of magnetic ferrite.
　コイル３１、第１入出力電極Ｐ１、第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１、第２接続電極ＣＰ２および層間接続導体Ｖ１，Ｖ２，Ｖ４，Ｖ５の構成は、第１の実施形態と実質的に同じである。 The configuration of the coil 31, the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, the second connection electrode CP2, and the interlayer connection conductors V1, V2, V4, V5 is the first configuration. This is substantially the same as the embodiment.
　引き回し導体Ｖ３Ｐは、基材１０Ｃの外面に形成される半円柱状の導体である。引き回し導体Ｖ３Ｐは、例えば厚み方向（Ｚ軸方向）に延伸する円柱状のビア導体やスルーホール等の中央を通るラインで基材ごと厚み方向（Ｚ軸方向）に切断したものである。 The lead conductor V3P is a semi-cylindrical conductor formed on the outer surface of the base material 10C. The lead conductor V3P is, for example, cut in the thickness direction (Z-axis direction) together with the substrate along a line passing through the center of a cylindrical via conductor or a through hole extending in the thickness direction (Z-axis direction).
　図１６（Ｂ）に示すように、第１入出力電極Ｐ１は、層間接続導体Ｖ１を介してコイル３１の第１端Ｅ１に接続される。第２入出力電極Ｐ２は、導体４１および層間接続導体Ｖ２，Ｖ５を介して、コイル３１の第２端に接続される。また、第１接続電極ＣＰ１は、導体４１および層間接続導体Ｖ４，Ｖ５を介して、コイル３１の第２端Ｅ２に接続される。また、第２接続電極ＣＰ２は、引き回し導体Ｖ３Ｐを介してグランド電極ＧＰに接続される。 As shown in FIG. 16B, the first input / output electrode P1 is connected to the first end E1 of the coil 31 via the interlayer connection conductor V1. The second input / output electrode P2 is connected to the second end of the coil 31 through the conductor 41 and the interlayer connection conductors V2 and V5. The first connection electrode CP1 is connected to the second end E2 of the coil 31 through the conductor 41 and the interlayer connection conductors V4 and V5. The second connection electrode CP2 is connected to the ground electrode GP through the lead conductor V3P.
　図１５に示すように、ダイオードチップ２は基材１０Ｃの第２主面ＶＳ２に搭載される。これにより、ダイオードチップ２の第１端子電極（ＥＰ１）および第２端子電極（ＥＰ２）は、ＬＧＡ型チップインダクタ１Ｃの第１接続電極ＣＰ１および第２接続電極ＣＰ２にそれぞれ接続される。 As shown in FIG. 15, the diode chip 2 is mounted on the second main surface VS2 of the substrate 10C. Thus, the first terminal electrode (EP1) and the second terminal electrode (EP2) of the diode chip 2 are connected to the first connection electrode CP1 and the second connection electrode CP2 of the LGA type chip inductor 1C, respectively.
　図１７はＥＳＤ保護機能付きインダクタ１０４の回路図である。図１７では、コイル３１をコイルＬ１で表し、図１６（Ａ）および図１６（Ｂ）で示した半導体基板２０に形成されるダイオードをダイオードＤ１で表している。 FIG. 17 is a circuit diagram of the inductor 104 with an ESD protection function. In FIG. 17, the coil 31 is represented by a coil L1, and the diode formed on the semiconductor substrate 20 illustrated in FIGS. 16A and 16B is represented by a diode D1.
　このように、第１の実施形態と同様に、ＬＧＡ型チップインダクタ１Ｃのインダクタンス成分（コイルＬ１）と、ダイオードＤ１が有する容量成分とで、ローパスフィルタが構成される。 Thus, as in the first embodiment, the low-pass filter is configured by the inductance component (coil L1) of the LGA chip inductor 1C and the capacitance component of the diode D1.
　本実施形態に係るＥＳＤ保護機能付きインダクタ１０４によれば、第１の実施形態で述べた効果以外に、次のような効果を奏する。 In addition to the effects described in the first embodiment, the inductor 104 with an ESD protection function according to the present embodiment has the following effects.
（ｃ）本実施形態では、基材１０Ｃが磁性体部材である。この構成により、コイル３１を大型化することなく（または、コイル３１のターン数を増やすことなく）、所定のインダクタンス値を有するチップインダクタが得られる。 (C) In this embodiment, the base material 10C is a magnetic member. With this configuration, a chip inductor having a predetermined inductance value can be obtained without increasing the size of the coil 31 (or without increasing the number of turns of the coil 31).
（ｄ）本実施形態では、図１７に示すダイオードＤ１とグランド電極ＧＰ（グランド）との間の配線である引き回し導体Ｖ３Ｐが、磁性体部材である基材１０Ｃの外面に形成される。この構成により、ダイオードＤ１とグランド電極ＧＰとの間の配線を磁性体部材（基材）の内部に形成する場合に比べて、ダイオードＤ１とグランド電極ＧＰとの間の配線に生じる寄生インダクタを抑制できる。したがって、この構成により、ＥＳＤ保護機能付きインダクタ１０４のＥＳＤ保護機能（除去機能）やフィルタの減衰特性が向上する。なお、この効果は特に高周波において顕著である。 (D) In the present embodiment, the lead conductor V3P, which is a wiring between the diode D1 and the ground electrode GP (ground) shown in FIG. 17, is formed on the outer surface of the base material 10C that is a magnetic member. With this configuration, the parasitic inductor generated in the wiring between the diode D1 and the ground electrode GP is suppressed as compared with the case where the wiring between the diode D1 and the ground electrode GP is formed inside the magnetic body member (base material). it can. Therefore, this configuration improves the ESD protection function (removal function) of the inductor 104 with ESD protection function and the attenuation characteristic of the filter. This effect is particularly remarkable at high frequencies.
　なお、本実施形態では、半円柱状の引き回し導体Ｖ３Ｐを示したが、引き回し導体はこの構成に限定されるものではない。引き回し導体は、基材の外面に形成される導体パターン等であってもよい。 In the present embodiment, the semi-cylindrical routing conductor V3P is shown, but the routing conductor is not limited to this configuration. The lead conductor may be a conductor pattern formed on the outer surface of the substrate.
　《その他の実施形態》
　以上に示した各実施形態では、基材の平面形状が矩形の直方体である例を示したが、この構成に限定されるものではない。基材の形状は、本発明の作用・効果を奏する範囲において適宜変更可能である。基材の平面形状は、例えば多角形、円形、楕円形、Ｌ字形、クランク形、Ｔ字形、Ｙ字形等であってもよい。 << Other Embodiments >>
In each of the embodiments described above, an example in which the planar shape of the base material is a rectangular parallelepiped has been shown, but the present invention is not limited to this configuration. The shape of the base material can be changed as appropriate within the range where the functions and effects of the present invention are exhibited. The planar shape of the substrate may be, for example, a polygon, a circle, an ellipse, an L shape, a crank shape, a T shape, a Y shape, or the like.
　以上に示した各実施形態では、基材が複数の絶縁基材層の積層体である例を示したが、この構成に限定されるものではない。基材は、単層であってもよい。また、以上に示した各実施形態では、基材が低温同時焼成セラミックス（ＬＴＣＣ）のような誘電体セラミック、または磁性体フェライトである例を示したが、この構成に限定されるものではない。基材は例えば熱硬化性樹脂からなる樹脂成型体であってもよい。 In each of the embodiments described above, an example in which the base material is a laminated body of a plurality of insulating base material layers is shown, but the present invention is not limited to this configuration. The substrate may be a single layer. Further, in each of the embodiments described above, an example in which the base material is a dielectric ceramic such as low temperature co-fired ceramics (LTCC) or a magnetic ferrite is shown, but the present invention is not limited to this configuration. The base material may be a resin molded body made of, for example, a thermosetting resin.
　以上に示した各実施形態では、厚み方向（Ｚ軸方向）に巻回軸を有する約１ターンのループ状または約２ターンのスパイラル状のコイルの例を示したが、この構成に限定されるものではない。コイルの形状、巻回数は本発明の作用・効果を奏する範囲において適宜変更可能である。コイルは例えばヘリカル状の導体であってもよい。また、コイルの巻回軸についても、本発明の作用・効果を奏する範囲において適宜変更可能であり、Ｘ軸方向またはＹ軸方向に沿っていてもよい。また、以上に示した各実施形態では、基材の内部にコイルが形成される例を示したが、例えばコイルの一部または全部が基材の端面（表面）等に形成されていてもよい。 In each of the embodiments described above, an example of a loop-shaped coil of about 1 turn or a spiral of about 2 turns having a winding axis in the thickness direction (Z-axis direction) is shown, but the present invention is limited to this configuration. It is not a thing. The shape of the coil and the number of turns can be changed as appropriate within the range where the functions and effects of the present invention are exhibited. For example, the coil may be a helical conductor. Also, the winding axis of the coil can be appropriately changed within the range where the operation and effect of the present invention are exhibited, and may be along the X-axis direction or the Y-axis direction. Moreover, in each embodiment shown above, although the example in which a coil was formed in the inside of a base material was shown, for example, a part or all of a coil may be formed in the end surface (surface) etc. of a base material. .
　また、以上に示した各実施形態では、ローパスフィルタが構成されたＥＳＤ保護機能付きインダクタの例を示したが、この構成に限定されるものではない。ＥＳＤ保護機能付きインダクタに構成される回路は、適宜変更可能である。また、ＬＧＡ型チップインダクタに搭載される部品は、ＥＳＤ保護機能付きインダクタに構成される回路によって変更可能である。例えば、ダイオードチップ以外にチップコンデンサ等が、ＬＧＡ型チップインダクタに搭載されていてもよい。 In each of the embodiments described above, an example of an inductor with an ESD protection function in which a low-pass filter is configured has been described, but the present invention is not limited to this configuration. The circuit configured in the inductor with an ESD protection function can be changed as appropriate. The components mounted on the LGA type chip inductor can be changed by a circuit configured as an inductor with an ESD protection function. For example, a chip capacitor or the like other than the diode chip may be mounted on the LGA type chip inductor.
　以上に示した各実施形態では、ダイオードチップを基材の第２主面ＶＳ２に搭載した例を示したが、この構成に限定されるものではない。ＬＧＡ型チップインダクタに搭載される部品は、第１主面ＶＳ１および第２主面ＶＳ２以外に形成されていてもよく、例えば端面等に搭載されていてもよい。同様に、第１接続電極ＣＰ１および第２接続電極ＣＰ２は、第１主面ＶＳ１および第２主面ＶＳ２以外に形成されていてもよい。 In each of the embodiments described above, the example in which the diode chip is mounted on the second main surface VS2 of the base material has been described. However, the present invention is not limited to this configuration. The components mounted on the LGA type chip inductor may be formed other than the first main surface VS1 and the second main surface VS2, for example, may be mounted on an end surface or the like. Similarly, the first connection electrode CP1 and the second connection electrode CP2 may be formed other than the first main surface VS1 and the second main surface VS2.
　以上に示した各実施形態では、第１入出力電極Ｐ１，第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１および第２接続電極ＣＰ２が矩形の導体である例について示したが、この構成に限定されるものではない。第１入出力電極Ｐ１，第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１および第２接続電極ＣＰ２の形状は適宜変更可能である。また、第１入出力電極Ｐ１，第２入出力電極Ｐ２、グランド電極ＧＰ、第１接続電極ＣＰ１および第２接続電極ＣＰ２の配置・個数についても、ＥＳＤ保護機能付きインダクタの回路構成によって適宜変更可能である。 In each of the embodiments described above, an example in which the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, and the second connection electrode CP2 are rectangular conductors has been described. It is not limited to this configuration. The shapes of the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, and the second connection electrode CP2 can be changed as appropriate. Further, the arrangement and number of the first input / output electrode P1, the second input / output electrode P2, the ground electrode GP, the first connection electrode CP1, and the second connection electrode CP2 can be appropriately changed depending on the circuit configuration of the inductor with the ESD protection function. It is.
　以上に示した各実施形態では、ダイオードチップの第１端子電極ＥＰ１および第２端子電極ＥＰ２を、半導体基板２０の素子形成面Ｓ１に形成した導体パターンによって構成する例を示したが、この構成に限定されるものではない。第１端子電極ＥＰ１および第２端子電極ＥＰ２は、半導体基板２０の素子形成面Ｓ１に再配線層を形成して構成してもよい。 In each of the embodiments described above, an example in which the first terminal electrode EP1 and the second terminal electrode EP2 of the diode chip are configured by the conductor pattern formed on the element formation surface S1 of the semiconductor substrate 20 has been described. It is not limited. The first terminal electrode EP1 and the second terminal electrode EP2 may be configured by forming a rewiring layer on the element formation surface S1 of the semiconductor substrate 20.
　以上に示した各実施形態では、ダイオードチップが、基材の第１主面ＶＳ１および第２主面ＶＳ２を平面視して、コイルに重なる構成例を示したが、これに限定されるものではない。ダイオードチップは、基材の第１主面ＶＳ１および第２主面ＶＳ２を平面視して、コイルに重なっていなくてもよい。 In each of the embodiments described above, the diode chip is shown as a configuration example in which the first main surface VS1 and the second main surface VS2 of the base material are planarly viewed and overlapped with the coil. However, the present invention is not limited to this. Absent. The diode chip does not have to overlap the coil in plan view of the first main surface VS1 and the second main surface VS2 of the base material.
　最後に、上述の実施形態の説明は、すべての点で例示であって、制限的なものではない。当業者にとって変形および変更が適宜可能である。本発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、本発明の範囲には、特許請求の範囲内と均等の範囲内での実施形態からの変更が含まれる。 Finally, the description of the above embodiment is illustrative in all respects and not restrictive. Modifications and changes can be made as appropriate by those skilled in the art. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.
Ｌ１，Ｌ２，Ｌ３…コイル
Ｄ１，Ｄ１Ａ，Ｄ１Ｂ…ダイオード
１，１Ａ，１Ｂ，１Ｃ…ＬＧＡ型チップインダクタ
１０，１０Ａ，１０Ｂ，１０Ｃ…基材
ＶＳ１…基材の第１主面
ＶＳ２…基材の第２主面
ＧＰ…グランド電極
Ｐ１…第１入出力電極
Ｐ２…第２入出力電極
ＣＰ１，ＣＰ１Ａ，ＣＰ１Ｂ…第１接続電極
ＣＰ２…第２接続電極
Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖ５…層間接続導体
Ｖ３Ｐ…引き回し導体
３１，３２，３２Ａ，３２Ｂ，３２Ｃ，３３，３３Ａ，３３Ｂ，３３Ｃ…コイル
Ｅ１…コイルの第１端
Ｅ２…コイルの第２端
Ｅ３…コイルの第３端
Ｅ４…コイルの第４端
４１…導体
２，２Ａ，２Ｂ…ダイオードチップ
ＥＰ１…第１端子電極
ＥＰ２…第２端子電極
２０…半導体基板
２１…半導体素子部
Ｓ１…半導体基板の素子形成面
３，４…絶縁層
５１，５２…電極
１０１，１０２，１０３，１０４…ＥＳＤ保護機能付きインダクタ L1, L2, L3 ... Coils D1, D1A, D1B ... Diodes 1, 1A, 1B, 1C ... LGA type chip inductors 10, 10A, 10B, 10C ... Base material VS1 ... First main surface VS2 of base material ... of base material Second main surface GP ... ground electrode P1 ... first input / output electrode P2 ... second input / output electrodes CP1, CP1A, CP1B ... first connection electrode CP2 ... second connection electrodes V1, V2, V3, V4, V5 ... interlayer connection Conductor V3P ... Leading conductor 31, 32, 32A, 32B, 32C, 33, 33A, 33B, 33C ... Coil E1 ... First end E2 of coil ... Second end E3 of coil ... Third end E4 of coil ... Third of coil 4 ends 41 ... conductors 2, 2A, 2B ... diode chip EP1 ... first terminal electrode EP2 ... second terminal electrode 20 ... semiconductor substrate 21 ... semiconductor element part S1 ... element formation surfaces 3, 4 ... insulation of the semiconductor substrate Layers 51, 52 ... electrodes 101, 102, 103, 104 ... ESD protection function inductor

Claims (7)

  1. 　実装面である第１主面を有する基材と、前記基材に形成されるコイルと、前記第１主面に形成され、前記コイルの第１端に接続される第１入出力電極と、前記第１主面に形成され、前記コイルの第２端に接続される第２入出力電極と、前記第１主面に形成されるグランド電極と、前記コイルに接続される第１接続電極と、前記グランド電極に接続される第２接続電極と、を有するＬＧＡ型チップインダクタと、
    　半導体基板と、ＥＳＤ保護素子として機能し、前記半導体基板に形成されるダイオードと、前記ダイオードの第１端および第２端にそれぞれ接続される第１端子電極および第２端子電極と、を有するダイオードチップと、
    　を備え、
    　前記ダイオードチップは、前記ＬＧＡ型チップインダクタに搭載され、
    　前記ダイオードチップの前記第１端子電極および前記第２端子電極は、前記ＬＧＡ型チップインダクタの前記第１接続電極および前記第２接続電極にそれぞれ接続される、ＥＳＤ保護機能付きインダクタ。     A base material having a first main surface which is a mounting surface; a coil formed on the base material; a first input / output electrode formed on the first main surface and connected to a first end of the coil; A second input / output electrode formed on the first main surface and connected to a second end of the coil; a ground electrode formed on the first main surface; and a first connection electrode connected to the coil; A LGA type chip inductor having a second connection electrode connected to the ground electrode;
    A diode having a semiconductor substrate, a diode that functions as an ESD protection element, formed on the semiconductor substrate, and a first terminal electrode and a second terminal electrode that are respectively connected to a first end and a second end of the diode Chips,
    With
    The diode chip is mounted on the LGA type chip inductor,
    The inductor with an ESD protection function, wherein the first terminal electrode and the second terminal electrode of the diode chip are connected to the first connection electrode and the second connection electrode of the LGA chip inductor, respectively.
  2. 　前記基材は、前記第１主面に対向する第２主面を有し、
    　前記第１接続電極および前記第２接続電極は、前記第２主面に形成され、
    　前記ダイオードチップは、前記基材の前記第２主面に搭載される、請求項１に記載のＥＳＤ保護機能付きインダクタ。     The base has a second main surface facing the first main surface;
    The first connection electrode and the second connection electrode are formed on the second main surface,
    The inductor with an ESD protection function according to claim 1, wherein the diode chip is mounted on the second main surface of the base material.
  3. 　前記ダイオードチップは、前記第１主面および前記第２主面を平面視して、前記コイルに重なる、請求項２に記載のＥＳＤ保護機能付きインダクタ。 3. The inductor with an ESD protection function according to claim 2, wherein the diode chip overlaps the coil in a plan view of the first main surface and the second main surface.
  4. 　前記基材は、複数の絶縁基材層の積層体である、請求項１から３のいずれかに記載のＥＳＤ保護機能付きインダクタ。 The inductor with an ESD protection function according to any one of claims 1 to 3, wherein the base material is a laminate of a plurality of insulating base material layers.
  5. 　前記ＬＧＡ型チップインダクタのインダクタンス成分と、前記ダイオードが有する容量成分とでローパスフィルタを構成する、請求項１から４のいずれかに記載のＥＳＤ保護機能付きインダクタ。 The inductor with an ESD protection function according to any one of claims 1 to 4, wherein a low-pass filter is constituted by an inductance component of the LGA type chip inductor and a capacitance component of the diode.
  6. 　前記基材に形成される第１層間接続導体を備え、
    　前記第１接続電極は、前記第１層間接続導体を介して前記コイルに接続される、請求項１から５のいずれかに記載のＥＳＤ保護機能付きインダクタ。     Comprising a first interlayer connection conductor formed on the substrate;
    The inductor with an ESD protection function according to claim 1, wherein the first connection electrode is connected to the coil via the first interlayer connection conductor.
  7. 　前記基材は磁性体部材であり、
    　前記基材の外面に形成される引き回し導体を備え、
    　前記グランド電極は、前記引き回し導体を介して前記第２接続電極に接続される、請求項１から６のいずれかに記載のＥＳＤ保護機能付きインダクタ。     The substrate is a magnetic member;
    A routing conductor formed on the outer surface of the base material,
    The inductor with an ESD protection function according to claim 1, wherein the ground electrode is connected to the second connection electrode via the lead conductor.
PCT/JP2017/023067 2016-07-06 2017-06-22 Inductor with esd protection function WO2018008422A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019202774A1 (en) * 2018-04-16 2019-10-24 株式会社村田製作所 Esd protective element
US11444078B2 (en) 2018-04-16 2022-09-13 Murata Manufacturing Co., Ltd. ESD protection element

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JPH059025U (en) * 1991-07-08 1993-02-05 株式会社村田製作所 Noise filter with varistor function
JP2007060892A (en) * 2005-07-25 2007-03-08 Tdk Corp Surge absorbing circuit
WO2007029615A1 (en) * 2005-09-07 2007-03-15 Matsushita Electric Industrial Co., Ltd. Composite electronic device
JP2012209767A (en) * 2011-03-30 2012-10-25 Tdk Corp Laminated band-pass filter
JP2014022426A (en) * 2012-07-13 2014-02-03 Panasonic Corp Laminated inductor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH059025U (en) * 1991-07-08 1993-02-05 株式会社村田製作所 Noise filter with varistor function
JP2007060892A (en) * 2005-07-25 2007-03-08 Tdk Corp Surge absorbing circuit
WO2007029615A1 (en) * 2005-09-07 2007-03-15 Matsushita Electric Industrial Co., Ltd. Composite electronic device
JP2012209767A (en) * 2011-03-30 2012-10-25 Tdk Corp Laminated band-pass filter
JP2014022426A (en) * 2012-07-13 2014-02-03 Panasonic Corp Laminated inductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019202774A1 (en) * 2018-04-16 2019-10-24 株式会社村田製作所 Esd protective element
US11444078B2 (en) 2018-04-16 2022-09-13 Murata Manufacturing Co., Ltd. ESD protection element

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