WO2017041691A1

WO2017041691A1 - Self-biased bandgap reference circuit with wide range of input voltages and high-precision output

Info

Publication number: WO2017041691A1
Application number: PCT/CN2016/098175
Authority: WO
Inventors: 许育森; 吴边
Original assignee: 卓捷创芯科技（深圳）有限公司; 无锡智速科技有限公司
Priority date: 2015-09-07
Filing date: 2016-09-06
Publication date: 2017-03-16
Also published as: CN105116954A; CN105116954B

Abstract

A self-biased bandgap reference circuit having a wide range of input voltages and a high-precision output. The circuit comprises a self-biasing unit. The self-biasing unit comprises a mirroring unit and a following unit. The self-biasing unit can reduce a voltage difference between bias points (x, y) at a high supply voltage effectively and increase the matching precision and thus the precision of an output reference voltage. Also, the self-biased circuit structure does not use an operational amplifier, and thus has a simple structure and reduces the power consumption, thereby addressing the application problem of a thin gate oxide high-voltage device and eliminating the clamping control specific to an output voltage of the operational amplifier, so as to prevent a gate of a high-voltage MOS transistor from being punctured at a high voltage of a thin gate oxide. Further, since a minimum value of an input voltage (Vdd) is a sum of threshold voltages of MOS transistors, and a maximum value of the input voltage (Vdd) is related to a Vds withstand value of the MOS transistor and can be a high value, therefore, the present invention can operate in a wide range of input voltages.

Description

Self-biased bandgap reference circuit with wide input voltage range and high precision output

Technical field

The invention relates to the field of analog integrated circuit design, in particular to a self-biased bandgap reference circuit having a wide input voltage range and high precision output.

Background technique

The reference circuit is a key circuit in an analog integrated circuit that provides a stable reference voltage inside the chip. The reference voltage is insensitive to changes in process, supply voltage and temperature and can be stable. The reference voltage can be used for biasing in the chip circuit, which is an important component of the low-dropout regulated power supply and analog-to-digital converter.

The bandgap reference circuit utilizes the bandgap voltage of silicon to provide such a reference voltage. To achieve a low temperature coefficient reference voltage, two quantities having opposite temperature coefficients are added with appropriate weights to obtain a voltage value that cancels the temperature coefficient. It is well known that the base-emitter voltage (V _BE ) of a bipolar transistor has a negative temperature coefficient.

The bipolar transistor collector current I _C and the base-emitter voltage V _BE satisfy the following relationship

Where I _S is the saturation current, which is proportional to the emitter area of the bipolar transistor, V _T is the thermal voltage and has a positive temperature coefficient. Assuming that the two bipolar transistors are biased at the same current, the ratio of the emission area between them is n, then I _C1 = I _C2 ,

Therefore, the base-emitter voltage difference of two bipolar transistors having different emitter areas biased at equal current densities has a positive temperature coefficient, and these characteristics of the bipolar transistor can be utilized to implement the bandgap reference circuit.

The traditional self-biased bandgap reference circuit is shown in Figure 1. The traditional self-biasing structure (PM1, PM2, NM1, and NM2) is itself a feedback loop. I _PM1 replicates I _PM2 and I _NM2 replicates I _NM1 . Where I _PM1 = I _NM1 , I _PM2 = I _NM2 . It can be seen that this loop is a positive feedback loop with a loop gain equal to the loop current gain. According to the feedback loop stability theory, the requirement that the positive feedback loop reaches a steady state is that its loop gain is less than 1, otherwise the positive feedback loop must cause self-oscillation. The loop gain A of the loop structure can be obtained by disconnecting the gates of NM1 and NM2 and adding a voltage vi to the gate of NM2 to calculate the loop return voltage vr.

R _Q1 and R _Q2 are the equivalent resistances of the emitters of transistors Q1 and Q2 to ground.

therefore

That is, A<1 is always true, so the positive feedback loop is stable. In the stable positive feedback loop, the nodes Vx and Vy can maintain a voltage equal to some extent according to the characteristics of the matching transistors in the integrated circuit manufacturing process, so that if the bias currents are supplied to the two bipolar transistors Q1 and Q2 The same, and the ratio of the emitter area of Q1 and Q2 is 1:n, then the current flowing through R1 is I _PM2 =V _T ln(n)/R1, I _PM3 =I _PM2 , then Vbg=V _BE3 +R2*I _PM3 V _BE3 +R2*V _T ln(n)/R1(1).

Whether Vx and Vy can ensure equality depends on the matching characteristics described above and the error correction capability of the positive feedback loop with gain less than one. In fact, the general circuit only has a negative feedback loop gain far greater than 1, forming a powerful error correction mechanism to ensure that the voltages of the two nodes are equal. In the structure of Fig. 1, Vx and Vy are not guaranteed to be completely equal. First, as described above, the relevant transistor matching characteristics make Vx and Vy equal to a certain extent, but very limited. Considering the influence of the channel modulation effect, the Vds difference between PM1 and PM2 will cause PM1 not to completely mirror the PM2 current. Thereby causing a voltage between Vx and Vy It is not equal, especially when Vdd changes over a large voltage range, Vx and Vy are more different; secondly, the positive feedback nature of the loop makes it impossible to have error correction mechanism like negative feedback, and the voltages of Vx and Vy are not guaranteed. Consistently under all changing conditions, that is, equality cannot be guaranteed. At the same time, the positive feedback property causes the circuit to have a relatively weak power supply rejection ratio, thereby affecting the accuracy and temperature drift of the output voltage of the conventional bandgap reference circuit. characteristic. Therefore, the circuit structure itself has neither effective avoidance of the adverse effects of the channel modulation effect, and no effective feedback mechanism to correct such voltage differences, which has a large disadvantage and limits its application. For example, in radio frequency identification (RFID) applications, when the RFID tag is far away from the card reader, the power supply voltage varies greatly, causing the consistency of Vx and Vy to deteriorate further, which is not suitable for RFID applications.

In order to make Vx and Vy consistently within the voltage variation range of Vdd, there is a circuit structure as shown in Fig. 2. The output of the op amp controls the gates of PM1 and PM2. If PM1 and PM2 are the same size, it can be guaranteed. The current flowing through PM1 and PM2 does not change with Vdd, and is almost equal. Its output V _{bg is the} same as equation (1). This technology utilizes the high gain negative feedback of the operational amplifier to form a powerful error correction mechanism, making Vx and Vy almost equal, which can better solve the above mentioned shortcomings, but also introduce other shortcomings.

First, the circuit uses the feedback of the op amp to achieve Vx=Vy. High-gain op amps are needed to achieve higher accuracy. Generally, two-stage op amps are used. Two-stage op amps require frequency compensation, which increases the design difficulty. Moreover, since the use of the op amp additionally increases circuit power consumption and circuit area, the circuit cost is further increased. Secondly, under high voltage Vdd, it is easy to cause the problem of gate oxide breakdown. The op amp uses Vdd as the power input and the output directly controls the gates of PM1 and PM2. In some processes, high voltage CMOS devices can be fabricated in standard CMOS processes without the need to adjust process steps. In such a process, the drain-source voltage of a CMOS device can be made very high, but the gate-source voltage needs to be particularly limited because a thin gate oxide is under high voltage. Easy to penetrate. Therefore, the high voltage design of the op amp and the op amp output voltage in these processes require special control to prevent breakdown of the gates of PM1, PM2, and PM3. The high cost of the high voltage CMOS process results in limited commercial value of the product under the process. In order to maximize the commercial profit, it puts higher requirements on the complexity of the process and improves the difficulty of circuit design.

Summary of the invention

This application proposes a self-biased bandgap reference circuit with a wide input voltage range and high precision output for the wide input voltage range and compatible standard CMOS process in the bandgap reference circuit to eliminate the use and tradition of the op amp. The disadvantage of the large offset of the self-biased bandgap reference circuit is that the present invention has no significant disadvantage in terms of circuit performance and the use of an operational amplifier.

To achieve the above object, the technical solution adopted by the present invention is: a self-biased bandgap reference circuit with a wide input voltage range and high precision output, including a first P-type MOS transistor connected to a power supply, and a second P-type MOS And a third P-type MOS transistor, and a first N-type MOS transistor and a second N-type MOS transistor respectively connected to the drain terminal of the first P-type MOS transistor and the drain terminal of the second P-type MOS transistor An N-type MOS transistor is grounded through a first triode, the second N-type MOS transistor is connected to the second triode through a first resistor and grounded, and the third P-type MOS transistor is connected to the gate a P-type MOS transistor and a second P-type MOS transistor gate, the drain terminal is connected to the third transistor through a second resistor and grounded, the circuit further comprising a self-biasing unit connected to the power source, the self-bias The unit includes a mirror unit and a follow unit.

The first power input end and the second power input end of the mirroring unit are respectively connected to the power source, and the first output end and the second output end are respectively connected to the following unit, for generating two current value signals of the same size and outputting to The following control unit is connected to the gate terminals of the first P-type MOS transistor, the second P-type MOS transistor and the third P-type MOS transistor for controlling the first P-type MOS transistor and the second P-type MOS a bias voltage between the tube and the gate terminal of the third P-type MOS transistor;

The first input end and the second input end of the following unit are respectively connected to the first output end and the second output end of the mirror unit, and the third input end of the follow unit is connected to the first P type MOS a drain of the tube and a drain of the first N-type MOS transistor, a fourth input terminal of the follower unit being connected to a drain of the second P-type MOS transistor and a drain of the second N-type MOS transistor, Ground the ground of the following unit.

According to the invention of the above structure, a further technical feature is that the mirror unit includes a fourth P-type MOS transistor and a fifth P-type MOS transistor.

The fourth P-type MOS transistor source is connected to a power source as a first power input end of the mirror unit, and a gate thereof is connected to a drain thereof and connected to a follower unit as a first output end of the mirror unit;

The fifth P-type MOS transistor source is connected to the power source as the second power input end of the mirror unit, and the drain thereof is connected to the following unit as the second output end of the mirror unit;

The fourth P-type MOS transistor gate is connected to the fifth P-type MOS transistor gate, and is simultaneously connected to the first P-type MOS transistor, the second P-type MOS transistor, and the third P-type MOS transistor The gate terminal serves as a control terminal of the mirror unit.

A further technical feature is that the following unit includes a third N-type MOS transistor, a fourth N-type MOS transistor, a fifth N-type MOS transistor, and a sixth N-type MOS transistor.

The drain of the third N-type MOS transistor is connected to the first output end of the mirror unit, as the first input end of the follower unit, the gate thereof is connected to the drain of the first P-type MOS transistor and the first a drain of the N-type MOS transistor as a third input terminal of the follower unit, a source thereof is connected to a drain of the sixth N-type MOS transistor, and a gate of the sixth N-type MOS transistor is connected to the a drain of the fourth N-type MOS transistor, and a source of the sixth N-type MOS transistor is grounded;

The drain of the fourth N-type MOS transistor is connected to the second output end of the mirror unit, as the a second input terminal of the cell, the gate of which is connected to the drain of the second P-type MOS transistor and the drain of the second N-type MOS transistor, as the fourth input terminal of the follower unit, the source of which is connected to the a source of the third N-type MOS transistor connected to the drain of the fifth N-type MOS transistor, and a gate of the fifth N-type MOS transistor connected to the drain of the fourth N-type MOS transistor, the fifth N The source of the MOS transistor is grounded as the ground of the follower unit.

The technical solution proposed by the present application can be directly applied to a wide input voltage range and a thin gate oxygen high voltage device application. The novel self-biasing structure adopted by the invention greatly reduces the voltage difference between the bias points Vx and Vy in the conventional self-biasing structure, and achieves the purpose of improving the accuracy of the output reference voltage. Because of the conventional self-biasing structure, the first P-type MOS transistor PM1 and the diode-connected second P-type MOS transistor PM2 (assuming the same size) are flowing through the PM1 over a wide input voltage range, especially at input high voltage. The current and PM2 current offsets are larger, and there is not enough gain feedback mechanism to reduce such offset, which ultimately results in Vx not being approximately equal to Vy. In the self-biasing structure of the present invention, the diode-connected PM2 is released. The tube makes the drain voltages of PM1 and PM2 (ie, Vx, Vy) almost the same under the input voltage change, and the channel modulation effect greatly reduces the current offset of the two branches of PM1 and PM2. In addition, the effect of the op amp of the present invention is such that the self-biasing structure itself has a certain gain feedback control Vx and Vy that are approximately equal. In summary: Compared with the bandgap reference circuit structure composed of the conventional self-biased structure, the novel self-biasing structure adopted by the present invention effectively reduces the voltage difference between the bias points Vx and Vy at a high power supply voltage, thereby improving the voltage difference. Matching accuracy, which in turn increases the accuracy of the output reference voltage.

At the same time, the self-biasing circuit structure of the invention does not adopt an operational amplifier, has a simple structure, reduces power consumption, solves the application in a thin gate oxygen high voltage device, and eliminates the special clamp control of the output voltage of the operational amplifier to prevent thinning. Breakdown of the gate of the high voltage MOS transistor under gate oxide high voltage. The bias current of the circuit of the present invention is determined by Q1, Q2 and R1. This current is not large. The current flows through the diode-connected fourth P-type MOS transistor PM4. The gate bias of PM4 follows the power supply voltage Vdd. The gate bias is an output control terminal, and the level range is not It will exceed the Vgs limit of the thin-gate oxygen high voltage device, so the invention itself is compatible with thin gate oxygen high pressure applications.

The minimum value of the input voltage Vdd of the present invention is VBE _Q1 + Vgs _NM1 + Vdsat _PM1 (or VBE _Q2 + Vgs _NM2 + Vdsat _PM2 ), which is approximately 2V, and the maximum value of Vdd is related to the Vds withstand voltage of the PM1 or PM2 MOS tube. This can be a very high value, so the invention can operate over a wide range of input voltages.

DRAWINGS

1 is a structural diagram of a conventional self-biased bandgap reference circuit;

2 is a structural diagram of a self-biased bandgap reference circuit with an operational amplifier;

3 is a block diagram showing the structure of a self-biased bandgap reference circuit of the present invention;

4 is a structural diagram of Embodiment 1 of a self-biased bandgap reference circuit of the present invention;

5 is a structural diagram of Embodiment 2 of a self-biased bandgap reference circuit of the present invention;

6 is a structural diagram of Embodiment 3 of a self-biased bandgap reference circuit of the present invention;

Figure 7 is a block diagram showing the fourth embodiment of the self-biased bandgap reference circuit of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

As shown in FIG. 3, a self-biased bandgap reference circuit with a wide input voltage range and high precision output according to the present invention includes a first P-type MOS transistor PM1 connected to a power supply Vdd, and a second P-type MOS transistor PM2. And the third P type a MOS transistor PM3, and a first N-type MOS transistor NM1 and a second N-type MOS transistor NM2 connected to the drain terminal of the first P-type MOS transistor PM1 and the drain terminal of the second P-type MOS transistor PM2, respectively, the first The N-type MOS transistor NM1 is grounded through the first transistor Q1, and the second N-type MOS transistor NM2 is connected to the second transistor Q2 through the first resistor R1 and grounded, and the gate of the third P-type MOS transistor PM3 Connected to the gates of the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2, the drain terminal is connected to the third transistor Q3 through the second resistor R2 and grounded.

The circuit further includes a self-biasing unit connected to the power source Vdd, the self-biasing unit including a mirror unit and a follow unit,

The first power input end and the second power input end of the mirroring unit are respectively connected to the power source Vdd, and the first output end O1 and the second output end O2 are respectively connected to the following unit for generating two current value signals of the same size And outputting to the following unit, the output control terminal Ctr is connected to the gate terminals of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, and the third P-type MOS transistor PM3 for controlling the first P-type a bias voltage of the gate end of the MOS transistor PM1, the second P-type MOS transistor PM2, and the third P-type MOS transistor PM3;

The first input end In1 and the second input end In2 of the following unit are respectively connected to the first output end O1 and the second output end O2 of the mirror unit, and the third input end In3 of the following unit is connected to the a drain of the first P-type MOS transistor PM1 and a drain of the first N-type MOS transistor NM1, and a fourth input terminal In4 of the follow-up unit is connected to a drain of the second P-type MOS transistor PM2 and a second N The drain of the MOS transistor NM2 is grounded to the ground of the follower unit.

In the self-biasing structure used in the present invention, the second P-type MOS transistor PM2 of the diode connection in the conventional self-biasing structure is released, and therefore, the first P-type MOS transistor PM1 and the second P-type MOS of the positive connection method In the wide input voltage range of the tube PM2, especially at high voltage, the channel modulation effect greatly reduces the current offset of the two branches of PM1 and PM2, so that Vx is approximately equal to Vy.

Embodiment 1

FIG. 4 is a structural diagram of a first embodiment of the present invention. The mirror unit includes a fourth P-type MOS transistor PM4 and a fifth P-type MOS transistor PM5,

The fourth P-type MOS transistor PM4 is connected to the power source Vdd as the first power input terminal In1 of the mirror unit, the gate thereof is connected to the drain thereof and is connected to the follower unit as the first of the mirror unit Output O1;

The fifth P-type MOS transistor PM5 source is connected to the power source Vdd as the second power source input terminal In2 of the mirror unit, the drain thereof is connected to the following unit, as the second output terminal O2 of the mirror unit;

The fourth P-type MOS transistor PM4 is gate-connected to the gate of the fifth P-type MOS transistor PM5, and is simultaneously connected to the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, and the third P The gate terminal of the MOS transistor PM3 serves as the output control terminal Ctr of the mirror unit.

The following unit includes a third N-type MOS transistor NM3, a fourth N-type MOS transistor NM4, and a fifth N-type MOS transistor NM5.

The drain of the third N-type MOS transistor NM3 is connected to the first output terminal O1 of the mirror unit, as the first input terminal In1 of the following unit, and the gate thereof is connected to the drain of the first P-type MOS transistor PM1 a drain of the first N-type MOS transistor NM1, as the third input terminal In3 of the following unit;

The drain of the fourth N-type MOS transistor NM4 is connected to the second output terminal O2 of the mirror unit, as the second input terminal In2 of the following unit, and the gate thereof is connected to the drain of the second P-type MOS transistor PM2 a drain of the pole and the second N-type MOS transistor NM2, as a fourth input terminal In4 of the follower unit, a source connected to a source of the third N-type MOS transistor NM3, and connected to the fifth a drain of the N-type MOS transistor NM5, a gate of the fifth N-type MOS transistor NM5 is connected to a drain of the fourth N-type MOS transistor NM4, and a source of the fifth N-type MOS transistor NM5 is grounded as a ground terminal of the follower unit .

In the above embodiment, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5 and the third N-type MOS transistor NM3, the fourth N-type MOS transistor NM4, and the fifth N-type MOS transistor NM5 form a novel self-bias. The fourth N-type MOS transistor NM4 and the fifth N-type MOS transistor NM5 form a parallel feedback voltage follower, which is different in structure from the conventional voltage follower: assuming that the fifth P-type MOS transistor PM5 is a current source bias, the following The device can adaptively draw more current through the gate feedback of the fifth N-type MOS transistor NM5, and the source-level output impedance is smaller, approximately 1/(gm _NM5 gm _NM4 ro _NM4 ), and Vc can better follow the voltage of Vb. Variety. The size of the circuit (ie, the width to length ratio of the MOS tube) is selected to be the same size as the third N-type MOS transistor NM3 and the fourth N-type MOS transistor NM4, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, and the first P-type The MOS tube PM1 and the second P-type MOS tube PM2 are the same size. Under the mirror image of the fourth P-type MOS transistor PM4 and the fifth P-type MOS transistor PM5, the current flowing through the third N-type MOS transistor NM3 and the fourth N-type MOS transistor NM4 is the same, and the current value thereof is determined by Va and Vb. The magnitude of the voltage determines that if the third N-type MOS transistor NM3 and the fourth N-type MOS transistor NM4 can be biased in the saturation region, Va=Vb can always be maintained, and the voltages of Va and Vb flow through the first P-type MOS. The current bias of the two branches of the tube PM1 and the second P-type MOS transistor PM2 is determined. The first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are mirror images of the fourth P-type MOS transistor PM4, so the current flowing through the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 is the same, Vx and Vy have the same voltage. Q1, Q2 and R1 determine the branch current, ie I=VTln(n)/R1, which determines the voltage of Va and Vb, that is, the current flowing through each branch is equal.

The above discussion is derived by the following formula:

Equation (2) and (3), the same as the third N-type MOS transistor NM3 and NM4 fourth N-MOS transistor dimensions, the same substrate, the _{_{V th (NM3) = V th}} (NM4). Also, because the same into a fourth P-type MOS transistor PM4 and PM5 fifth P-type MOS transistor structure of the image size, the same substrate, then _{_{I (PM4) = I (PM5}} ), i.e. _{_{I (NM3) = I (NM4}} ), Therefore V _ac =V _bc . For the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2, since the gate voltages of the two MOS transistors are the same, and V _a = V _b such that the drain terminals of the two MOS transistors have the same voltage, the two MOS transistors The source extreme voltage must be the same, ie V _x =V _y .

It should be noted that when Vdd changes over a wide voltage range, there is a certain imbalance in the existence of the channel modulation effect of the fourth P-type MOS transistor PM4 and the fifth P-type MOS transistor PM5, resulting in I _(PM4). There is a certain difference between I and _{PM (PM5)} . However, according to equations (2) and (3), the current difference between the two branches is reflected to the gate of the third N-type MOS transistor NM3 and the fourth N-type MOS transistor NM4. There is a weakening of the square root, so the difference in Vgs will be smaller, so that Va and Vb are almost the same.

The self-biasing structure of the present invention is itself a closed loop, similar to a conventional self-biasing structure. The structure has a stable working point degenerate state of "0", and it is necessary to start the circuit to deviate from the "0" degeneracy state. Once the startup is completed, although the structural loop is positive feedback, the bias currents determined by Q1, Q2, and R1 are substantially constant, that is, Va and Vb are substantially constant, and the current flowing in the loop is substantially constant, resulting in loop gain. If it is less than 1, another stable operating point can be reached, and the bias current of this stable operating point is determined by Q1, Q2 and R1.

In addition, the two-input pair of tubes NM3 and NM4 of the self-biasing structure of the present invention form a certain gain at the output control end, and the gain is expressed as gm _NM3/ gm _PM4 , similar to the action of the operational amplifier, and feedback through PM1 and PM2. Control so that Va = Vb. The current of the third P-type MOS transistor PM3 mirror is proportional to the absolute temperature, and the expression of Vbg is the same as the formula (1).

Embodiment 2

FIG. 5 is a structural diagram of Embodiment 2 of the present invention. The difference between this embodiment and the first embodiment is In the embodiment, the fifth N-type MOS transistor NM5 is split into a fifth N-type MOS transistor NM5 and a sixth N-type MOS transistor NM6 to ensure matching and symmetry of the circuit layout.

The mirror unit includes a fourth P-type MOS transistor PM4 and a fifth P-type MOS transistor PM5,

The following unit includes a third N-type MOS transistor NM3, a fourth N-type MOS transistor NM4, a fifth N-type MOS transistor NM5, and a sixth N-type MOS transistor NM6.

The drain of the third N-type MOS transistor NM3 is connected to the first output terminal O1 of the mirror unit, as the first input terminal In1 of the following unit, and the gate thereof is connected to the drain of the first P-type MOS transistor PM1 a drain of the first N-type MOS transistor NM1, a third input terminal In3 of the follower unit, a source connected to a drain of the sixth N-type MOS transistor NM6, the sixth N-type MOS a gate of the NM6 is connected to the drain of the fourth N-type MOS transistor NM4, and a source of the sixth N-type MOS transistor NM6 is grounded;

The drain of the fourth N-type MOS transistor NM4 is connected to the second output terminal O2 of the mirror unit, as the second input terminal In2 of the following unit, and the gate thereof is connected to the drain of the second P-type MOS transistor PM2 a drain of the pole and the second N-type MOS transistor NM2, as a fourth input terminal In4 of the follower unit, a source connected to a source of the third N-type MOS transistor NM3, and connected to the fifth The drain of the N-type MOS transistor NM5, The gate of the fifth N-type MOS transistor NM5 is connected to the drain of the fourth N-type MOS transistor NM4, and the source of the fifth N-type MOS transistor NM5 is grounded as the ground of the follower unit.

Embodiment 3

FIG. 6 is a structural diagram of a third embodiment of the present invention. The difference between this embodiment and the second embodiment is that the sixth P-type MOS transistor PM6, the seventh P-type MOS transistor PM7, the eighth P-type MOS transistor PM8, and the ninth P-type MOS transistor PM9 using the cascode constitute a current mirror. The fourth P-type MOS transistor PM4 and the fifth P-type MOS transistor PM5 are replaced to reduce the offset of the mirror current of the fourth P-type MOS transistor PM4 and the fifth P-type MOS transistor PM5.

The mirroring unit includes a sixth P-type MOS transistor PM6, a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, and a ninth P-type MOS transistor PM9.

The sixth P-type MOS transistor PM6 is connected to the power source Vdd as the first power input terminal In1 of the mirror unit, and has a gate connected to the drain thereof and connected to the source of the eighth P-type MOS transistor PM8. The gate of the eighth P-type MOS transistor PM8 is connected to its drain and is connected to the follower unit as the first output terminal O1 of the mirror unit;

The seventh P-type MOS transistor PM7 is connected to the power source Vdd as the second power input terminal In2 of the mirror unit, and the drain thereof is connected to the source of the ninth P-type MOS transistor PM9, the ninth P-type The gate of the MOS transistor PM9 is connected to the gate of the eighth P-type MOS transistor PM8, and the drain of the ninth P-type MOS transistor PM9 is connected to the follower unit as the second output terminal O2 of the mirroring unit;

The sixth P-type MOS transistor PM6 is gate-connected to the gate of the seventh P-type MOS transistor PM7, and is connected to the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, and the third P-type The gate terminal of the MOS transistor PM3 serves as the output control terminal Ctr of the mirror unit.

The following unit includes a third N-type MOS transistor NM3, a fourth N-type MOS transistor NM4, and a fifth N-type MOS Tube NM5 and sixth N-type MOS tube NM6,

Embodiment 4

FIG. 7 is a structural diagram of a fourth embodiment of the present invention. The difference between the embodiment and the above three embodiments is that the input end of the above three embodiments adopts an N-type MOS tube, and the input end of the embodiment adopts a P-type MOS tube, and correspondingly, the mirror unit adopts an N-type. The MOS transistor and the follower unit adopt a P-type MOS transistor. This structure can reduce the use of the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2, which reduces the use of the MOS transistor to a certain extent and reduces the chip cost. Specifically, its structure is:

The mirroring unit includes a seventh N-type MOS transistor NM7, an eighth N-type MOS transistor NM8, a ninth N-type MOS transistor NM9, and a fourteenth P-type MOS transistor PM14.

The seventh N-type MOS transistor NM7 is connected to the gate thereof and connected to the follower unit as the The first output end O1 of the mirror unit is grounded as the first input end In1 of the mirror unit,

The drain of the eighth N-type MOS transistor NM8 is connected to the follower unit as the second output terminal O2 of the mirror unit, the gate thereof is connected to the gate of the seventh N-type MOS transistor NM7, and the source thereof is grounded as a mirror image The second input of the unit, In2,

The gate of the ninth N-type MOS transistor NM9 is connected to the gate of the seventh N-type MOS transistor NM7 and the gate of the eighth N-type MOS transistor NM8, and the source thereof is grounded as a third input terminal In3 of the mirror unit. The drain is connected to the drain of the fourteenth P-type MOS transistor PM14, and the source of the fourteenth P-type MOS transistor PM14 is connected to the power source as the fourth input terminal In4 of the mirror unit, and the gate thereof is connected to the drain thereof. Connecting to the gate terminals of the first P-type MOS transistor PM1, the second P-type MOS transistor PM2, and the third P-type MOS transistor PM3 as the output control terminal Ctr of the mirroring unit;

The following unit includes a tenth P-type MOS transistor PM10, an eleventh P-type MOS transistor PM11, a twelfth P-type MOS transistor PM12, and a thirteenth P-type MOS transistor PM13,

The source of the tenth P-type MOS transistor PM10 is connected to the source of the eleventh P-type MOS transistor PM11 and is connected to the power source Vdd, and the drain of the tenth P-type MOS transistor PM10 is connected to the eleventh P-type MOS. The drain of the PM11 is connected to the source of the twelfth P-type MOS transistor PM12, and the gate of the twelfth P-type MOS transistor PM12 is connected to the drain of the first P-type MOS transistor PM1 and the first N-type MOS The drain of the tube NM1, as the third input terminal In3 of the following unit, the drain of the twelfth P-type MOS transistor PM12 is connected to the mirror unit as the first input terminal In1 of the following unit;

The drain of the eleventh P-type MOS transistor PM11 is connected to the source of the thirteenth P-type MOS transistor PM13, and the gate of the thirteenth P-type MOS transistor PM13 is connected to the drain of the second P-type MOS transistor PM2 and a drain of the second N-type MOS transistor NM2 as a fourth input terminal In4 of the following unit, the thirteenth P-type MOS transistor PM13 having a drain connected to the gate of the tenth P-type MOS transistor PM10 and Eleven P-type MOS tube PM11 gate, And connected to the mirror unit as the second input terminal In2 of the following unit.

The invention adopts a fourth P-type MOS tube PM4, a fifth P-type MOS tube PM5 and a third N-type MOS tube NM3, a fourth N-type MOS tube NM4, and a fifth N-type MOS tube NM5 to form a novel self-biasing structure. On the one hand, such a structure can be directly applied to a wide input voltage range, especially under high voltage input, on the other hand, it does not increase large power consumption and layout area, and reduces chip cost. Compared with the traditional self-biased structure and the bandgap reference structure of the op amp structure, the circuit greatly reduces the channel modulation effect, and the structure is relatively simple, that is, economical and practical. At the same time, the two input-to-tube external feedback circuits of the self-biasing structure can effectively control the bias voltages of the two output terminals to be almost equal. This technical point can also be applied to other structures similar to the bandgap reference circuit. Ensure that two equal output voltages of the same size are generated in the circuit.

Claims

A self-biased bandgap reference circuit with a wide input voltage range and high precision output, including a first P-type MOS transistor, a second P-type MOS transistor, and a third P-type MOS transistor connected to a power supply, and respectively connected to the a first N-type MOS transistor and a second N-type MOS transistor of a drain terminal of the first P-type MOS transistor and a drain terminal of the second P-type MOS transistor, wherein the first N-type MOS transistor is grounded through the first transistor The second N-type MOS transistor is connected to the second triode through a first resistor and grounded, and the third P-type MOS transistor gate is connected to the first P-type MOS transistor and the second P-type MOS transistor gate a drain terminal connected to the third transistor through a second resistor and grounded, wherein the circuit further comprises a self-biasing unit connected to the power source, the self-biasing unit comprising a mirror unit and a follow unit,

The first power input end and the second power input end of the mirroring unit are respectively connected to the power source, and the first output end and the second output end are respectively connected to the following unit, for generating two current value signals of the same size and outputting to The following control unit is connected to the gate terminals of the first P-type MOS transistor, the second P-type MOS transistor and the third P-type MOS transistor for controlling the first P-type MOS transistor and the second P-type a bias voltage of the gate end of the MOS transistor and the third P-type MOS transistor;

The first input end and the second input end of the following unit are respectively connected to the first output end and the second output end of the mirror unit, and the third input end of the follow unit is connected to the first P type MOS a drain of the tube and a drain of the first N-type MOS transistor, a fourth input terminal of the follower unit being connected to a drain of the second P-type MOS transistor and a drain of the second N-type MOS transistor, Ground the ground of the following unit.
A self-biased bandgap reference circuit with a wide input voltage range and a high precision output according to claim 1, wherein said mirror unit comprises a fourth P-type MOS transistor and a fifth P-type MOS transistor.

The fourth P-type MOS transistor source is connected to a power source as a first power input end of the mirror unit, and a gate thereof is connected to a drain thereof and connected to a follower unit as a first output end of the mirror unit;

The source of the fifth P-type MOS transistor is connected to a power source as a second power input end of the mirror unit. a drain connected to the follower unit as a second output of the mirror unit;

The fourth P-type MOS transistor gate is connected to the fifth P-type MOS transistor gate, and is simultaneously connected to the first P-type MOS transistor, the second P-type MOS transistor, and the third P-type MOS transistor The gate terminal serves as an output control terminal of the mirror unit.
A self-biased bandgap reference circuit for wide input voltage range and high precision output according to claim 1, wherein said mirror unit comprises a sixth P-type MOS transistor, a seventh P-type MOS transistor, and an eighth P Type MOS tube and ninth P type MOS tube,

The sixth P-type MOS transistor source is connected to the power source as a first power input terminal of the mirror unit, the gate thereof is connected to the drain thereof and is connected to the source of the eighth P-type MOS transistor, the eighth a gate of the P-type MOS transistor is connected to its drain and connected to the follower unit as a first output end of the mirror unit;

The seventh P-type MOS transistor source is connected to the power source as a second power input end of the mirror unit, the drain thereof is connected to the source of the ninth P-type MOS transistor, and the gate of the ninth P-type MOS transistor The pole is connected to the gate of the eighth P-type MOS transistor, and the drain of the ninth P-type MOS transistor is connected to the follower unit as a second output end of the mirror unit;

The sixth P-type MOS transistor gate is connected to the seventh P-type MOS transistor gate, and is connected to the gates of the first P-type MOS transistor, the second P-type MOS transistor, and the third P-type MOS transistor Extremely, as the output control end of the mirror unit.
A self-biased bandgap reference circuit for wide input voltage range and high precision output according to claim 1, wherein said following unit comprises a third N-type MOS transistor, a fourth N-type MOS transistor, and a fifth N Type MOS tube,

The drain of the third N-type MOS transistor is connected to the first output end of the mirror unit, as the first input end of the follower unit, the gate thereof is connected to the drain of the first P-type MOS transistor and the first N type MOS tube a drain as a third input of the following unit;

The fourth N-type MOS transistor drain is connected to the second output end of the mirror unit, as a second input end of the follow unit, the gate thereof is connected to the drain and the second of the second P-type MOS transistor a drain of the N-type MOS transistor, as a fourth input terminal of the follower unit, a source connected to a source of the third N-type MOS transistor and connected to a drain of the fifth N-type MOS transistor The fifth N-type MOS transistor gate is connected to the fourth N-type MOS transistor drain, and the fifth N-type MOS transistor source is grounded as the ground terminal of the follower unit.
A self-biased bandgap reference circuit for wide input voltage range and high precision output according to claim 1, wherein said following unit comprises a third N-type MOS transistor, a fourth N-type MOS transistor, and a fifth N Type MOS tube and sixth N type MOS tube,

The drain of the third N-type MOS transistor is connected to the first output end of the mirror unit, as the first input end of the follower unit, the gate thereof is connected to the drain of the first P-type MOS transistor and the first a drain of the N-type MOS transistor as a third input terminal of the follower unit, a source thereof is connected to a drain of the sixth N-type MOS transistor, and a gate of the sixth N-type MOS transistor is connected to the a drain of the fourth N-type MOS transistor, and a source of the sixth N-type MOS transistor is grounded;

The fourth N-type MOS transistor drain is connected to the second output end of the mirror unit, as a second input end of the follow unit, the gate thereof is connected to the drain and the second of the second P-type MOS transistor a drain of the N-type MOS transistor, as a fourth input terminal of the follower unit, a source connected to a source of the third N-type MOS transistor and connected to a drain of the fifth N-type MOS transistor The fifth N-type MOS transistor gate is connected to the fourth N-type MOS transistor drain, and the fifth N-type MOS transistor source is grounded as the ground terminal of the follower unit.
A self-biased bandgap reference circuit for wide input voltage range and high precision output according to claim 1, wherein said mirror unit comprises a seventh N-type MOS transistor, an eighth N-type MOS transistor, and a ninth N Type MOS tube and fourteenth P type MOS tube,

The seventh N-type MOS transistor has a drain connected to the gate thereof, and is connected to the follower unit as a first output end of the mirror unit, and a source thereof is grounded as a first input end of the mirror unit.

The eighth N-type MOS transistor drain is connected to the follower unit as a second output end of the mirror unit, the gate thereof is connected to the seventh N-type MOS transistor gate, and the source is grounded as a mirror unit Two inputs,

The ninth N-type MOS transistor gate is connected to the seventh N-type MOS transistor gate and the eighth N-type MOS transistor gate, and the source thereof is grounded, as a third input end of the mirror unit, and the drain connection thereof Up to the drain of the fourteenth P-type MOS transistor, the source of the fourteenth P-type MOS transistor is connected to the power source as a fourth input terminal of the mirror unit, and the gate thereof is connected to the drain thereof and connected to the first P-type MOS a gate end of the tube, the second P-type MOS transistor and the third P-type MOS transistor as an output control end of the mirror unit;

The following unit includes a tenth P-type MOS transistor, an eleventh P-type MOS transistor, a twelfth P-type MOS transistor, and a thirteenth P-type MOS transistor.

The tenth P-type MOS transistor source is connected to the eleventh P-type MOS transistor source and is connected to a power source, and the tenth P-type MOS transistor drain is connected to the eleventh P-type MOSFET drain Connected to the twelfth P-type MOS transistor source, the twelfth P-type MOS transistor gate is connected to the drain of the first P-type MOS transistor and the drain of the first N-type MOS transistor as the a third input end of the following unit, the twelfth P-type MOS transistor drain is connected to the mirror unit as a first input end of the following unit;

The eleventh P-type MOS transistor drain is connected to the thirteenth P-type MOS transistor source, and the thirteenth P-type MOS transistor gate is connected to the drain of the second P-type MOS transistor and the second N-type a drain of the MOS transistor as a fourth input terminal of the follower unit, the thirteenth P-type MOS transistor drain is connected to the tenth P-type MOSFET gate and the eleventh P-type MOSFET gate And connected to the mirroring unit as the second input of the following unit.