WO2016182205A2

WO2016182205A2 - Lighting device and driving circuit therefor

Info

Publication number: WO2016182205A2
Application number: PCT/KR2016/003418
Authority: WO
Inventors: 이주현; 유순건; 김해봉; 구만원; 김성환; 하주완; 홍주표; 이세원; 정병호
Original assignee: 주식회사 실리콘웍스
Priority date: 2015-05-13
Filing date: 2016-04-01
Publication date: 2016-11-17
Also published as: WO2016182205A3

Abstract

The present invention provides a lighting device. The lighting device comprises a driving circuit therefor, which provides a switching driving signal of a converter, wherein the driving circuit comprises: an end time point generation unit for generating a control pulse which expresses an end time point of a minimum on-time according to a frequency change of an oscillation signal used to generate the driving signal, within a turn-on interval of the converter; and a minimum on-time determination unit for providing, within a turn-on interval of the converter, a minimum on-time pulse which defines the minimum on-time including a time from a turn-on start time point of the converter to the end time point, using the control pulse.

Description

Lighting device and its driving circuit

The present invention relates to a lighting device, and more particularly, to a lighting device that can be used as a lighting lamp for a vehicle such as a rear combination lamp (REAR COMBINATION LAMP) and a driving circuit of the lighting device.

In general, a vehicle is equipped with a lighting device for a variety of applications indoors or outdoors. An example of a lighting device may be a rear combination lamp installed at both rear of the vehicle.

The rear combination lamp includes a direction indicator lamp, a brake lamp, a tail lamp, a reversing lamp, and the like, and is used as a means for informing the driver of another vehicle located behind the vehicle to inform the driving intention or driving condition of the vehicle.

Recently, a lighting device using a high brightness light emitting diode (LED) has been developed, and a rear combination lamp employing LED as a lighting device for a vehicle has been developed. The rear combination lamp may be configured in various designs as the LED is used as a light source, and the number of LEDs employed in the rear combination lamp of various designs is gradually increasing.

The lighting device of a vehicle such as the rear combination lamp needs to be stably operated, and can be developed to save power and to be implemented with a small number of components.

Lighting devices using LEDs can be configured to provide an output voltage to a plurality of LED channels. When the number of LED channels emitting light changes, a load amount change occurs in the lighting device, and the output voltage of the lighting device provided to the LED channels may become temporarily unstable at the time when the load amount change occurs.

In response to the change in the output voltage, the lighting device may compensate for the change in the output voltage according to the load change and stabilize the output voltage by the compensation of the output voltage using the feedback voltage and the linear regulation using the sensing signal.

However, a general lighting device spends a lot of time compensating and stabilizing the output voltage corresponding to the load change described above. If it takes a long time to stabilize the output voltage, the change in the output voltage may affect the illuminance.

Therefore, there is a need to improve the lighting device using the LED so that the output voltage can be stabilized even when the load changes.

In addition, the lighting apparatus performs power conversion using a converter including a switching element and provides an output voltage generated as a result of the power conversion. The converter of the lighting device may for example be configured as a buck converter.

The converter consumes a lot of power at the switching point for power conversion, which may cause electro magnetic interference (EMI). EMI generated by the converter may be reduced because it may affect the operation of the lighting device. Therefore, there is a need for the development of a drive technology of a converter in which EMI can be reduced.

In addition, when the duty of the driving signal for driving the converter to provide the output voltage is 50% or more, unstable sub-harmonic oscillation may occur in the converter of the lighting device. The unstable sub-harmony oscillation may act as an element that destabilizes the operation of the lighting device.

The unstable sub harmony oscillation of the converter may be controlled by SLOP compensation of a driving signal for driving the converter. The slope compensation of the driving signal means controlling the slopes of the rising edge and the falling edge of the driving signal. The slope compensation is implemented by a slope compensation voltage charged with a fixed value of current.

In the buck converter, a variable range of the switching frequency may be large, and for example, the variable range may be set from 100 KHz to 1 MHz. The switching frequency of the buck converter may be determined by a driving signal provided from a driving circuit. If the variable range of the switching frequency is large, the value of the inductance of the buck converter must also be set for the variable switching frequency. However, if the value of the inductance of the buck converter is varied, the value of the slope compensation voltage for controlling the sub harmony oscillation should be changed.

In general, the value of the slope compensation voltage is provided based on a fixed value of current as described above. Therefore, the drive circuit needs to externally receive a voltage or a current for changing the slope compensation voltage in accordance with a variable switching frequency, and a connection terminal for receiving an external current or voltage may be additionally required in the drive circuit. Can be. In addition, there is a problem that an additional circuit configuration including many components is required to generate a voltage or current for changing the slope compensation voltage.

In addition, the LED channels of the lighting device are configured to emit light at different times for power concentration and consequent EMI cancellation, as described above. In addition, the LED current of each LED channel should be guaranteed to be kept above a certain amount for normal light emission.

In order to ensure that the LED current of each LED channel is maintained above a certain amount, the lighting device detects the lowest voltage among the feedback voltages of each LED channel as the detection voltage, compares the detection voltage with a fixed level of reference voltage, The output voltage can be controlled by the comparison result. As described above, a technique for controlling the output voltage of the lighting device has been disclosed in Korean Patent No. 10-0941509.

The bias voltage of the LED channels may vary depending on the characteristic variation. In one example, if the bias voltages of the LED channels are all different, the lowest feedback voltage of the LED channels may change each time the LED channels emit light.

Therefore, the output voltage produced by the converter can change from time to time. As such, when the output voltage is unstable, an audible noise corresponding to a change in the output change in the converter may occur.

In addition, when a large number of LED channels are configured in the lighting device, it is difficult to cover all the LED channels with one driving circuit. Therefore, in order to control the light emission of a large number of LED channels, a plurality of driving circuits need to be configured. In this case, the driving circuits may be implemented as a multi chip.

When the driving circuits are implemented as multi-chips, there is a need to share components such as a converter to reduce the number of components and the manufacturing cost.

As described above, in the case where the driving circuits are composed of multi-chips corresponding to a large number of LED channels, a proposal of a lighting device that can share a component such as a converter in order to eliminate the need to reduce the number of components and manufacturing cost Required.

In addition, the converter switched by the drive signal must ensure a minimum on time and a minimum off time. The minimum on time means the smallest time that the switch of the converter can turn on, and the minimum off time means the smallest time that the switch of the converter can turn off. In general, the minimum on time for turning on the converter and the minimum off time for turning off the converter are fixed.

However, when the switching frequency of the converter is changed, ensuring an effective duty of the drive signal for controlling dimming can be difficult due to a fixed minimum on time. More specifically, as the switching frequency of the converter increases, the fixed minimum on time takes up a larger portion of the turn on period of the converter. As a result, it becomes increasingly difficult to ensure sufficient duty of the drive signal for use in dimming.

In addition, when the switching frequency of the converter is changed, it may be difficult to secure an effective duty of the drive signal for controlling the dimming by a fixed minimum off time. More specifically, as the switching frequency of the converter increases, the minimum off time takes up more and more in one period of the drive signal. As a result, it becomes increasingly difficult to ensure sufficient duty of the drive signal for use in dimming.

Therefore, there is a need for a method of securing an effective duty of a drive signal for controlling dimming of an LED lamp, regardless of the switching frequency change of the converter.

On the other hand, the converter providing the output voltage includes a power switch to repeatedly switch in response to a pulse width modulation (PWM) signal, performs a power conversion by the switching operation of the power switch, the output voltage generated by the power conversion To the LED channel.

However, since repetitive switching of the power switch involves a sudden voltage change, it may act as a main cause of generating EMI (Electro Magnetic Interference). Therefore, there is a need for a technique capable of reducing EMI due to repetitive switching.

An object of the present invention is to stably maintain an output voltage provided to loads in response to a load change of lighting loads such as LEDs for stable operation of the lighting device.

The present invention quickly compensates the on time of a drive signal for generating an output voltage at a point of load change of lighting loads included in a lighting device to a predetermined value, thereby stabilizing and stably output voltage in response to a load change. For other purposes.

It is another object of the present invention to reduce EMI generated in the power conversion process for generating an output voltage to be provided to the lighting loads of the lighting device.

The present invention is to control the drive signal provided for the power conversion of the converter in the lighting device to have a distributed frequency applied to the scattering spectrum to distribute the switching time of the converter and solve the problem that the power consumption is concentrated at the switching time of the converter and EMI Another aim is to reduce the

It is another object of the present invention to provide a slope compensation voltage in response to a variable switching frequency for power conversion of a converter in a lighting device, thereby controlling sub-harmonic oscillations that may occur depending on the duty state of the output voltage. .

According to the present invention, when a switching frequency for power conversion of a converter in a lighting device is changed, the switching frequency is linked to a change in current or voltage corresponding to a change in switching frequency of an oscillating circuit that provides a PWM signal used to generate a drive signal. It is another object of the present invention to provide a slope compensation voltage corresponding to a variable of.

The present invention can be simply implemented by the interlocking structure of the internal drive circuit of the chip configuration without the need to configure a separate terminal or components to actively respond to the switching frequency change for the power conversion of the converter in the lighting device Is another purpose.

The present invention raises the reference voltage when the feedback voltage of the minimum level among the feedback voltages corresponding to the bias voltages of each LED channel is lower than the preset level, and uses the elevated reference voltage to generate an output voltage generated by the converter. It is another object to stabilize.

The present invention generates a reference voltage by charging and discharging according to the feedback voltage of the minimum level among the feedback voltages corresponding to the bias voltages of the respective LED channels, and generates in the converter by regulating the output voltage using the reference voltage being charged and discharged. Another aim is to stabilize the output voltage.

Another object of the present invention is to eliminate audible noise that may occur in a converter by an unstable output voltage by controlling an output voltage unstable due to a difference in bias voltages of respective LED channels.

Another object of the present invention is to reduce the number of components and the manufacturing cost by sharing components such as a converter when a plurality of driving circuits are configured to correspond to a large number of LED channels.

Another object of the present invention is to drive LED channels using a single converter when a plurality of driving circuits are configured to correspond to a large number of LED channels.

According to the present invention, when a plurality of driving circuits are configured to correspond to a large number of LED channels, the lowest feedback voltage for LED channels corresponding to the respective driving circuits is shared, and the lowest feedback voltage for all LED channels is provided. It is another object to detect and control the output voltage provided to the LED channels using the lowest feedback voltage for all the LED channels.

Another object of the present invention is to secure an effective duty of a drive signal for controlling dimming of an LED lamp even when the switching frequency of the converter changes.

Another object of the present invention is to secure an effective duty of a driving signal for dimming control regardless of the change in the switching frequency of the converter by changing the minimum on time corresponding to the change in the switching frequency of the converter.

Another object of the present invention is to secure an effective duty of a driving signal for dimming control regardless of a change in the switching frequency of the converter by changing the minimum off time in response to a change in the switching frequency of the converter.

Another object of the present invention is to reduce EMI by controlling the rise and fall times of a drive signal for driving a power switch of a converter.

Another object of the present invention is to precisely control the switching time by adjusting the rise and fall times of the driving signal by using the control current.

The driving circuit of the lighting apparatus for providing a drive signal to the converter of the present invention is a control that expresses the end time of the minimum on-time following the frequency change of the oscillation signal used to generate the drive signal within the turn-on period of the converter. An end point generation unit generating a pulse; And a minimum on-time determining unit configured to provide a minimum on-time pulse that defines the minimum on-time including a turn-on start point of the converter to the end point of time using the control pulse within the turn-on period of the converter. It is characterized by including.

The driving circuit of the lighting apparatus for providing a drive signal to the converter of the present invention, which represents the start time of the minimum off time in accordance with the frequency change of the oscillation signal used to generate the drive signal within the turn-off period of the converter. A start point generation unit generating a control pulse; And a minimum off time determination unit configured to provide a minimum off time pulse that defines the minimum off time including the control point from the start time to the turn off end time of the converter in the turn off period of the converter. Characterized by including.

The driving circuit of the lighting apparatus for providing a driving signal to the converter of the present invention comprises a first time representing an end point of the minimum on-time following a frequency change of the oscillation signal used to generate the driving signal within a turn-on period of the converter. An end point generation unit generating one control pulse; A minimum on-time determining unit configured to provide a minimum on-time pulse that defines the minimum on-time including a turn-on start point of the converter to the end point of the converter using the first control pulse within the turn-on period of the converter; A start point generation unit generating a second control pulse representing a start point of a minimum off time according to a frequency change of the oscillation signal used to generate the driving signal within a turn-off period of the converter; And a minimum off time for providing a minimum off time pulse that defines the minimum off time that includes the second control pulse within the turn off period of the converter, from the start time to the turn off end time of the converter. Determination unit; characterized in that it comprises a.

A drive circuit of the lighting apparatus of the present invention includes a control current generation circuit for generating a control current; And a gate driver configured to receive the control current, generate a drive signal having the control current in response to a PWM signal, and drive a power switch using the drive signal.

Lighting device of the present invention, the LED module; A converter for regulating an output voltage provided to the LED module; And a driving circuit generating a driving signal having a control current corresponding to the PWM signal, and controlling the converter through the driving signal.

The driving circuit of the lighting apparatus of the present invention, the current generating unit for generating a current; A current adjusting unit having a current mirror structure with respect to the current generating unit, generating a first control current and a second control current using the current, and providing the first control current and the second control current; And receiving the first control current and the second control current, operating a pull up and pull down in response to a PWM signal, and forming a first current path and a second current path in response to the pull up and pull down operations. And a gate driver configured to provide a control current and the second control current to the power switch.

The present invention has the effect of providing an output voltage to the lighting loads using the LED, and can quickly maintain the output voltage by performing a compensation corresponding to the load change of the loads.

In addition, the present invention provides an output voltage to the lighting loads by the power conversion using a drive signal, and stabilizes the output voltage in a short time by quickly compensating the on time of the drive signal to a predetermined value in response to the load change of the load It is effective to keep it stable.

According to the present invention, power conversion for providing an output voltage may be performed using a drive signal having a distributed frequency, and the switching time of the converter for power conversion is distributed by the distributed frequency of the drive signal, Concentration can be reduced and EMI can be reduced.

According to the present invention, it is possible to control the sub-harmonic oscillation that may occur according to the state of the voltage output from the converter of the lighting device, and to change the slope compensation voltage that is actively changed even when the switching frequency for power conversion of the converter is varied. The sub harmony oscillation can be controlled effectively.

According to the present invention, since the configuration of the drive circuit for actively responding to the switching frequency change for power conversion of the converter of the lighting device can be simply implemented by the internal interlocking structure, the number of parts and the manufacturing cost can be reduced. .

According to the present invention, by changing the reference voltage according to the change of the minimum level of the feedback voltage, it is possible to stabilize the output voltage generated in the converter by using the changed reference voltage, and can eliminate audible noise caused by the unstable output voltage. .

According to the present invention, the output voltage generated in the converter is stabilized by generating a reference voltage by charging and discharging according to a change in the feedback voltage of the minimum level, and regulating the output voltage by using the reference voltage generated by charging and discharging. Can eliminate the audible noise caused by unstable output voltage.

According to the present invention, a plurality of driving circuits may be configured to drive circuits corresponding to a large number of LED channels, and components such as a converter may be shared, thereby reducing the number of components and the manufacturing cost.

According to the present invention, the LED channels can be driven using a single converter corresponding to a large number of LED channels, thereby reducing the number of components and the manufacturing cost.

According to the present invention, the lowest feedback voltage for LED channels corresponding to the respective driving circuits is shared, the lowest feedback voltage for all LED channels is detected, and the lowest feedback voltage for all LED channels is detected. Can be used to control the output voltage provided to the LED channels.

According to the present invention, even if the switching frequency of the converter changes, the corrected minimum on time or corrected minimum off time can be applied, thereby ensuring an effective duty for controlling the dimming of the LED lamp.

According to the present invention, the minimum on-time is corrected in response to a change in the switching frequency of the converter, so that the converter can be switched while ensuring an effective duty even when the switching frequency of the converter changes.

According to the present invention, the minimum off time is corrected in response to a change in the switching frequency of the converter, so that the converter can be switched while ensuring an effective duty even if the switching frequency of the converter changes.

The present invention generates a drive signal having a constant control current corresponding to the PWM signal, and regulates the output voltage of the converter through the drive signal, thereby reducing EMI (Electro Magnetic Interference) that may be caused by the repetitive switching of the power switch. have.

The present invention can control the rise and fall time of the driving signal through the control current, thereby accurately controlling the switching time of the power switch regardless of the output impedance variation of the gate driver. Therefore, the present invention can improve the EMI characteristics caused by the switching of the power switch.

1 is a view for explaining embodiments of the lighting device of the present invention.

FIG. 2 is a detailed circuit diagram corresponding to FIG. 1 for explaining the first embodiment of the present invention. FIG.

3 is a waveform diagram illustrating an operation of a general lighting device.

4 is a waveform diagram illustrating the operation of the first embodiment of FIG. 2;

5 is a waveform diagram illustrating that the center frequency Fc of a drive signal is varied.

6 is a waveform diagram illustrating the bandwidth of a frequency modulated waveform of a drive signal.

7 is a circuit diagram for explaining a second embodiment of the present invention.

8 is a timing diagram illustrating that a PWM signal is adjusted according to the embodiment of FIG. 7.

9 is a waveform diagram illustrating a frequency dithered drive signal.

10 is a circuit diagram for explaining a third embodiment of the present invention.

11 is a graph illustrating the slope compensation voltage according to the third embodiment.

12 is a circuit diagram for explaining a fourth embodiment of the present invention.

FIG. 13 is a circuit diagram illustrating the reference voltage generation circuit of FIG. 12. FIG.

14 is a waveform diagram of voltages of the reference voltage generation circuit of FIG.

15 is a block diagram for explaining a fifth embodiment of the present invention.

FIG. 16 is a circuit diagram illustrating linear regulators and a detection voltage generation circuit of the master driving circuit and the slave driving circuit of FIG. 15. FIG.

Fig. 17 is a circuit diagram for explaining the sixth embodiment of the present invention.

18 is a waveform diagram illustrating the operation of the embodiment of FIG. 17;

19 is a graph illustrating a minimum on time versus frequency change according to the embodiment of FIG. 17.

20 is a circuit diagram for explaining the seventh embodiment of the present invention.

21 is a waveform diagram for explaining the operation of the embodiment of FIG. 20;

22 is a graph illustrating a minimum off time versus frequency change according to the embodiment of FIG. 20.

FIG. 23 is a circuit diagram illustrating an embodiment of the drive circuit of FIG. 1.

24 is a timing diagram for explaining the operation of FIG. 23.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention. The terms used in the present specification and claims are not to be construed as being limited to ordinary or dictionary meanings, but should be interpreted as meanings and concepts corresponding to the technical matters of the present invention.

The embodiments described in the specification and the configuration shown in the drawings are preferred embodiments of the present invention, and do not represent all of the technical idea of the present invention, various equivalents and modifications that can replace them at the time of the present application are There may be.

1 is a view for explaining embodiments of the present invention. Referring to FIG. 1, the lighting device includes a converter 10 and a driving circuit 20. The lighting device may include a vehicle controller 30, a path unit 40, and an LED lamp 50. In the above configuration, the driving circuit 20 may be implemented as a one chip.

The LED lamp 50 may be configured for a vehicle, and as a specific example, rear combination lamps installed at both rear sides of the vehicle may be applied. The LED lamp 50 is an example of a light source used as a load, and a light source using various optical elements may be used as a load.

The LED lamp 50 may include a plurality of LED channels CH1 to CH8, each LED channel CH1 to CH8 may include one or more LEDs, and the plurality of LED channels CH1 to CH8 may be configured in parallel. have.

FIG. 1 illustrates that one driving circuit 20 drives a plurality of LED channels CH1 to CH8 included in the LED lamp 50. When the LED lamp 50 is a rear combination lamp, the LED lamp 50 may be classified into a type in which the LED channels are configured only in the vehicle body and a type in which the LED channels are distributed in the doors of the vehicle body and the trunk. The LED lamp 50 of FIG. 1 may be defined as including LED channels configured in various types without being limited to a specific type. The current of each LED channel CH1 to CH8 is represented by " ICH1 to ICH8. &Quot;

The vehicle controller 30 may be configured to include a micro controller unit (MCU) 32, the MCU 32 is interlocked with the main MCU or the main MCU to provide a variety of control signals for driving the vehicle and to drive the vehicle. It can be understood as an auxiliary MCU that provides a control signal auxiliary to perform some necessary functions.

The vehicle controller 30 of FIG. 1 controls the battery voltage VB to be transmitted to the converter 10 in response to the direction indication signal T / S of the MCU 32, and in response to the rapid braking signal ESS. The voltage VB is controlled to be transmitted to the converter 10 and the driving circuit 20. Here, the battery voltage VB exemplifies a constant voltage source and may be replaced with various constant voltage sources. In this case, the battery voltage VB transmitted to the driving circuit 20 in response to the rapid braking signal ESS may be defined as a dim signal DIM. The direction indication signal T / S and the sudden braking signal ESS are examples of a control signal provided from the MCU 32. However, the present invention is not limited thereto and may be configured to provide a voltage corresponding to various control signals for driving the LED lamp 50 to at least one of the converter 10 and the driving circuit 20 according to the needs of the manufacturer. .

The path part 40 may be configured between the vehicle control part 30, the converter 10, and the driving circuit 20. The path unit 40 includes paths through which the battery voltage VB is provided to the converter 10 and the driving circuit 20, and each path is exemplarily represented by diodes.

More specifically, the path unit 40 may include paths D1 and D2 through which the battery voltage VB is transmitted to the converter 10 and paths D3 through which the dim signal DIM is transmitted to the driving circuit 20. Include. When the direction indication signal T / S is activated, the battery voltage VB is transmitted to the converter 10 through the path D1. When the rapid braking signal ESS is activated, the battery voltage VB is transmitted to the converter 10 through the path D2, and the battery voltage VB is the driving circuit as the dim signal DIM through the path D3. 20 is passed. In response to the activation of the rapid braking signal ESS, the activated dim signal DIM is input to the driving circuit 20. For example, the path D3 may include a circuit for outputting a dim signal DIM having a logic level corresponding to the battery voltage VB. The battery voltage VB transferred from the path part 40 to the converter 10 may be defined as an input voltage VIN.

The converter 10 generates the output voltage VOUT and the internal voltage VDIN using the input voltage VIN, supplies the output voltage VOUT to the LED lamp 50, and drives the internal voltage VDIN into a driving circuit. It supplies to (20). For example, the converter 10 may use various power conversion circuits such as a buck converter or a flyback converter.

The driving circuit 20 is configured to perform sensing and control of the converter 10 and the LED lamp 50.

The driving circuit 20 may receive the internal voltage VDIN and the sensing signal SEN from the converter 10 and provide the driving signal GATE to the converter 10. Herein, the internal voltage VDIN is a voltage for the operation of the controller 20, and the sensing signal SEN determines the level of the input voltage VIN, or the operating state or the output voltage VOUT state of the converter 10. Is a voltage for directly or indirectly sensing the driving signal, and the driving signal GATE is a signal used for a switching operation for power conversion of the converter 10 and may be provided as a pulse width modulation (PWM) signal. .

In addition, the driving circuit 20 may include regulation resistors R1 to linear regulation of the feedback voltages FB1 to FB8 of the LED channels CH1 to CH8 and the LED channels CH1 to CH8 of the LED lamp 50. The bin voltage BIN applied to the regulation voltages RCH1 to RCH8 applied to R8 and the bin resistor RBIN for controlling the dimming of all the LED channels CH1 to CH8 of the LED lamp 50 is determined. Can be received.

Here, the bin resistor RBIN may be defined as a load current control resistor acting on all of the LED channels CH1 to CH8 serving as loads, and the bin voltage BIN applied to the bin resistor RBIN is a load amount change. It can be used to determine the timing and can be defined as the load current control voltage.

More specifically, each of the LED channels CH1 to CH8 may be configured to emit light at different times for load distribution, and the empty voltage RB of the empty resistor RBIN at the time at which each of the LED channels CH1 to CH8 emits light. BIN) can be changed. For example, the bin voltage (BIN) of one LED channel emitting light is higher than that of all LED channels being extinguished, and the bin voltage of two LED channels emitting light than one LED channel emitting light ( BIN) is high. The time point at which the empty voltage BIN changes may be determined as the time point at which the load amount changes.

As a result, the driving circuit 20 may determine the load change time point using the empty voltage BIN and generate a control voltage V _N corresponding to the load amount after the load change time point. The control voltage V _N may be generated corresponding to a preset value, and a detailed description thereof will be described later with reference to the control voltage providing circuit 230.

1, the converter 10 provides the output voltage VOUT to the LED channels CH1 to CH8 serving as loads by using the driving signal GATE.

Hereinafter, a detailed configuration of the converter 10 and the driving circuit 20 constituted by the embodiment of the present invention will be described with reference to FIG.

The converter 10 includes a switching element Qb, the input voltage VIN is transmitted to the switching element Qb through the resistor Rb, and the voltage across the resistor Rb is sensed by the amplifier 110. The signal is output as the sensing signal SEN. The switching element Qb may be composed of an NMOS transistor, and a FET may be used. In addition, the inductor Lb and the capacitor Cb are connected in series with the switching element Qb, the diode Db is connected in parallel between the switching element Qb and the inductor L, and the diode Db is The current is configured to flow in the reverse direction to the current flow provided from the switching element Qb.

The converter 10 performs power conversion by periodically turning on and off the switching element Qb, and the turning on and off of the switching element Qb may be determined by the driving signal GATE.

When the switching element Qb is turned on, a current loop including the switching element Qb, the inductor Lb, and the capacitor Cb is formed, a current flows through the inductor Lb, and energy is accumulated. Flowing increases through the capacitor (Cb). At this time, the LED channels CH1 to CH8 serving as loads are connected in parallel with the capacitor Cb and are supplied with an increasing current, such as the capacitor Cb.

When the switching element Qb is turned off, a current loop including a diode Db, an inductor Lb, and a capacitor Cb is formed, and an inductor current which is energy accumulated in the inductor Lb is a capacitor. It is supplied to (Cb). In this case, the inductor current gradually decreases after the turn-off time of the switching element Qb, and the LED channels CH1 to CH8 connected in parallel with the capacitor Cb also receive a gradually decreasing current.

In the converter 10, the voltage accumulated and output in the capacitor Cb is the output voltage VOUT and is equal to the voltage applied to the LED channels LED1 to LED8.

Meanwhile, the driving circuit 20 provides a control voltage V _N corresponding to the load amount changed for each load amount change time point of the LED channels CH1 to CH8, and adjusts the voltage V _NC using the control voltage V _N. ) And provide a drive signal (GATE) compensated for the load change by having an On Time corresponding to the regulated voltage (V _NC ) to the converter 10. Further, the driving circuit 20 for generating a detection voltage (V _D) corresponding to the minimum voltage of the LED channels of the feedback voltage (CH1 ~ CH8) (FB1 ~ FB8), and the detection voltage (V _D) The compensation voltage Vc may be generated. Then, the driving circuit 20 is combined with the compensation voltage (Vc) to a control voltage (V _N) may generate a control voltage (V _N).

As described above, the feedback voltages FB1 to FB8 are voltages applied to the linear regulators 201 to 208. The drive circuit 20 includes linear regulators 201-208 and feeds back to monitor whether the output voltage VOUT maintains a minimum voltage above which the LED channels CH1-CH8 maintain illumination normally. The voltages FB1 to FB8 are received, and the received feedback voltages FB1 to FB8 are provided to the detection voltage generation circuit 220 inside the driving circuit 20.

The linear regulators 201 to 208 are configured between the regulation resistors R1 to R8 and the LED channels CH1 to CH8, respectively. The linear regulator 201 includes a comparator 211 and an NMOS transistor M1. The comparator 211 compares the regulation voltage RCH1 applied to the regulation resistor R1 with a preset reference voltage VREF1, and the NMOS transistor M1 corresponds to an LED channel (eg, a voltage output from the comparator 211). Controls the current flowing between LED1) and regulation resistor (R1). The linear regulators 202 to 208 also include comparators 212 to 218 and NMOS transistors M2 to M8, similarly to the linear regulator 201.

The linear regulators 201 to 208 control a current flowing through the LED channels CH1 to CH8 in response to a result of comparing the regulation voltages RCH1 to RCH8 and the reference voltage VREF1, respectively. Do this. By the linear regulation operation, the amount of current in the LED channels CH1 to CH8 may be limited by the reference voltage VREF1.

1 or 2, LED channels CH1 to CH8, linear regulators 201 to 208, comparators 211 to 218, NMOS transistors M1 to M8, regulation resistors R1 to R8, Some of the regulation voltages RCH1 to RCH8 and the feedback voltages FB1 to FB8 are not shown for simplicity.

The driving circuit 20 further includes a detection voltage generating circuit 220, a control voltage providing circuit 230, a load change detection circuit 232, and a driving signal providing circuit as well as the linear regulators 201 to 208 described above. .

The detection voltage generation circuit 220 detects a feedback voltage having a minimum value among the feedback voltages FB1 to FB8, and provides a feedback voltage having a minimum value as the detection voltage V _D.

The load amount change detection circuit 232 detects a load amount change time point using the empty voltage BIN. The load change detection circuit 232 may not only detect a load change time point, but also provide the control voltage providing circuit 230 with a digital value N corresponding to the load after the load change time when the empty voltage BIN changes. .

The empty voltage BIN may change in level at a load change point at which the number of LED channels CH1 to CH8 emitting light is changed. For example, the load change detection circuit 232 may output a binary code? 0000 "when all the LED channels CH1 to CH8 are extinguished, and a point in time at which the number of the LED channels CH1 to CH8 emits light increases. The digital value N represented by the binary code can be increased by 1 bit, and the digital value N is decreased by 1 bit when the number of LED channels CH1 to CH8 to emit light decreases. can do.

That is, when the number of LED channels CH1 to CH8 that emit light is increased, the digital value N is (0000) ₂ , (0001) ₂ , (0010) ₂ , (0011) ₂ , (0100) ₂ , ( 0101) ₂ , (0110) ₂ , (0111) ₂ , (1000) ₂ may be sequentially increased and output. On the contrary, when the number of LED channels CH1 to CH8 that emit light decreases, the digital value N is equal to (1000) ₂ , (0111) ₂ , (0110) ₂ , (0101) ₂ , (0100) ₂ , (0011) ₂ , (0010) ₂ , (0001) ₂ , (0000) ₂ may be sequentially reduced to the output.

For example, when the LED channels CH1 to CH8 are all extinguished and one is changed to a light emitting state, the load change detection circuit 232 detects a load change time point by a change in the empty voltage BIN. . The digital value N corresponding to the state where all the LED channels CH1 to CH8 are extinguished is (0000) ₂ , and the digital value N corresponding to the state where one of the LED channels CH1 to CH8 emits light. If (0001) ₂ , the load amount change detection circuit 232 changes the digital value N from (0000) ₂ to (0001) ₂ and outputs it.

The control voltage providing circuit 230 outputs a control voltage V _N corresponding to the digital value N. When the digital value N increases, the control voltage providing circuit 230 outputs a control voltage V _N of an increased level. When the value N decreases, the control voltage V _N of the reduced level is output. For example, when the digital value N is (0001) ₂ rather than (0000) ₂ , the control voltage providing circuit 230 outputs a high level control voltage V _N. As described above, the control voltage V _N may be determined by the digital value N input to the control voltage providing circuit 230, and the control voltage providing circuit 230 may control the control voltage corresponding to the digital value N. FIG. It may be configured as a digital-to-analog converter that outputs (V _N ).

Meanwhile, the driving signal providing circuit generates a compensation voltage Vc corresponding to the detection voltage V _D , generates a control voltage V _NC by adding the control voltage V _N and the compensation voltage V c, and adjusts the voltage. The driving signal GATE is generated using the result of comparing the voltage V _NC and the comparison voltage Vs as a reset signal. Here, the comparison voltage Vs is the sum of the sensing signal SEN provided by the converter 10 and the slope compensation voltage provided by the slope compensator 240. Assuming that the comparison signal Vs has a fixed value, the driving signal GATE has an on time corresponding to the adjustment voltage V _NC .

To this end, the driving signal providing circuit may include a comparator 222, an adder 234, a slope compensator 240, an adder 242, a comparator 244, and an SR latch 250. Here, the SR latch 250 is configured as a pulse generator for generating a gate signal, and may be configured using an SR flip-flop.

The comparator 222 compares the detection voltage V _D0 output from the detection voltage generation circuit 220 with the reference voltage VREF2 having a predetermined level and outputs a compensation voltage Vc. In this case, the compensation voltage Vc may be stabilized by a capacitor Cd connected to the output terminal of the comparator 222. In one embodiment of the present invention, the comparator 222 is configured such that the detection voltage V _D0 is applied to the negative terminal (−) and the reference voltage VREF2 is applied to the positive terminal (+).

The summer 234 generates the adjustment voltage V _NC by adding the control voltage V _N provided from the control voltage providing circuit 230 and the compensation voltage Vc output from the comparator 222. V _NC ) is output to the negative terminal (−) of the comparator 244.

Meanwhile, an embodiment of the present invention may include a slope compensator 240, and the slope compensator 240 compensates a slope when it is necessary to adjust a slope of a rising edge of a driving signal GATE. A slope compensation voltage is output.

The summer 242 adds the slope compensation voltage of the slope compensator 240 and the sensing signal SEN output from the converter 10 to output the comparison voltage Vs.

The comparator 244 outputs a result of comparing the comparison voltage Vs and the adjustment voltage V _NC . In one embodiment of the present invention, the comparator 244 is configured such that the comparison voltage Vs is applied to the positive terminal + and the regulation voltage V _NC is applied to the negative terminal −. By the configuration of the comparator 244 and the adder 242, the driving signal GATE may have a waveform reflecting the slope compensation voltage of the slope compensator 240 and the sensing signal SEN of the converter 10. The on time may be determined by the adjustment voltage V _NC .

The SR latch 250 receives a PWM signal including a periodic pulse at the set terminal S and receives an output of the comparator 244 at the reset terminal R. The SR latch 250 outputs the driving signal GATE through the output terminal Q, and the driving signal GATE is applied to the gate of the switching element Qb. The PWM signal may be provided in an oscillator circuit such as an oscillator (not shown), and the oscillator circuit may use one configured inside or outside the driving circuit 20. By the configuration of the SR latch 250 described above, the output of the comparator 244 serves as a reset signal for determining the on time of the driving signal GATE. That is, the SR latch 250 determines an on time at which the driving signal GATE is output to the output terminal Q by a reset by the output of the comparator 244, and a periodic pulse through the output terminal Q after the on time. And output a PWM signal including the drive signal (GATE).

When the control voltage providing circuit 230 is not configured in the embodiment of the present invention, the correlation between the output current IL, the output voltage VOUT, and the compensation voltage Vc may be described as shown in FIG. 3. In FIG. 3, Real Vc shows a change in the compensation voltage Vc, and Ideal Vc shows an ideal compensation voltage Vc corresponding to the change in load amount.

That is, when the number of LED channels emitting from the LED lamp 50 increases, the output voltage VOUT is temporarily lowered by the increase in the load amount. When the output voltage VOUT is lowered, the feedback voltages FB1 to FB8 are also lowered, and the detection voltage V _D output from the detection voltage generation circuit 220 is also lowered.

The comparator 222 outputs a compensation voltage Vc having a level rising in proportion to the difference between the reference voltage VREF2 and the detection voltage V _D , and is output from the SR latch 250 by the compensation voltage Vc. The on point of the driving signal GATE to be accelerated. As soon as the driving signal GATE is turned on, the level of the output voltage VOUT output from the converter 10 increases.

When the compensation of the output voltage VOUT is performed as described above, the amount of reduction of the feedback voltages FB1 to FB8 and the detection voltage V _D decreases, and the compensation voltage Vc gradually increases, so that the output voltage VOUT becomes After a certain time, it may return to the normal level.

On the contrary, when the number of LED channels emitting from the LED lamp 50 decreases, the output voltage VOUT is temporarily increased by the decrease in the load amount. The temporary increase in the output voltage VOUT due to the decrease in the load amount is compensated gradually because the compensation voltage Vc gradually decreases due to the increase in the feedback voltages FB1 to FB8 and the detection voltage V _D , and the output voltage V VOUT) can be returned to the normal level.

However, since the compensation of the output voltage VOUT by the compensation voltage Vc proceeds slowly in response to the load change, it is difficult for the output voltage VOUT to be stably maintained.

In addition, when the output voltage VOUT is severely lowered, it may be difficult to ensure the minimum voltage at which the LED channels CH1 to CH8 can stably emit light, which may cause difficulty in maintaining a stable lighting state.

According to the exemplary embodiment of the present invention, the output voltage VOUT may be stably maintained even when a load change occurs due to the operation of the control voltage providing circuit 230. Output current IL according to the embodiment of the present invention described above. The correlation between the control voltage V _N , the compensation voltage Vc, and the output voltage VOUT may be described as shown in FIG. 4.

That is, when the number of LED channels emitting from the LED lamp 50 increases, the load amount detection circuit 232 provides the control voltage providing circuit 230 with a digital value N corresponding to the load amount increased at the point of change of the load amount. In addition, the control voltage providing circuit 230 provides a control voltage V _N having a raised level corresponding to an increased load amount from a load change point. The adjustment voltage V _Nc also rises from the point of change of the load due to the change of the control voltage V _N , and the SR latch 250 increases the output voltage VOUT from the point of change of the load by the adjustment voltage V _Nc . The driving signal GATE is outputted with a changed on-time that can be stably maintained.

In addition, when the number of LED channels emitted from the LED lamp 50 decreases, the load amount detection circuit 232 provides the control voltage providing circuit 230 with a digital value N corresponding to the load amount reduced at the point of change of the load amount. In addition, the control voltage providing circuit 230 provides a control voltage V _N having a lowered level corresponding to the reduced load amount from a load change point. According to the change of the control voltage (V _N ), the adjustment voltage (V _Nc ) is also lowered from the load amount change point, SR latch 250 is the output voltage (VOUT) from the load amount change point by the adjustment voltage (V _Nc ). The driving signal GATE having the changed on-time is outputted so as to be stably maintained.

In the above-described embodiment of the present invention, the adjustment voltage V _Nc follows the change of the control voltage V _N. That is, the embodiment of the present invention adjusts the control voltage V _Nc by the control voltage V _N corresponding to the digital value N determined according to the load change instead of the compensation voltage Vc that changes slowly in response to the load change. This is quickly determined. Therefore, the embodiment of the present invention can quickly compensate the output voltage (VOUT) in response to the load change time, it is possible to maintain the output voltage (VOUT) stably. Meanwhile, the feedback voltages FB1 to FB8 are also stabilized by keeping the output voltage VOUT stable, and as a result, the compensation voltage Vc also maintains a constant level without change.

Therefore, the embodiment of the present invention can quickly perform the compensation corresponding to the load amount change of the loads to keep the output voltage VOUT stable, and there is an effect of maintaining a good lighting state.

In the above-described embodiment of the present invention, the drive signal GATE is generated using a PWM signal including a periodic pulse. When the drive signal GATE includes pulses of a fixed frequency by the PWM signal of a constant frequency, the converter 10 of the lighting device may consume a lot of power at the time of switching by the drive signal GATE and may reduce EMI. May cause

In order to reduce the above-described EMI, the present invention discloses an embodiment in which the frequency of the PWM signal used to generate the driving signal GATE can be changed over time by a spread spectrum method. According to the embodiment of the present invention described above, the driving signal GATE may have pulses of a distributed frequency. By the pulses of the distributed frequency of the driving signal GATE, the converter 10 may perform power conversion at distributed switching points, and power consumption may be distributed by switching switching points, and EMI may be reduced. Can be.

The frequency of the PWM signal can be dispersed using Carson's rule. FIG. 5 shows that the center frequency fc varies over time according to Carson's law within a constant variable frequency f range. 6 illustrates the bandwidth of a waveform frequency modulated by Carson's law, where the modulation frequency of variable frequency f is denoted by "fm".

The scatter spectrum can be implemented as "center frequency (fc) ± variable frequency (f)" or "center frequency (fc)-variable frequency (f)". Embodiments of the present invention can be implemented using "center frequency (fc) + variable frequency (f)".

The variable frequency f may be adjusted using option information. For example, the variable frequency f may be adjusted by non-dithering, 5%, 10%, 20%, or 30%. have. Non-dithering means maintaining the original frequency, and the option information means a value set to change the resistance value of the dithering resistor Rf described later.

The modulation frequency fm of the variable frequency f is a frequency that is changed by the change of the frequency reference voltage FREF, and the frequency reference voltage FREF is varied by 5 msec, 10 msec, 40 msec by using a digital control method. can do. The digital control method means that the step control unit 304 to be described later is controlled by the dithering control signal DMOD.

By applying the spread spectrum, the frequency of the pulse included in the driving signal FATE may be changed over time. An embodiment for this may be illustrated as shown in FIG. 7.

Referring to FIG. 7, an embodiment of the present invention may include a dithering control unit 300,

filters

310 and 320, and an oscillator 330.

The dithering control unit 300 has a configuration for varying the frequency reference voltage FREF by 64 steps, for example, and includes a dithering resistor Rf and a dithering control signal DMOD whose resistance is changed by option information. And a step controller 304 for changing the frequency reference voltage FREF. In addition, the dithering control unit 300 further includes a comparator 302, a PMOS transistor Qp, and a resistor string.

First, the resistance string includes resistors Rd1 to Rd64 connected in series corresponding to 64 steps, respectively, and a dithering resistor Rf connected in series to the resistors Rd1 to RD64. The dithering resistor Rf is located at the end of the resistor string and is grounded, and it is preferable that the dithering resistor Rf is made of a variable resistor whose resistance value can be changed in response to the option information. The resistors Rd1 to Rd64 are divided into lower resistance groups Rd1 to Rd32 of 32 steps and upper resistance groups Rd33 to Rd64 of 32 steps.

The comparator 302 outputs a voltage corresponding to the result of comparing the voltages Vf1 and Vf2, and the PMOS transistor Qp is driven by the voltage output from the comparator 302 and the driving voltage VDD to the resistor string. To pass. Here, the voltage Vf1 input to the negative terminal (-) of the comparator 302 may be provided with a fixed level of voltage. The voltage Vf2 input to the positive terminal + of the comparator 302 may use a voltage applied to a node between the lower resistance groups Rd1 to Rd32 and the upper resistance groups Rd33 to Rd64.

The step controller 304 includes switches connected to nodes between the resistors Rd1 to Rd64 of the resistor string, respectively. The switches of the step controller 304 are configured with the same number as the resistors Rd1 to Rd64. The switches are individually controlled by a dithering control signal DMOD having a digital value, and the dithering control signal DMOD has a number of bits that can be allocated by 1 bit for each switch.

In the step controller 304, one end of the switches is connected to nodes between the resistors Rd1 to Rd64 of the resistor string as described above, and the other end of the switches is commonly connected to output the frequency reference voltage FREF. An output terminal of the dithering control unit 300 is formed.

The dithering control unit 300 configured as described above may be understood as a digital analog converter configured to provide a frequency reference voltage FREF expressed as an analog value in response to the dithering control signal DMOD having a digital value.

The step controller 304 sequentially turns on the switches connected to the lower resistance groups Rd1 to Rd32, and as a result, the frequency reference voltage FREF gradually increases from a low level to a high level. Thereafter, the step controller 304 sequentially turns on the switches connected to the upper resistance groups Rd33 to Rd64, and as a result, the frequency reference voltage FREF gradually descends from a high level to a low level. Under the control of the step controller 304, the frequency reference voltage FREF has a triangular waveform in which a rising section of 32 steps and a falling section of 32 steps are formed.

The period of the frequency reference voltage FREF may be controlled by adjusting the switching period of 64 steps of the step controller 304. That is, when the period in which the dithering control signal DMOD is provided is changed, the period of the frequency reference voltage FREF may be changed correspondingly. According to the embodiment of the present invention, the frequency reference voltage FREF may be It can be configured to change the period.

In addition, the period of the frequency reference voltage FREF may be controlled by adjusting the voltage change width for each step. The voltage change width for each step may be adjusted according to the option information provided to the dithering resistor Rf.

The sum of the height change of each step according to the change in the resistance value of the dithering resistor Rf is expressed as the change in height of the triangular waveform of the frequency reference voltage FREF. Therefore, the height of the triangular waveform of the frequency reference voltage FREF can be controlled by the resistance value of the dithering resistor Rf which is varied by the option information.

More specifically, when the height of the triangular waveform of the frequency reference voltage VREF increases, it takes more time for the frequency reference voltage FREF to rise from the lowest level to the highest level and for the time to descend from the highest level to the lowest level. That is, the period of the frequency reference voltage FREF may be long. On the contrary, when the height of the triangular waveform of the frequency reference voltage VREF is lowered, the time for the frequency reference voltage FREF to rise from the lowest level to the highest level and the time for descending from the highest level to the lowest level decrease. That is, the period of the frequency reference voltage FREF may be shortened.

The step controller 304 configured in the embodiment of the present invention may change the shape of the frequency reference voltage VREF.

As described above, the frequency reference voltage FREF of the triangular waveform output from the dithering control unit 300 is applied to the filter 310, and by the action of the filter 310 in which the resistor and the capacitor are connected in parallel, the frequency reference voltage ( The step of FREF) is relaxed.

In addition, the frequency reference voltage FREF is applied to the filter 320 via the filter 310, and the filter 320 applies the oscillation signal VOSC shaped by a triangular waveform to the oscillator 330.

The oscillator 330 may output a PWM signal having a periodic pulse waveform by comparing the triangular waveform oscillation signal VOSC with an internal reference voltage (not shown).

The above-described embodiment of FIG. 7 may be applied to the driving circuit 20, and the frequency of the PWM signal may change according to the shape change of the oscillation signal Vosc. When the oscillation signal Vosc changes every cycle, the oscillator 330 provides a PWM signal having a frequency distributed every cycle. As a result, the driving circuit 20 may provide the converter 10 with a driving signal GATE having frequency-dispersed pulses due to frequency dithering. Therefore, the converter 10 may perform switching for power conversion at a time dispersed by the frequency dithered drive signal Gate, and as a result, concentration of power consumption may be alleviated and EMI may be reduced.

Referring to FIG. 8, DIM_EN is a dimming control enable signal of a lighting device, JIT_EN is a frequency dithering enable signal, and MAX and MIN are signals for controlling the point of time when the oscillation signal Vosc of the triangular waveform has the highest or lowest value. It is a signal for.

The lighting apparatus performs an initialization operation in which the oscillation signal Vosc maintains a constant level after being powered on, and then outputs an oscillation signal Vosc having a triangular waveform when the dimming control enable signal DIM_EN is enabled. Can be configured.

Before the frequency dithering enable signal JIT_EN is enabled, the oscillation signal Vosc is output to have a uniform triangular waveform. That is, the period T of the oscillation signal Vosc at this time is uniform.

After the frequency dithering enable signal JIT_EN is enabled, the frequency reference according to the change in the magnitude of the frequency reference voltage FREF or the change in the dithering control signal DMOD due to the change in the option information applied to the dithering resistor Rf. According to the period change of the voltage FREF, at least one of the magnitude and the period of the triangular waveform of the oscillation signal Vosc may be changed every cycle.

The driving circuit 20 configured as an embodiment of the present invention may store a plurality of values corresponding to the option information or the dithering control signal DMOD in the storage, and allow the frequency reference voltage FREF to change regularly or irregularly. Information or a dithering control signal DMOD may be provided.

In addition, the dithering control unit 300 of the driving circuit 20 may allow the first period after a certain time since the enable of the drive signal GATE to elapse and a predetermined time before the enable of the drive signal GATE ends. The frequency dithering may be performed at a time including at least one of the second periods in which the enable ends.

In addition, the driving circuit 20 may perform frequency dithering on the driving signal GATE by periodically changing the option information or the dithering control signal DMOD and providing the dithering control signal to the dithering control unit 300. In addition, the driving circuit 20 may perform frequency dithering on the driving signal GATE by changing the option information or the dithering control signal DMOD in a pattern repeated in units of a plurality of periods and providing the dithering control signal to the dithering control unit 300. Can be. In addition, the driving circuit 20 may perform frequency dirun by changing the frequency reference voltage VREF in a pattern of gradually changing frequency.

As a result of the frequency digging of the driving signal GATE described above, the driving signal GATE may have a peak value reduced by frequency dithering as shown in FIG. 9 and frequency may be dispersed. Therefore, the converter 10 may be distributed in the switching time for power conversion can be alleviated the concentration of power consumption, EMI can be reduced.

Meanwhile, the driving circuit 20 of the present invention may include a slope compensator 241 for generating a slope compensation voltage at a value that is linked to a variable switching frequency of the converter 10 as shown in FIG. 10.

In order for the slope compensation voltage to be linked to the varying switching frequency of the converter 10, the drive circuit 20 is configured to use a frequency source that provides varying frequency information of the drive signal GATE. Here, the oscillator 330 may be used as the frequency source to provide a PWM signal used to generate the driving signal GATE. In addition, the output of the oscillator 330 may be used as the frequency information. More specifically, any one of voltage or current corresponding to the output of the oscillator 330 may be used as frequency information.

The slope compensator 241 may include a slave current source IS2 and a charging device Cc connected in series. The slave current source IS2 controls an amount of current in response to frequency information, and the charging device Cc. Can be configured using a capacitor and charges the current provided by the slave current source IS2 and provides the charged voltage as the slope compensation voltage.

The slope compensator 241 may be configured to generate a lower slope compensation voltage as the frequency of the driving signal GATE increases.

Meanwhile, in FIG. 10, the current source IS1 and the PMOS transistor MS may be understood as configurations corresponding to the summer 242 of FIG. 2, and FIG. 10 illustrates the sensing signal SEN and the slope compensator 241. The slope compensation voltages output from are summed up by way of example. The summer 242 is not limited to FIG. 10 and may be variously performed by the manufacturer.

As shown in FIG. 10, the unstable sub harmony oscillation generated when the duty of the driving signal GATE provided to the converter 10 is 50% or more to generate the output voltage is controlled by the slope compensator 241. Can be.

In order to vary the switching frequency of the converter 10, the frequency of the driving signal GATE must be varied. That is, the switching frequency of the converter 10 varies depending on the frequency of the driving signal GATE.

In addition, when the switching frequency is changed, the value of the inductance of the converter 10 is also changed. In this case, the slope compensation voltage of the slope compensator 241 of FIG. 10 also changes in response to the change of the inductance.

More specifically, in order to change the frequency of the driving signal GATE, the frequency of the PWM signal output from the oscillator 330 must also be changed. Therefore, the oscillator 330 has variable frequency information and as a result can be used as a frequency source as described above.

In one example, the dependent current source IS2 may be configured to provide the charging element Cc with a current mirroring the output current of the oscillator 330. That is, the dependent current source IS2 may provide the charging element Cc with a current corresponding to the changed frequency of the PWM signal of the oscillator 330 in order to change the frequency of the driving signal GATE. In this case, the current mirroring increases the frequency of the oscillator 330 to increase the output current of the slave current source IS2, and decreases the frequency of the oscillator 330 to reduce the output current of the slave current source IS2. Can be implemented. The relationship between the frequency of the oscillator 30 and the amount of current in the dependent current source IS2 may be determined for slope compensation to reduce sub-harmony oscillation.

Unlike the above, the dependent current source IS2 may be configured to provide the charging element Cc with a current that is linked to a PWM signal or a voltage corresponding to the PWM signal of the oscillator 330. In this case, the dependent current source IS2 reduces the amount of current by the voltage corresponding to the PWM signal or the PWM signal of the oscillator 330 having a higher frequency and is reduced by a voltage corresponding to the PWM signal or the PWM signal of the oscillator 330 having a lower frequency. It can be configured to increase the amount of current.

The current provided from the dependent current source IS2 is charged in the charging element Cc, and the voltage charged in the charging element Cc may be provided as a slope compensation voltage. That is, the slope compensation voltage may be provided to vary with frequency as shown in FIG. 11. FIG. 11 is a graph illustrating a slope compensation voltage according to the related art compared with a slope compensation voltage according to the present invention, in which a voltage charged by a fixed current is provided as a slope compensation voltage.

Therefore, even if the switching frequency of the converter 10 is variable, the embodiment of the present invention is a frequency source without having to configure a separate terminal in the driving circuit 20 implemented as a chip or an additional circuit outside the chip. The slope compensation voltage can be provided in conjunction with the frequency variation of the PWM signal output from the oscillator.

Therefore, in the embodiment of the present invention, a function for actively responding to the switching frequency change of the converter 10 may be simply implemented, and the number of parts and the manufacturing cost may be reduced.

In addition, a fourth embodiment for ensuring that the LED current of each of the LED channels CH1 to CH8 included in the LED lamp 50 is maintained above a certain amount may be illustrated as shown in FIG. 12. In FIG. 12, the same parts as those of FIG. 2 are denoted by the same reference numerals, and redundant description of the configuration and operation thereof will be omitted.

The lighting device of FIG. 12 includes an output sensing circuit 60 for sensing the output voltage VOUT of the converter 10, wherein the output sensing circuit 60 includes a series of resistors RV1 and RV2 connected to the converter 10. Are connected in parallel to the output terminal. The output sensing circuit 60 provides the driving circuit 20 with a voltage applied to the node between the series connected resistors RV1 and RV2, and the voltage provided to the driving circuit 20 in the output sensing circuit 60 is This is called the output sensing voltage. The output sensing circuit 60 may be configured inside or outside the driving circuit 20.

The driving circuit 20 includes the linear regulators 201 to 208, the detection voltage generation circuit 220, the reference voltage generation circuit 221, the comparator 223, the capacitor Cd, the slope compensator 240, and the adder. 242, comparator 244, and SR latch 250.

The driving circuit of FIG. 12 includes a reference voltage generation circuit 221. The reference voltage generation circuit 221 receives the detection voltage V _D and the internal reference voltage VREFi of the detection voltage generation circuit 220, uses an external capacitor Cs, and compares the reference voltage VREF with a comparator ( And output to the negative end (−) of 223.

According to the above configuration, the reference voltage generation circuit 221 has an internal reference voltage at which one or more of the feedback voltages FB1 to FB8 corresponding to the bias voltages of the LED channels LED1 to LED8 have a preset value. Below VREFi), the reference voltage VREF at which the level is increased is generated. The reference voltage generator 221 may be configured to generate a reference voltage VREF that increases until all of the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi. The reference voltage generation circuit 221 is configured to charge or discharge the reference voltage VREF using an external capacitor Ce.

The configuration of the reference voltage generator 221 in more detail will be described later with reference to FIG. 13.

In addition, the driving circuit 20 of FIG. 12 is configured such that the comparator 223 outputs the compensation voltage Vc by comparing the reference voltage VREF with the output sensing voltage of the output sensing circuit 60. The reference voltage VREF is applied to the negative terminal (-) of the comparator 223, and the output sensing voltage of the output sensing circuit 60 is applied to the positive terminal (+) of the comparator 223.

In addition, the driving circuit 20 of FIG. 12 is configured such that the comparator 244 compares and outputs the compensating voltage Vc and the comparison voltage Vs of the summer 242. The compensation voltage Vc is applied to the negative terminal (-) of the comparator 244, and the comparison voltage Vs is applied to the positive terminal (+) of the comparator 244.

According to the above configuration, the SR latch 250, which is a pulse generator, generates a driving signal GATE in response to the output of the comparator 244 whose level is determined in response to the compensation voltage Vc. That is, the SR latch 25 generates a drive signal GATE having an adjusted on time corresponding to the compensation voltage Vc and provides the drive signal GATE to the converter 10 for power conversion.

Meanwhile, the configuration of the reference voltage generation circuit 221 will be described in more detail with reference to FIG. 13.

The reference voltage generator 221 charges or discharges the reference voltage VREF by using an external capacitor Ce, and charging of the reference voltage VREF is performed by one or more of the feedback voltages FB1 to FB8. When the voltage VREFi is less than or equal to, the discharge of the reference voltage VREF is performed until all of the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi. The voltage charged in the capacitor Ce is output as the reference voltage VREF.

To this end, the reference voltage generation circuit 221 includes a comparator 225 and a current control circuit, the comparator 225 is a switching control voltage (VCT) comparing the detection voltage (V _D ) and the internal reference voltage (VREFi) The output current control circuit includes a switch SW that is switched according to the switching control voltage VCT, and when the switch SW is turned on, the current control circuit provides a current for charging the capacitor Ce. The comparator 225 may output the switching control voltage VCT to 0V, for example, at a low level when the detection voltage V _D is less than the internal reference voltage VREFi, and the detection voltage V _D may be an internal reference voltage. If greater than VREFi, the switching control voltage VCT may be output as a high level illustratively VDD. The switch SW is turned on when the switching control voltage VCT is at a low level, and the switch SW is turned off when the switching control voltage VCT is at a high level.

The current control circuit may further include a plurality of PMOS transistors MP1 to MP7 to control providing current to the capacitor Ce by turning on the switch SW. The plurality of PMOS transistors MP1 to MP7 may be configured to have a current mirror structure for controlling a current provided to the capacitor Ce by the operation of the switch SW.

That is, the PMOS transistors MP1 and MP2 form a first path including a constant current source, the PMOS transistors MP3, MP4 and MP5 form a second path that provides a radiated current, and the PMOS transistors MP6, The switch SW and the PMOS transistor MP7 form a third path for controlling the current provided to the capacitor Ce by the current in the second path. The first to third paths are configured such that respective transistors included therein are connected in series, and the first to third paths are configured in parallel with respect to the constant voltage VDD.

By the resistance ratio (channel ratio) of the PMOS transistors MP3 and MP4 and the PMOS transistors MP1 and MP2, the amount of current flowing through the PMOS transistors MP3 and MP4 in the second path is determined by the PMOS transistor in the first path. It can be controlled based on the amount of current flowing through the fields (MP1, MP2). The amount of current flowing through the PMOS transistor MP6 may also be controlled based on the amount of current flowing through the PMOS transistor MP1 in the first path. The amount of current flowing through the PMOS transistor MP7 may be controlled based on the amount of current flowing through the PMOS transistor MP5 in the second path.

The operation of the reference voltage generator 221 configured as shown in FIG. 13 will be described with reference to FIG. 14.

In the reference voltage generation circuit 221, if the detection voltage VD is less than the internal reference voltage VREFi, the switching control voltage VCT of the comparator 225 becomes low level, and as a result, the switch SW is turned on. do.

When the switch SW is turned on, the flow of the current Ir1 is started, the current Ir3 is provided to the capacitor Ce, and the voltage of the capacitor Ce rises by charging by the current Ir3. The voltage charged in the capacitor Ce is the reference voltage VREF output from the reference voltage generation circuit 221. As described above, the amount of current Ir3 may be determined as "amount of current Ir1"-"amount of current Ir2 of the PMOS transistor MP7".

The detection voltage V _D is the lowest feedback voltage among the feedback voltages FB1 to FB8. The switching control voltage VCT of the comparator 225 transitions to a high level when all the feedback voltages FB1 to FB8 are greater than or equal to the internal reference voltage VREFi. Therefore, the reference voltage VREF charged to the capacitor Ce is also charged until the feedback voltages FB1 to FB8 are greater than or equal to the internal reference voltage VREFi and the level rises.

Thereafter, when all the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi, the switching control voltage VCT transitions to a high level, and the switch SW is turned off. When the switch SW is turned off, the flow of the current Ir1 is stopped.

After the flow of the current Ir1 is stopped, the capacitor Ce starts to discharge, so that the level of the reference voltage VREF output from the reference voltage generator 221 gradually decreases.

As described above, the reference voltage VREF provided from the reference voltage generation circuit 221 may increase or decrease according to the states of the feedback voltages FB1 to FB8.

The increase in the reference voltage VREF corresponds to a case in which it is necessary to compensate for the amount of LED current for the normal emission of the LED channels CH1 to CH8. At this time, the output voltage VOUT is increased by the increasing reference voltage VREF. The reference voltage VREF decreases when the amount of LED current of the LED channels CH1 to CH8 can maintain normal light emission.

A series of operations in which the output voltage VOUT is raised by the rise of the reference voltage VREF will be described in more detail. When the reference voltage VREF rises, the comparator 223 compares the output sensing voltage of the output sensing circuit 60 with the raised reference voltage VREF. As a result, when the output sensing voltage of the output sensing circuit 60 is lower than the reference voltage VREF, the compensation voltage Vc is applied to the negative terminal (-) of the comparator 244 at a negative level. When the compensation voltage Vc is applied at the negative level, the output of the comparator 244 rises. When the output of the comparator 244 rises, the SR latch 25 generates a drive signal GATE with an increased on time. As a result, the output voltage VOUT output from the converter 10 rises.

As described above, the output voltage VOUT is regulated to maintain a certain level or more by the increasing reference voltage VREF.

As described above, the fourth embodiment of the present invention may be regulated by the reference voltage VREF at which the output voltage VOUT is changed.

Therefore, the bias voltages of the LED channels CH1 to CH8 vary depending on the characteristic variation, and the lowest feedback voltage among the feedback voltages of the LED channels CH1 to CH8 emits light from the LED channels CH1 to CH8, respectively. It can change every time. According to the fourth embodiment of the present invention, the output voltage VOUT can be stably maintained in response to the environment in which the lowest feedback voltage is changed as described above, and as a result, audible noise can be prevented from occurring.

Meanwhile, the fifth embodiment of the present invention may be configured as shown in FIG. 15 in order to reduce the number of components and the manufacturing cost by sharing components such as a converter.

The embodiment of FIG. 15 illustrates that the driving circuits are configured in multiple chips with respect to one converter 10. The driving circuit which provides the driving signal GATE to the converter 10 to distinguish the driving circuits is a master driving circuit. This is referred to as M20, and the remaining driving circuit is referred to as slave driving circuit S20.

In the embodiment of FIG. 15, the converter 10 performs power conversion to output an output voltage VOUT corresponding to the input voltage VIN, and to provide the output voltage VOUT to the LED lamps M50 and S50. It is composed.

The LED lamps M50 and S50 respectively include a plurality of LED channels CH1 to CH8 configured in parallel as shown in FIG. 1, and the plurality of LED channels CH1 to CH8 of the LED lamps M50 and S50. Emits light by the output voltage VOUT.

On the other hand, an overvoltage detection circuit 70 for detecting the level of the output voltage VOUT is configured at the output terminal of the converter 10. The overvoltage detection circuit 70 outputs a voltage applied to a node between the resistors ROVP1 and ROVP2 connected in series as an overvoltage detection signal, and the overvoltage detection signal of the master driving circuit M20 and the slave driving circuit S20. It is shared by the overvoltage detection terminal OVP.

When it is determined that the output voltage VOUT is in the overvoltage state by the overvoltage detection signal, the master driving circuit M20 controls the level of the output voltage VOUT by adjusting the output of the driving signal GATE or the LED lamp M50. Can be controlled. In addition, the slave driving circuit S20 may also control the light emission state of the LED lamp S50 in response to the overvoltage detection signal.

In addition, the master driving circuit M20 and the slave driving circuit S20 have substantially the same configuration as the driving circuit 20 of FIG. 1 except that the common terminal CON and the high ground terminal HGND are formed. Duplicate explanations are omitted. The master driving circuit M20 and the slave driving circuit S20 may use chips having the same structure.

The shared terminals CON of the master driving circuit M20 and the slave driving circuit S20 are electrically connected to each other. In addition, the high ground terminals HGND of the master driving circuit M20 and the slave driving circuit S20 are set to have a predetermined voltage biased using the capacitor CH.

The master driving circuit M20 performs linear regulation on the LED channels CH1 to CH8 of the LED lamp M50, and feedback voltages FB1 to LED channels CH1 to CH8 of the LED lamp 50. The first minimum feedback voltage of the lowest level of FB8) is detected. In addition, the master driving circuit M20 generates a detection voltage V _D corresponding to a lower level among the first minimum feedback voltage and the second minimum feedback voltage shared through the sharing terminal CON, and the detection voltage V _D. ) Generates a driving signal GATE, and provides a driving signal GATE to the converter 10 for power conversion. As described above, the generation of the driving signal GATE by the master driving circuit M20 using the detection voltage V _D may be variously performed as in the embodiment of FIGS. 1 and 2 or the embodiment of FIG. 12. The detailed description thereof will be omitted.

The slave driving circuit S20 performs linear regulation on the LED channels CH1 to CH8 of the LED lamp S50, and has the lowest feedback voltages of the LED channels CH1 to CH8 of the LED lamp S50. The second minimum feedback voltage of the level is detected, and the second minimum feedback voltage is shared with the master driving circuit M20 through the sharing terminal CON.

The slave driving circuit S20 has input and output terminals related to generation and output of a driving signal, similarly to the master driving circuit M20. However, the slave driving circuit S20 does not generate and output the driving signal GATE. Therefore, some of the input / output terminals of the slave driving circuit S20 (VIN, SEN, GATE) related to the generation and output of the driving signal GATE are masked. Here, the masking process means that the input level is fixed by the high level voltage charged in the capacitor CH, or is fixed to the ground level of the capacitor CIN, and may also include a floating state.

The master driving circuit M20 and the slave driving circuit S20 described above may each include a detection voltage generation circuit 220 for generating the detection voltage V _D. The configuration and operation of the detection voltage generation circuit 220 of the master driving circuit M20 and the slave driving circuit S20 will be described with reference to FIG. 16. FIG. 16 schematically illustrates the detection voltage generation circuit 220 and the linear regulators 201 to 208 of the master driving circuit M20 and the slave driving circuit S20.

The feedback voltages FB1 to FB8 of the master driving circuit M20 and the slave driving circuit S20 are voltages applied to the respective linear regulators 201 to 208. Since each of the linear regulators 201 to 208 is the same as that of FIG. 2, detailed configuration and operation thereof will be omitted.

The feedback voltages FB1 to FB8 are applied to the detection voltage generation circuit 220 inside the master driving circuit M20 and the slave driving circuit S20.

The detection voltage generation circuit 220 of the master driving circuit M20 and the slave driving circuit S20 may include transistors TFB1 to TFB8 and switches SFB1 to SFB8 for respective paths of the feedback voltages FB1 to FB8. have.

The transistors TFB1 to TFB8 transfer the feedback voltages FB1 to FB8 to the switches SFB1 to SFB8 when the switches SFB1 to SFB8 are turned on, and the switches SFB1 to SFB8 are switching control signals. In order to transfer the feedback voltages FB1 to FB8 switched by the FBS1 to FBS8 and transferred through the transistors TTF1 to TTF8 to the output terminal of the detection voltage generation circuit 220.

Herein, the output terminal of the detection voltage generation circuit 220 refers to a node that outputs the detection voltage V _{D by} connecting the switches SFB1 to SFB8 in common, and the output terminal of the detection voltage generation circuit 220 is illustrated in FIG. 16. As illustrated, the constant current may be supplied by the constant current source.

The detection voltage generation circuit 220 may include a circuit (not shown) for comparing the levels of the feedback voltages FB1 to FB8 to determine the lowest level feedback voltage (minimum feedback voltage). The above circuit provides the switching control signals FBS1 to FBS8 for outputting only the minimum feedback voltage as the detection voltage V _D , and a person who understands the technical idea of the present specification using a conventional comparator or a level detector Since it can be comprised easily, a specific example is abbreviate | omitted.

The detection voltage generation circuit 220 may provide the switching control signals FBS1 to FBS8 to the switches SFB1 to SFB8 for outputting only the minimum feedback voltage as the detection voltage V _D.

For example, the detection voltage generation circuit 220 of the master driving circuit M20 turns on only the switch SFB1 when the feedback voltage “FB1” is determined as the first minimum feedback voltage, and the remaining switches SFB2 to SFB8 are turned on. Turn off. As a result, the feedback voltage FB1 determined as the first minimum feedback voltage may be transmitted to the output terminal of the detection voltage generation circuit 220 of the master driving circuit M20. The detection voltage generation circuit 220 of the slave driving circuit S20 may also operate in the same manner as the detection voltage generation circuit 220 of the master driving circuit M20 described above.

As described above, the detection voltage generation circuit 220 of the master driving circuit M20 and the slave driving circuit S20 may transfer the first minimum feedback voltage and the second minimum feedback voltage to the output terminal, respectively.

The output terminal of the detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20 is electrically connected to each other through the shared terminals CON. Therefore, the first minimum feedback voltage and the second minimum feedback voltage transmitted to the output terminals of the detection voltage generation circuit 220 of the master driving circuit M20 and the slave driving circuit S20 are shared.

As a result, the detection voltage generation circuit 220 of the master driving circuit M20 may output the detection voltage V _D generated by sharing the first minimum feedback voltage and the second minimum feedback voltage.

The master driving circuit M20 may generate a driving signal GATE as in the embodiment of FIGS. 1 and 2 or the embodiment of FIG. 12, in response to the detected voltage V _D generated as described above. (GATE) may be provided to the converter 10 for power conversion.

Meanwhile, among the master driving circuit M20 and the slave driving circuit S20, the slave driving circuit S20 may include the feedback voltages of the LED channels CH1 to CH8 of the LED lamp S50. It may be configured to perform only a function of detecting the second minimum feedback voltage of the lowest level among the FB1 to FB8 and linear regulation of the LED channels CH1 to CH8 of the LED lamp S50. In this case, the master driving circuit M20 may be referred to as a first circuit, and the slave driving circuit S20 may be referred to as a second circuit.

As described above, the present invention allows the driving circuits to be composed of multi-chips corresponding to a large number of LED channels. Therefore, it shares the lowest feedback voltage for the LED channels corresponding to the respective drive circuits, detects the lowest feedback voltage for all LED channels, and uses the lowest feedback voltage for all LED channels. It is possible to control the output voltage provided to the channels.

As a result, parts such as converters can be shared and the number of parts and manufacturing cost can be reduced.

The present invention may be practiced to ensure an effective duty of the drive signal GATE for controlling dimming regardless of the switching frequency of the converter 10. To this end, a sixth embodiment for guaranteeing the minimum on time of the converter 10 may be configured as shown in FIGS. 17 to 19 regardless of the switching frequency of the converter 10. In addition, a seventh embodiment for guaranteeing the minimum off time of the converter 10 may be configured as shown in FIGS. 20 to 22 regardless of the switching frequency of the converter 10.

First, a sixth embodiment will be described in detail with reference to FIGS. 17 to 19.

In the driving circuit 20, the driving signal GATE may be generated using the PWM signal of the oscillator 330. Generation of the driving signal GATE using the PWM signal may be understood by the above description with reference to FIG. 2, and thus description thereof will be omitted. Hereinafter, the PWM signal of the oscillator 330 will be described as an oscillation signal.

The switching frequency of the converter 10 may be determined by the driving signal GATE, and the driving circuit 20 provides the converter 10 with a driving signal GATE capable of guaranteeing a minimum on time of the converter 10. do.

To this end, the driving circuit 20 includes a constant current supply unit 80, a control current supply unit 82, a charging element CN, a switch SWT, a comparator 86, a NAND gate 88 and an inverter as shown in FIG. IV1).

The constant current supply unit 80 is for providing the charging element CN with a constant current by the constant voltage VDD. To this end, the constant current supply unit 80 copies the current flowing in the PMOS transistors MS1 and MS2 connected in series to the PMOS transistors MS3 and MS4 by mirroring, respectively, and flows the PMOS transistors MS3 and MS4. It is configured to provide a current to the charging element CN.

The control current supply unit 82, the charging element CN, and the switch SWT described above are included in a control voltage generation circuit described later.

The control current supply unit 82 is configured to provide the control current to the charging element CN by using the oscillator current iosc by the oscillation signal output from the oscillator 330. To this end, the control current supply unit 82 flows a current corresponding to the oscillator current iosc and the current flowing through the PMOS transistors MC1 and MC2 and the PMOS transistors MC1 and MC2 connected in series is copied by mirroring. PMOS transistors MC3 and MC4 that flow and are connected in series. Here, the current flowing through the PMOS transistors MC3 and MC4 is provided to the charging element CN.

The oscillator current iosc may vary in proportion to the frequency change of the oscillation signal. Therefore, the amount of control current provided by the control current supply unit 82 to the charging element CN can also be changed in proportion to the frequency change of the oscillation signal.

More specifically, when the frequency of the oscillation signal is high, the amount of oscillator current iosc increases and the amount of control current of the control current supply unit 82 also increases. In contrast, when the frequency of the oscillation signal is low, the amount of oscillator current iosc is reduced, and the amount of control current of the control current supply 82 is also reduced.

In addition, the switch SWT is connected in parallel to the charging element CN and blocks the supply of current to the charging element CN when turned on. That is, providing current to the charging element CN is regulated by the switch SWT. The switch SWT is switched by the driving signal GATE which is inverted and input through the inverter IV1. That is, the switch SWT is turned off during the turn-on period of the converter 10 and turned on during the turn-off period of the converter 10. Accordingly, the charging element CN is charged during the turn-on period of the converter 10 and discharged during the turn-off period of the converter 10.

The charging element CN may perform charging by the current supplied from the constant current supply unit 80 and the control current supply unit 82, and generate a control voltage. In particular, the charging element CN generates a control voltage by the control current of the control current supply unit 82 whose amount is changed in proportion to the frequency change of the oscillation signal, and the charging speed of the control voltage in proportion to the frequency change of the oscillation signal. May vary.

More specifically, when the frequency of the oscillation signal is high, the amount of control current of the control current supply unit 82 increases, and the rate at which the control voltage is charged in the charging element CN is fast. On the contrary, when the frequency of the oscillation signal is low, the amount of control current of the control current supply unit 82 decreases, and the rate at which the control voltage is charged in the charging element CN is slow.

The comparator 86 compares the control voltage of the charging element CN applied to the positive terminal (+) with the reference voltage VREF applied to the negative terminal (−) and outputs a control pulse VA as shown in FIG. 18. . More specifically, the comparator 86 outputs a control pulse VA that transitions to a high level when the control voltage reaches the reference voltage VREF and maintains a transition state while the control voltage maintains the reference voltage VREF or more. do. The comparator 86 performing the above operation corresponds to a control pulse generation circuit described later.

When the frequency of the oscillation signal is high and the control voltage of the capacitor CN is rapidly charged, the comparator 86 outputs a control pulse VA with a fast level transition time. On the contrary, when the frequency of the oscillation signal is low and the charge voltage of the capacitor CN is increased to increase, the comparator 86 outputs the control pulse VA with a late level transition time.

The NAND gate 88 NAND combines the control pulse VA and the inverted driving signal GATE to output the minimum ON time pulse ON_MIN as shown in FIG. 18. The inverted driving signal GATE is used to determine the turn-on period of the converter 10.

That is, the NAND gate 88 defines a minimum on time including the end point of the minimum on time from the start of turn-on of the converter 10 using the control pulse VA within the turn-on period of the converter 10. Generate the minimum on time pulse (ON_MIN). The NAND gate 88 performing the above operation corresponds to the minimum on time determination unit described later.

When the comparator 86 outputs the control pulse VA with a high level transition time due to the high frequency of the oscillation signal, the end point of the minimum on time is faster, and as a result, the NAND gate 88 has a minimum on width with a narrow pulse width. Output a time pulse (ON_MIN). On the contrary, when the frequency of the oscillation signal is low and the comparator 86 outputs a control pulse VA having a slow level transition time, the end time of the minimum on time becomes slow, and as a result, the NAND gate 88 has a pulse width. Output a wide minimum on-time pulse (ON_MIN).

That is, in the embodiment of FIG. 17, the width of the minimum ON time pulse ON_MIN may be adjusted in response to the frequency change of the oscillation signal as shown in FIG. 19. The width of the minimum on time pulse ON_MIN means a minimum on time that can be guaranteed for turning on the converter 10. That is, the minimum on time for turning on the converter 10 may change in response to the frequency change of the oscillation signal.

Therefore, the embodiment of FIGS. 17 to 19 can secure an effective duty capable of controlling dimming regardless of the switching frequency of the converter 10.

17 may be described as including an end time generation unit and a minimum on time determination unit.

The end point generator generates a control pulse VA representing the end point of the minimum on time following the frequency change of the oscillation signal using the oscillation signal used to generate the driving signal GATE within the turn-on period of the converter 10. It is configured to generate.

The end point generation unit may be described as including a control voltage generation circuit and a control pulse generation circuit.

Here, the control voltage generation circuit is configured to generate a control voltage whose increase time varies according to the frequency change of the oscillation signal using the oscillation signal used to generate the drive signal GATE within the turn-on period of the converter 10. do. The control pulse generation circuit corresponds to the comparator 86 described above.

The control voltage generation circuit may include a control current supply unit 82, a charging element CN, and a switch SWT.

Meanwhile, the seventh embodiment will be described in detail with reference to FIGS. 20 to 22.

The embodiment of FIG. 20 is to ensure the minimum off time of the converter 10 irrespective of the switching frequency of the converter 10, and the drive circuit 20 drives to ensure the minimum off time of the converter 10. The signal GATE is provided to the converter 10.

To this end, the driving circuit 20 is a constant current supply unit 80, the control current supply unit 82, the charging element (CN), the switch (SWT), the comparator 86, the end gate 89 and the inverter ( IV2).

In comparison with the embodiment of FIG. 17, the structure of the AND gate 89 and the inverter IV2 are different from each other, and the charging capacity of the charging element CN is different. Since the remaining components of FIG. 20 are the same as those of FIG. 17, redundant description is omitted.

In FIG. 20, the switch SWT is switched by a non-inverting input drive signal GATE. That is, the switch SWT is turned off during the turn-off period of the converter 10 and turned on during the turn-on period of the converter 10. Accordingly, the charging element CN is charged during the turn-off period of the converter 10 and discharged during the turn-on period of the converter 10.

The charging element CN may be configured to have a charging capacity larger than that of FIG. 17.

Comparator 86 outputs a control pulse VA as shown in FIG. More specifically, in the embodiment of FIG. 20, the time when the control voltage reaches the reference voltage VREF is slower than the embodiment of FIG. 17 due to the difference in the charging capacity of the charging element CN. Therefore, the control pulse VA output from the comparator 86 is delayed by a predetermined time after the turn-off period of the converter 10 is started, and the transition level is maintained until the turn-on period of the converter 10 is started. . Comparator 86 outputs a control pulse VA that maintains a transition state while the control voltage maintains the reference voltage VREF or more.

The AND gate 89 combines the control pulse VA and the inverted driving signal GATE and outputs the minimum OFF time pulse OFF_MIN as shown in FIG. 21. The inverted driving signal GATE is used to determine the turn-off period of the converter 10.

That is, the AND gate 88 uses the control pulse VA to set the minimum off time including the turn off end point of the converter 10 using the control pulse VA within the turn off period of the converter 10. Generates the minimum off time pulse (OFF_MIN) that you define. The AND gate 89 performing the above operation corresponds to the minimum off time determination unit described later.

When the comparator 86 outputs a control pulse VA with a fast level transition time due to the high frequency of the oscillation signal, the start time of the minimum off time is faster, and as a result, the AND gate 88 has a minimum off with a wide pulse width. Output a time pulse (OFF_MIN). On the contrary, when the frequency of the oscillation signal is low and the comparator 86 outputs a control pulse VA having a slow level transition time, the start time of the minimum off time is slowed, and as a result, the AND gate 89 has a pulse width. Output a narrow minimum off time pulse (OFF_MIN).

That is, in the embodiment of FIG. 20, the width of the minimum off time pulse OFF_MIN may be adjusted in response to the frequency change of the oscillation signal as shown in FIG. 22. The width of the minimum off time pulse OFF_MIN means the minimum off time that can be guaranteed for the turn-off of the converter 10. That is, the minimum off time for turning off the converter 10 may change in response to the frequency change of the oscillation signal.

Therefore, the embodiment of FIGS. 20 to 22 can ensure an effective duty of the drive signal GATE for controlling dimming regardless of the switching frequency of the converter 10.

20 may be described as including a start time generation unit and a minimum off time determination unit.

The start point generator generates a control pulse VA representing a start point of a minimum off time following a frequency change of the oscillation signal using the oscillation signal used to generate the driving signal GATE within the turn-off period of the converter 10. Is generated).

The start point generation unit may be described as including a control voltage generation circuit and a control pulse generation circuit.

Here, the control voltage generation circuit generates a control voltage whose increase time varies according to the frequency change of the oscillation signal using the oscillation signal used to generate the drive signal GATE within the turn-off period of the converter 10. It is composed. The control pulse generation circuit corresponds to the comparator 86 described above.

The control voltage generation circuit may include a control current supply unit 82, a charging device CN, and a switch SWT.

Meanwhile, the embodiment of FIG. 17 and the embodiment of FIG. 20 may be applied to the driving circuit 20 in the same manner. In this case, the minimum on time of the turn-on period and the minimum off time of the turn-off period may be guaranteed at the same time regardless of the switching frequency.

According to the present invention, the internal voltage VIN at the time when the drain voltage of the power switch FET_P provided in the converter 10 of FIG. 23 falls to the ground voltage at the time of rising and falling of the PWM signal is grounded. It is to provide a lighting device that can reduce the EMI by adjusting the time to climb.

FIG. 23 is a circuit diagram for explaining an embodiment provided in the drive circuit 20. As shown in FIG. This embodiment includes a control current generation circuit and a gate driver 205. The control current generating circuit includes a current generating unit 203 and a current adjusting unit 204.

The current generator 203 generates a current through an internal or external resistance. The current generator 203 may include a variable resistor, and the magnitude of the current may be set corresponding to the magnitude of the power switch FET_P.

The current controller 204 has a current mirror structure with the current generator 203. The current controller 204 generates the control currents I1 and I2 by using the current of the current generator 203.

Current paths of the control currents I1 and I2 are formed corresponding to pull-up and pull-down driving of the gate driver 205. For example, the current path of the control current I1 is formed when the gate driver 205 pulls up, and the current path of the control current I2 is formed when the gate driver 205 pulls down. The magnitudes of the control currents I1 and I2 may be set corresponding to the magnitudes of the power switch FET_P.

The control current generation circuit configured as described above provides the control current I1 to the pull-up driver PMOS of the gate driver 205 at the rising time of the PWM signal, and the control current at the falling time of the PWM signal. (I2) is provided to the pull-down driver NMOS of the gate driver 205. Here, the rise and fall times of the driving signal GATE may be set corresponding to the magnitudes of the control currents I1 and I2.

The gate driver 205 provides a driving signal GATE to the power switch FET_P in response to the PWM signal. The gate driver 205 includes non-overlap circuits NOC1 and NOC2 for outputting a signal such that a signal does not overlap with a delay or the like in response to a PWM signal, and includes a signal overlap prevention circuit NOC1, And a pull-up driver PMOS and a pull-down driver NMOS that pull-up and pull-down the driving signal GATE in response to the signal of NOC2. When the pull-up driving unit PMOS is driven by the control current I1 during the pull-up driving, the driving signal GATE rises through the flat section as shown in FIG. 3, and the pull-down driving unit NMOS is the control current during the pull-down driving. The driving signal GATE falls through the flat section by (I2).

The rise and fall times of the driving signal GATE may be adjusted corresponding to the magnitudes of the control currents I1 and I2. In one example, the drive signal GATE rises to the slope set by the control current I1 at the time of rising of the PWM signal and then remains flat while the capacitor Cgd between the gate and the drain is discharged. GATE terminates the state that remains flat when the discharge of the capacitor Cgd is completed and rises again to the slope set by the control current I1. Thereafter, when the current path of the control current I1 is blocked by the turn-on of the power switch FET_P, the rise of the driving signal GATE is stopped.

Then, the driving signal GATE falls to the slope set by the control current I2 at the time of polling the PWM signal and then remains flat while the capacitor Cgd between the gate and the drain is charged. The driving signal GATE terminates the state that remains flat when the charging of the capacitor Cgd is completed and falls back to the slope set by the control current I2. Thereafter, when the current path of the control current I2 is blocked by turning off the power switch FET_P, the falling of the driving signal GATE is stopped.

As described above, the present invention can accurately set the rise and fall times of the driving signal GATE to the target time using the control currents I1 and I2.

The present invention adjusts the rise and fall times of the drive signal GATE by the control currents I1 and I2 at the transition point of the PWM signal, thereby reducing the time when the drain voltage of the power switch FET_P falls to the ground voltage and the ground voltage. The rise time to the internal voltage can be adjusted. The present invention can reduce the EMI that may be caused by the repetitive switching of the power switch (FET_P) by adjusting the time when the drain-source voltage of the power switch (FET_P) is changed as described above.

23 and 24, the operation of this embodiment configured as described above will be described.

First, the operation at the rising time of the PWM signal will be described.

When the PWM signal rises in the gate driver 205, the pull-up driver PMOS is turned on, and a current path of the control current I1 is formed by turning on the pull-up driver PMOS. The capacitor Cgs between the gate and the source of the power switch FET_P is charged by the control current I1, and the driving signal GATE rises to the set slope by the charging of the capacitor Cgs.

When the driving signal GATE reaches a predetermined level, the power switch FET_P starts to turn on, and the capacitor Cgd between the gate and the drain of the power switch FET_P starts to be discharged by turning on the power switch FET_P. do. The driving signal GATE does not rise due to the discharge of the capacitor Cgd and maintains the level during the flat period. When the discharge of the capacitor Cgd is completed, the driving signal GATE rises again to the set slope, and when the driving signal GATE reaches a predetermined level and the power switch FET_P is turned on, the current path of the control current I1 is turned on. Is blocked. For example, when the driving signal GATE reaches the half power voltage VDD, the capacitor Cgd starts discharging by turning on the power switch FET_P, and the driving signal GATE is applied to the power voltage VDD. When reaching, the current path of the control current I1 is interrupted by the turn-on of the power switch FET_P.

As such, the driving signal GATE rises to the slope set at the rising point of the PWM signal and remains flat while the capacitor Cgd between the gate and the drain is discharged. When the discharge of the capacitor Cgd is completed, the driving signal GATE rises again to the set slope. When the current path of the control current I1 is blocked by turning on the power switch FET_P, the rising of the driving signal GATE is stopped.

Next, the operation at the time of falling the PWM signal will be described.

When the PWM signal is polled by the gate driver 205, the pull-down driver NMOS is turned on, and a current path of the control current I2 is formed by turning on the pull-down driver NMOS. The capacitor Cgs between the gate and the source of the power switch FET_P is discharged by the control current I2, and the driving signal GATE is lowered to the set slope by the discharge of the capacitor Cgs.

When the driving signal GATE reaches a predetermined level, the power switch FET_P starts to be turned off, and the capacitor Cgd between the gate and the drain of the power switch FET_P is charged by turning off the power switch FET_P. It begins to be. By charging the capacitor Cgd, the driving signal GATE does not fall but maintains the level during the flat period. When charging of the capacitor Cgd is completed, the driving signal GATE falls back to the slope set by the control current I2, and when the driving signal GATE reaches a predetermined level and the power switch FET_P is turned off, the control is performed. The current path of current I2 is interrupted. For example, when the driving signal GATE reaches the half power supply voltage VDD, the capacitor Cgd starts to charge by turning off the power switch FET_P, and the driving signal GATE becomes the ground voltage GND. When is reached, the current path of the control current I2 is interrupted by turning off the power switch FET_P.

As such, the driving signal GATE is lowered to the set slope when the PWM signal is polled, and then remains flat while the capacitor Cgd between the gate and the drain is charged. When the charging of the capacitor Cgd is completed, the driving signal GATE descends again to the set slope. When the current path of the control current I2 is blocked by the turning off of the power switch FET_P, the falling of the driving signal GATE is stopped.

As described above, the present invention adjusts the rise and fall times of the driving signal GATE at the transition point of the PWM signal, so that the drain voltage of the power switch FET_P falls to the ground voltage and the ground voltage rises to the internal voltage VIN. Can be adjusted.

The present invention can reduce the EMI (Electro Magnetic Interference) that can be caused by the repetitive switching of the power switch (FET_P) by adjusting the time when the drain-source voltage of the power switch (FET_P) is changed.

The present invention can control the rise and fall time of the driving signal GATE through the control current, so that the switching time can be accurately controlled regardless of the output impedance variation of the gate driver. Therefore, the present invention can improve the EMI characteristic caused by the switching of the power switch (FET_P).

Claims

In the driving circuit of the lighting device for providing a drive signal to the converter,

An end point generation unit generating a control pulse representing an end point of a minimum on time in accordance with a frequency change of an oscillation signal used to generate the driving signal within a turn-on period of the converter; And

And a minimum on time determination unit configured to provide a minimum on time pulse that defines the minimum on time including the control pulse from the start point of turn-on of the converter to the end point in the turn-on period of the converter. The driving circuit of the lighting device, characterized in that.
The method of claim 1, wherein the end time generation unit,

A control voltage generation circuit generating a control voltage having an increase time depending on a frequency change of an oscillation signal used to generate the driving signal within a turn-on period of the converter; And

And a control pulse generation circuit configured to generate the control pulse whose level is shifted when the control voltage reaches a preset reference voltage.

And the end point is represented by a level transition point of the control pulse.
The circuit of claim 2, wherein the control voltage generation circuit comprises:

A control current supply unit providing a control current whose amount is changed in proportion to a frequency change of the oscillation signal;

A charging element generating a control voltage charged by the control current; And

And a switch configured to limit the control current to the charging element during a turn-on period of the converter.
The method of claim 3, wherein

And the control current supply unit provides the control current by using an oscillator current generated by the oscillation signal output from the oscillator.
The method of claim 2,

The control pulse generation circuit compares the control voltage with the reference voltage, and when the control voltage reaches the reference voltage, the control pulse shifts in level and maintains a transition state while the control voltage is maintained above the reference voltage. The driving circuit of the lighting device including a comparator for outputting.
The method of claim 1, wherein the minimum on time determination unit,

And the minimum on time pulse outputting the minimum on time pulse for enabling the minimum on time by the combination of the drive signal and the control pulse to define the minimum on time.
In the driving circuit of the lighting device for providing a drive signal to the converter,

A start time generation unit generating a control pulse representing a start time of a minimum off time according to a frequency change of an oscillation signal used to generate the driving signal within a turn-off period of the converter; And

A minimum off time determiner configured to provide a minimum off time pulse that defines the minimum off time including the control point from the start time to the turn off end time of the converter in the turn off period of the converter; And a drive circuit of the lighting device.
The method of claim 7, wherein the start time generation unit,

A control voltage generation circuit for generating a control voltage in which an increase time varies according to a frequency change of an oscillation signal used to generate the driving signal within a turn-off period of the converter; And

And a control pulse generation circuit configured to generate the control pulse whose level is shifted when the control voltage reaches a preset reference voltage.

The start time point is represented by a level transition time point of the control pulse.
The method of claim 8, wherein the control voltage generation circuit,

A control current supply unit providing a control current whose amount is changed in proportion to a frequency change of the oscillation signal;

A charging element generating a control voltage charged by the control current; And

And a switch for limiting the control current to the charging element during a turn-off period of the converter.
The method of claim 9,

And the control current supply unit provides the control current by using an oscillator current generated by the oscillation signal output from the oscillator.
The method of claim 8,

The control pulse generation circuit compares the control voltage with the reference voltage, and when the control voltage reaches the reference voltage, the control pulse shifts in level and maintains a transition state while the control voltage is maintained above the reference voltage. The driving circuit of the lighting device including a comparator for outputting.
The method of claim 7, wherein the minimum off time determination unit,

And outputting the minimum off time pulse for maintaining the enable state for the minimum off time by a combination of the drive signal and the control pulse to define the minimum off time.
In the driving circuit of the lighting device for providing a drive signal to the converter,

An end point generation unit configured to generate a first control pulse representing an end point of a minimum on time following a change in frequency of an oscillation signal used to generate the driving signal within a turn-on period of the converter;

A minimum on-time determining unit configured to provide a minimum on-time pulse that defines the minimum on-time including a turn-on start point of the converter to the end point of the converter using the first control pulse within the turn-on period of the converter;

A start point generation unit generating a second control pulse representing a start point of a minimum off time according to a frequency change of the oscillation signal used to generate the driving signal within a turn-off period of the converter; And

Determining a minimum off time within the turn-off period of the converter, using the second control pulse to provide a minimum off time pulse defining the minimum off time including from the start time to the turn off end time of the converter The driving circuit of the lighting device comprising a.
A control current generation circuit for generating a control current; And

And a gate driver configured to receive the control current, generate a drive signal having the control current in response to a PWM signal, and drive a power switch using the drive signal.
The method of claim 14, wherein the gate driver,

And a rising time and a falling time of the driving signal in response to the magnitude of the control current.
15. The circuit of claim 14, wherein the control current generation circuit is

A current generator for generating a current; And

And a current adjusting unit having a current mirror structure for the current generating unit, generating the control current by using the current, and providing the control current to the gate driving unit.
The method of claim 14, wherein the gate driver

A pull-up and pull-down drive in response to the PWM signal, a first current path and a second current path are formed in response to the pull-up and the pull-down drive, and a first control is performed by the first current path and the second current path. A power supply circuit for providing a current and a second control current to the power switch.
The method of claim 17, wherein the gate driver

A power supply driving circuit controlling a time at which the drain voltage of the power switch falls to the ground voltage by using the first control current, and controlling a time at which the ground voltage of the power switch rises to an internal voltage by using the second control current .
LED module;

A converter providing an output voltage to the LED module; And

And a driving circuit configured to generate a driving signal having a control current in response to the PWM signal, and to control the converter using the driving signal.
The method of claim 19,

And the driving circuit controls the rise and fall times of the drive signal in response to the magnitude of the control current.
The method of claim 19, wherein the driving circuit

A current generator for generating a current;

A current adjusting unit having a current mirror structure for the current generating unit and generating and providing the control current using the current; And

And a gate driver configured to receive the control current, generate the driving signal whose rise and fall times are set by the control current in response to the PWM signal, and drive a power switch of the converter.
A current generator for generating a current;

A current adjusting unit having a current mirror structure for the current generating unit, generating the first control current and the second control current using the current, and providing the first control current and the second control current; And

Receiving the first control current and the second control current, driving pull-up and pull-down in response to a PWM signal, and forming a first current path and a second current path in response to the pull-up and pull-down driving to control the first control; And a gate driver configured to provide a current and the second control current to a power switch.
The method of claim 22, wherein the gate driver

The driving signal rising by the first control current is generated when the first current path is formed, and the driving signal falling by the second control current is generated when the second current path is formed, and the driving signal is generated. A driving circuit of the lighting device for driving the power switch using.
The method of claim 22,

The rise and fall time of the drive signal is controlled in correspondence with the magnitude of the first control current and the second control current.