WO2016080244A1

WO2016080244A1 - Optical device

Info

Publication number: WO2016080244A1
Application number: PCT/JP2015/081604
Authority: WO
Inventors: 弘幸森脇
Original assignee: シャープ株式会社
Priority date: 2014-11-19
Filing date: 2015-11-10
Publication date: 2016-05-26

Abstract

An optical device (100) is provided with an optical panel (110) composed of pixels having the reflectivity or transmittance thereof changed according to the magnitude of a voltage applied thereto, and a driver (120) for supplying the optical panel with a signal voltage. The voltage-reflectivity characteristics or voltage-transmittance characteristics of the pixels include hysteresis characteristics, and the threshold voltage in a boosting curve is higher than the threshold voltage in a step down curve. The pixels do not have memory capabilities while the applied voltage is zero. The reflectivity or transmittance is substantially constant from a writing voltage until a prescribed voltage lower than the writing voltage in the step down curve when reducing the applied voltage from the writing voltage. The optical device may execute a standby drive during which the driver is placed in a standby state after the writing drive.

Description

Optical device

The present invention relates to an optical device, and more particularly to an optical device having a pixel whose reflectance or transmittance changes according to the magnitude of an applied voltage.

In recent years, various proposals for reducing power consumption of display devices have been made.

For example, Patent Document 1 discloses a liquid crystal display device using the memory property of cholesteric liquid crystal. The cholesteric liquid crystal has a property (memory property) that can maintain the alignment state when the applied voltage is zero. Therefore, power consumption can be reduced by reducing the number of times image data is written using this memory property.

Patent Document 2 discloses a liquid crystal display device with a built-in pixel memory. In this liquid crystal display device, since a static memory is included in the pixel circuit of each pixel, a refresh operation is not necessary when displaying a still image, and thus power consumption can be reduced.

Japanese Patent Laid-Open No. 10-105085 JP 2007-199441 A International Publication No. 2013/0665529

Since the technology of Patent Document 1 uses the memory property of a cholesteric liquid crystal material that is a constituent material of the display medium layer (liquid crystal layer), naturally, the display medium layer itself has no memory property. Not applicable.

On the other hand, although the technique of Patent Document 2 can be applied to a display device in which the display medium layer itself does not have a memory property, in order to operate the pixel memory when the applied voltage at the time of writing image data is high. Necessary power consumption increases.

The present invention has been made in view of the above problems, and an object thereof is to provide an optical device excellent in low power consumption.

An optical device according to an embodiment of the present invention includes a pixel, and an optical panel in which the reflectance or transmittance of the pixel changes according to the magnitude of a voltage applied to the pixel, and supplies a signal voltage to the optical panel. An optical device, wherein the voltage-reflectance characteristic or voltage-transmittance characteristic of the pixel has hysteresis, and the voltage-reflectance characteristic when the applied voltage is increased or The threshold voltage in the step-up curve showing the voltage-transmittance characteristic is higher than the threshold voltage in the voltage-reflectance characteristic or the step-down curve showing the voltage-transmittance characteristic when the applied voltage is decreased, and the applied voltage is In the state of zero, the pixel does not have a memory property, and the applied voltage is changed from a write voltage that is an applied voltage at the time of writing driving for writing data to the pixel. In the step-down curve when decreasing, the reflectance or transmittance is substantially constant in a range from the write voltage to a predetermined voltage lower than the write voltage, and after performing the write drive, Pause driving for pausing the driver can be performed.

In one embodiment, the reflectance or transmittance value in the boosting curve when the applied voltage is increased from zero is determined substantially in a one-to-one relationship with the voltage value.

In one embodiment, after performing the pause drive, refresh drive can be performed in which the applied voltage that has decreased during the pause drive is returned to the write voltage.

In one embodiment, the write drive and / or the refresh drive are performed over a plurality of frames.

In one embodiment, the period during which the refresh drive is performed is shorter than the period during which the write drive is performed.

In one embodiment, when the pause drive and the refresh drive are alternately and repeatedly performed, the first pause drive is performed and the nth (n is an integer of 2 or more) pause drive is performed. The polarity of the applied voltage is opposite in the period of time.

In one embodiment, the write drive is performed over a plurality of frames, and a waveform pattern of a signal voltage supplied from the driver in a final frame in a period during which the write drive is performed is determined by the driver in a frame before the final frame. This is different from the waveform pattern of the signal voltage supplied from.

In one embodiment, an optical device according to the present invention includes a first substrate and a second substrate provided to face each other, and an optical layer provided between the first substrate and the second substrate. The optical layer includes a medium and shape anisotropic particles dispersed in the medium and having shape anisotropy, the medium includes a liquid crystal material, and a lateral electric field and / or fringe is applied to the optical layer. An electric field can be applied.

In one embodiment, an optical device according to the present invention includes a thin film transistor provided in the pixel, and the thin film transistor includes an oxide semiconductor layer.

According to the embodiment of the present invention, an optical device excellent in low power consumption is provided.

1 is a block diagram schematically showing a display device (optical device) 100 according to an embodiment of the present invention. 4 is a cross-sectional view schematically showing a display panel 110 included in the display device 100, and shows a cross section taken along line 2A-2A 'in FIG. 4 is a plan view schematically showing a display panel 110. FIG. (A) is a figure which shows typically the display panel 110 when the electric field is not applied to the optical layer 30, (b) is the display panel 110 when the fringe electric field is applied to the optical layer 30. FIG. 3 is a diagram schematically showing the display panel 110 when a vertical electric field is applied to the optical layer 30. FIG. 3 is a diagram schematically showing the display panel 110 when a fringe electric field and a lateral electric field are applied to the optical layer 30. FIG. (A) is a figure which shows the mode of the optical layer 30 immediately after changing the electric field currently applied to the optical layer 30 from a fringe electric field and / or a horizontal electric field to a vertical electric field, (b) is enough after that It is a figure which shows the mode of the optical layer 30 after time passes. It is a top view which shows the electrode structure in a test cell. The potential V ₁ of the first electrode 11 in the test cell, the potential V ₂ of the second electrode 12 is a timing chart showing the potential V ₄ in the potential V ₃ and the fourth electrode 21 of the third electrode 13. It is a graph which shows the relationship between pixel voltage (The voltage between the 1st electrode 11, the 2nd electrode 12, and the 3rd electrode 13) Vop (V) and the reflectance (Y value) of a SCE system. The orientation state of the shape anisotropic particles 32 at points A-1, A-2, B-3, B-4, C-5, C-6, C-7, and A-8 in FIG. FIG. It is a graph which shows a step-up curve and a step-down curve when the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage corresponding to white display and then decreasing it again to the off voltage is repeated three times. It is a graph which shows a step-up curve and a step-down curve when the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage and then decreasing it again to the off voltage is repeated five times. 6 is a graph showing a step-up curve and a step-down curve including a point P1 corresponding to data writing in a certain halftone D and a point P2 stepped down therefrom. (A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P1 and P2 in FIG. 14, respectively. It is a graph which shows the pressure | voltage rise curve and pressure | voltage fall curve of the display panel 110 (test cell). (A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P4 and P5 in FIG. 16, respectively. (A) And (b) is a figure which shows the orientation state of the shape anisotropic particle 32 corresponding to the points P6 and P7 in FIG. 16, respectively. 5 is a flowchart illustrating an example of driving in the display device 100. In each of the write drive, resting drive and refresh driving, the potential V ₁ of the first electrode 11, the potential V ₂ of the second electrode 12, the potential V ₃ of the third electrode 13, the potential V ₄ and the gate voltage of the fourth electrode 21 It is a timing chart which shows (scanning signal voltage) Vg. FIG. 6 is a cross-sectional view schematically showing an FFS mode liquid crystal display device 800. (A) And (b) is sectional drawing which shows the liquid crystal display device 900 of patent document 3 typically. It is a figure which shows typically a mode that the weak electric field area | region WR generate | occur | produces in the liquid crystal display device 900 of patent document 3. FIG. FIG. 11 is a diagram schematically showing how a weak electric field region WR is generated in an FFS mode liquid crystal display device 800. (A) And (b) is a figure which shows the electric field produced | generated in the optical layer 30 when 1st write drive WD1 is performed, (a) is 1st write drive WD1 performed. (B) corresponds to the second frame when the first write drive WD1 is performed. It is a figure which shows the state in which the application of a horizontal electric field and a fringe electric field is performed in the liquid crystal display device 900 of patent document 3. FIG. FIG. 11 is a diagram illustrating a state in which a fringe electric field is applied in the FFS mode liquid crystal display device 800. It is a figure which shows the electric field produced | generated by the optical layer 30 at the time of 1st pause drive PD1 start. When the waveform pattern of the signal voltage in the last frame of the first write drive WD1 is made the same as the waveform pattern of the signal voltage in the previous frame, it is generated in the optical layer 30 at the start of the first pause drive PD1. FIG. It is a graph which shows the relationship between the elapsed time after turning off TFT of a pixel, and the retention rate of a pixel voltage, and the attenuation factor of a reflectance. (A) and (b) show the potential V of the first electrode 11 in the first write drive WD1 and the first refresh drive RD1 when the drive frequency is 120 Hz (that is, one frame is about 8.3 msec). _1, the potential V ₂ of the second electrode 12, the potential V ₃ of the third electrode 13 is a timing chart showing the potential V ₄ and the gate voltage (scan signal voltage) Vg of the fourth electrode 21. (A) is a figure which shows the electric field produced | generated in an odd-numbered frame and an even-numbered frame in the case of performing write drive at a comparatively low frequency, (b) is a case in which write drive is performed at a comparatively high frequency. It is a figure which shows the electric field produced | generated in an odd frame and an even frame. 6 is a diagram showing another electrode configuration of the display panel 110. FIG. FIG. 10 is a diagram showing still another electrode configuration of the display panel 110. It is a top view which shows the example of the specific wiring structure in the back substrate 10 in the case of performing active matrix drive. It is a block diagram showing typically electronic equipment 200 provided with display 100 by an embodiment of the present invention.

An optical device according to an embodiment of the present invention includes an optical panel having pixels and a driver that supplies a signal voltage to the optical panel. The optical characteristics (specifically, reflectance or transmittance) of the pixel change depending on the magnitude of the voltage applied to the pixel, and the voltage-reflectance characteristic or voltage-transmittance characteristic of the pixel has a hysteresis characteristic. . Further, the threshold voltage in the curve indicating the voltage-reflectance characteristic or voltage-transmittance characteristic when the applied voltage is increased (hereinafter referred to as “boost curve”) is the voltage when the applied voltage is decreased. The pixel does not have a memory property in a state where it is higher than a threshold voltage in a curve indicating reflectance characteristics or voltage-transmittance characteristics (hereinafter referred to as “step-down curve”) and the applied voltage is zero.

Further, in the optical device according to the embodiment of the present invention, in the step-down curve when the applied voltage is decreased from the write voltage (applied voltage at the time of write driving for writing data to the pixel), the write voltage is more than the write voltage. The reflectance or transmittance is substantially constant in the range up to a low predetermined voltage. Therefore, even if the voltage supply is stopped after writing driving and the applied voltage to the pixel is lowered, the reflectance or transmittance is substantially reduced in a predetermined voltage range after the reduction (that is, in a certain period after the voltage reduction starts). Can be kept constant. Therefore, the power consumption can be reduced by performing the pause drive that pauses the driver after the write drive.

Hereinafter, an optical device according to an embodiment of the present invention will be described in more detail with reference to the drawings. In addition, this invention is not limited to the following embodiment.

FIG. 1 shows an optical device (display device) 100 according to an embodiment of the present invention. FIG. 1 is a block diagram schematically showing the display device 100.

The display device 100 includes an optical panel (display panel) 110 and a driver (drive circuit) 120 as shown in FIG.

The display panel 110 has pixels whose reflectance or transmittance changes according to the magnitude of the applied voltage. Here, the display panel 110 includes a plurality of pixels arranged in a matrix and is driven by an active matrix method.

The driver 120 supplies a signal voltage to the display panel 110. In the example illustrated in FIG. 1, the display device 100 includes a gate driver (scanning line driver circuit) 120 g that supplies a scanning signal voltage to the display panel 110 and a source driver (a source driver that supplies the display signal voltage to the display panel 110). Signal line driving circuit) 120s.

Here, a specific configuration of the display panel 110 will be described with reference to FIGS. 2 and 3.

FIG. 2 is a cross-sectional view schematically showing the display panel 110, and FIG. 3 is a plan view schematically showing the display panel 110. FIG. 2 shows a cross section taken along line 2A-2A 'in FIG. Here, the display panel 110 is a reflective display panel that can perform display in a reflection mode using light incident from the outside (ambient light).

As shown in FIG. 2, the display panel 110 includes a first substrate 10 and a second substrate 20 provided so as to face each other, and an optical layer (display) provided between the first substrate 10 and the second substrate 20. Medium layer) 30. Hereinafter, of the first substrate 10 and the second substrate 20, the first substrate 10 positioned relatively on the back side may be referred to as a “back side substrate” and may be referred to relatively on the front side (that is, on the viewer side). The second substrate 20 positioned at () may be referred to as a “front substrate”.

The first substrate (back substrate) 10 has a first electrode 11 and a second electrode 12 that can be given different potentials. The first electrode 11 and the second electrode 12 are provided in each of the plurality of pixels. Each of the 1st electrode 11 and the 2nd electrode 12 has a comb-tooth shape, as shown in FIG.

The first electrode 11 has a trunk portion 11b and a plurality of branch portions 11a extending from the trunk portion 11b. Similarly, the second electrode 12 includes a trunk portion 12b and a plurality of branch portions 12a extending from the trunk portion 12b. The first electrode 11 and the second electrode 12 are arranged so that the plurality of

branch portions

11a and 12a mesh with each other via a predetermined gap (hereinafter also referred to as “interelectrode distance”) g. Yes.

There is no restriction | limiting in particular in the distance g between electrodes. Further, the width w ₁ of the branch part 11 a of the first electrode 11 and the width w ₂ of the branch part 12 a of the second electrode 12 are not particularly limited. The inter-electrode distance g, the width w ₁ of the branch portion 11a of the first electrode 11, and the width w ₂ of the branch portion 12a of the second electrode 12 are each about several μm to several tens of μm, for example. The width w ₁ of the branch portion 11a of the first electrode 11 and the width w ₂ of the branch portion 12a of the second electrode 12 may be the same or different.

The first substrate 10 further includes a third electrode 13 provided below the first electrode 11 and the second electrode 12 with the insulating layer 14 interposed therebetween. Hereinafter, the first electrode 11, the second electrode 12, and the third electrode 13 may be referred to as “first upper layer electrode”, “second upper layer electrode”, and “lower layer electrode”, respectively. In the example shown in FIGS. 2 and 3, the third electrode 13 is a so-called solid electrode in which no slit or notch is formed.

The first substrate 10 is typically an active matrix substrate, and includes a plurality of thin film transistors (TFTs) provided in each pixel and various wirings (a gate wiring, a source wiring, etc. electrically connected to the TFT). (Both not shown here). The first electrode 11, the second electrode 12, and the third electrode 13 are electrically connected to the corresponding TFTs, respectively.

The first substrate 10 further includes a light absorption layer 16 that absorbs light. There is no restriction | limiting in particular in the material of the light absorption layer 16. FIG. As a material of the light absorption layer 16, for example, a pigment used for a black matrix material included in a color filter of a liquid crystal display device or the like can be used. Alternatively, a low-reflection chromium film having a two-layer structure (having a structure in which a chromium layer and a chromium oxide layer are stacked) can be used as the light absorption layer 16.

The components of the first substrate 10 (such as the first electrode 11 described above) are supported by an insulating substrate (for example, a glass substrate) 10a. In FIG. 2, the light absorption layer 16 is provided on the back side of the substrate 10a. However, the light absorption layer 16 may be provided on the optical layer 30 side of the substrate 10a.

The second substrate (front substrate) 20 has a fourth electrode (counter electrode) 21 facing the first electrode 11, the second electrode 12 and the third electrode 13. The fourth electrode 21 may be a so-called solid electrode in which no slit or notch is formed. In the example illustrated in FIG. 2, the second substrate 20 further includes a dielectric layer (overcoat layer) 22 provided on the fourth electrode 21. The fourth electrode 21 does not need to be electrically independent for each pixel, and may be a continuous single conductive film (that is, a common electrode) common to all pixels. When the fourth electrode 21 is a solid electrode common to all the pixels, patterning by a photolithography technique is not necessary, so that the manufacturing cost can be reduced. When performing color display, the second substrate 20 includes a color filter (not shown).

The components of the second substrate 20 (such as the fourth electrode 21 described above) are supported by an insulating substrate (for example, a glass substrate) 20a.

Each of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 is made of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide). There is no particular limitation on the method for depositing the conductive film to be these electrodes, and various known methods such as a sputtering method, a vacuum evaporation method, and a plasma CVD method can be used. Further, there is no particular limitation on the method for patterning the conductive film in order to form the first electrode 11 and the second electrode 12 having a comb-teeth shape, and a known patterning method such as photolithography can be used. The thicknesses of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 are, for example, 100 nm.

The optical characteristics of the optical layer 30 change according to the applied electric field. The optical layer 30 includes a liquid medium 31 and particles 32 dispersed in the medium 31 and having shape anisotropy (hereinafter referred to as “shape anisotropic particles”). The first substrate 10 and the second substrate 20 described above are bonded together via a seal portion (not shown here) formed so as to surround the display region, and the medium 31 and the shape anisotropic particles 32 are: It is enclosed in a region (that is, a display region) surrounded by the seal portion. There is no particular limitation on the thickness (cell gap) of the optical layer 30. The thickness of the optical layer 30 is, for example, 5 μm to 30 μm.

The shape anisotropic particle 32 has light reflectivity. The shape anisotropic particle 32 has, for example, a flake shape (flaky shape).

The orientation direction of the shape anisotropic particles 32 changes according to the electric field (voltage) applied to the optical layer 30. Since the shape anisotropic particles 32 have shape anisotropy, when the orientation direction of the shape anisotropic particles 32 changes, the substrate surface of the shape anisotropic particles 32 (the substrate surface of the first substrate 10). The projected area on the screen also changes, and the optical characteristics (reflectance in this case) of the optical layer 30 change accordingly. The display panel 110 performs display using this fact. The reason why the orientation direction of the shape anisotropic particles 32 changes according to the applied electric field will be described in detail later.

In the display panel 110 according to the present embodiment, the medium 31 is a liquid crystal material and includes liquid crystal molecules. Here, the liquid crystal material is a nematic liquid crystal material having positive dielectric anisotropy. That is, the medium 31 is a so-called positive nematic liquid crystal material, and the dielectric constant ε _{// in} the major axis direction of the liquid crystal molecules is larger than the dielectric constant ε _{の in the} minor axis direction. Since the medium 31 is a nematic liquid crystal material, the pixel does not have a memory property when the applied voltage is zero.

Each of the first substrate 10 and the second substrate 20 has

vertical alignment films

15 and 25 provided on the optical layer 30 side. The

vertical alignment films

15 and 25 have an alignment regulating force for vertically aligning liquid crystal molecules contained in the medium (liquid crystal material) 31 (aligned substantially perpendicularly to the substrate surface of the first substrate 10 or the second substrate 20). Further, the

vertical alignment films

15 and 25, as will be described in detail later, are alignment restrictions that cause the shape anisotropic particles 32 to be vertically aligned (aligned substantially perpendicularly to the substrate surface of the first substrate 10 or the second substrate 20). Also has power. Note that the vertical alignment film is not necessarily provided on both the first substrate 10 and the second substrate 20, and the vertical alignment film may be provided on only one (for example, only the first substrate 10).

In the display panel 110 according to the present embodiment, a fringe electric field is generated in the optical layer 30 by the first electrode (first upper layer electrode) 11, the second electrode (second upper layer electrode) 12, and the third electrode (lower layer electrode) 13. Is done. In the display device 100 according to the embodiment of the present invention, a vertical electric field is generated in the optical layer 30 by the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode (counter electrode) 21.

Hereinafter, the reason why the orientation direction of the shape anisotropic particles 32 changes according to the applied electric field (applied voltage) will be described in more detail with reference to FIGS. 4 (a) and 4 (b). 4A is a diagram schematically showing the display panel 110 when no electric field is applied to the optical layer 30, and FIG. 4B is a diagram when a fringe electric field is applied to the optical layer 30. It is a figure which shows typically the display panel 110 of.

When no electric field is applied to the optical layer 30, as shown in FIG. 4 (a), the shape anisotropic particles 32 are first (its longitudinal direction) due to the alignment regulating force of the

vertical alignment films

15 and 25. The substrate 10 is oriented so as to be substantially perpendicular to the substrate surface (that is, in a vertically oriented state). In addition, the alignment of the liquid crystal molecules substantially perpendicular to the substrate surface by the alignment regulating force of the

vertical alignment films

15 and 25 serves to support the shape anisotropic particles 32 taking a vertical alignment state. In this state, most of the incident ambient light L is transmitted through the optical layer 30. That is, the optical layer 30 is in a transparent state. Since ambient light transmitted through the optical layer 30 is absorbed by the light absorption layer 16, black display can be performed in this state. In the present specification, “the shape anisotropic particles 32 are oriented substantially perpendicular to the substrate surface” means that the shape anisotropic particles 32 are oriented strictly perpendicular to the substrate surface. Refers to a state of being oriented at an angle exhibiting substantially the same optical characteristics as the state of being, specifically, the shape anisotropic particles 32 are oriented at an angle of 75 ° or more with respect to the substrate surface. Refers to the state.

As shown in FIG. 4B, when a fringe electric field (represented by the electric lines of force Ef) is applied to the optical layer 30, the shape anisotropic particles 32 have a longitudinal direction of the first substrate 10. Align so as to be substantially parallel to the substrate surface (that is, take a horizontal alignment state). The liquid crystal molecules are also aligned substantially parallel to the substrate surface of the first substrate 10. In this state, most of the incident ambient light L is reflected by the shape anisotropic particles 32 in the optical layer 30. That is, the optical layer 30 is in a reflective state, and white display can be performed in this state. Further, halftone display can be performed by applying a voltage lower than that during white display.

In the display panel 110, the second substrate 20 includes the fourth electrode 21 that faces the first electrode 11, the second electrode 12, and the third electrode 13, and thus generates a vertical electric field in the optical layer 30. You can also.

As shown in FIG. 5, when a longitudinal electric field (represented by electric lines of force Ev) is applied to the optical layer 30, the shape anisotropic particles 32 (on the longitudinal direction) are formed on the substrate surface of the first substrate 10. Align so as to be substantially vertical (that is, take a vertical alignment state). The liquid crystal molecules are also aligned substantially perpendicular to the substrate surface of the first substrate 10. In this state, most of the incident ambient light L is transmitted through the optical layer 30. That is, the optical layer 30 is in a transparent state. Since ambient light transmitted through the optical layer 30 is absorbed by the light absorption layer 16, black display can be performed in this state.

In addition, when performing white display and halftone display, a lateral electric field (represented by an electric force line Eh) may be applied to the optical layer 30 in addition to the fringe electric field, as shown in FIG. A transverse electric field can be generated by the first electrode 11 and the second electrode 12. In this specification, an electric field generated by a potential difference between two electrodes provided on the same substrate on the same level is called a “lateral electric field”, and is generated by a potential difference between two electrodes provided on different levels on the same substrate. The electric field is called a “fringe electric field”. Further, in this specification, a mode in which display is performed by applying a fringe electric field and / or a lateral electric field to the optical layer 30 is referred to as a “lateral electric field mode”, and a mode in which display is performed by applying a vertical electric field to the optical layer 30. This is called “vertical electric field mode”.

The orientation change of the shape anisotropic particles 32 as described above is caused by the dielectrophoretic force due to the interaction between the electric field and the electric dipole moment induced thereby. Hereinafter, a more specific description will be given with reference to FIGS. 7 (a) and 7 (b). FIGS. 7A and 7B show the optical layer immediately after the electric field applied to the optical layer 30 is changed from a fringe electric field and / or a horizontal electric field to a vertical electric field, and after a sufficient time has elapsed thereafter. It is a figure which shows the mode 30 (electric charge distribution and an electric force line).

When the dielectric constant of the shape anisotropic particle 32 and the dielectric constant of the medium 31 are different, when the direction of the electric field applied to the optical layer 30 changes, as shown in FIG. Large distortion occurs. Therefore, as shown in FIG. 7B, the shape anisotropic particles 32 rotate so that the energy is minimized.

In general, the dielectrophoretic force F _dep acting on particles dispersed in a medium is expressed as follows, where the dielectric constant of the particles is ε _p , the dielectric constant of the medium is ε _m , the radius of the particles is a, and the strength of the electric field is E. It is represented by Formula (1). Re in the expression (1) is an operator that extracts a real part. In the present embodiment, the medium 31 is a liquid crystal material and has dielectric anisotropy. That is, the dielectric constant epsilon _⊥ the long axis direction of the dielectric constant epsilon _// and the minor axis direction of liquid crystal molecules is different, is considered to correspond to _{_{_{ε m = ε // -ε ⊥ =}}} Δε.

Further, as can be seen from the above description, in addition to the above-described dielectrophoretic force, the shape anisotropic particles 32 are allowed to develop a vertical alignment state by the alignment regulating force of the

vertical alignment films

15 and 25 and the support of liquid crystal molecules. Thus, the vertical alignment operation and the horizontal alignment operation of the shape anisotropic particles 32 can be suitably switched.

As described above, in the display panel 110, the orientation direction of the shape anisotropic particles 32 can be changed by applying a voltage to the optical layer 30, and display can be performed using this. Since the display panel 110 does not require a polarizing plate, high light utilization efficiency can be realized.

反射 The reflectance of each pixel changes according to the magnitude of the voltage applied to the pixel. In the display panel 110 having the above-described configuration, the voltage-reflectance characteristic of the pixel has a hysteresis characteristic. Hereinafter, this hysteresis property will be specifically described. In the following explanation, the step-up curve (showing voltage-reflectance characteristics when the applied voltage is increased) and the step-down curve (showing voltage-reflectance characteristics when the applied voltage is reduced) are shown as examples. The display panel 110 having the above-described configuration was actually prototyped (that is, a test cell was manufactured), and the test cell was obtained.

The test cell adopts an electrode structure as shown in FIG. 8 instead of active matrix driving. In the electrode structure shown in FIG. 8,

terminals

11t, 12t, and 13t are provided at the respective ends of the first electrode 11, the second electrode 12, and the third electrode 13. A voltage having a desired waveform was input from the arbitrary waveform generator to the first electrode 11, the second electrode 12, and the third electrode 13 via the

terminals

11t, 12t, and 13t.

In the test cell, the optical layer 30 has a thickness (cell thickness) of 15 μm. The medium 31 is a positive nematic liquid crystal material (manufactured by Merck & Co., Inc.) having a dielectric anisotropy Δε of 20.4. The average particle diameter of the shape anisotropic particles 32 is 7 μm, and the content of the shape anisotropic particles 32 in the optical layer 30 is 6% by weight. The

substrates

10a and 20a are glass substrates, respectively. Each of the first electrode (first upper layer electrode) 11 and the second electrode (second upper layer electrode) 12 has a comb-tooth shape. The third electrode (lower layer electrode) 13 has a plurality of slits (see FIG. 34 described later). The fourth electrode (counter electrode) 21 is a solid electrode. Each of the first electrode 11, the second electrode 12, the third electrode 13, and the fourth electrode 21 is made of IZO and has a thickness of 100 nm. The width w ₁ of the branch portion 11a of the first electrode 11 and the width w ₂ of the branch portion 12a of the second electrode 12 are each 3 μm, and the inter-electrode distance g is 10 μm. The insulating layer 14 is made of SiNx and has a thickness of 350 nm. The overcoat layer 22 is formed of a photoresist (manufactured by Toppan Printing Co., Ltd.) having a relative dielectric constant εr = 3.4, and has a thickness of 3 μm. The

vertical alignment films

15 and 25 are polyamic acid-based vertical alignment films (manufactured by Nissan Chemical Industries) having a surface energy of 35 mJ / m ² .

9, the potential V ₁ of the first electrode 11 in the test cell, the potential V ₂ of the second electrode 12 is a timing chart showing the potential V ₄ in the potential V ₃ and the fourth electrode 21 of the third electrode 13. As shown in FIG. 9, the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 is a rectangular wave having a period of four frames, each frame within one period (about 16.7 msec) Change to + aV, 0V, -aV, 0V. The potential V ₃ and the potential V ₄ of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential).

FIG. 10 shows the step-up curve and the step-down curve of the display panel 110 (test cell). FIG. 10 is a graph showing the relationship between the pixel voltage (the voltage between the first electrode 11 and the second electrode 12 and the third electrode 13) Vop (V) and the reflectance (Y value) of the SCE method. .

As can be seen from FIG. 10, the voltage-reflectance characteristic of the pixel has a hysteresis characteristic, and the threshold voltage in the boost curve is higher than the threshold voltage in the buck curve. In the step-down curve when the applied voltage is decreased from the write voltage, the reflectance is substantially constant in a range r from the write voltage to a predetermined voltage lower than the write voltage. Here, “the reflectance is substantially constant” specifically means that the reflectance R is 0.8 times or more the reflectance Rw when the write voltage is applied within the range r. It means that it is 2 times or less (that is, the relationship of 0.8Rw ≦ R ≦ 1.2Rw is satisfied). Further, the reflectance value in the boost curve when the applied voltage is increased from zero is substantially determined in a one-to-one relationship with the voltage value. Hereinafter, the mechanism by which such hysteresis is developed will be described with reference to FIG.

FIG. 11 shows the orientation state of the shape anisotropic particles 32 at points A-1, A-2, B-3, B-4, C-5, C-6, C-7 and A-8 in FIG. FIG. As can be seen from FIG. 11 (see the alignment states corresponding to points A-1, A-2, B-3, B-4, and C-5), as the applied voltage increases, the optical layer 30 increases. The electric field strength in the thickness direction (cell thickness direction) increases. Accordingly, the shape anisotropic particles 32 in the vertical alignment state move to the first substrate 10 side and are horizontally aligned. Further, as can be seen from FIG. 11 (see the alignment state corresponding to points C-6 and C-7), the applied voltage is applied from the state in which many shape anisotropic particles 32 are horizontally aligned on the first substrate 10 side. However, since the shape anisotropic particles 32 do not exist so much on the counter substrate 20 side where the electric field strength is weak, most of the shape anisotropic particles 32 are in the horizontal alignment state on the first substrate 10 side. To maintain. This is the cause of the hysteresis. In addition, as can be seen from FIG. 11 (see the alignment state corresponding to points A-8 and A-1), as the applied voltage is further reduced, the shape anisotropy can no longer maintain the horizontal alignment state. The particles 32 diffuse toward the second substrate 20 side.

As can be seen from the above description, the step-up curve and the step-down curve (see FIG. 10) of the display panel 110 include three regions A, B, and C. In the region A (including points A-1, A-2, and A-8), the orientation direction of the shape anisotropic particles 32 on the first substrate 10 side where the electric field strength is relatively strong changes. In the region B (including points B-3 and B-4), the shape anisotropic particles 32 on the second substrate 20 side having relatively weak electric field strength move to the first substrate 10 side, and the orientation direction thereof changes. To do. In the region C (including the points C-5, C-6, and C-7), the shape anisotropic particles 32 maintain the horizontal alignment state on the first substrate 10 side.

As described above, in the display device 100 according to the embodiment of the present invention, the voltage-reflectance characteristic of the pixel has a hysteresis characteristic, and the write voltage in the step-down curve when the applied voltage is decreased from the write voltage. The reflectivity is substantially constant in a range from a voltage to a predetermined voltage lower than the write voltage (range r in FIG. 10). Therefore, even if the voltage supply is stopped after writing driving and the applied voltage to the pixel is lowered, the reflectivity is maintained substantially constant in a predetermined voltage range after the reduction (that is, in a certain period after the voltage reduction starts). can do. Therefore, the power consumption can be reduced by performing the pause drive that pauses the driver 120 after the write drive.

Further, in the display device 100, the reflectance value in the boosting curve when the applied voltage is increased from zero is substantially determined in a one-to-one relationship with the voltage value. Therefore, halftone display can be suitably performed by setting the write voltage based on the boost curve. On the other hand, since the pixel memory used in the technique of Patent Document 2 is a binary digital circuit, the technique of Patent Document 2 cannot perform halftone display.

Here, the display method using the hysteresis characteristic will be described more specifically.

First, black display and white display will be described. FIG. 12 shows the result of verifying the repeatability of hysteresis. FIG. 12 is a graph showing a step-up curve and a step-down curve when the driving of increasing the pixel voltage Vop from the off-voltage (0 V) to the writing voltage corresponding to white display and then reducing it again to the off-voltage is repeated three times. It is.

From FIG. 12, it can be seen that the first time, the second time and the third time pressure increase curve and the pressure decrease curve are overlapped, and the hysteresis property is reproduced with high accuracy. Accordingly, it is possible to suitably perform switching between black display and white display repeatedly.

Next, the halftone display will be explained. First, switching between black display and halftone display will be described with reference to FIG. FIG. 13 is a graph showing a step-up curve and a step-down curve when the driving of increasing the pixel voltage Vop from the off voltage (0 V) to the writing voltage and then decreasing the pixel voltage Vop again to the off voltage is repeated five times. The first and fifth writing voltages are voltages corresponding to white display, whereas the second, third and fourth writing voltages are voltages corresponding to halftone display.

FIG. 13 shows that the boosting curve in the second and subsequent driving matches the boosting curve in the first driving. For this reason, switching from the black display to the halftone display may be performed by writing data with the pixel voltage Vop having a reflectance corresponding to the desired halftone display in accordance with the boost curve. In addition, it can be seen from FIG. 13 that there is a range r in which the reflectance is substantially constant in the step-down curve after the data is written with the voltage corresponding to the halftone display.

Next, with reference to FIG. 14 and FIG. 15, switching from a halftone (halftone D) display to a higher halftone (halftone E) display or white display will be described. FIG. 14 is a graph showing a step-up curve and a step-down curve including the point P1 corresponding to data writing in the halftone D and the point P2 stepped down from the point P2 within the range r described above. ) Is a diagram showing the orientation state of the shape anisotropic particles 32 corresponding to the points P1 and P2, respectively.

As can be seen from FIG. 14, a state in which the write voltage corresponding to the halftone D is applied to the pixel (point P1: see FIG. 15A) and a state in which the voltage is stepped down within the range r from that state (point P2: FIG. 15 (b)) is reversible. That is, in the voltage range (corresponding to the region C in FIG. 10) in which the shape anisotropic particles 32 maintain the horizontal alignment state on the first substrate 10 side, the change in the alignment state is reversible. For this reason, switching from the display of halftone D to the display of halftone E on the higher gradation side (or white display) is performed by changing the write voltage corresponding to halftone E as it is from the step-down state after writing the data of halftone D. Application may be performed (point P3 in FIG. 14).

Subsequently, switching from white or a certain halftone D display to a lower halftone (halftone F) display will be described with reference to FIGS. FIG. 16 is a graph showing a step-up curve and a step-down curve. FIGS. 17A, 17B, 18A, and 18B are respectively shown at points P4, P5, P6, and P7 in FIG. It is a figure which shows the orientation state of the corresponding shape anisotropic particle.

When white or halftone D data is written and then stepped down within the range r and then the pixel voltage Vop is further reduced to the point P4, the step-down curve differs depending on the magnitude of the previous writing voltage. For this reason, the pixel voltage Vop and the reflectance are not determined in a one-to-one relationship. In addition, when data is written by increasing the pixel voltage Vop from the point P4, the boosting curve differs depending on the amount of the shape anisotropic particles 32 maintaining the horizontal alignment state. Vop and reflectance are not determined in a one-to-one relationship. Therefore, when switching from white or a certain halftone D display to a lower halftone F display, the pixel voltage Vop is once set to zero (hereinafter also referred to as “black insertion”). Accordingly, the pixel voltage Vop and the reflectance can be determined in a one-to-one relationship according to a boosting curve (including points P6 and P7) with the starting point being zero. From FIG. 16, after black insertion is performed, data is written with the write voltage corresponding to the halftone F (point P7), and when data is written directly from the point P4 with the write voltage corresponding to the halftone F. It can be seen that the reflectance is different between (Point P5).

Thus, when the reflectance corresponding to the applied voltage of the current frame is higher than the reflectance corresponding to the writing voltage of the next frame, the applied voltage to the pixel is once reduced to zero, and then the original writing voltage is applied to the pixel. do it.

As described above, in the display device 100 according to the embodiment of the present invention, after performing the write drive, the drive 120 can be paused so that the power consumption can be reduced. Note that the reflectance Rp of the pixel in the period in which the pause driving is performed is 0.9 to 1.1 times the reflectance Rw of the pixel when the writing voltage is applied (that is, 0.9 Rw). ≦ Rp ≦ 1.1Rw is satisfied). If the former reflectance Rp is 0.9 times or more and 1.1 times or less than the latter reflectance Rw, it is difficult for an observer to recognize a change in reflectance due to rest driving.

In addition, if the period of pause driving is too long, the reflectance Rp of the pixel may be too low (below 0.9 times the reflectance Rw of the pixel when the writing voltage is applied). . For this reason, it is preferable that the display device 100 can perform refresh driving that returns the applied voltage, which has been reduced during the period of performing pause driving, to the writing voltage after performing pause driving. By performing the refresh drive, the reflectance of the pixel can be kept sufficiently high.

An example of driving in the display device 100 capable of performing refresh driving in addition to writing driving and pause driving will be described with reference to FIGS. 19 and 20. FIG. 19 is a flowchart illustrating an example of driving in the display device 100. Further, FIG. 20, in each of the write drive, resting drive and refresh driving, the potential V ₁ of the first electrode 11, the potential V ₂ of the second electrode 12, the potential V ₃ of the third electrode 13, the fourth electrode 21 potential V ₄ and the gate voltage is a timing chart showing the (scan signal voltage) Vg.

In the example shown in FIGS. 19 and 20, first write drive WD1 is performed first. In the first write drive WD1, the signal voltage is naturally supplied from the gate driver 120g and the source driver 120s (that is, the driver 120 is on). In the first write driver WD1, the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 is a rectangular wave having a period of four frames, if one frame (60 Hz driving in one cycle, It changes to + 10V, 0V, -10V, 0V every about 16.7msec). However, the potential V ₁ of the first electrode 11 and the potential V ₂ of the second electrode 12, one frame of phase (towards the potential V ₂ of the second electrode 12 is delayed by one frame). The potential V ₃ and the potential V ₄ of the fourth electrode 21 of the third electrode 13 is much 0V (ground potential).

When the response time of the display panel 110 is, for example, about 600 msec, the first write drive WD1 is performed for 9 cycles (36 frames). In the example shown in FIG. 20, the waveform pattern of the signal voltage in the last frame of the first write drive WD1 is different from the waveform pattern of the signal voltage in the frame before the last frame. More specifically, in the frame before the last frame, whereas the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 are different from each other in the final frame, the potential of the first electrode 11 V ₁ and the potential V ₂ of the second electrode 12 are the same (both are −10 V).

Next, the first pause drive PD1 is performed. In the first pause drive PD1, no signal voltage is supplied from the gate driver 120g and the source driver 120s, and the gate driver 120g and the source driver 120s are paused (that is, the driver 120 is off). Therefore, the gate voltage Vg remains off voltage much, the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 is gradually with time from the first rest driving PD1 starting -10V It approaches 0V. Potential V ₃ and the potential V ₄ of the fourth electrode 21 of the third electrode 13 is much 0V. The length of the period during which the first pause drive PD1 is performed is, for example, 40 seconds.

Subsequently, the first refresh drive RD1 is performed. Also in the first refresh drive RD1, the signal voltage is supplied from the gate driver 120g and the source driver 120s (that is, the driver 120 is in the on state). In the first refresh driving RD1, the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 is a rectangular wave having a period of four frames, -10 V for each frame within one period, 0V , + 10V and 0V. However, the potential V ₁ of the first electrode 11 and the potential V ₂ of the second electrode 12, one frame of phase (towards the potential V ₁ of the first electrode 11 is delayed by one frame). The potential V ₃ and the potential V ₄ of the fourth electrode 21 of the third electrode 13 is much 0V.

The first refresh drive RD1 is performed, for example, for 3 periods (12 frames). In addition, the waveform pattern of the signal voltage in the last frame of the first refresh drive RD1 is different from the waveform pattern of the signal voltage in the frame before the last frame. More specifically, in the frame before the last frame, whereas the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 are different from each other in the final frame, the potential of the first electrode 11 V ₁ and the potential V ₂ of the second electrode 12 are the same (both are +10 V).

Next, the second pause drive PD2 is performed. In the second pause drive PD2, the signal voltage is not supplied from the gate driver 120g and the source driver 120s, and the gate driver 120g and the source driver 120s are paused (that is, the driver 120 is off). Therefore, the gate voltage Vg remains off voltage much, the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 gradually with time from the second rest driving PD2 starting + 10V It approaches 0V. Potential V ₃ and the potential V ₄ of the fourth electrode 21 of the third electrode 13 is much 0V. The length of the period during which the second pause drive PD2 is performed is, for example, 40 seconds.

Subsequently, the second refresh drive RD2 is performed. Also in the second refresh drive RD2, a signal voltage is supplied from the gate driver 120g and the source driver 120s (that is, the driver 120 is in an on state). In the second refresh driving RD2, the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 is a rectangular wave having a period of four frames, + 10V for each frame within one period, 0V, Varies between -10V and 0V. However, the potential V ₁ of the first electrode 11 and the potential V ₂ of the second electrode 12, one frame of phase (towards the potential V ₂ of the second electrode 12 is delayed by one frame). The potential V ₃ and the potential V ₄ of the fourth electrode 21 of the third electrode 13 is much 0V.

The second refresh drive RD2 is performed, for example, for 3 cycles (12 frames). Further, the waveform pattern of the signal voltage in the last frame of the second refresh drive RD2 is different from the waveform pattern of the signal voltage in the frame before the last frame. More specifically, in the frame before the last frame, whereas the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 are different from each other in the final frame, the potential of the first electrode 11 V ₁ and the potential V ₂ of the second electrode 12 are the same (both are −10 V).

Next, the first pause drive PD1 is performed again. Thereafter, the first refresh drive RD1, the second pause drive PD2, the second refresh drive RD2, and the first pause drive PD1 are repeated, or the second write drive WD2 is performed.

In the second write drive WD2, the signal voltage is naturally supplied from the gate driver 120g and the source driver 120s (that is, the driver 120 is in the on state). In the second write driver WD2, the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 is a rectangular wave having a period of four frames, -10 V for each frame within one period, 0V , + 10V and 0V. However, the potential V ₁ of the first electrode 11 and the potential V ₂ of the second electrode 12, one frame of phase (towards the potential V ₂ of the second electrode 12 is delayed by one frame). The potential V ₃ and the potential V ₄ of the fourth electrode 21 of the third electrode 13 is much 0V.

The second write drive WD2 is performed, for example, for 9 cycles (36 frames). In addition, the waveform pattern of the signal voltage in the last frame of the second write drive WD2 is different from the waveform pattern of the signal voltage in the frame before the last frame. More specifically, in the frame before the last frame, whereas the potential V ₂ of the potentials V ₁ and second electrode 12 of the first electrode 11 are different from each other in the final frame, the potential of the first electrode 11 V ₁ and the potential V ₂ of the second electrode 12 are the same (both are +10 V).

Here, for the sake of simplicity of explanation, a case where data writing of the same gradation is performed by the first write drive WD1 and the second write drive WD2 is shown. Data writing of different gradations may be performed between the write drive WD1 and the second write drive WD2.

After the second write drive WD2, the second pause drive PD2, the second refresh drive RD2, the first pause drive PD1, the first refresh drive RD1, and the second pause drive PD2 are sequentially performed. Thereafter, the second refresh drive RD2, the first pause drive PD1, the first refresh drive RD1, and the second pause drive PD2 are repeated, or the first write drive WD1 is performed.

In the example described with reference to FIGS. 19 and 20, each of the first write drive WD1, the second write drive WD2, the first refresh drive RD1, and the second refresh drive RD2 is performed over a plurality of frames. . When the response speed of the display panel 110 is not sufficiently high, a sufficiently high reflectivity may not be obtained only by performing one frame of write driving and / or refresh driving. By performing the writing drive and / or the refresh drive over a plurality of frames, a sufficiently high reflectance can be obtained.

In the example described above, the period in which each of the first refresh drive RD1 and the second refresh drive RD2 is performed is shorter than the period in which each of the first write drive WD1 and the second write drive WD2 is performed. . This is because most of the shape anisotropic particles 32 maintain the same alignment state as at the time of data writing at the start of the refresh drive, so that some shape anisotropic particles 32 are reoriented in the refresh drive. It is only necessary. By making the period during which refresh driving is performed shorter than the period during which writing driving is performed, further reduction in power consumption can be realized.

Furthermore, in the above-described example, the polarity of the voltage applied to the pixels is opposite between the period in which the first pause drive PD1 is performed and the period in which the second pause drive PD2 is performed. In other words, the polarity of the applied voltage is reversed every pause driving. In the period in which the pause driving is performed, a DC voltage is continuously applied to the optical layer 30. However, by performing the polarity reversal as described above, the bias of the electric field is alleviated and seizure due to adsorption of ionic impurities. It is possible to suppress a decrease in reliability. Note that it is not always necessary to perform the polarity reversal for each pause drive. For example, the polarity inversion may be performed after the pause drive with the same polarity applied voltage is performed twice or more. That is, when the pause drive and the refresh drive are alternately repeated, the first pause drive is performed and the n-th (n is an integer of 2 or more) pause drive is performed. The polarity of the applied voltage may be opposite. However, from the viewpoint of suppressing the decrease in reliability, it is preferable to perform polarity inversion every pause drive.

In the example described above, the waveform pattern of the signal voltage in the last frame in the period in which each of the first write drive WD1 and the second write drive WD2 is performed is the waveform pattern of the signal voltage in the frame before the last frame. Is different. This makes it possible to apply a voltage with a waveform pattern suitable for sufficiently increasing the reflectance during writing driving, and to realize an electric field distribution in which the reflectance is stably maintained during rest driving. be able to. Hereinafter, this will be described more specifically.

First, the reason why the illustrated waveform pattern in the write drive is suitable for sufficiently increasing the reflectance will be described. The applicant of the present application has made various studies in order to further improve the light utilization efficiency of a display panel including an optical layer containing shape anisotropic particles. Hereinafter, the knowledge obtained by the examination will be described.

As a display mode of a liquid crystal display device, a VA (Vertical Alignment) mode and an FFS (Fringe Field Switching) mode are known. In the VA mode, display is performed by applying a vertical electric field to the vertically aligned liquid crystal layer. On the other hand, in the FFS mode, display is performed by applying a fringe electric field to the horizontally aligned liquid crystal layer.

FIG. 21 shows a general structure of an FFS mode liquid crystal display device. A liquid crystal display device 800 illustrated in FIG. 21 includes a TFT substrate 810 and a counter substrate 820, and a liquid crystal layer 830 provided therebetween.

The TFT substrate 810 is provided on the transparent substrate 810a, the common electrode (lower layer electrode) 812 provided on the transparent substrate 810a, the insulating layer 813 provided to cover the common electrode 812, and the insulating layer 813. A pixel electrode (upper layer electrode) 811.

The pixel electrode 811 has a comb shape. The pixel electrode 811 has a plurality of comb teeth 811a extending in a predetermined direction and slits 811b formed between adjacent comb teeth 811a.

The counter substrate 820 includes a transparent substrate 820a and a color filter layer (not shown) provided on the transparent substrate 820a.

The liquid crystal layer 830 is a horizontal alignment type liquid crystal layer. A horizontal alignment film (not shown) is provided on the surface of the TFT substrate 810 and the counter substrate 820 on the liquid crystal layer 830 side, and the liquid crystal molecules contained in the liquid crystal layer 830 are horizontally aligned in a state where no voltage is applied (that is, Oriented substantially parallel to the surfaces of the TFT substrate 810 and the counter substrate 820).

In the FFS mode liquid crystal display device 800, when a predetermined potential difference is applied between the pixel electrode 811 and the common electrode 812, a fringe electric field (represented by an electric force line Ef) is generated in the liquid crystal layer 830. For example, when a potential of + 14V and + 7V is applied to the pixel electrode 811 and the common electrode 812, respectively, a fringe electric field corresponding to 7V is applied to the liquid crystal layer 830. The alignment direction of the liquid crystal molecules is changed by the fringe electric field applied to the liquid crystal layer 830, and thus display is performed.

The FFS mode described above can achieve a wide viewing angle characteristic. The VA mode can also realize a wide viewing angle characteristic.

Patent Document 3 discloses an electrode structure capable of achieving high-speed response and high transmittance of a VA mode liquid crystal display device. 22A and 22B show the structure of the liquid crystal display device disclosed in Patent Document 3. FIG. A liquid crystal display device 900 shown in FIGS. 22A and 22B includes a TFT substrate 910 and a counter substrate 920, and a liquid crystal layer 930 provided therebetween.

The TFT substrate 910 includes a glass substrate 910a, a lower layer electrode 913 provided on the glass substrate 910a, an insulating layer 914 provided so as to cover the lower layer electrode 913, and a pair of upper layer electrodes provided on the insulating layer 914. (First upper layer electrode and second upper layer electrode) 911 and 912. Each of the first upper layer electrode 911 and the second upper layer electrode 912 has a comb shape.

The counter substrate 920 includes a glass substrate 920a and a counter electrode 921 provided on the glass substrate 920a.

The liquid crystal layer 930 is a vertical alignment type liquid crystal layer. A vertical alignment film (not shown) is provided on the surface of the TFT substrate 910 and the counter substrate 920 on the liquid crystal layer 930 side, and the liquid crystal molecules contained in the liquid crystal layer 930 are vertically aligned in a state where no voltage is applied (that is, Oriented substantially parallel to the surfaces of the TFT substrate 910 and the counter substrate 920).

In the liquid crystal display device 900, at the time of start-up (when the alignment state changes from the black display state to the white display state), as shown in FIG. 22A, the first upper layer electrode 911 and the second upper layer electrode 912 are arranged. A lateral electric field (represented by electric lines of force Eh) due to the potential difference is generated in the liquid crystal layer 930. At this time, a fringe electric field (represented by electric lines of force Ef) due to a potential difference between the first upper layer electrode 911 and the lower layer electrode 913 and a potential difference between the second upper layer electrode 912 and the lower layer electrode 913 is also generated in the liquid crystal layer 930. Is done. Patent Document 3 describes an example in which potentials of +7 V, +14 V, +10.5 V, and +7 V are applied to the first upper layer electrode 911, the second upper layer electrode 912, the lower layer electrode 913, and the counter electrode 921, respectively. In this example, a lateral electric field corresponding to 7 V and a fringe electric field corresponding to 3.5 V are applied to the liquid crystal layer 930.

Further, at the time of falling (when the orientation state changes from the white display state to the black display state), as shown in FIG. 22B, the first upper layer electrode 911, the second upper layer electrode 912, and the lower layer electrode 913 A vertical electric field (represented by lines of electric force Ev) due to a potential difference with the counter electrode 921 is generated in the liquid crystal layer 930. Patent Document 3 describes an example in which potentials of + 14V, + 14V, + 14V, and 0V are applied to the first upper layer electrode 911, the second upper layer electrode 912, the lower layer electrode 913, and the counter electrode 921, respectively. In this example, a vertical electric field corresponding to 14 V is applied to the liquid crystal layer 930.

The inventor of the present application examined the use of an electrode structure proposed for a liquid crystal display device as a method for further improving the light utilization efficiency of a display panel including an optical layer containing shape anisotropic particles. As a result, it has been found that the following problems occur when the electrode structure as described above is simply adopted.

First, in the electrode structure of Patent Document 3, the potential of the lower layer electrode 913 is limited, and a sufficiently strong fringe electric field cannot be generated. Specifically, in order to maintain the symmetry of orientation, the potential of the lower layer electrode 913 needs to be set to an intermediate potential between the potential of the first upper layer electrode 911 and the potential of the second upper layer electrode 912. As in the example described in Patent Document 3, if the potentials of the first upper electrode 911 and the second upper electrode 912 are +7 V and +14 V, respectively, it is necessary to set the potential of the lower electrode 913 to +10.5 V. Therefore, since the generated fringe electric field is equivalent to 3.5 V, compared to the case where the FFS mode electrode structure is adopted (a fringe electric field equivalent to 7 V is generated as shown in FIG. 21). The alignment regulating force due to the fringe electric field is weakened.

In addition, in the electrode structure of Patent Document 3, in order to generate a fringe electric field having the same strength as that of the FFS mode electrode structure, the potential of the lower layer electrode 913 is made the same as the potential of the first upper layer electrode 911 (for example, the first The first upper layer electrode 911, the second upper layer electrode 912, the lower layer electrode 913, and the counter electrode 921 are applied with potentials of + 7V, + 14V, + 7V, and + 7V, respectively), and as shown in FIG. Although a strong fringe electric field (equivalent to 7 V) is generated due to a potential difference from 913, no fringe electric field is generated in the vicinity of the first upper layer electrode 911, and a weak electric field region WR having a relatively weak electric field strength is formed. Due to the presence of the weak electric field region WR, the light use efficiency (mode efficiency) is lowered.

On the other hand, when the FFS mode electrode structure is adopted, the plurality of comb-tooth portions 811a of the pixel electrode 811 are at the same potential, so that no horizontal electric field is generated between the adjacent comb-tooth portions 811a. Therefore, as shown in FIG. 24, a weak electric field region WR is generated near the center of the slit 811b, and the light utilization efficiency is lowered.

When the first write drive WD1 and the second write drive WD2 illustrated in FIG. 20 are performed, it is possible to suppress a decrease in light utilization efficiency due to a weak electric field region formed when a lateral electric field and a fringe electric field are applied. it can.

FIGS. 25A and 25B are diagrams showing the electric field generated in the optical layer 30 when the first write drive WD1 is performed, and FIG. 25A shows the first write drive. FIG. 25B corresponds to the second frame when the first write drive WD1 is performed, corresponding to the first frame when the WD1 is performed.

When an electric field is applied to the optical layer 30, as shown in FIGS. 25A and 25B, each pixel has a first region SR in which the electric field has the first electric field strength, and the electric field is greater than the first electric field strength. The second region WR having a weak second electric field strength has an electric field distribution arranged along the in-plane direction of the optical layer 30. Hereinafter, the first region SR having a relatively strong electric field strength is referred to as a “strong electric field region”, and the second region WR having a relatively weak electric field strength is referred to as a “weak electric field region”.

In the state shown in FIG. 25A, a fringe electric field (hereinafter referred to as “first fringe electric field” for convenience) is generated by the potential difference between the first electrode 11 and the third electrode 13, but the second electrode A fringe electric field (hereinafter referred to as “second fringe electric field” for convenience) is not generated due to a potential difference between the electrode 12 and the third electrode 13. In this state, the region where the fringe electric field is not generated in the vicinity of the branch portion 12a of the second electrode 12 is the weak electric field region WR, and the other region including the vicinity of the branch portion 11a of the first electrode 11 is the strong electric field region SR. Become.

In the state shown in FIG. 25B, the second fringe electric field is generated, but the first fringe electric field is not generated. In this state, the region where the fringe electric field is not generated near the branch portion 11a of the first electrode 11 is the weak electric field region WR, and the other region including the vicinity of the branch portion 12a of the second electrode 12 is the strong electric field region SR. Become.

When the first write drive WD1 illustrated in FIG. 20 is performed, as shown in FIGS. 25A and 25B, the period during which the same display is performed (that is, a certain pixel has the same gradation level). The arrangement of the strong electric field region SR and the weak electric field region WR in the electric field distribution is exchanged one or more times within a period during which the display is performed. That is, the position of the weak electric field region WR is not fixed, and the region that has been the weak electric field region WR in one frame becomes the strong electric field region SR in another certain frame. Therefore, the orientation direction of the shape anisotropic particles 32 can be changed over almost the entire pixel, and a decrease in light use efficiency (mode efficiency) due to the weak electric field region WR can be suppressed.

25A and 25B, the potentials of the first electrode 11, the second electrode 12, and the third electrode 13 are set so that only one of the first fringe electric field and the second fringe electric field is generated. However, the potential setting of the first electrode 11, the second electrode 12, and the third electrode 13 is not limited to this example. As long as the strengths of the first fringe field and the second fringe field are different from each other, both the first fringe field and the second fringe field may be generated simultaneously. In that case, the region in which the fringe electric field having the relatively strong electric field strength of the first fringe electric field and the second fringe electric field is generated becomes the strong electric field region SR, and the fringe electric field having the relatively weak electric field strength. The region in which is generated becomes the weak electric field region WR.

Further, there is no restriction that the potential of the third electrode 13 must be set to an intermediate potential between the potential of the first electrode 11 and the potential of the second electrode 12. By making the potential of one of the first electrode 11 and the second electrode 12 the same as the potential of the third electrode 13, the fringe due to the potential difference between the other of the first electrode 11 and the second electrode 12 and the third electrode 13. The electric field can be strongest. For example, when the potential of the first electrode 11 is B [V], the potential of the second electrode 12 is A [V], and the potential of the third electrode 13 is C [V], the first electrode 11 and the second electrode 12 The horizontal electric field due to the potential difference is equivalent to | A−B | [V], and the fringe electric field due to the potential difference between the first electrode 11 and the third electrode 13 is equivalent to | BC−V. Here, if the potential C [V] of the third electrode 13 is made the same as the potential A [V] of the second electrode 12 (C = A), a fringe electric field due to the potential difference between the first electrode 11 and the third electrode 13. Is equivalent to | BC | = | BA | = | AB | [V]. Further, when the potential of the first electrode 11 is A [V], the potential of the second electrode 12 is B [V], and the potential of the third electrode 13 is C [V], the first electrode 11, the second electrode 12, The lateral electric field due to the potential difference is equivalent to | AB | [V], and the fringe electric field due to the potential difference between the second electrode 12 and the third electrode 13 is equivalent to | BC | V. Here, if the potential C [V] of the third electrode 13 is made the same as the potential A [V] of the first electrode 11 (C = A), a fringe electric field due to the potential difference between the second electrode 12 and the third electrode 13. Is equivalent to | BC | = | BA | = | AB | [V]. Thus, if there is no restriction on the potential of the third electrode 13, a fringe electric field having the same strength as when the FFS mode electrode structure is employed can be applied to the optical layer 30. Further, as shown in FIGS. 25A and 25B, the arrangement of the strong electric field region SR and the weak electric field region WR can be changed by, for example, switching the potential of the first electrode 11 and the potential of the second electrode 12. Can be replaced.

On the other hand, in the electrode structure of Patent Document 3, when the potential of the first upper layer electrode 911 is A [V] and the potential of the second upper layer electrode 912 is B [V], as shown in FIG. Is required to be Min (A, B) + | (AB) | / 2 [V]. Therefore, the lateral electric field due to the potential difference between the first upper electrode 911 and the second upper electrode 912 is equivalent to | AB | [V], whereas the fringe electric field due to the potential difference between the first upper electrode 911 and the lower electrode 913 is used. The fringe electric field due to the potential difference between the second upper layer electrode 912 and the lower layer electrode 913 is equivalent to | AB | / 2 [V]. For this reason, the fringe electric field becomes weaker than when the FFS mode electrode structure is adopted.

In the FFS mode electrode structure, as shown in FIG. 27, when the potential of the common electrode 812 is A [V] and the potential of the pixel electrode 811 is B [V], the potential difference between the pixel electrode 811 and the common electrode 812 is obtained. The fringe electric field due to is equivalent to | AB | [V]. The FFS mode electrode structure can generate a sufficiently strong fringe electric field, but a horizontal electric field is not generated between adjacent comb-tooth portions 811a, so that a weak electric field region WR is generated near the center of the slit 811b. . On the other hand, in the write drive described above, a lateral electric field can be generated between the first electrode 11 and the second electrode 12, so that the vicinity of the middle between the branch portion 11a of the first electrode 11 and the branch portion 12a of the second electrode 12 is obtained. In addition, a decrease in light utilization efficiency due to the formation of the weak electric field region WR can be suppressed.

When performing active matrix driving, the period in which the arrangement of the strong electric field region SR and the weak electric field region WR is switched (hereinafter also simply referred to as “switching cycle”) is typically an integer multiple of the time corresponding to one frame. . From the viewpoint of improving the light utilization efficiency, the replacement period is preferably short, and most preferably a time corresponding to one frame. Since the replacement cycle is short, the number of fluctuations in the electric field distribution per unit time can be increased, and the light utilization efficiency can be further improved. Further, the switching period may not be constant within the period in which the same display is performed, but the total time during which the positive voltage is applied to the optical layer 30 and the negative voltage are applied. It is preferable that the total amount of time is substantially equal.

As already described, the arrangement of the strong electric field region SR and the weak electric field region WR can be replaced by, for example, switching the potential of the first electrode 11 and the potential of the second electrode 12. In other words, the arrangement of the strong electric field region SR and the weak electric field region WR can be exchanged by the first substrate 10 having two comb electrodes (electrodes having a comb shape) that can be given different potentials. it can.

Next, it will be described that the electric field distribution in which the reflectance is stably maintained can be realized by the illustrated pause driving.

FIG. 28 is a diagram illustrating an electric field generated in the optical layer 30 at the start of the first pause drive PD1. As already described, in the last frame of the first write driver WD1, the potential V ₁ of the first electrode 11 and the potential V ₂ of the second electrode 12 are the same as each other. Therefore, during the period in which the first pause drive PD1 is performed, a fringe electric field is generated both in the vicinity of the branch portion 11a of the first electrode 11 and in the vicinity of the branch portion 12a of the second electrode 12, as shown in FIG. Is done. Therefore, the shape anisotropic particles 32 that are uniformly dispersed during the first writing drive WD1 are stably held, and thus the reflectance can be stably maintained.

FIG. 29 shows the optical layer at the start of the first pause drive PD1 when the waveform pattern of the signal voltage in the last frame of the first write drive WD1 is the same as the waveform pattern of the signal voltage in the previous frame. It is a figure which shows the electric field produced | generated by 30. FIG. In this case, in the period during which the first pause drive PD1 is performed, as shown in FIG. 29, a fringe electric field is generated in the vicinity of the branch portion 12a of the second electrode 12, but the branch portion of the first electrode 11 is generated. No fringe electric field is generated in the vicinity of 11a. That is, the weak electric field region WR exists. Thus, since the electric field is fixed in a non-uniform state, the shape anisotropic particles 32 are biased and the reflectance cannot be stably maintained.

As described above, the waveform pattern of the signal voltage in the last frame in the period in which the write drive is performed is different from the waveform pattern of the signal voltage in the frame before the last frame. By applying a voltage with a waveform pattern suitable for sufficiently increasing the voltage, it is possible to realize an electric field distribution in which the reflectance is stably maintained during rest driving.

FIG. 30 shows the relationship between the elapsed time after the pixel TFT is turned off and the pixel voltage retention rate and reflectance attenuation rate. As can be seen from FIG. 30, the pixel voltage drops to 65% after 40 seconds, but the reflectance is attenuated by only about 1%. Therefore, in the display panel 110 as illustrated, it can be seen that there is no problem in visibility even when the pause driving is performed for a relatively long time.

FIG. 20 illustrates the case where the drive frequency is 60 Hz (that is, one frame is about 16.7 msec), but it is also preferable to increase the frequency of the write drive and the refresh drive as shown in FIG. 31A and 31B show the first electrode 11 in the first write drive WD1 and the first refresh drive RD1 when the drive frequency is 120 Hz (that is, one frame is about 8.3 msec). potential V _1, the potential V ₂ of the second electrode 12, the potential V ₃ of the third electrode 13 is a timing chart showing the potential V ₄ and the gate voltage (scan signal voltage) Vg of the fourth electrode 21.

The response speed at the time of write drive and refresh drive can be improved by increasing the frequency of write drive and refresh drive. For example, when the drive frequency is 120 Hz, the write drive and refresh drive periods can be halved (eg, 600 msec to 300 msec) as compared with the case where the drive frequency is 60 Hz.

Further, by increasing the frequency of the write drive and the refresh drive, it is possible to suppress the display quality from being deteriorated due to the flicker (flicker) being visually recognized. FIG. 32A is a diagram showing the electric field generated in the odd-numbered frame and the even-numbered frame when writing driving is performed at a relatively low frequency, and FIG. 32B is a diagram illustrating writing driving at a relatively high frequency. It is a figure which shows the electric field produced | generated in an odd-numbered frame and an even-numbered frame when performing.

When the drive frequency is low, as shown in FIG. 32 (a), the shape anisotropic particles 32 in the region where the electric field strength is weak may fluctuate, and the fluctuation of the reflectance resulting from the fluctuation causes flicker. On the other hand, when the driving frequency is high, as shown in FIG. 32B, the fluctuation of the shape anisotropic particles 32 is suppressed, so that the flicker caused by the fluctuation of the reflectance can be suppressed.

As already described, the display device 100 according to the embodiment of the present invention uses the hysteresis of the optical characteristics of the pixels. The above-described hysteresis property of the optical characteristics appears in the display panel 110 in which the optical layer 30 includes the medium 31 and the shape anisotropic particles 32 as illustrated.

The medium 31 of the optical layer 30 is preferably a liquid crystal material. When the medium 31 is a liquid crystal material, the orientation direction of the shape anisotropic particles 32 can be efficiently changed by utilizing the change of the director of the liquid crystal molecules.

In addition, since the liquid crystal material generally has a high specific resistance, when the medium 31 is a liquid crystal material, off-leakage through the medium 31 is prevented in a state where the TFT after writing to the pixel is off. Therefore, a high voltage holding ratio can be obtained, and active matrix driving can be suitably performed. In addition, since the leakage current is small, power consumption can be further reduced. The power consumption P of the display device 100 is expressed by the following formula (2), where C is the panel capacitance, V is the voltage applied to the optical layer 30, f is the drive frequency, and I is the leakage current.
P = C · V · f + I · V (2)

The first term on the right side of Equation (2) should be called the pixel capacitance term, and the second term should be called the leakage current term. That is, the power consumption P can be considered separately for the pixel capacitance component and the leakage current component. When the specific resistance of the medium 31 is high, the leakage current I decreases, so that the power consumption P can be reduced as is apparent from the equation (2).

Further, if the liquid crystal material is a positive type, the behavior of the shape anisotropic particles 32 and the behavior of the liquid crystal molecules when an electric field is applied to the optical layer 30 match. For example, when the electric field applied to the optical layer 30 is switched from a fringe electric field and / or a horizontal electric field to a vertical electric field, the shape anisotropic particles 32 try to change from the horizontal alignment state to the vertical alignment state, and the liquid crystal molecules are also aligned horizontally. Attempts to change from state to vertical alignment. Therefore, since the number (existence probability) of the shape anisotropic particles 32 that are properly vertically aligned can be increased, a higher contrast ratio can be realized.

As the positive liquid crystal material, a liquid crystal material for a liquid crystal display device can be used widely and suitably. For example, a fluorine-based liquid crystal material in which fluorine is introduced into the side chain can be suitably used. Fluorine-based liquid crystal materials are often used in active matrix-driven liquid crystal display devices and have large dielectric anisotropy and high specific resistance. Specifically, for example, a dielectric constant in the major axis direction epsilon _// 24.7, the short axial permittivity epsilon _⊥ 4.3, the specific resistance ρ is a liquid crystal material 6 × 10 ¹³ Ω · cm be able to. Of course, the dielectric constant and specific resistance of the liquid crystal material are not limited to those exemplified here. From the viewpoint of sufficiently suppressing the occurrence of off-leakage through the medium 31, the specific resistance of the liquid crystal material is preferably 1 × 10 ^{11 to 12} Ω · cm or more. The dielectric anisotropy Δε of the liquid crystal material preferably exceeds 10 (Δε> 10).

Note that a liquid crystal material having negative dielectric anisotropy (that is, a negative liquid crystal material) may be used as the medium 31.

Further, when the first substrate 10 and the second substrate 20 have the

vertical alignment films

15 and 25 as in the present embodiment, the shape anisotropic particles 32 are caused by the alignment regulating force of the

vertical alignment films

15 and 25. Is prevented from sticking to the substrate surface in a horizontal state. As the

vertical alignment films

15 and 25, a vertical alignment film for a liquid crystal display device in a VA (Vertical Alignment) mode (for example, a polyimide-based or polyamic acid-based vertical alignment film manufactured by JSR or Nissan Chemical) is preferably used. be able to. In order to vertically align a high dielectric constant positive liquid crystal material, it is preferable to use a vertical alignment film in which a relatively large number of hydrophobic structures such as alkyl groups and fluorine-containing groups are introduced into the side chain. The thickness of each of the

vertical alignment films

15 and 25 is, for example, 100 nm. Of course, it is not limited to this.

It is preferable that the display device 100 can apply a lateral electric field and / or a fringe electric field to the optical layer 30 as in the present embodiment. That is, it is preferable that the display device 100 can use the horizontal electric field mode. As described above, each shape anisotropic particle 32 basically takes only one of a horizontal alignment state and a vertical alignment state (that is, a binary state). Since the electric field strength in the thickness direction can be changed, the amount (number) of the shape anisotropic particles 32 horizontally oriented on the first substrate 10 side can be controlled. Therefore, halftone display can be suitably performed. On the other hand, in the vertical electric field mode, since the electric field strength in the cell thickness direction is constant, halftone display is difficult. In the horizontal electric field mode, the shape anisotropic particles 32 are attracted toward the first substrate 10 having a high electric field strength in accordance with the applied voltage at the time of data writing. In the range r) in FIG. 10, the horizontal orientation state of the shape anisotropic particles 32 can be maintained.

In addition, the structure of the 1st electrode 11, the 2nd electrode 12, and the 3rd electrode 13 is not limited to what was illustrated in FIG. FIG. 33 shows another electrode configuration of the display panel 110.

33, a further insulating layer 17 is provided so as to cover the first electrode 11, and the second electrode 12 is provided on the further insulating layer 17. In the example shown in FIG. That is, the second electrode 12 is provided above the first electrode 11 via the further insulating layer 17. In the configuration shown in FIG. 33, since the first electrode 11 and the second electrode 12 are provided at different levels, a fringe electric field (electric field lines) is generated instead of a lateral electric field due to a potential difference between the first electrode 11 and the second electrode 12. Ef ′) is generated. In the configuration shown in FIG. 33, since a further insulating layer 17 is located between the first electrode 11 and the second electrode 12, a short circuit occurs even if the interval between the first electrode 11 and the second electrode 12 is narrowed. The advantage is that there is no.

FIG. 34 shows still another electrode configuration of the display panel 110. In the example shown in FIG. 34, the third electrode 13 has a plurality of slits 13 s formed at positions overlapping the first electrode 11 and the second electrode 12. In the configuration shown in FIG. 34, the fringe electric field distribution is concentrated from the end of the first electrode 11 or the second electrode 12 to between the first electrode 11 and the second electrode 12 (between

adjacent branch portions

11a and 12a). ), It is possible to make it closer to the center. On the other hand, as shown in FIG. 2 and the like, in the configuration in which the third electrode 13 is a solid electrode, the first electrode 11 and the second electrode 12, the third electrode 13, and the insulating layer 14 positioned between them. The advantage that an auxiliary capacity can be configured is obtained.

Of course, modifications other than the electrode configuration illustrated in FIGS. 33 and 34 may be adopted. For example, one of the first electrode 11 and the second electrode 12 may be omitted.

Here, an example of a specific wiring structure in the rear substrate 10 when active matrix driving is performed will be described with reference to FIG.

In the example shown in FIG. 35, three TFTs (first TFT, second TFT, and third TFT) t1, t2, and t3 are provided for each pixel. The first electrode 11, the second electrode 12, and the third electrode 13 are electrically connected to the first TFT t1, the second TFT t2, and the third TFT t3, respectively. In the example shown in FIG. 35, a gate line GL extending in the row direction and a first source line SL1, a second source line SL2, and a third source line SL3 extending in the column direction are provided. The first TFT t1 is supplied with a gate signal and a first source signal from the gate line GL and the first source line SL1. The second TFT t2 is supplied with a gate signal and a second source signal from the gate line GL and the second source line SL2. The third TFT t3 is supplied with the gate signal and the third source signal from the gate line GL and the third source line SL3.

As the material of the semiconductor layer included in the first TFT t1, the second TFT t2, and the third TFT t3, various known semiconductor materials can be used. For example, amorphous silicon, polycrystalline silicon, continuous grain boundary crystal silicon (CGS: Continuous Grain Silicon) Etc. can be used.

The semiconductor layer may be an oxide semiconductor layer formed from an oxide semiconductor. The oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor. Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is It is not specifically limited, For example, In: Ga: Zn = 2: 2: 1, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 1: 1: 2, etc. are included. The In—Ga—Zn—O-based semiconductor may be amorphous or crystalline. As the crystalline In—Ga—Zn—O-based semiconductor, a semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable. Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference. A TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). Therefore, when an oxide semiconductor layer formed using an In—Ga—Zn—O-based semiconductor is used as the semiconductor layer, power consumption can be further reduced because off-leakage is small.

Note that the oxide semiconductor layer is not limited to the In—Ga—Zn—O-based semiconductor layer. The oxide semiconductor layer includes, for example, a Zn—O based semiconductor (ZnO), an In—Zn—O based semiconductor (IZO), a Zn—Ti—O based semiconductor (ZTO), a Cd—Ge—O based semiconductor, a Cd—Pb— An O-based semiconductor, an In—Sn—Zn—O based semiconductor (eg, In ₂ O ₃ —SnO ₂ —ZnO), an In—Ga—Sn—O based semiconductor, or the like may be included.

35. Active matrix driving can be performed by the wiring structure shown in FIG. Of course, the wiring structure of the back substrate 10 is not limited to the example shown in FIG. When an oxide semiconductor TFT including an oxide semiconductor layer is used as a thin film transistor (TFT) provided in each pixel, the off-leakage is small, so that the voltage holding ratio in active matrix driving can be increased. For this reason, it is possible to lengthen the period of pause driving and further reduce power consumption.

Subsequently, an example of a more specific configuration for performing the pause drive in the display device 100 according to the embodiment of the present invention will be described with reference to FIG. In the configuration illustrated in FIG. 36, the display device 100 constitutes a part of the electronic device 200.

The electronic device 200 includes a display device 100, a touch panel 210, and a main body device 220 as shown in FIG.

The display device 100 includes the display panel 110, the gate driver (scanning line driving circuit) 120g, and the source driver (signal line driving circuit) 120s already described. In addition, the display device 100 includes a common electrode driving circuit 130 and a timing controller 140.

The display panel 110 includes a plurality of gate wirings GL that are electrically connected to the gate electrodes of the TFTs of the corresponding pixels, and a plurality of source wirings SL1 that are electrically connected to the source electrodes of the TFTs of the corresponding pixels. SL2 and SL3.

The gate driver 120g supplies a scanning signal voltage to each gate wiring GL. The source driver 120s calculates the value of the voltage to be output to each pixel from the video signal VS input from the main body device 220 via the timing controller 140, and displays the calculated display signal voltage for each source line SL1, SL2. And supplied to SL3.

The common electrode driving circuit 130 outputs a common voltage to the counter electrode 21 based on a signal input from the timing controller 140.

The timing controller 140 outputs, to each driver 120, a reference signal for each driver 120 to operate in synchronization based on the clock signal, horizontal synchronization signal, and vertical synchronization signal input from the main unit 220. Specifically, the timing controller 140 outputs a gate start pulse signal, a gate clock signal, and a gate output enable signal to the gate driver 120g based on the vertical synchronization signal. The timing controller 140 outputs a source start pulse signal, a source latch strobe signal, and a source clock signal to the source driver 120s based on the horizontal synchronization signal.

The gate driver 120g starts scanning the display panel 110 with the gate start pulse signal received from the timing controller 140 as a cue, and applies to each gate line GL according to a gate clock signal that is a signal for shifting the selection state of the gate line GL. The on-voltage is applied sequentially. Based on the source start pulse signal received from the timing controller 140, the source driver 120s stores the input image data of each pixel in a register according to the source clock signal. Then, after storing the image data, the source driver 120s writes the image data to each source wiring of the display panel 110 in accordance with the next source latch strobe signal. For example, an analog amplifier included in the source driver 120s is used for writing the image data.

The touch panel 210 includes a detection unit 211 and a control unit 212.

The detecting unit 211 is provided on the screen of the display panel 110 of the display device 100, and detects the position on the screen specified by the user's finger or the like. The control unit 212 controls the detection unit 211. Specifically, when the control unit 212 drives the detection unit 211 via the drive line Tx, the detection unit 211 detects the position and transmits a detection signal to the control unit 212 via the detection line Sx. . The control unit 212 creates detection data indicating the detected position based on the detection signal from the detection unit 211, and transmits the detection data to the main device 220.

The touch panel 210 is, for example, a projected capacitive touch panel. In the projected capacitive touch panel 210, the detection unit 211 has a matrix-like transparent electrode pattern formed on a transparent substrate such as glass or plastic. When a user's finger or the like touches or approaches the detection unit 211, the electrostatic capacity of the transparent electrode pattern in the vicinity thereof changes. Therefore, the control unit 212 can detect the position where the user's finger or the like has touched or approached by detecting a change in the current or voltage of the transparent electrode pattern.

Note that the touch panel 210 may detect that a user's finger or the like has touched or approached an arbitrary position on the screen. In this case, it is only necessary to detect contact or approach of a finger or the like, and it is not necessary to detect the position.

The main body device 220 transmits a video signal and a video synchronization signal to the display device 100 in order to recognize a user operation based on detection data from the touch panel 210 and to control display of the display device 100.

In the example shown in FIG. 36, the timing controller 140 outputs a pause signal PS, which is a signal for pausing the gate driver 120g and the source driver 120s, to the gate driver 120g and the source driver 120s. When the pause driving is performed, the pause signal PS is output from the timing controller 140 to the gate driver 120g and the source driver 120s, whereby the gate driver 120g and the source driver 120s are paused.

Further, when the pause driving is started, the timing controller 140 outputs a detection instruction signal DS that is a signal for instructing a detection operation in the touch panel 210 to the control unit 212 of the touch panel 210. In the touch panel 210, when the control unit 212 receives the detection instruction signal DS from the timing controller 140, the detection unit 211 performs a detection operation, and the control unit 212 outputs detection data indicating the detection result to the main body device 220.

In the present embodiment, the fourth electrode 21 is provided on the second substrate 20 side, but the fourth electrode 21 may be omitted. This is because, when the optical layer 30 is in a state where no electric field is applied, the shape anisotropic particles 32 take a vertical alignment state. However, from the viewpoint of response speed, it is preferable to adopt a configuration in which the fourth electrode 21 is provided on the second substrate 20 side (that is, a configuration in which a vertical electric field can be applied to the optical layer 30). That is, it is preferable that display is performed by switching between a state in which a vertical electric field is generated in the optical layer 30 and a state in which a horizontal electric field and / or a fringe electric field is generated in the optical layer 30. Since the change from the former state to the latter state and the change from the latter state to the former state are both performed by changing the direction of the applied electric field, a sufficient response speed can be realized. .

Also, as already described, the display device 100 according to the embodiment of the present invention can suitably perform halftone display. Therefore, by providing a color filter for each pixel, multicolor display corresponding to gradation can be performed.

The shape anisotropic particles 32 are not particularly limited in specific shape and material as long as the projected area on the substrate surface changes according to the applied voltage (direction of applied electric field) as described above. The shape anisotropic particles 32 may have a flake shape (flaky shape), a cylindrical shape, an oval shape, or the like. From the viewpoint of realizing a high contrast ratio, the shape anisotropic particle 32 preferably has a shape such that the ratio of the maximum projected area to the minimum projected area is 2: 1 or more.

As a material of the shape anisotropic particle 32, a metal material, a semiconductor material, a dielectric material, and a composite material thereof can be used. The shape anisotropic particles 32 may be a dielectric multilayer film or may be formed from a cholesteric resin material. When a metal material is used as the material for the shape anisotropic particles 32, an insulating layer (dielectric layer) is preferably formed on the surface of the shape anisotropic particles 32. Although the dielectric constant of a single metal is an imaginary number, by forming an insulating layer (for example, a resin layer or a metal oxide layer) on the surface, the shape anisotropic particles 32 formed of a metal material can be handled as a dielectric. it can. In addition, since the insulating layer is formed on the surface, an effect of preventing conduction due to contact between the shape anisotropic particles 32 formed of a metal material, aggregation due to physical interaction, and the like can be obtained. As such shape anisotropic particles 32, for example, aluminum flakes whose surfaces are coated with a resin material (for example, acrylic resin) can be used. The aluminum flake content of the display medium layer 30 is, for example, 6% by weight. Alternatively, aluminum flakes having an SiO ₂ layer formed on the surface, aluminum flakes having an aluminum oxide layer formed on the surface, or the like can also be used. Of course, a metal material other than aluminum may be used as the metal material. Further, the shape anisotropic particles 32 may be colored.

The length of the shape anisotropic particles 32 is not particularly limited, but is preferably 4 μm or more and 10 μm or less. If the length of the shape anisotropic particles 32 exceeds 10 μm, the shape anisotropic particles 32 may be difficult to move. On the other hand, when the length of the shape anisotropic particles 32 is less than 4 μm, it may be difficult to produce the shape anisotropic particles 32 or the reflective performance of the shape anisotropic particles 32 may be insufficient. Further, in the reflective display device as in the present embodiment, when it is desired to cover the substrate surface with the shape anisotropic particles 32 in the horizontal alignment state in order to obtain a high reflectance, the length of the shape anisotropic particles 32 is increased. It is preferable that the pitch be equal to or greater than the electrode pitch p (see FIG. 3). The thickness of the shape anisotropic particle 32 is not particularly limited. However, since the transmittance of the display medium layer 30 in the transparent state can be increased as the thickness of the shape anisotropic particles 32 is smaller, the thickness of the shape anisotropic particles 32 is larger than the inter-electrode distance g. It is preferably small (for example, 4 μm or less), and more preferably light wavelength or less (for example, 0.5 μm or less).

The specific gravity of the shape anisotropic particles 32 is preferably 11g / cm ³ or less, more preferably 3 g / cm ³ or less, further preferably the specific gravity substantially equal to that of the medium 31. This is because if the specific gravity of the shape anisotropic particles 32 is significantly different from the specific gravity of the medium 31, there may be a problem that the shape anisotropic particles 32 settle or float. From the viewpoint of increasing the effect of moving the shape anisotropic particles 32 by the peristaltic motion of the medium 31, the shape anisotropic particles 32 are preferably light.

In the above description, the configuration in which the first substrate 10 which is an active matrix substrate is arranged on the back side is illustrated, but the arrangement of the first substrate 10 is not limited to this. The first substrate 10 may be disposed on the front side. Since the first substrate 10 that is an active matrix substrate includes components formed from a light-shielding material, if the configuration in which the first substrate 10 is disposed on the back side is adopted, the shape anisotropic particles 32 The reflection effect can be used to the maximum.

In the above description, the reflective display device 100 has been described as an example. However, the embodiment of the present invention is also suitable for a transmissive display device (or a transmissive / reflective display device for transparent display). Used for. In the transmissive display device, a light absorption layer (the light absorption layer 16 illustrated in FIG. 1 and the like) is not provided on the back substrate. In a transmissive display device, an illumination element (backlight) that irradiates light to the display panel is provided.

When the embodiment of the present invention is applied to a transmissive display device, the voltage-transmittance characteristic of the pixel has hysteresis, and the threshold value in the boost curve indicating the voltage-transmittance characteristic when the applied voltage is increased The voltage is higher than the threshold voltage in the step-down curve indicating the voltage-transmittance characteristics when the applied voltage is decreased. In the step-down curve when the applied voltage is decreased from the write voltage, the transmittance is substantially constant in the range from the write voltage to a predetermined voltage lower than the write voltage. Therefore, even if the voltage supply is stopped after writing driving and the applied voltage to the pixel is reduced, the transmittance is maintained substantially constant in the predetermined voltage range after the reduction (that is, in a certain period after the voltage reduction starts). can do. Therefore, the power consumption can be reduced by performing the pause drive that pauses the driver after the write drive.

Further, when the transmittance value in the boosting curve when the applied voltage is increased from zero is determined in a substantially one-to-one relationship with the voltage value, the write voltage is set based on the boosting curve. Thus, halftone display can be suitably performed.

According to the embodiment of the present invention, an optical device excellent in low power consumption is provided. The optical device according to the embodiment of the present invention is suitably used as a display device, for example. In addition, the optical device according to the embodiment of the present invention is suitably used for various electronic devices.

DESCRIPTION OF SYMBOLS 10 1st board | substrate 10a board | substrate 11 1st electrode (1st upper layer electrode)
11a Branch portion of the first electrode 11b Trunk portion of the first electrode 12 Second electrode (second upper layer electrode)
12a Branch portion of second electrode 12b Trunk portion of second electrode 13 Third electrode (lower layer electrode)
13s Slit of third electrode 14 Insulating

layer

15, 25 Vertical alignment film 16 Light absorbing layer 17 Further insulating layer 20 Second substrate 20a Substrate 21 Fourth electrode (counter electrode)
22 Dielectric layer (overcoat layer)
30 Optical layer (display medium layer)
31 Medium (Liquid Crystal Material)
32 shape anisotropic particles 100 display device 110 display panel 120 driver (drive circuit)
120g Gate driver (scan line drive circuit)
120s source driver (signal line drive circuit)
130 common electrode driving circuit 140 timing controller 200 electronic device 210 touch panel 211 detection unit 212 control unit 220 main unit GL gate wiring SL1 first source wiring SL2 second source wiring SL3 third source wiring t1 first thin film transistor t2 second thin film transistor t3 second 3 Thin film transistor

Claims

An optical panel having pixels, the reflectance or transmittance of the pixels changing according to the magnitude of the voltage applied to the pixels;
A driver for supplying a signal voltage to the optical panel;
The voltage-reflectance characteristic or voltage-transmittance characteristic of the pixel has hysteresis.
The threshold voltage in the boost curve indicating the voltage-reflectance characteristic or the voltage-transmittance characteristic when the applied voltage is increased is the voltage-reflectance characteristic or the voltage- when the applied voltage is decreased. It is higher than the threshold voltage in the step-down curve indicating the transmittance characteristic,
In a state where the applied voltage is zero, the pixel does not have a memory property,
A range from the write voltage to a predetermined voltage lower than the write voltage in the step-down curve when the applied voltage is decreased from a write voltage that is an applied voltage at the time of write driving for writing data to the pixel. The reflectance or transmittance is substantially constant,
An optical apparatus capable of performing pause driving for pausing the driver after performing the writing driving.
2. The optical apparatus according to claim 1, wherein a value of reflectance or transmittance in the step-up curve when the applied voltage is increased from zero is substantially determined by a one-to-one relationship with the voltage value.
3. The optical device according to claim 1, wherein after the pause drive, the refresh drive can be performed to return the applied voltage, which has been reduced during the pause drive, to the write voltage.
4. The optical apparatus according to claim 3, wherein the writing drive and / or the refresh drive are performed over a plurality of frames.
The optical apparatus according to claim 4, wherein a period during which the refresh drive is performed is shorter than a period during which the write drive is performed.
In the case where the pause drive and the refresh drive are alternately and repeatedly performed, a period in which the first pause drive is performed and a period in which the nth (n is an integer of 2 or more) pause drive is performed. The optical device according to claim 3, wherein the polarity of the applied voltage is opposite.
The write drive is performed over a plurality of frames,
The waveform pattern of the signal voltage supplied from the driver in the last frame of the period during which the write drive is performed is different from the waveform pattern of the signal voltage supplied from the driver in a frame before the last frame. 7. The optical device according to any one of 6.
A first substrate and a second substrate provided to face each other;
An optical layer provided between the first substrate and the second substrate,
The optical layer includes a medium, and shape anisotropic particles dispersed in the medium and having shape anisotropy,
The medium includes a liquid crystal material,
The optical apparatus according to claim 1, wherein a lateral electric field and / or a fringe electric field can be applied to the optical layer.
A thin film transistor provided in the pixel;
The optical device according to claim 1, wherein the thin film transistor includes an oxide semiconductor layer.