KR102298850B1 - Liquid crystal display device - Google Patents

Abstract

In the present invention, a lower plate of the liquid crystal display includes a lower electrode and an upper electrode overlapping with an insulating film therebetween, and an alignment film in contact with the lower electrode and the upper electrode. The alignment layer is in contact with the lower electrode through a hole penetrating the insulating layer.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display having a low-speed driving mode.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices are being developed. A liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter, referred to as “TFT”) is formed for each pixel.

The liquid crystal display includes a liquid crystal display panel, a backlight unit irradiating light to the liquid crystal display panel, a source drive integrated circuit (hereinafter referred to as “IC”) for supplying data voltages to data lines of the liquid crystal display panel, and liquid crystal display. A gate drive IC for supplying a gate pulse (or scan pulse) to the gate lines (or scan lines) of the display panel, a control circuit for controlling the ICs, a light source driving circuit for driving a light source of a backlight unit, etc. be prepared

When a DC voltage is applied to the liquid crystal of the liquid crystal display, an afterimage may be seen. An afterimage is a phenomenon in which the previous image is visible even when the image is changed. The afterimage becomes more prominent as a still image is displayed for a long time in the liquid crystal display device or the DC voltage applied to the liquid crystal is applied for a longer time. One of the mechanisms by which the afterimage is generated is a phenomenon in which impurity ions in the liquid crystal layer are accumulated in the alignment layer for setting the pretilt angle of the liquid crystal molecules. Depending on the polarity of the electric field applied to the liquid crystal, negatively charged ions and positively charged ions move in opposite directions along the movement vector direction and are polarized. Since the motion vectors are the same, the amount of ions accumulated on the alignment layer increases over time. When the amount of accumulation of ions increases, an afterimage is seen by affecting the behavioral characteristics of the liquid crystal to be restored to the initial alignment state.

In order to reduce power consumption of the liquid crystal display, it is operated in a low speed driving mode to lower a frame rate or frame frequency when the input image is a still image. However, if the frame frequency is lowered, a phenomenon in which the luminance changes rapidly whenever the data voltage is changed or a flicker phenomenon in which the image flickers due to a prolonged voltage discharge time of the pixel may be observed.

In addition, the low-speed driving mode is vulnerable to an afterimage problem because the DC voltage applied to the liquid crystal takes a long time. Accordingly, there is a need for a method for preventing image quality deterioration in a low-speed driving mode of the liquid crystal display device.

The present invention provides a liquid crystal display capable of preventing image quality deterioration in a low-speed driving mode.

The liquid crystal display device of the present invention includes upper and lower plates facing each other with a liquid crystal layer interposed therebetween, and a spacer disposed between the upper and lower plates.

The lower plate includes a lower electrode and an upper electrode overlapping with an insulating film therebetween, and

and an alignment layer in contact with the lower electrode and the upper electrode.

The alignment layer is in contact with the lower electrode through a hole penetrating the insulating layer.

According to the present invention, in a liquid crystal display having a structure in which a lower electrode and an upper electrode are overlapped with an insulating film interposed therebetween, the alignment film is in contact with the lower electrode through a hole penetrating the insulating film. As a result, in the present invention, the alignment layer is directly in contact with the lower electrode and the upper electrode to form a discharge path of ions accumulated on the alignment layer, thereby preventing the accumulation of ions in normal driving and low speed driving modes, thereby reducing image quality deterioration due to afterimage and flicker. can be prevented Furthermore, the present invention can improve image quality in a low-speed driving mode by using a negative liquid crystal, a photo-alignment layer, and an oxide TFT.

1 is a block diagram showing a liquid crystal display according to an embodiment of the present invention.
2 is a view showing the structure of the lower plate of the liquid crystal display according to the first embodiment of the present invention.
3 is a view showing a structure of a lower plate of a liquid crystal display according to a second embodiment of the present invention.
4A and 4B are diagrams showing the afterimage test results of the prior art and the present invention.
5 is a view showing an image pattern of a sample used for an afterimage test result.
6A to 6E are diagrams illustrating various contact area ratios between a pixel electrode and a common electrode in an alignment layer.
7 is an enlarged plan view of one sub-pixel in the liquid crystal display according to the first exemplary embodiment of the present invention.
FIG. 8 is a cross-sectional view showing the cross-sectional structure of the lower plate of the liquid crystal display device taken along the line "I-I'" in FIG. 7 .
9 is a cross-sectional view illustrating conductive connections overlapping a data line and a column spacer.
10 is a view showing a structure of a lower plate of a liquid crystal display according to a third embodiment of the present invention.
11 is a view showing a structure of a lower plate of a liquid crystal display according to a fourth embodiment of the present invention.
12 is an enlarged plan view of one sub-pixel in the liquid crystal display according to the third exemplary embodiment of the present invention.
13 is a cross-sectional view showing a cross-sectional structure of a lower plate of the liquid crystal display device taken along line "II-II'" in FIG. 12 .
14 is a cross-sectional view illustrating a method of forming an open hole in the liquid crystal display of FIG. 13 .
15 is a plan view comparing the aperture area Apxl of the pixel structure of the present invention with that of a comparative example.
16 is a cross-sectional view showing a cross-sectional structure of the lower plate of the liquid crystal display device taken along the line “III-III′” and the line “IV-IV′” in FIG. 15 .

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 1 , the liquid crystal display of the present invention includes a display panel 100 having a pixel array formed thereon, display panel drivers 102 and 104 for writing input image data to the display panel 100 , and a power supply unit 112 . ), etc. A backlight unit for uniformly irradiating light to the display panel 100 may be disposed under the display panel 100 .

The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel 100 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer interposed therebetween. The pixel array of the display panel 100 includes pixels arranged in a matrix form by a cross structure of data lines S1 to Sm and gate lines G1 to Gn. Each of the pixels adjusts the amount of light transmission by using liquid crystal molecules driven by the voltage difference between the pixel electrode 1 that charges the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. .

On the lower plate of the display panel 100 , data lines S1 to Sm, gate lines G1 to Gn, a common electrode 2 , TFTs, a pixel electrode 1 connected to the TFT, and a pixel electrode 1 are provided. ) and the like connected to a storage capacitor (Storage Capacitor, Cst). TFTs are formed one for each sub-pixel and are connected to the pixel electrode 1 . The TFTs may be implemented as an amorphous silicon (a-Si) TFT, a LTPS (Low Temperature Poly Silicon) TFT, an oxide TFT (Oxide TFT), or the like. The TFTs are connected 1:1 to the pixel electrode of the sub-pixels. The common electrode 2 and the pixel electrode 1 are separated with an insulating film interposed therebetween.

A color filter array including a black matrix (BM) and a color filter (CF) is formed on the upper plate of the display panel 100 .

A liquid crystal layer is formed between the upper and lower plates of the display panel 100 . A polarizing plate is attached to each of the upper and lower plates of the display panel 100 , and an alignment layer for setting a pretilt angle of the liquid crystal is formed. The alignment layer is formed of a polymer material capable of photo-alignment, for example, polyimide. A spacer for maintaining a cell gap of the liquid crystal cell may be formed between the upper plate and the lower plate.

In the present invention, a discharge path is formed on the alignment layer by bringing the alignment layer into contact with the common electrode 2 and the pixel electrode 1 in order to reduce the afterimage and flicker of the liquid crystal display device.

In order to further improve image quality in the low-speed driving mode, the TFT of the pixel array is implemented as an oxide TFT, and the liquid crystal layer is implemented as a negative liquid crystal (nLC). The alignment layer is subjected to photo-alignment treatment.

The oxide TFT can suppress the discharge of pixels in the low-speed driving mode because the leakage current in the OFF state is very low. The oxide TFT can be applied to a liquid crystal display device using an etch stopper (ES) as shown in FIGS. 7 to 9 and can also be applied to a back channel etch (BCE) type liquid crystal display device.

The photo-alignment layer treated with photo-alignment may reduce light leakage and improve the contrast ratio. The photo-alignment layer makes the pretilt angle of the liquid crystal close to zero, enabling uniform image quality regardless of the viewing angle.

The negative liquid crystal has a higher transmittance than the positive liquid crystal, so that the luminance of an image can be improved. The negative liquid crystal is a liquid crystal in which the difference in permittivity between the major axis and the minor axis is negative (-). In the negative liquid crystal, when a voltage is applied, the shortening of the liquid crystal molecules is parallel to the electric field (E).

The display panel drivers 102 and 104 include a data driver 102 and a gate driver 104 . The display panel drivers 102 and 104 operate in a low-speed driving mode when a still image is input under the control of the timing controller 106 and operate in a normal driving mode when a moving image is input. The frame frequency in the low-speed driving mode is lower than that in the normal driving mode.

The data driver 102 includes a plurality of source drive ICs. Data output channels of the source drive ICs are connected to data lines S1 to Sm of the pixel array. The source drive ICs receive digital video data of an input image from the timing controller 106 . The source drive ICs convert the input image into digital video positive/negative gamma compensation voltages under the control of the timing controller 106 to output positive/negative data voltages. Output voltages of the source drive ICs are supplied to the data lines S1 to Sm. Since the frame frequency of the source drive ICs of the data driver 102 is lowered in the low speed driving mode, the operating frequency is lowered.

Each of the source drive ICs inverts the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 106 and outputs the inverted polarity to the data lines S1 to Sm. The source drive ICs may maintain the polarity of the data voltage applied to the data lines for one frame period and then invert the polarity of the data voltage every frame. In the low-speed drive mode, one frame period becomes longer due to the lowered frame frequency.

The gate driver 104 sequentially supplies gate pulses synchronized with the data voltage to the gate lines G1 to Gn under the control of the timing controller 106 . The gate pulse output from the gate driver 104 is synchronized with the positive/negative data voltage to be charged in the pixels. The gate driver 104 may be directly formed on the lower substrate of the display panel 100 together with the pixel array in order to reduce the cost of the IC. Since the frame frequency of the gate driver 104 is lowered in the low speed driving mode, the operating frequency is lowered.

The timing controller 106 transmits digital video data of an input image received from the host system 110 to the data driver 102 . The timing controller 106 receives timing signals synchronized with the input image data from the host system 110 . The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock CLK, and the like. The timing controller 106 controls operation timings of the data driver 102 and the gate driver 104 based on the timing signals Vsync, Hsync, DE, and CLK received together with the pixel data of the input image. The timing controller 106 may transmit a polarity control signal for controlling the polarity of the pixel array to each of the source drive ICs of the data driver 102 .

The timing controller 106 may control the operation timing of the display panel drivers 102 and 104 in a normal driving mode with a frame frequency of the input image×N (N is a positive integer) Hz. . In the normal driving mode, the frame rate of the input image is 60 Hz in the NTSC (National Television Standards Committee) method and 50 Hz in the PAL (Phase-Alternating Line) method. In the low speed driving mode, the frame frequency may be lowered to about 30 Hz to 1 Hz, but is not limited thereto.

The host system 110 may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The liquid crystal display device of the present invention further includes a power supply (not shown). The power supply unit generates voltages necessary for driving the display panel 100 using a DC-DC converter. These voltages include a high potential power voltage Vdd, a logic power supply voltage Vcc, a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL, and a common voltage Vcom. The high potential power voltage Vdd is the maximum data voltage to be charged in the pixels of the display panel 100 . The logic power voltage Vcc is a voltage voltage necessary for driving the timing controller 106 , the source drive ICs of the data driver 102 , and the gate drive ICs of the gate driver 104 . The gate high voltage VGH is the high logic voltage of the gate pulse set to be higher than the threshold voltage of the TFTs of the pixel array, and the gate low voltage VGL is the low logic voltage of the gate pulse set to a voltage lower than the threshold voltage of the TFTs of the pixel array. am. The gate high voltage VGH and the gate low voltage VGL are supplied to the gate driver 104 . The gate pulse swings between the gate high voltage VGH and the gate low voltage VGL. The common voltage Vcom is supplied to the common electrode 2 of the liquid crystal cells Clc. The power supply part divides the high potential power voltage Vdd to generate a gamma reference voltage. The gamma reference voltage is supplied to the source drive ICs. Source drive ICs divide the gamma reference voltage to generate positive/negative gamma compensation voltages for each gray level, and convert digital video data into positive/negative gamma compensation voltages to output data voltages.

2 is a view showing the structure of the lower plate of the liquid crystal display according to the first embodiment of the present invention.

Referring to FIG. 2 , the liquid crystal display of the present invention includes a pixel electrode PXL disposed on a common electrode COM with an insulating layer interposed therebetween, a conductive connection part CNT in contact with the common electrode COM, and a pixel electrode (PXL) and an alignment layer (PI) in contact with the conductive connection portion (CNT). The passivation layer PAS1 is an insulating layer formed between the common electrode COM and the pixel electrode PXL. Since the conductive connection part CNT is connected to the common electrode COM, it may be viewed as a part of the common electrode COM. In this embodiment, the common electrode COM is a lower electrode positioned below the pixel electrode PXL, and the pixel electrode PXL is an upper electrode.

The conductive connection part CNT is formed on the same layer as the pixel electrode PXL and is filled in a contact hole penetrating the passivation layer PAS1 to contact the common electrode COM. The conductive connection part CNT is in contact with the alignment layer PI. The conductive connection part CNT may be formed of the same material as the pixel electrode PXL and may be patterned simultaneously with the pixel electrode PXL, but is not limited thereto. The conductive connection part CNT may be formed of a metal different from that of the pixel electrode PXL. The conductive connection part CNT connects the alignment layer PI to the pixel electrode PXL and the common electrode COM to form a discharge path of ions accumulated on the alignment layer PI. The conductive connection part CNT covers the common electrode COM to prevent the common electrode COM from being etched in the etching process of the pixel electrode PXL, and a step difference between the alignment layer PI and the common electrode COM is connected. prevent it from growing

The common electrode COM may be formed on the organic passivation layer PAC. The conductive connection part CNT may overlap the data line DL or overlap the spacer in order to minimize the decrease in the aperture ratio of the pixel. In addition, the conductive connection part CNT may overlap the data line DL and may also overlap the spacer.

The black matrix overlaps the TFT, the data line DL, the gate line GL, the spacer, the conductive connection part CNT, and the like to make these components invisible.

3 is a view showing a structure of a lower plate of a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 3 , the liquid crystal display of the present invention includes a common electrode COM disposed on the pixel electrode PXL with an insulating layer interposed therebetween, a conductive connection part CNT in contact with the pixel electrode PXL, and the common electrode. (COM) and an alignment layer (PI) in contact with the conductive connection portion (CNT). The passivation layer PAS1 is an insulating layer formed between the common electrode COM and the pixel electrode PXL. The conductive connection part CNT is a part of the pixel electrode PXL because it is connected to the pixel electrode PIX. In this embodiment, the pixel electrode PXL is a lower electrode positioned below the common electrode COM, and the common electrode COM is an upper electrode.

The conductive connection part CNT is formed on the same layer as the common electrode COM and is filled in a contact hole penetrating the passivation layer PAS1 to contact the pixel electrode PXL. The conductive connection part CNT is in contact with the alignment layer PI. The conductive connection part CNT may be formed of the same material as the common electrode COM and may be patterned simultaneously with the common electrode COM, but is not limited thereto. The conductive connection part CNT may be formed of a metal different from that of the common electrode COM. The conductive connection part CNT connects the alignment layer PI to the pixel electrode PXL and the common electrode COM to form a discharge path of ions accumulated on the alignment layer PI. The conductive connection part CNT covers the pixel electrode PXL to prevent the pixel electrode PXL from being etched in the etching process of the common electrode COM, and there is a step difference between the alignment layer PI and the common electrode COM. prevent it from growing

The pixel electrode PXL may be formed on the organic passivation layer PAL. The conductive connection part CNT may overlap the data line DL or overlap the spacer in order to minimize the decrease in the aperture ratio of the pixel. The black matrix overlaps the TFT, the data line DL, the gate line GL, the spacer, the conductive connection part CNT, and the like to make these components invisible.

The inventors of the present application conducted an afterimage test on various alignment layers having different resistances, and as a result, when the alignment layer was in contact with the pixel electrode PXL and the common electrode COM, a discharge path of ions was formed and the afterimage problem was improved. . The inventor confirmed the afterimage improvement effect even if the resistance of the alignment layer was high. As a result of an afterimage experiment by varying the contact area ratio between the pixel electrode PXL and the common electrode COM of the alignment layer, the inventors confirmed that the afterimage problem was improved even when the contact area ratio was changed. 4A is a view showing an afterimage test result of the prior art and the present invention. In this experiment, the sample selected as a conventional technique is a liquid crystal display device in which the common electrode COM and the pixel electrode PXL are separated with an insulating layer interposed therebetween, and the alignment layer PI is connected only to the pixel electrode.

The sample selected as the present invention in the afterimage experiment is the liquid crystal display shown in FIGS. 7 to 9 having a lower plate having the structure as shown in FIG. 2 . In the afterimage and flicker experiment, after displaying the white grayscale block and the black grayscale block on the screen of the liquid crystal display and maintaining it for a certain period of time, the grayscale value of the pixel data on the entire screen is changed to an intermediate grayscale, for example, 127 to check whether an afterimage is visible. It is an experiment to As a result of the afterimage test, an afterimage as shown in FIG. 4A was seen in the case of the prior art, whereas the afterimage was not seen in the case of the present invention as shown in FIG. 4B.

5 is a view showing an image pattern of a sample used for an afterimage test result.

FIG. 5A is a diagram illustrating some pixels in a white grayscale block in a solid pattern for inducing an afterimage in a liquid crystal display. In the case of the solid pattern, after a predetermined time elapses after the white gray voltage is supplied to the positive pixels and the negative pixels in the white gray block, the half gray voltage is supplied. In the case of the solid pattern, after a predetermined time elapses after the black gray voltage is supplied to the positive pixels and the negative pixels in the black gray block, the half gray voltage is supplied. The positive polarity pixels are pixels to which a positive polarity data voltage is supplied. The negative polarity pixels are pixels to which a negative polarity data voltage is supplied. The polarity of the data voltage is inverted in units of frame periods.

FIG. 5B is a diagram illustrating some pixels within a white grayscale block in a flicker pattern for inducing flicker in a liquid crystal display. In the case of the flicker pattern, a white gradation voltage is supplied to pixels of the same first polarity in a white gradation block, a black gradation voltage is supplied to pixels of a second polarity, and then, after a predetermined time elapses, the intermediate gradation voltage is supplied do. The first polarity is positive or negative. The second polarity is different from the first polarity. After a predetermined time elapses after the black gray voltage is supplied to the positive pixels and the negative pixels in the black gray block, the half gray voltage is supplied. The data voltage is inverted in units of frame periods.

The inventors of the present inventors changed the ratio of the area in which the alignment layer PI was in contact with the pixel electrode PXL and the area in which the alignment layer PI was in contact with the common electrode COM in the afterimage experiment, as shown in FIGS. The improvement effect was confirmed. 6A to 6E , the area ratio of the alignment layer PI and the pixel electrode PXL is the same, and the area ratio of the alignment layer PI and the common electrode COM is different. The area ratio of the alignment layer PI and the common electrode COM varies according to the number and size of the conductive connection parts CNT as shown in FIGS. 6A to 6E .

The alignment layer PI is in contact with the common electrode COM through the conductive connections CNT, CNT1, and CNT2 disposed on the data line DL or on the column spacer CS, and is in direct contact with the pixel electrode PXL. do. In FIG. 6E , “CNT1” is a first conductive connection disposed on the data line DL, and “CNT2” is a second conductive connection overlapping the column spacer CS. The conductive connection portions CNT, CNT1, and CNT2 overlap the black matrix BM and are covered by the black matrix BM. FIG. 9 is a cross-sectional view illustrating conductive connection parts CNT1 and CNT2 as shown in FIG. 6E .

Based on the afterimage and flicker test results, the inventors of the present invention have obtained an afterimage improvement effect when the ratio of the alignment layer (PI) to the pixel electrode (PXL) and the common electrode (COM) is 2:1 to 6:1, as shown in Table 1 could check

drawing Figure 5a Figure 5b Figure 5c Figure 5d Figure 5e the contact area of the alignment layer
pixel electrode
(PXL) 4776.0 μm ² 4776.0 μm ² 4776.0 μm ² 4776.0 μm ² 4776.0 μm ² common electrode
(COM) 729.1 μm ² 727.4 μm ² 1212.8 μm ² 1480.6 μm ² 2303.9 μm ² contact area ratio
(PXL: COM) 6:1 6:1 4:1 3 : 1 2:1 contact location
Contacted on both data lines (DL) for every sub-pixel Contacted on one data line DL for every sub-pixel Enlarges the contact area on both data lines DL for every sub-pixel The contact area on both data lines DL is further enlarged for every sub-pixel Contacted on both data lines DL for every sub-pixel, and contacted at a spacer position

7 is an enlarged plan view of one sub-pixel in the liquid crystal display according to the first exemplary embodiment of the present invention. FIG. 8 is a cross-sectional view showing the cross-sectional structure of the lower plate of the liquid crystal display device taken along the line "I-I'" in FIG. 7 . FIG. 9 is a cross-sectional view illustrating conductive connection parts CNT1 and CNT2 as shown in FIG. 6E . The liquid crystal display shown in FIGS. 7 to 9 includes a lower plate having the same structure as in FIG. 2 .

7 to 9 , the lower plate includes a TFT, a gate insulating layer (GI), an etch stopper layer (ES), a first inorganic passivation layer (PAS0), an organic passivation layer (PAC), a common electrode (COM), and a second 2 includes an inorganic passivation layer PAS1 , a conductive connection part CNT, a pixel electrode PXL, and a lower alignment layer PI.

The gate line GL and the gate G of the TFT are formed on the lower substrate SUBS1. The gate insulating film GI is formed of an inorganic insulating film such as SiOx or SiNx to cover the gate G of the TFT. The gate G of the TFT is integrated with the gate line GL. The semiconductor pattern ACT is formed on the gate insulating layer GI to overlap the gate G of the TFT. The semiconductor pattern ACT is formed of a semiconductor material such as amorphous silicon (a-Si) LTPS or an oxide semiconductor and is used as an active channel layer of the TFT. Sources and drains S and D of the TFT are formed on the semiconductor pattern ACT to overlap the gate G of the TFT. The drain D is integrated with the data line DL. The source S is in contact with the pixel electrode PXL through a contact hole CH passing through the first inorganic passivation layer PAS0 , the organic passivation layer PAC, and the second inorganic passivation layer PAS1 . The etch stopper layer ES is made of an inorganic insulating material such as SiOx and is formed on the semiconductor pattern ACT and the gate insulating layer GI. ) to protect The first inorganic passivation layer PAS0 is formed of an inorganic insulating layer such as SiOx or SiNx to cover the TFT and the etch stopper ES. The organic passivation layer PAC is formed of an organic insulating material such as photo-acryl and covers the first inorganic passivation layer PAS0. The common electrode COM, the conductive connection part CNT, and the pixel electrode PXL may be formed of a transparent electrode material such as indium-tin oxide (ITO).

The common electrode COM is formed on the organic passivation layer PAC. The second inorganic passivation layer PAS1 is formed of an inorganic insulating layer such as SiOx or SiNx to cover the common electrode COM. The conductive connection part CNT is connected to the common electrode COM through a contact hole penetrating the second inorganic passivation layer PAS1 . The pixel electrode PXL is formed on the second inorganic passivation layer PAS1 to overlap the common electrode COM. The pixel electrode PXL and the conductive connection part CNT may be simultaneously formed of the same material. The pixel electrode PXL is in contact with the source S of the TFT through the contact hole CH.

The lower alignment layer PI is formed on the second inorganic passivation layer PAS1 to cover the pixel electrode PXL and the conductive connection part CNT. The lower alignment layer PI directly contacts the pixel electrode PXL and is connected to the common electrode COM through the conductive connection part CNT. The lower alignment layer PI is photo-aligned in contact with the negative liquid crystal nLC on the lower plate to set a pretilt angle of the liquid crystal molecules.

A black matrix BM, a color filter CF, an upper alignment layer PI, and a column spacer CS are formed on the upper plate. The black matrix BM and the color filter CF are formed on the upper substrate SUBS2. The upper alignment layer PI is photo-aligned in contact with the negative liquid crystal nLC on the upper plate to set a pre-tilt angle of the liquid crystal molecules. The column spacer CS is formed between the upper and lower plates to maintain a cell gap of the negative liquid crystal layer.

In the case of the liquid crystal display according to the second embodiment of the present invention, positions of the pixel electrode PXL and the common electrode COM are opposite to each other in FIGS. 7 to 9 , and the pixel electrode PXL is connected to the TFT.

10 is a view showing a structure of a lower plate of a liquid crystal display according to a third embodiment of the present invention.

Referring to FIG. 10 , the liquid crystal display of the present invention includes a pixel electrode PXL disposed on the common electrode COM with an insulating layer interposed therebetween, and an alignment layer PI in contact with the pixel electrode PXL and the common electrode COM. ) is included. The passivation layer PAS1 is an insulating layer formed between the common electrode COM and the pixel electrode PXL.

In this embodiment, the common electrode COM is a lower electrode positioned below the pixel electrode PXL, and the pixel electrode PXL is an upper electrode.

An open hole OH exposing the common electrode COM is formed in the passivation layer PAS1 . The open hole OH exposes the common electrode COM in all areas except the pixel electrode PXL. For example, the open hole OH exposes the common electrode COM between the pixel electrodes PXL in the opening area of the pixel, and also exposes the common electrode COM in the non-opening area covered by the black matrix. . The alignment layer PI contacts the pixel electrode PXL and also contacts the common electrode COM through the open hole OH. Ions accumulated in the alignment layer PI are discharged through the electrodes PXL and COM because the alignment layer PI is directly connected to the pixel electrode PXL and the common electrode COM.

Since the open hole OH exposes the common electrode COM at a portion other than the pixel electrode, a contact area between the alignment layer PI and the common electrode COM may be increased compared to the above-described exemplary embodiment. When the contact area between the alignment layer PI and the common electrode COM is small or the contact resistance thereof is high, the effect of improving afterimage and flicker is different depending on the alignment layer material. As a result of the experiment, if the contact area between the alignment layer PI and the common electrode COM is enlarged as shown in FIG. 10 , even if there is a difference in composition or physical properties of the alignment layer, the image quality and flicker can be significantly improved.

11 is a view showing a structure of a lower plate of a liquid crystal display according to a fourth embodiment of the present invention.

Referring to FIG. 11 , the liquid crystal display of the present invention includes a common electrode COM disposed on the pixel electrode PXL with an insulating layer interposed therebetween, and an alignment layer PI in contact with the pixel electrode PXL and the common electrode COM. ) is included. The passivation layer PAS1 is an insulating layer formed between the common electrode COM and the pixel electrode PXL.

In this embodiment, the pixel electrode PXL is a lower electrode positioned below the common electrode COM, and the common electrode COM is an upper electrode.

An open hole OH exposing the pixel electrode PXL is formed in the passivation layer PAS1 . For example, the open hole OH exposes the pixel electrode PXL between the common electrodes COM in the opening region of the pixel. The alignment layer PI contacts the pixel electrode PXL and also contacts the common electrode COM through the open hole OH. Ions accumulated in the alignment layer PI are discharged through the electrodes PXL and COM because the alignment layer PI is directly connected to the pixel electrode PXL and the common electrode COM.

This embodiment is substantially the same as the third embodiment of the present invention except for a structure in which the positions of the common electrode COM and the pixel electrode PIX are exchanged.

12 is an enlarged plan view of one sub-pixel in the liquid crystal display according to the third exemplary embodiment of the present invention. 13 is a cross-sectional view showing a cross-sectional structure of a lower plate of the liquid crystal display device taken along line "II-II'" in FIG. 12 .

12 and 13 , the liquid crystal display includes an upper plate and a lower plate bonded to each other with a liquid crystal layer interposed therebetween. The structure of the upper plate is substantially the same as that of the above-described embodiments. The lower plate is TFT, gate insulating layer (GI), etch stopper layer (ES), first inorganic passivation layer (PAS0), organic passivation layer (PAC), common electrode (COM), second inorganic passivation layer (PAS1), pixel electrode (PXL) , and a lower alignment layer PI.

The gate line GL and the gate G of the TFT are formed on the lower substrate SUBS1. The gate insulating film GI is formed of an inorganic insulating film such as SiOx or SiNx to cover the gate G of the TFT. The gate G of the TFT is integrated with the gate line GL. The semiconductor pattern ACT is formed on the gate insulating layer GI to overlap the gate G of the TFT. The semiconductor pattern ACT is formed of a semiconductor material such as amorphous silicon (a-Si) LTPS or an oxide semiconductor and is used as an active channel layer of the TFT. Sources and drains S and D of the TFT are formed on the semiconductor pattern ACT to overlap the gate G of the TFT. The drain D is integrated with the data line DL. The source S is in contact with the pixel electrode PXL through a contact hole CH passing through the first inorganic passivation layer PAS0 , the organic passivation layer PAC, and the second inorganic passivation layer PAS1 . The etch stopper layer ES is made of an inorganic insulating material such as SiOx and is formed on the semiconductor pattern ACT and the gate insulating layer GI. ) to protect The first inorganic passivation layer PAS0 is formed of an inorganic insulating layer such as SiOx or SiNx to cover the TFT and the etch stopper ES. The organic passivation layer PAC is formed of an organic insulating material such as photo-acryl and covers the first inorganic passivation layer PAS0. The common electrode COM and the pixel electrode PXL may be formed of a transparent electrode material such as ITO.

The common electrode COM is formed on the organic passivation layer PAC. The second inorganic passivation layer PAS1 is formed of an inorganic insulating layer such as SiOx or SiNx to cover a portion of the common electrode COM. An open hole OH exposing the common electrode COM is formed in the second inorganic passivation layer PAS1 . Since the open hole OH is patterned using the pixel electrode pattern as a mask, the common electrode COM is exposed in all areas except the pixel electrode.

The pixel electrode PXL is formed on the second inorganic passivation layer PAS1 to overlap the common electrode COM. The pixel electrode PXL is in contact with the source S of the TFT through the contact hole CH.

The lower alignment layer PI is formed on the second inorganic passivation layer PAS1 to cover the pixel electrode PXL and also to cover the common electrode COM through the open hole OH. The lower alignment layer PI directly contacts the pixel electrode PXL and the common electrode COM. The lower alignment layer PI is photo-aligned in contact with the negative liquid crystal nLC on the lower plate to set a pretilt angle of the liquid crystal molecules.

12 and 13, when the positions of the pixel electrode PXL and the common electrode COM are changed to be opposite to each other and the pixel electrode PXL is connected to the TFT, the structure is the same as in the fourth embodiment of the present invention as shown in FIG. It is the same as the liquid crystal display according to the

14 is a cross-sectional view illustrating a method of forming an open hole in the liquid crystal display of FIG. 13 .

Referring to FIG. 14 , a passivation layer PAS1 and a pixel electrode material layer are stacked on the common electrode COM.

The pixel electrode PXL and the passivation layer PAS1 may be patterned through a single photolithography process. A photoresist is applied on the pixel electrode material layer, a photomask is arranged thereon, and exposure and development processes are performed to pattern the photoresist, thereby forming a photoresist pattern (PR) on the pixel electrode material layer. to form

In the present invention, the pixel electrode PXL is formed on the passivation layer PAS1 by performing wet etching to remove only the pixel electrode material layer under the photoresist pattern PR and etching away the other pixel electrode material layers. . Next, in the present invention, the common electrode COM is exposed by performing dry etching while the photoresist pattern PR remains and etching a protective layer other than the protective layer covered by the photoresist pattern PR. An open hole (OH) is formed. An alignment layer PI (not shown) is applied over the entire lower plate. The alignment layer PI contacts the pixel electrode PXL and also contacts the common electrode COM through the open hole OH.

When the positions of the pixel electrode PXL and the common electrode COM are changed in FIG. 14 , the structure is the same as in FIG. 11 .

In the liquid crystal display of the present invention, the pixel electrode PXL and the common electrode COM are vertically overlapped to form a storage capacitor Cst therebetween. As a result, according to the present invention, the alignment layer PI is brought into contact with the pixel electrode PXL and the common electrode COM to improve afterimage and flicker, and since a wide storage capacitor Cst is not separately formed in the pixel. It is possible to increase the aperture ratio of the pixel. The effect of the aperture ratio can be clearly seen in FIGS. 15 and 16 .

15 and 16 are diagrams comparing the pixel structure of the present invention and the pixel structure of the comparative example. The comparative example is an example of a pixel structure in which the common electrode COM is exposed through an open hole passing through the insulating layer PAS1 and the pixel electrode PXL and the common electrode COM do not overlap each other. The comparative example is a pixel structure of an example similar to the pixel structure of the present invention, but in which the storage capacitor is different. It should be noted that the comparative example is not a well-known prior art.

15 is a plan view comparing the aperture area Apxl of the pixel structure of the present invention with that of a comparative example. FIG. 16 is a cross-sectional view showing a cross-sectional structure of a lower plate of the liquid crystal display device taken along the lines “III-III′” and “IV-IV′” in FIG. 15 .

15A and 16A are the pixel structures of the present invention as shown in FIGS. 11 and 12 . 15(B) and 16(B) are pixel structures of a comparative example.

Since the pixels of the present invention overlap the pixel electrode PXL and the common electrode COM, a storage capacitor Cst is formed therebetween. In contrast, in the comparative example, since the pixel electrode PXL and the common electrode COM do not overlap, a storage capacitor Cst having a large area should be provided in each of the pixels. Accordingly, in the present invention, since the aperture area Apxl of the pixel can be wider than that of the comparative example, the aperture ratio and transmittance of the pixel can be increased.

In the present invention, since the fringe field capacitance Cf between the pixel electrode PXL and the common electrode COM is larger than that of the comparative example, the fringe field for driving the liquid crystal may be applied more strongly than that of the comparative example.

As described above, according to the present invention, in a liquid crystal display having a structure in which a lower electrode and an upper electrode are overlapped with an insulating film interposed therebetween, the alignment film is in contact with the lower electrode through a hole penetrating the insulating film. As a result, in the present invention, the alignment layer is directly in contact with the lower electrode and the upper electrode to form a discharge path of ions accumulated on the alignment layer, thereby preventing the accumulation of ions in normal driving and low speed driving modes, thereby reducing image quality deterioration due to afterimage and flicker. can be prevented Furthermore, the present invention can improve image quality in a low-speed driving mode by using a negative liquid crystal, a photo-alignment layer, and an oxide TFT.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUBS1, SUBS2: Substrate GI: Gate Insulation Film
GL: gate line ACT: semiconductor pattern
G: gate electrode of TFT S, G: source and drain electrode of TFT
PAS1, PAS2: inorganic protective film PAC: organic protective film
COM: common electrode PXL: pixel electrode
CNT: conductive connection part PI: alignment layer

Claims (12)

In the liquid crystal display device comprising an upper plate and a lower plate facing each other with a liquid crystal layer interposed therebetween, and a spacer disposed between the upper plate and the lower plate,
The lower plate is
a lower electrode and an upper electrode overlapping with an insulating film therebetween;
a TFT connected to any one of the lower electrode and the upper electrode; and
an alignment layer in contact with the lower electrode and the upper electrode;
The alignment layer is in contact with the lower electrode through a conductive connection portion disposed in a hole passing through the insulating layer and in contact with the lower electrode,
The conductive connection portion overlaps the TFT. The method of claim 1,
The lower electrode is a common electrode to which a common voltage is supplied,
The upper electrode is a pixel electrode to which a data voltage is supplied. The method of claim 1,
The upper electrode is a common electrode to which a common voltage is supplied,
The lower electrode is a pixel electrode to which a data voltage is supplied. delete The method of claim 1,
The hole exposes the lower electrode in a region other than the upper electrode. The method of claim 1,
The lower plate is
Further comprising a data line and a gate line crossing each other,
The conductive connection part is disposed on the data line. The method of claim 1,
The conductive connection portion overlaps the spacer. The method of claim 1,
The lower plate is
Further comprising a data line and a gate line crossing each other,
The conductive connection portion overlaps the data line and overlaps the spacer. The method of claim 1,
The liquid crystal layer includes a negative liquid crystal display. The method of claim 1,
The lower plate is
data lines and gate lines crossing each other; and
and an oxide TFT disposed between the data line and the gate line. The method of claim 1,
The liquid crystal display device wherein the alignment layer is a photo-alignment layer. The method of claim 1,
The upper plate includes a black matrix,
The conductive connection portion overlaps the black matrix.

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