WO2015152817A1

WO2015152817A1 - Methods of recycling substrates and carrier substrates

Info

Publication number: WO2015152817A1
Application number: PCT/SG2015/000048
Authority: WO
Inventors: Hilmi Volkan Demir; Swee Tiam TAN
Original assignee: Nanyang Technological University
Priority date: 2014-03-31
Filing date: 2015-02-16
Publication date: 2015-10-08
Also published as: EA201691900A1; CN106463451A; EP3127143A1; TW201601192A; CN106463451B; EP3127143A4

Abstract

In various embodiments, a method of recycling a carrier substrate is provided. The method comprises: providing said carrier substrate; forming a buffer layer by depositing a suitable material on the carrier substrate, forming one or more component layers over the buffer layer; separation of the one or more component layers from the carrier substrate so that at least a portion of the buffer layer remains on the carrier substrate after separation; and forming a further buffer layer from the portion of the buffer layer after the separation by depositing the suitable material to recycle the carrier substrate. Also a method of recycling a substrate is provided that comprises: forming an insulating layer on a substrate; removing a first portion of the insulating layer to expose a first portion of the substrate; forming one or more component layers over the first portion of the substrate; and separating the one or more component layers from the substrate for recycling the substrate.

Description

METHODS OF RECYCLING SUBSTRATES AND CARRIER SUBSTRATES

CROSS-REFERENCE TO RELATED APPLICATIONS

[001] This application claims the benefit of priority of United States application No. 61/972,575 filed March 31, 2014, the contents of it being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[002] Various aspects of this disclosure relate to methods of recycling substrates and carrier substrates.

BACKGROUND

[003] In Indium Gallium Nitride/Gallium Nitride (InGaN/GaN) based light- emitting devices have shown tremendous progress with the design of the vertical light-emitting diodes (LEDs). Manufacturing processes of vertical LEDs may include the transfer of the epitaxial layer from sapphire substrate to metal substrate (such as copper) for better heat management. It is well known that the sapphire substrate can be recycled to reduce the cost after the removal process. However, for the conventional vertical LED fabrication process, there are several technical challenges need to be addressed.

SUMMARY

[004] In various embodiments, a method of recycling a carrier substrate may be provided. The method may include providing said carrier substrate. The method may further include forming a buffer layer by depositing a suitable material on the carrier substrate, thereby forming a composite substrate comprising the carrier substrate and the buffer layer. The method may also include forming one or more component layers over the buffer layer. The method may additionally include separating in a separation process the one or more component layers from the carrier substrate so that at least a portion of the buffer layer remains on the carrier substrate when the one or more component layers are separated from the carrier substrate. The method may further include forming a further buffer layer from the portion of the buffer layer after the separation process by depositing the suitable material to recycle the carrier substrate.

[005] In various embodiments, a method of recycling a substrate may be provided. The method may include providing said substrate. The method may further include forming an insulating layer over the substrate. The method may additionally include removing a first portion of the insulating layer so that a first portion of the substrate is exposed and a second portion of the substrate is covered by a second portion of the insulating layer. The method may also include forming one or more component layers over the first portion of the substrate after the first portion of the insulating layer is removed. The method may further include separating the one or more component layers from the substrate in a separation process for recycling the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[006] The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which:

FIG. 1 is a schematic illustrating a method of recycling a carrier substrate according to various embodiments.

FIG. 2A is a schematic illustrating forming of a composite substrate according to various embodiments.

FIG. 2B is a schematic illustrating epitaxial layers formed over the composite substrate according to various embodiments. FIG. 2C is a schematic illustrating an isolation process according to various embodiments.

FIG. 2D is a schematic illustrating processing steps subsequent to the isolation process according to various embodiments.

FIG. 2E is a schematic illustrating the separation process according to various embodiments.

FIG. 2F is a schematic illustrating further processes after separation according to various embodiments.

FIG. 3 is a schematic illustrating a method of recycling a substrate according to various embodiments.

FIG. 4A is a schematic illustrating forming a continuous insulating layer on a substrate according to various embodiments.

FIG. 4B is a schematic showing a photolithographic process involving a photoresist on the insulating layer according to various embodiments.

FIG. 4C is a schematic illustrating removal of a first portion of the insulating layer so that a second portion of the insulating layer remains on the substrate.

FIG. 4D is a schematic showing a top planar view of the structure in FIG. 5C according to various embodiments.

FIG. 4E is a schematic illustrating a light emitting diode (LED) epitaxial stack grown in the substrate according to various embodiments.

FIG. 4F is a schematic illustrating further process steps to the light emitting diode (LED) epitaxial stacks according to various embodiments.

FIG. 4G is a schematic illustrating the separation process according to various embodiments.

FIG. 4H is a schematic illustrating further processing step after the separation process according to various embodiments.

FIG. 5 is a schematic illustrating a method involving both template growth and partition growth according to various embodiments. DETAILED DESCRIPTION

[007] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[008] In order that the invention may be readily understood and put into practical effect, particular embodiments will now be described by way of examples and not limitations, and with reference to the figures.

[009] It should be understood that the terms "on", "over", "lateral", "top", "bottom", "down", "side", "back", "left", "right", "front" etc., when used in the following description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of any device or structures or any part of any device or structure.

[010] It is also known that the surface of the recycled substrates may be polished by removing some material from the substrate to recover the surface. However, this method may reduce the thickness of the substrates physically, which may then limit the number of. substrate recycling. Moreover, the polishing process may involve labour and machine cost, thus increasing the cost of the recycled substrates.

[011] FIG. 1 is a schematic 100 illustrating a method of recycling a carrier substrate according to various embodiments. The method may include, in 102, providing said carrier substrate. The method may further include, in 104, forming a buffer layer by depositing a suitable material on the carrier substrate, thereby forming a composite substrate including the carrier substrate and the buffer layer. The method may also include, in 106, forming one or more component layers over the buffer layer. The method may additionally include, in 108, separating in a separation process the one or more component layers from the composite substrate so that at least a portion of the buffer layer remains on the carrier substrate when the one or more component layers are separated from the composite substrate. The method may further include, in 110, forming a further buffer layer from the portion of the buffer layer after the separation process by depositing the suitable material to recycle the carrier substrate.

[012] In other words, the method may include forming a composite substrate including a buffer layer on a carrier substrate. The method may include forming one or more component layers over the buffer layer. The one or more component layers may subsequently be separated from the composite substrate. A portion of the buffer layer may remain on the carrier substrate. A further buffer layer may be regrown based on the portion of the buffer layer remaining on the carrier substrate.

[013] During the separation portion, a further portion of the buffer layer may be lost or defects may appear on the buffer layer. As such, the suitable material may be deposited to regrow the buffer layer.

[014] A first layer over a second layer may include a first layer on the second layer or may include situations in which the first layer is separated from the second layer by one or more intervening layers.

[015] In various embodiments, at least a further portion of the buffer layer may be removed from the composite substrate during the separation process. The further portion of the buffer layer may be attached/adhered to the one or more component layers or may be removed (e.g. being vaporized) during the separation process.

[016] Separating the one or more component layers from the composite substrate may include irradiating the radiation absorption layer with electromagnetic waves, e.g. with ultraviolet radiation or ultraviolet light. In various embodiments, the separation process may be or may include an ultraviolet laser lift-off (LLO) process. The carrier substrate and the buffer layer may be transparent to the electromagnetic waves. The further buffer layer may also be transparent to the electromagnetic waves. The electromagnetic waves may be introduced on a side of the carrier substrate opposite the side of the carrier substrate attached or adhered to the buffer layer. The electromagnetic waves may pass through the carrier substrate and the buffer layer to irradiate the radiation absorption layer. Irradiating the radiation absorption layer with the electromagnetic waves may decompose the radiation absorption layer. For instance, irradiation an unintentionally doped or doped gallium nitride (GaN) layer may decompose the GaN into gaseous nitrogen and liquid gallium.

[017] Other types of electromagnetic radiation or electromagnetic waves suitable for causing internal and/or external exfoliation of the radiation absorption layer may include X-rays, milli-waves, micro-waves, infra-red waves or gamma rays.

[018] In various embodiments, a thickness of the further buffer layer may be substantially equal to a thickness of the buffer layer. In other words, the thickness of the further buffer layer may be regrown to the thickness of the buffer layer. In various embodiments, the further buffer layer may be regrown to reduce or remove defects in the buffer layer. In various embodiments, a thickness of the further buffer layer is substantially different from a thickness of the buffer layer. In other words, the thickness of the further buffer layer may be thicker or thinner than the thickness of the buffer layer.

[019] In various embodiments, the lattice spacing of the substrate may be substantially equal or substantially matched to the lattice spacing of the buffer layer. The difference between the lattice spacing of the substrate and the lattice spacing of the buffer layer may be less than 15% or less than 5% or less than 1% of the lattice spacing of the substrate. In particular, the lattice mismatch between A1N and sapphire may be about 13.3% (after crystal rotation of about 30°). [020] The suitable material (for the buffer layer) may include aluminum nitride (AIN). The substrate may include one or more selected from a group consisting of sapphire (A1₂0₃), silicon carbide (SiC) or aluminum nitride (AIN).

[021] In various embodiments, the method may include forming a radiation absorption layer on the buffer layer. The method may also include forming the one or more component layers on the radiation absorption layer. The radiation absorption layer may be or may include (crystalline) gallium nitride (GaN) such as unintentionally doped GaN. The one or more component layers may include a layer of a first conductivity type on the radiation absorption layer. The one or more component layers may further include an active layer on the layer of the first conductivity type. The one or more component layers may additionally include a layer of a second conductivity type on the active layer. In various, the one or more component layers may be a light-emitting device/diode or a portion of a light emitting device/diode. In various other embodiments, the one or more component layers may be a transistor or portion of a transistor or any other suitable electronic device or portion of an electronic device.

[022] In various alternate embodiments, the one or more component layers may include a radiation absorption layer. The radiation absorption layer may be on the buffer layer. The radiation absorption layer may be or may include (crystalline) gallium nitride (GaN) such as doped GaN. The radiation absorption layer may be of a first conductivity type. The one or more component layers may further include an active layer on the radiation absorption layer. The one or more component layers may additionally include a layer of a second conductivity type on the active layer.

[023] In various embodiments, the radiation absorption layer may instead include mixed nitrides of one or more of indium, gallium and aluminum. The radiation absorption layer may additionally or alternatively include poly silicon or single- crystalline silicon. [024] . The method may also include forming one or more isolation trenches before the separation process. The one or more isolation trenches may extend through the one or more component layers. The one or more isolation trenches may terminate at the buffer layer. The one or more isolation trenches may terminate at the interface of the buffer layer and the radiation absorption layer. The method may also include depositing insulating material in the one or more isolation tranches to form passivation structures. The method may further include forming one or more electrode structures on the one or more component layers before the separation process. The method may additionally include forming a supporting layer on the one or more electrode structures before the separation process.

[025] An intermediate structure including the one or more component layers, the one or more electrode structures and the supporting layer may be separated from the composite structure during the separation process. The intermediate structure may be flipped during or after the separation process so that a bottom surface of the intermediate structure becomes a top surface of the intermediate structure. The method may further include forming one or more further electrode structures over the intermediate structure after the separation process.

[026] The method may further include forming one or more further component layers on or over the further buffer layer. By forming a further buffer layer from the portion of the buffer layer, a further composite substrate including the carrier substrate and the further buffer layer (on the carrier substrate) may be formed. The one or more further component layers may be formed on or over the further buffer layer to recycle or reuse the carrier substrate. In various embodiments, the one or more further component layers may be a (further) light-emitting diode/device or a portion of a (further) light-emitting diode/device. In various embodiments, the one or more component layers may be a (further) transistor or a portion of a (further) transistor or a (further) electronic device or a portion of a (further) electronic device. [027] The method may further mclude separating in a further separation process the one or more further component layers from a further composite substrate including the carrier substrate and the further buffer layer.

[028] In various embodiments, a device or structure formed by any method described herein may also be provided. The device or structure may be a light- emitting device/diode or a portion of a light-emitting device/diode. The device or structure may instead be a transistor or a portion of a transistor or an electronic device or a portion of an electronic device.

[029] FIG. 2A is a schematic 200a illustrating forming of a composite substrate according to various embodiments. A buffer layer 204 may be grown on a carrier substrate 202 to form the composite substrate. The buffer layer 204 may be or may include aluminum nitride (A1N). The carrier substrate 202 may be sapphire (A1₂0₃), silicon carbide (SiC) or aluminum nitride (A1N). The carrier substrate 202 may also be referred to as a carrier wafer. The buffer layer 204 may be grown on a surface of the carrier substrate 202. The buffer layer 204 may be deposited using metalorganic chemical vapour deposition (MOCVD), molecular beam epitaxy (MBE) or atomic layer deposition (ALD). The thickness of the buffer layer 204 may be a suitable value in the range of about 0.1 μιη to about 10 μπι. The composite substrate may also be referred to as an epitaxial template.

[030] FIG. 2B is a schematic 200b illustrating epitaxial layers formed over the composite substrate according to various embodiments. The epitaxial layers may be or may include a light emitting diode (LED) epitaxial wafer. The epitaxial layers may include one or more component layers. In various embodiments, the epitaxial layers may include a separate radiation absorption layer 206. The one or more component layers may include a layer of n-type doped GaN 208, an active layer 210 (which may include or consists of InGaN/GaN. multiple quantum wells), and a layer of p-type doped GaN 212. The one or more component layers may be formed on or over an optional layer of unintentionally doped GaN (u-GaN) 206. The epitaxial layers may be grown using metalorganic chemical vapour deposition (MOCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD).

[031] In various embodiments, the optional layer of unintentionally doped GaN (u-GaN) 206 may be the radiation absorption layer formed on the buffer layer 204. One or more component layers 208, 210, 212 may be formed on or over the radiation absorption layer 206.

[032] The n-type doped layer 208 may be interchanged with the p-type doped layer 212. In general, the one or more component layers may include a layer of a first conductivity type on the radiation absorption layer. The one or more component layers may further include an active layer on the first conductivity layer. The one or more component layers may also include a layer of a second conductivity type on the active layer.

[033] In various embodiments, the one or more component layers may include the radiation absorption layer. For instance, the n-type doped GaN layer 208 may be the radiation absorption layer formed on the buffer layer. The unintentionally doped GaN layer 206 may be absent. The one or more component layers may further include active layer 210 on the n-type doped GaN layer 208 and a p-type doped GaN layer 212 on the active layer 210.

[034] The n-type doped layer 208 may be interchanged with the p-type doped layer 212. In general, the radiation layer may be of a first conductivity type. The one or more component layers may further include an active layer on the radiation absorption layer and a layer of a second conductivity type on the active layer.

[035] FIG. 2C is a schematic 200c illustrating an isolation process according to various embodiments. The isolation process may be executed to cut through the LED epitaxial layers 206, 208, 210, 212, stopping at the buffer layer 204, to define the chip size and to isolate the individual devices. The chip size may each have a suitable dimension ranging from about 0.3 mm to about 5.0 mm. The isolation may be achieved by inductively coupled plasma (ICP) etching, reactive ion etching (RIE), or laser scribing. The isolation process may include forming one or more isolation trenches 214. The isolation trenches 214 may be formed before the separation process. The one or more isolation trenches 214 may extend through the one or more component layers 208, 210, 212. The one or more isolation trenches 214 may further extend through layer 206. The one or more isolation trenches 214 may terminate at the buffer layer 204. The one or more isolation trenches 214 may terminate at the interface of buffer layer 204 and layer 206.

[036] FIG. 2D is a schematic 200d illustrating processing steps subsequent to the isolation process according to various embodiments. The method may further include forming one or more electrode structures, e.g. p-electrode stacks 216, on or over the one or more component layers. Each electrode structures 216 may be an electrode stack. The one or more electrode structures 216 may be formed before the separation process. The one or more electrode structures 216 may be formed on layer 212. The one or more electrode structures 216 may serve as ohmic contacts with layer 212. The one or more component , layers may include a reflective layer and a lateral current conductor. The reflective layer may be between the one or more component layers and the one or more electrode structures. The reflective layer and the lateral current conductor in each structure may be in ohmic contact with the electrode structures. The one or more electrode structures 216 may include a suitable material that allow light to arrive at (and pass through) the reflective layer. The suitable material for the electrode structures 216 may be transparent and conductive. The suitable material may be a transparent conductive oxide such as indium-tin-oxide (ITO) or may be a semi-transparent film such as nickel (Ni), silver (Ag), chromium (Cr), aluminum (Al) etc. The reflective layer may include one or more suitable materials selected from a group consisting of silver (Ag), aluminum (Al), Ag-based alloys and Al-based alloys. The lateral current conductor may include gold (Au), platinum (Pt), nickel (Ni), silver (Ag), aluminum (Al), tungsten (W), chromium (Cr), tin (Sn), copper (Cu) etc. The materials for the electrode structures 216 as well as the materials for the reflective layer and the lateral current conductor, may be deposited through electron beam evaporation or sputtering. The electrode structures 216 may be patterned using a photolithography process. The pattern may be generally designed with a marge between the edge of the layer 212 and the edge of the electrode structure 216.

[037] The method may further include depositing insulating material in the one or more isolation trenches 214 to form passivation structures 218. The passivation structures 218 may also be referred to as passivation layers or isolation structures. The space between the sidewalls of the devices may be protected by passivation structures 218. At the same time, the passivation structures 218 may cover layer 208 to prevent any possible leakage current. The passivation structure may extend from layer 206 to layer 210 or layer 212. If layer 206 is absent, the passivation structure may extend from layer 208 to layer 210 or layer 212. The passivation structures 218 may be patterned to partially expose the electrode structures 216 at the center. The passivation structures 218 may include a suitable passivation material such as an inorganic insulator like silicon oxide (SiO_x), silicon nitride (SiN_x), titanium dioxide (Ti0 ) and aluminum oxide (A1₂0₃), or an organic material such as photoresist, polymer, and SU- 8.

[038] The method may also include forming a supporting layer 220 on the one or more electrode structures. The supporting layer 220 may be formed before the separation process. After the passivation structures 218 are patterned, a supporting layer 220 may be applied to the whole wafer area. The supporting layer may include any one of Au, Ag, Ni, Cu, Pd, Ti, W, Cr, Al, Mo, Sn, etc. The supporting layer 220 may be formed by deposition methods such as electron beam evaporation, sputtering, or chemical electro-plating. The supporting layer may alternatively be or include silicon wafers, copper wafers or plastic films, which may be stuck to the LED wafer (the component layers and/or the electrode structures) through a wafer bonding process. The thickness of the supporting layer may be a suitable value in the range of about 10 μηι to about 1000 μηι. [039] The method may also include separating in a separation process the one or more component layers from the composite substrate so that at least a portion of the buffer layer remains on the carrier substrate when the one or more component layers are separated from the composite substrate. FIG. 2E is a schematic 200e illustrating the separation process according to various embodiments. The LED epitaxial layer may be transferred from the composite substrate to the supporting layer 220. The separation process may involve ultraviolet (UV) laser lift-off, which irradiates laser beam with selected wavelengths from the side of the composite substrate. Since the carrier substrate 202 and the buffer layer 204 are transparent to the UV laser, the UV photons may be absorbed by the GaN at the interface between layers 204, 206. The temperature at the interface may be sufficiently high to decompose the crystal GaN into gaseous nitrogen and liquid gallium. Hence the whole stack of materials may be separated at the interface. The spot size and shape of the laser beam may be patterned to match with the pattern of the isolation process, so that the edge of the beam may overlap with the isolation gap in process.

[040] After the separation process, the LED epitaxial layer may be transferred to the supporting layer, with the p-i-n structure reversed. An intermediate structure including the one or more component layers, the one or more electrode structures and the supporting layer may be separated from the composite structure during the separation process.

[041] FIG. 2F is a schematic 200f illustrating further processes after separation according to various embodiments. The method may further include thinning of the intermediate structure. The layer 206 may be (completely) removed during thinning. The layer 208 may be thinned or partially removed. An inductively coupled plasma (ICP) or reactive ion etching (RIE) etching process may be applied to etch down to a certain depth to the n-GaN layer .208, completely removing the u-GaN layer 206. The n-GaN layer 208 may be then randomly textured using wet chemical etching or periodically patterned through nano-imprinting or photolithography combined with " drying etching, to enhance the light extraction efficiency. Finally, one or more further electrode structures (e.g. n-electrode stacks) 222 may be deposited on the surface of the n-GaN layer 208, as shown in FIG. 2F. The further electrode structure 222 may spread the current laterally and serves as ohmic contact to the n-GaN layer 208. The material for the further electrode structure 222 may be selected from Ti, Al, Ag, Au, Pt, Cr, Pd, W, etc, and the deposition may be achieved by electron beam evaporation, thermal evaporation or sputtering.

[042] The buffer layer 204 on the original substrate wafer 202 may be cleaned using organic or acid based chemicals to remove any residuals and contaminations. The surface of the buffer layer 204 may also be smoothed through chemical- mechanical polishing (CMP) to remove any surface defects. The method may include forming a further buffer layer from the portion of the buffer layer after the separation process. The further buffer layer may be formed or grown from the remaining of the buffer layer 204 on the carrier substrate 202. The further buffer layer may be regrown to reduce or remove the defects in the buffer layer 204. The composite substrate including the carrier substrate 202 and the further buffer layer may then be recycled and ready for further fabrication processes.

[043] Various embodiments seek to reduce cost and increase yield. The carrier substrate may be recycled with the buffer layer 204 as a template. The buffer layer 204 may protect the carrier substrate 202 during the laser lift off (LLO) process. The laser may be strongly absorbed by the radiation absorption layer (sacrificial layer) on the buffer layer/ radiation absorption layer interface and only a very thin portion of the buffer layer may be damaged during the LLO process. As the buffer layer may be easily re-grown (e.g. in the MOCVD reactor prior to the growth of LED), the surface damage of the buffer layer may not be a critical issue. In addition to act as the protection layer, the buffer layer may also be a good buffer for the growth of the component layers (e.g. GaN epilayers. With a proper design and optimized buffer engineering, the growth time of the GaN epilayers may be reduced as well. [044] FIG. 3 is a schematic 300 illustrating a method of recycling a substrate according to various embodiments. The method may include, in 302, providing said substrate. The method may further include, in 304, forming an insulating layer on the substrate. The method may additionally include, in 306, removing a first portion of the insulating layer so that a first portion of the substrate is exposed and a second portion of the substrate is covered by a second portion of the insulating layer. The method may also include, in 308, forming one or more component layers over the first portion of the substrate after the first portion of the insulating layer is removed. The method may further include, in 310, separating the one or more component layers from the substrate in a separation process for recycling the substrate.

[045] In other words, the method may include forming an insulating layer on a substrate. The insulating layer may include a first portion and a second portion. The first portion of the insulating layer may be removed to expose an underlying first portion of the substrate. The second portion of the insulating layer remains on the substrate to cover an underlying second portion of the substrate. After removal of the first portion of the insulating layer, one or more component layers are formed over the first portion of the substrate. The one or more component layers may be separated from the substrate.

[046] The one or more component layers may be absent over the second portion of the substrate. The one or more component layers may be discontinuous over the substrate. . '

[047] Removing the first portion of the insulating layer may involve a photolithographic process. In various embodiments, the method may include depositing photoresist on the insulating layer after forming the insulating layer on the substrate.

[048] The method may include arranging a mask over the photoresist. The method may include directing electromagnetic radiation through the mask to 'the photoresist. The method may also include removing the portion of the photoresist over the portion of the insulating layer to expose the first portion of the insulating layer for removal. The photoresist may be patterned based on the mask. The insulating layer may be patterned based on the photoresist overlying the insulating layer. ·.

[049] In various embodiments, the photoresist may be or may include a positive photoresist. The portion of the photoresist may be exposed to the electromagnetic radiation before removal. The electromagnetic radiation may pass through holes on the mask (the holes overlying the portion of the photoresist) to reach the portion of the photoresist (i.e. the unmasked portion of the photoresist) over the portion of the insulating layer. The portion of the photoresist may absorb the electromagnetic radiation and may become soluble in a developer solution after the absorption of the electromagnetic radiation. The portion of the photoresist may subsequently be removed by the developer solution to expose the underlying first portion of the insulating layer. In other words, the method may further include removing the portion of the photoresist over the first portion of the insulating layer to expose the first portion of the insulating layer for removal.

[050] In various embodiments, the photoresist may be or may include a negative photoresist. The portion of the photoresist may be shielded from the electromagnetic radiation by the mask before removal. A further portion of the photoresist not shielded from the electromagnetic radiation by the mask (i.e. exposed to the electromagnetic radiation) may become less soluble in a developer solution. The portion of the photoresist may subsequently be removed by the developer solution to expose the underlying first portion of the insulating layer while the further portion of the photoresist may remain on the insulating layer. In other words, the method may further include removing the portion of the photoresist over the first portion of the insulating layer to expose the first portion of the insulating layer for removal.

[051] The second portion of the insulating layer may be or may include a partition grid. The partition grid may include a plurality of partition cells. The one or more component layers may be formed within each partition cell. The one or more component layers formed comprises a plurality of layered stacks. Each of the plurality of layered stacks may be within each partition cell. In other words, each layered stack may be surrounded by a partition cell. The partition cell may enclose the layered stack. The partition cells may isolate neighbouring layered stacks.

[052] In various embodiments, the method may further include forming a radiation absorption layer on the first portion of the substrate after removing the first portion of the insulating layer. The radiation absorption layer may also be formed within each partition cell. The method may further include forming the one or more component layers on the radiation absorption layer. The one or more component layers may include a layer of a first conductivity type on the radiation absorption layer. The one or more component layers may also include an active layer on the layer of the first conductivity type. The one or more component layers may further include a layer of a second conductivity type on the active layer.

[053] In various other embodiments, the one or more component layers may include a radiation absorption layer. The radiation absorption layer may be formed on the substrate. The radiation absorption layer may be one layer of the one or more component layers. The radiation absorption layer is of a first conductivity type. The remaining layers of the one or more component layer may be formed over the radiation absorption layer. The one or more component layers may further include an active layer on the radiation absorption layer. The one or more component layers may also include a layer of a second conductivity type on the active layer.

[054] Forming the one or more component layers may include forming a layer of a first conductivity type over the first portion of the substrate, forming an active layer on the layer of the first conductivity type, and forming a layer of a second conductivity type on the active layer.

[055] Separating the one or more component layers from the substrate may include irradiating the radiation absorption layer with electromagnetic waves or electromagnetic waves. The separation process may include or may be an ultraviolet (uv) laser lift-off process. The electromagnetic waves may be or may include ultraviolet light or ultraviolet radiation. The substrate may be transparent to the electromagnetic waves. The electromagnetic waves may be introduced on a side of the substrate opposing the side of the substrate attached or adhered to the radiation absorption layer. The electromagnetic waves may pass through the substrate to irradiate the radiation absorption layer. Irradiating the radiation absorption layer with electromagnetic waves may decompose the radiation absorption layer.

[056] Other types of electromagnetic radiation or electromagnetic waves suitable for causing internal and/or external exfoliation of the radiation absorption layer may include X-rays, milli- waves, micro-waves, infra-red waves or gamma rays.

[057] The method may further include forming passivation structures on the second portion of the insulating material so that each of the plurality of layered stack is surrounded by the passivation structures. The passivation structures may include a suitable inorganic material selected from a group consisting of silicon oxide, silicon nitride, titanium dioxide, aluminum oxide. The passivation structure may include a suitable organic material. Alternatively, the passivation structures may include a suitable inorganic material selected from a group consisting of silicon oxide, silicon nitride, titanium dioxide, aluminum oxide.

[058] The method may further include forming an electrode structure on each of the plurality of layered stacks. The method may also include forming a supporting layer on the electrode structures before the separation process. The method may additionally include forming a further electrode structure on each of the plurality of discrete layered stacks on a side of each of the plurality of discrete layered structures opposite each electrode structure.

[059] The substrate may be or may include a composite substrate comprising a carrier substrate and a buffer layer on the carrier substrate. The buffer layer may include aluminum nitride (A1N). [060] The method may also include forming a further insulating layer on the substrate after separating the one or more component layers from the substrate. The method may additionally include removing a further first portion of the further insulating layer so that a further first portion of the substrate is exposed and a further second portion of the substrate is covered by a further second portion of the further insulating layer. The method may also include separating the one or more further component layers from the substrate in a further separation process.

[061] In various embodiments, a device or structure formed by any method described herein may also be provided. The device or structure may be a light- emitting device/diode or a portion of a light-emitting device/diode. The device or structure may instead be a transistor or a portion of a transistor or an electronic device or a portion of a electronic device.

[062] FIG. 4A is a schematic 400a illustrating forming a continuous insulating layer 404 on a substrate 402 according to various embodiments. The method may include providing the substrate 402 and forming the insulating layer 404 on the substrate according to various embodiments. The substrate 402 may be or may include a carrier substrate or carrier wafer. The insulating layer 404 may include a suitable material selected from a group consisting of silicon oxide (SiO_x), silicon nitride (SiN_x), aluminum oxide (A1₂0₃) and zirconium oxide (Zr0₂). The deposition of the insulating layer 504 may be achieved through chemical vapor deposition, electron beam deposition, thermal evaporation, or sputtering. The thickness of the film may be a suitable value selected from a range from about 0.05 μηι to about 20 μηι.

[063] FIG. 4B is a schematic 400b showing a photolithographic process involving a photoresist 406 on the insulating layer 404 according to various embodiments. The method may include depositing photoresist 406 on the insulating layer 404 after forming the insulating layer 404 on the substrate 402. The method may also include arranging a mask over the photoresist 406 and directing electromagnetic radiation through the mask to the photoresist 406. The photolithographic process may define the partition grid pattern on the insulating layer 404. The photoresist 406 used for the photolithography may be positive photoresist such as AZ-9260 or AZ-5214, or may be negative photoresist (with reversed mask design) such as n-Lof. FIG. 4C is a schematic 400c illustrating removal of a first portion of the insulating layer 404 so that a second portion 404a of the insulating layer 404 remains on the substrate 402. FIG. 4D is a schematic 400d showing, a top planar view of the structure in FIG. 4C according to various embodiments. The first portion of the insulating layer 404 may be removed via an etching process such as wet chemical etching or plasma etching. A portion of the photoresist over a portion of the insulating layer (i.e. the first portion of the insulating layer) may be removed prior to etching.

[064] The photoresist over the second portion of the insulating layer 404a may be stripped after etching. After photoresist stripping, only the partition grids 404a may remain on the substrate 402. The exposed area 402a may be left behind for the epitaxial growth of the component layers, e.g. GaN LED layers. The area of the exposed area, which may be equal to the chip area of the LED die, may range from about 0.1 mm to about 5.0 mm, while the width of the grid strips 404a may range from about 5 μιη to about 500 μιη.

[065] FIG. 4E is a schematic 400e illustrating a light emitting diode (LED) epitaxial stack grown in the substrate 402 according to various embodiments. Each LED epitaxial stack (or layered stack) may include a layer of unintentionally doped material 408, a layer of n-type doped material 410, an active layer 412 which includes several pairs of quantum wells/quantum barriers, and a layer of p-type doped material 14. Each epitaxial stack may be only grown on the square region 402a on the surface of the substrate 402. There may be no epitaxial material grown on or over the partition material, i.e. on or over the second portion of the insulating layer 404a. The epitaxial growth can be carried out using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). [066] In various embodiments, the method may include forming a radiation absorption layer (e.g. layer of unintentionally doped material 408) on the first portion of the substrate 402 after removing the first portion of the insulating layer 404. The method may further include forming the one or more component layers (e.g. the layer of n-type doped material 410, the active layer 412 and the layer of p-type doped material 414) on the radiation absorption layer 408.

[067] In various other embodiments, the layer of unintentionally doped material 508 may be absent. The one or more component layers may include a radiation absorption layer (e.g. the layer of n-type doped material 410), which may be formed on the substrate 402. The remaining component layers (e.g. active layer 412 and layer of p-type doped material 414) may be formed on or over the radiation absorption layer 410.

[068] FIG. 4F is a schematic 400f illustrating further process steps to the light emitting diode (LED) epitaxial stacks according to various embodiments. The epitaxial stack may include the one or more component layers and may also include the radiation absorption layer. Since there is no epitaxial material on or over the partition region 404a, the devices may be automatically isolated from the neighbouring dies. Various embodiments may not require isolation processes for isolating the devices. An electrode layer, e.g. a p-electrode stack 416, may be formed on the surface of the p-doped layer 414, e.g. by deposition of a suitable electrode material. The p-electrode stack 416 may serve as an ohmic contact with the p-doped layer 414. The one or more component layers may also include a reflective layer and a lateral current conductor. The reflective layer may be between the p-electrode stack 416 and the one p-doped layer 414. To form ohmic contact with the p-doped layer 414 and allow light to arrive at the reflective layer, the material may be both transparent and conductive. The electrode layer may include one or more suitable materials selected from transparent conductive oxides like indium-tin-oxide (ITO), or semi- transparent metal films like Ni, Ag, Cr, Al, etc. The material(s) for the reflective layer may be selected from Ag, Al, or Ag-based, Al-based alloy. The lateral current conductive layer may include Au, Pt, Ni, Ag, Al, W, Cr, Sn, Cu, etc. The materials may be deposited using electron beam evaporation or sputtering. The p-electrode is patterned through photolithography process and the pattern may generally be designed with a marge between the edge of the p-type doped layer 414 and the edge of the p- electrode 416.

[069] The method may also include forming passivation structures 418 on or over the second portion 404a of the insulating material 404 so that each of the plurality of layered stack or plurality of epitaxial stack is surrounded by the passivation structures. The passivation structures may also be referred to as passivation layers. The space between the sidewalls of the devices may be protected by the passivation structures 418. The passivation structures may cover the n-doped layer 410, to prevent any possible leakage current. The isolation may be patterned to partially expose the p- electrode 416 at the center. The passivation structures may include a suitable passivation material such as inorganic insulators like silicon oxide (SiO_x), silicon nitride (SiN_x), titanium dioxide (Ti0₂) and aluminum oxide (A1₂0₃), or organic materials such as photoresist, polymer, and SU-8.

[070] The method may further include forming a supporting layer 420 on the electrode structures before the separation process. The supporting layer 420 may be applied to the whole wafer area. The suitable layer 420 may include a suitable material such as Au, Ag, Ni, Cu, Pd, Ti^ W, Cr, Al, Mo, Sn, etc. The suitable material for the supporting layer 420 may be deposited by electron beam evaporation, sputtering, or chemical electro-plating. Alternatively, the supporting layer may be a silicon wafer, a copper wafer or a plastic film, which may be attached or stuck to the LED wafer through a wafer bonding process. The thickness of the supporting layer may be any suitable value from about 10 μηι to about 1000 μ ι.

[071] FIG. 4G is' a schematic 400g illustrating the separation process according to various embodiments. The method may include separating the one or more component layers from the substrate 402 in the separation process for recycling the substrate. The separation process may involve a UV laser lift-off process. An UV laser beam with selected wavelengths may be irradiated from the substrate 402 to the LED epitaxial layers. Since the substrate 402 is transparent to the selected wavelengths, the. UV laser photons or electromagnetic waves may reach the radiation absorption layer 408 (GaN epitaxial layer) and may be absorbed by the epitaxial material at the substrate/absorption layer (substrate/epitaxy) interface. The generated high temperature may be sufficiently high to decompose (at least a portion of) the radiation absorption layer 408. The radiation absorption layer 408 may include crystalline GaN material which may be decomposed to gaseous nitrogen and liquid phase gallium. Hence the epitaxial stack (or the one or more component layers) and the substrate 402 may be separated at the interface. In the absence of layer 408, the the UV laser photons or electromagnetic waves may reach layer 410 to decompose at least a portion of layer 410.

[072] FIG. 4H is a schematic 400h illustrating further processing step after the separation process according to various embodiments. After the lift-off process, the one or more component layers 410, 412, 414 may be transferred to the supporting layer, with the p-i-n structure reversed. An etching process (e.g. ICP or RIE) may be applied to etch the layer 410 to a suitable thickness. The etching process may also completely remove the layer 408. The exposed surface of layer 410 may then be randomly textured using wet chemical etching or periodically patterned (e.g. through nano-imprinting or photolithography combined with drying etching) to enhance the light extraction efficiency. A further electrode layer, e.g. n-electrode stack 422, may be formed on the surface of the layer 410, as shown in FIG. 4H. The n-electrode stack 422 may be configured to spread the current laterally and may serve as ohmic contact to the layer 410. The material for the n-electrode stack 422 may be selected from Ti, Al, Ag, Au, Pt, Cr, Pd, W, etc, and the deposition may be achieved by electron beam evaporation, thermal evaporation or sputtering. [073] Since there is no isolation process to separate the individual LED dies during the fabrication process, the substrate 402 may be well protected from any surface damage. Hence, the substrate 402 may be reused for the next rounds of epitaxial growth and fabrication process. The wafer cleaning process may be performed with an acid based solution, such as hydrochloric acid (HO), hydrofluoric acid (HF), nitric acid (HN0₃), phosphoric acid (H3PO₄), sulphuric acid (H₂S0₄), piranha solution, or alkaline solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), to remove any epitaxial material or metal residuals. Organic solutions like isopropanol alcohol (LAP), acetone may also be used to strip any organic contaminations before the next round epitaxy.

[074] Various embodiments may combine the idea of template growth with the partition growth to protect the template from the possible damage by the isolation etching process, so that the carrier wafer, together with the template layer (i.e. the buffer layer) may be recycled.

[075] FIG. 5 is a schematic 500 illustrating a method involving both template growth and partition growth according to various embodiments. FIG. 5 may be similar to FIG. 4E with the substrate 402 in FIG. 4E being replaced by a carrier substrate 524 and a buffer layer 526 on the carrier substrate 524. The method may further include forming patterned insulating layer 504a (including the second portion of the insulating layer) on the buffer layer 526. The method may further include forming the radiation absorption layer 508 on a first portion of the buffer layer 526 not covered by the patterned insulating layer. The second portion of the buffer layer 526 may be covered by the insulating layer 504a. The one or more component layers, i.e. the layer of a first conductivity type 510, the active layer 512 and the layer of a second conductivity type 514 may be formed over the first portion of the buffer layer 526.

[076] The buffer layer 526 may also be referred to as a template layer. The buffer layer 526 may include aluminum nitride (AIN). The carrier wafer substrate may include a suitable material such as sapphire, silicon carbide (SiC) or aluminum nitride (AIN). The buffer layer 526 may have a thickness in the range of about 0.1 μιη to about 10 μπι. The buffer layer 526 may be deposited using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or atomic layer deposition (ALD),

[077] The second portion of the insulating layer or partition grid 504a may be formed similar to processes illustrated by FIGS. 4A-D. Further processing steps for the structure illustrated in FIG. 5 may be similar to that illustrated in FIGS. 4F-H.

[078] The template layer 526 together with the carrier wafer 524 may be recycled. The partition grid 504a may help prevent surface damage to the template layer 526. Hence, the template layer 526 may be reused after cleaning process.

[079] Various embodiments may be applied in the fabrication of optoelectronic devices such as high power LEDs, photodetectors, laser diodes and microelectronics such as bipolar transistors.

[080] Various embodiments may relate to methods to recycle substrates for fabricating GaN based vertical light-emitting diodes (LEDs). The substrate recycling purpose may be realized through growing the epitaxial wafers on the AIN as the buffer layer or the partition growth and the combination thereof. A process involving a buffer layer may also be referred to as template growth.

[081] The epitaxial growth may be initiated from an external substrate or carrier substrate (e.g., sapphire, silicon, SiC, etc) and the AIN maybe deposited as the buffer layer, which may range from about 20 nm to about 4 μηι. The buffer layer may be realized through a metal organic chemical vapour deposition (MOCVD) or a plasma enhanced chemical vapour deposition (PECVD) system.

[082] Alternatively, the substrate recycling may be achieved through partition growth. Prior to the epitaxial growth, an insulating layer such as a Si0₂ layer (about 20 nm to about 8 um) may be deposited by a plasma enhanced chemical vapour deposition (PECVD) or a low pressure chemical vapour deposition (LPCVD) system on the bare substrates. The Si0₂ film may then patterned and dry etched by reactive ion etch (RIE) method or wet etched by hydrofluoric (HF) acid to form Si0₂ networks. A buffer layer such as GaN, AIN may be selectively grown on those exposed substrate regions. Alternatively, the Si0₂ layer may be grown on the buffer layer before the subsequent selective epitaxial deposition.

[083] For both the template growth and partition growth, the following epitaxial layer may include an electron injector layer such as n-type GaN, AlGaN, InGaN and any combination thereof is grown. The n-type conductivity may be realized through doping the layers with such as Si, Ge, O, Ga, Al, and any combination thereof. The light emission layer or active layer may include a stack of Al_xIn_yGai_-x-yN/Al_wIn_zGai_-w- _ZN superlattice, where the Al_xIn_yGa_1-x-yN (0 < x < l, 0 < y < l, 0 < 1-x-y < 1) is the quantum well layer with the energy band gap smaller than the Al_wIn_zGa_1-w-zN (0 < w < 1, 0 < Z < 1, 0 < 1-w-z < 1) quantum barrier. A p-type Al_aGa_bIni_-a-bN (0 < a < 1, 0 < b < 1, 0 < 1-a-b < 1) may be utilized as the electron blocking layer before finally covering the epitaxial wafer by the p-type GaN layer. The p-type dopants may be realized through Be, Mg, Zn, P, N, As, Sb, and any combination thereof.

[084] The chip fabrication may start from the sample cleaning after the epitaxial film has been grown. For the template-grown LED wafers, a hard mask with thickness (> 1 μπι) such as Si0₂, SiN_x, thick photo resist and any combination thereof may be prepared and patterned before performing the isolation etching by inductively coupled plasma (ICP) etching process to form each LED die. The isolation etching, however, may not be required for the partition-grown LED wafers, since the LED dies have already been in-situ shaped within the Si0₂ networks. Then, an Ag-based mirror layer or reflective layer may be prepared on the p-GaN layer. The thermal annealing, which may be between about 0.5 minute and about 10 minutes at 300-800 °C in ai or N₂/0₂ mixture, may be performed to form the better ohmic contact between the mirror or reflective layer and the p-GaN layer. Thus far, the LED dies may be passivated through a suitable passivation layer or passivation structure such as Si0₂, SiN_x, robust photoresist and any combination thereof. The fabrication process of vertical LEDs may also involve a temporary substrate working as the adhesive layer for those separated LED dies. The temporary substrate may be formed through wafer bonding, electroplated metal (e.g., copper) and any combination thereof. Then, a UV laser may be used to irradiate on the wafer from the carrier substrate side. After the UV laser lift-off process, the substrate may be removed from the LED wafer to expose the GaN surface, which may be further removed by ICP or RIE method until n-GaN is exposed. Due to the negligible UV absorption by the A1N material, the A1N buffer layer may remain on the substrate for the future usage, i.e., substrate recycling. In addition, the LED dies obtained from the partition growth method may avoid any surface damages by the ICP/RIE isolation etch, hence promising a higher LED efficiency. The exposed n-GaN surface may be then roughened/textured by wet etching, or surface patterning techniques including photolithography, nano-imprinting and nano-sphere lithography so that the improved light extraction efficiency may be realized. Finally, a metal stack may be deposited as the n-type ohmic contact on the n- GaN surface. Vertical LED chips may be formed by processes described herein.

[085] A1N template growth may guarantee the recycling usage of the substrates, and therefore this approach may significantly reduce the LED cost, and thus is a promising solution to achieve a higher yield/$. On the other hand, the partition growth technique may substantially suppress the inevitable surface damages during the isolation etching process, leading to an enhanced device stability and efficiency and improved lumen/watt. The combination of the template growth and partition growth techniques may further produce an even better lumen/$.

[086] Compared with the conventional substrate recycling process, the A1N template may be introduced as intermediate and protecting layer for the sapphire recycling. Accordingly, the A1N template may be recycled with the original sapphire substrate. Further, compared with the conventional sapphire recycling, the processes described herein may enable LED structures to be grown from the n-GaN with a high crystal quality. [087] With the AIN as template for InGaN LED growth, the LED layers growth may only start from the AIN template or AIN and sapphire template, which may reduce much time consumption for the buffer growth. Therefore, it may reduce the total growth time for the LED epitaxial layers, and at the same time keeping high crystal quality, thus reducing the growth cost.

[088] Template growth with AIN as buffer layer may also reduce the time of the recycling, since only the AIN surface is exposed during the laser lift-off (LLO) process, which may be easily recovered. Various embodiments may increase the yield accordingly.

[089] Compared with the conventional LED growth, partition growth may allow the LED structures to be grown within the defined die areas. The etching process for the die separation may be avoided. There may be no etching markers left on the surface. Further, compared with the conventional LED chip with vertical side wall, the LED die fabricated with partition growth may obtain a natural slope side wall during the growth process.

[090] With partition growth, the strain in the LED epitaxial layers may be reduced, which may in turn increase the internal quantum efficiency of the LED by reducing the quantum confined stark effect. Further, the light extract efficiency may be increased through the naturally formed slope side wall. The current leakage path from the defects formed by etching may be avoided since the deep etching step can be eliminated from the process flow.

[091] Methods described herein may further contain analogous features of any structure or device described herein. Correspondingly, structures or devices described herein may further contain analogous features of any method described herein.

[092] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the. invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

1. A method of recycling a carrier substrate, the method comprising:

providing said carrier substrate;

forming a buffer layer by depositing a suitable material on the carrier substrate, thereby forming a composite substrate comprising the carrier substrate and the buffer layer;

forming one or more component layers over the buffer layer;

separating in a separation process the one or more component layers from the carrier substrate so that at least a portion of the buffer layer remains on the carrier substrate when the one or more component layers are separated from the carrier substrate;

and

forming a further buffer layer from the portion of the buffer layer after the - separation process by depositing the suitable material to recycle the carrier substrate.

2. The method according to claim 1 ,

wherein at least a further portion of the buffer layer is removed from the composite substrate during the separation process.

3. The method according to claim 1 or claim 2,

wherein a thickness of the further buffer layer is substantially equal to a thickness of the buffer layer.

4. The method according to claim 1 or claim 2, wherein a thickness of the further buffer layer is substantially different from a thickness of the buffer layer.

5. The method according to any of claims 1 to 4,

wherein the suitable material comprises aluminum nitride.

6. The method according to any of claims 1 to 5 further comprising;

forming a radiation absorption layer on the buffer layer; and

forming the one or more component layers on the radiation absorption layer.

7. The method according to claim 6,

wherein the one or more component layers comprises:

a layer of a first conductivity type on the radiation absorption layer;

an active layer on the layer of the first conductivity type; and

a layer of a second conductivity type on the active layer.

8. The method according to claims 1 to 5,

wherein the one or more component layers comprises a radiation absorption layer; and

wherein the radiation absorption layer is on the buffer layer.

9. The method according to claim 8,

wherein the radiation absorption layer is of a first conductivity type; and wherein the one or more component layers further comprises:

an active layer on the radiation absorption layer; and

a layer of a second conductivity type on the active layer.

10. The method according to any of claims 6 to 9, wherein separating the one or more component layers from the composite substrate comprises irradiating the radiation absorption layer with electromagnetic waves.

11. The method according to claim 10,

wherein the carrier substrate and the buffer layer are transparent to the electromagnetic waves. .

12. The method according to claim 10 or claim 11,

wherein the electromagnetic waves passes through the carrier substrate and the buffer layer to irradiate the radiation absorption layer.

13. The method according to any of claims 10 to 12 further comprising:

wherein irradiating the radiation absorption layer with the electromagnetic waves decomposes the radiation absorption layer.

14. The method according to any of claims 1 to 13 further comprising:

forming one or more isolation trenches before the separation process, the one or more isolation trenches extending through the one or more component layers.

15. The method according to claim 14,

wherein the one or more isolation trenches terminates at the buffer layer. .

16. The method according to claim 14 or claim 15 further comprising:

depositing insulating material in the one or more isolation trenches to form passivation structures.

17. The method according to any of claims 1 to 16 further comprising:

forming one or more electrode structures on the one or more component layers before the separation process.

18. The method according to claim 17 further comprising

forming a supporting layer on the one or more electrode structures before the separation process. .

19. The method according to claim 18,

wherein an intermediate structure comprising the one or more component layers, the one or more electrode structures and the supporting layer is separated from the composite structure during the separation process.

20. The method according to any of claims 17 to 19,

forming one or more further electrode structures over the intermediate structure after the separation process.

21. The method according to any of claims 1 to 20 further comprising

wherein the one or more component layers is a portion of a light-emitting diode.

22. The method according to any of claims 1 to 21,

forming one or more further component layers over the further buffer layer.

23. The method according to claim 22 further comprising:

separating in a further separation process the one or more further component layers from a further composite substrate comprising the carrier substrate and the further buffer layer.

24. The method according to any of claims 1 to 23,

wherein the carrier substrate comprises one or more selected from a group consisting of sapphire, silicon carbide and aluminum nitride.

25. A method of recycling a substrate, the method comprising:

providing said substrate;

forming an insulating layer on the substrate;

removing a first portion of the insulating layer so that a first portion of the substrate is exposed and a second portion of the substrate is covered by a second portion of the insulating layer;

forming one or more component layers over the first portion of the substrate after the first portion of the insulating layer is removed; and

separating the one or more component layers from the substrate in a separation process for recycling the substrate.

26. The method according to claim 25,

wherein the one or more component layers is absent over the second portion . of the substrate.

27. The method according to claim 25 or claim 26 further comprising:

.. depositing photoresist on the insulating layer after forming the insulating layer on the substrate.

28. The method according to claim 27 further comprising:

arranging a mask over the photoresist; and

directing electromagnetic radiation through the mask to the photoresist.

29. The method according to claim 28,

wherein the photoresist is a positive photoresist;

wherein a portion of the photoresist is exposed to the electromagnetic radiation before removal; and ..·^'. .

wheren the method further comprises removing the portion of the photoresist over the first portion of the insulating layer to expose the first portion of the insulating layer for removal.

30. The method according to claim 28,

wherein the photoresist is a negative photoresist;

wherein a portion of the photoresist is shielded from the electromagnetic radiation by the mask before removal; and

31. The method according to any of claims 25 to 30,

wherein the second portion of the insulating layer comprises a partition grid.

32. The method according to any of claims 25 to 31 further comprising:

forming a radiation absorption layer on the first portion of the substrate after ■^" removing the first portion of the insulating layer; and

forming the one or more component layers on the radiation absorption layer.

33. The method according to any of claims 25 to 31,

wherein the radiation absorption layer is formed on the substrate.

34. The method according to claim 32 or claim 33,

wherein separating the one or more component layers from the substrate comprises irradiating the radiation absorption layer with electromagnetic waves.

35. The method according to claim 34,

wherein the substrate is transparent to the electromagnetic waves.

36. The method according to claim 34 or claim 35,

wherein the electromagnetic waves passes through the substrate to irradiate the radiation absorption layer.

37. The method according to any of claims 25 to 36,

wherein forming the one or more component layers comprises:

forming a layer of a first conductivity type over the first portion of the substrate;

forming an active layer on the layer of the first conductivity type; and forming a layer of a second conductivity type on the active layer.

38. The method according to any of claims 25 to 37,

wherein the one or more component layers formed comprises a plurality of layered stacks.

39. The method according to claim 38 further comprising:

forming passivation ^"structures on the second portion of the insulating material so that each of the plurality of layered stack is surrounded by the passivation structures.

40. The method according to claim 39,

wherein the passivation structures comprises a suitable inorganic material selected from a group consisting of silicon oxide, silicon nitride, titanium dioxide, aluminum oxide.

41. The method according to claim 39,

wherein the passivation structure comprises a suitable organic material.

42. The method according to any of claims 38 to 41 further comprising;

forming an electrode structure on each of the plurality of layered stacks.

43. The method according to claim 42,

forming a supporting layer on the electrode structures before the separation process.

44. The method according to claim 42 or claim 43 further comprising:

forming a further electrode structure on each of the plurality of discrete layered stacks on a side of each of the plurality of discrete layered structures opposite each electrode structure.

45. The method according to any of claims 25 to 44,

wherein the substrate is a composite substrate comprising a carrier substrate and a buffer layer on the carrier substrate.

46. The method according to claim 45,

wherein the buffer layer comprises aluminum nitride.

47. Trie method according to any of claims 25 to 46 further comprising:

forming a further insulating layer on the substrate after separating the one or more component layers from the substrate.

48. The method according to claim 47 further comprising:

removing a further first portion of the further insulating layer so that a further first portion of the substrate is exposed and a further second portion of the substrate is covered by a further second portion of the further insulating layer;

forming one or more further component layers over the further first portion of the substrate; and

separating the one or more further component layers from the substrate in a further separation process.