WO2015085891A1 - Method, device and system for establishing processor cache checkpoint - Google Patents

Abstract

Disclosed in an embodiment of the present invention are a method, device and system for establishing a processor cache checkpoint to ensure that establishing a cache checkpoint does not affect the operation of the processor, the method comprising: in the process of exporting content line by line, when a signal is received for the processor to write to the cache, determining that a cache line corresponding to the cache write operation belongs to the already exported portion of the cache, executing the cache write operation by the processor, and exporting the content written to the cache line through the cache write operation; when a signal is received for the processor to write to the cache, determining that the cache line corresponding to the cache write operation belongs to the unexported portion of the cache, executing the cache write operation by the processor, and suspending the export of the content from the cache; and when a signal is received for the processor to read from the cache, executing the cache read operation by the processor, and suspending the export of the content from the cache.

Description

Method, device and system for establishing processor Cache checkpoint

This application claims priority to Chinese Patent Application No. 201310662178.8, entitled "A Method, Apparatus and System for Establishing Processor Cache Checkpoints", filed on December 9, 2013, the entire contents of which is hereby incorporated by reference. This is incorporated herein by reference.

Technical field

The present invention relates to the field of computer technologies, and in particular, to a method, device and system for establishing a processor Cache checkpoint.

Background technique

In computer systems, the processor cache (CPU Cache) is the component used to reduce the average time required for the processor to access memory. Its capacity is much smaller than the memory, but the speed can be close to the processor's frequency. At the same time, a process periodically saves the state of the execution program to the stable memory. After the system fails, the system can recover according to the information. Each saved program state is called a checkpoint. Currently, the checkpoint technology is widely used for fault tolerance of the system. designing. The Cache checkpoint is a checkpoint established for the Cache. It saves the entire Cache state at a certain time. In the fault migration and state recovery, if the Cache checkpoint can be used to restore the Cache state, the processor does not need to initialize the Cache. A large number of Cache rebuild times speed up system recovery and state migration.

In the prior art, the method for establishing a Cache checkpoint is to use the idle time of the Cache to derive the Cache state of the start time of the process into the compressor during the operation of the processor, thereby establishing a Cache checkpoint. During the Cache checkpoint establishment process, if there is no update operation to the Cache, all Cache contents are sequentially exported to the compressor in the order of the Cache address. However, if there is an update operation on the Cache, and the original content in the Cache line corresponding to the update operation has not been exported, the processor operation needs to be suspended, and the original content of the Cache line is first exported to the compressor, and then started. The processor updates the cache line, that is, when the data of the unexported area needs to be updated, the original data needs to be saved first, and the operation of updating the data by the processor is delayed, the pipeline is suspended, or the memory access operation is suspended. Therefore, the prior art method of establishing a processor Cache checkpoint affects the running of the processor and affects the normal operation of the system.

Summary of the invention

In view of this, the main purpose of the embodiments of the present invention is to provide a method, an apparatus, and a system for establishing a processor Cache checkpoint, so as to solve the problem that the method for establishing a processor Cache checkpoint in the prior art affects the operation of the processor. A problem that affects the normal operation of the system.

In order to solve the above problems, the technical solution provided by the present invention is as follows:

In a first aspect, the present invention provides a method for establishing a processor Cache checkpoint, the method comprising:

In the process of exporting the contents of the Cache row by row, when receiving the processor write Cache signal, detecting that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, performing a processor write Cache operation, and At the same time, the write Cache operation is written into the cache line to be exported;

When receiving the processor write Cache signal, detecting that the cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache, performing a processor write Cache operation, and suspending the content in the Cache;

When receiving the processor read Cache signal, the processor reads the Cache operation and pauses the export of the content in the Cache.

In a first possible implementation manner of the first aspect, the method further includes:

When the received processor reads the Cache signal, it is determined that the Cache line corresponding to the processor read Cache operation is the next exported Cache line, and then the processor reads the Cache operation, and simultaneously performs the Cache corresponding to the read Cache operation. The contents of the line are exported.

In combination with the first aspect or the first possible implementation of the first aspect, in the first aspect In two possible implementation manners, the method further includes:

The control address generator generates a first address starting from one end of the Cache line address range.

With reference to the second possible implementation of the first aspect, in a third possible implementation, the process of exporting the content in the Cache row by row is specifically: the Cache line corresponding to the first address is The content is exported to the compressor for storage. After each cache line is exported, the address generator is controlled to change the first address to the next cache line address.

With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner, the determining, by the cache line, that the cache line corresponding to the write operation is an exported cache line includes:

The detecting determines that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, and includes:

Receiving a comparison result of the comparator, the comparator is configured to compare a cache line address corresponding to the processor write Cache operation with a current first address size;

When the address generator starts to generate the first address by the low address end of the Cache line address range, the comparison result is that the cache cache address corresponding to the processor write Cache operation is smaller than the current first address, and the processor write Cache operation is determined to be corresponding. The Cache line is in the exported portion of the Cache;

When the address generator starts to generate the first address by the high address end of the Cache line address range, the comparison result is that the Cache line address corresponding to the processor write Cache operation is greater than the current first address, and the processor write Cache operation is determined to be corresponding. The Cache line is in the exported portion of the Cache.

In conjunction with the third possible implementation of the first aspect, in a fifth possible implementation, the detecting determines that the cache line corresponding to the processor write Cache operation is in an unexported portion of the Cache, and includes:

Receiving a comparison result of the comparator, the comparator is configured to compare a cache line address corresponding to the processor write Cache operation with a current first address size;

When the address generator starts to generate the first address by the low address end of the Cache line address range, the comparison result is that the Cache line address corresponding to the processor write Cache operation is greater than or equal to the current first address, and the processor write Cache is determined. The corresponding Cache line of the operation is in the unexported part of the Cache;

When the address generator starts to generate the first address by the high address end of the cache line address range, the comparison result is that the cache cache address corresponding to the processor write cache operation is less than or equal to the current first address, and the processor write cache is determined. The corresponding Cache line is operated in the unexported part of the Cache.

With reference to the third possible implementation of the first aspect, in a sixth possible implementation, the detecting determines that the cache line corresponding to the processor read Cache operation is the next exported cache line, including:

Receiving a comparison result of the comparator, the comparator is further configured to compare a cache line address corresponding to the processor read Cache operation with a current first address size;

The comparison result is that the cache line address corresponding to the processor read Cache operation is equal to the current first address, and the cache line corresponding to the processor read Cache operation is determined to be the next exported cache line.

In a second aspect, the present invention provides an apparatus for establishing a processor Cache checkpoint, the apparatus comprising:

a receiving unit, configured to receive a processor write Cache signal or receive a processor read Cache signal during the process of exporting the content in the Cache row by row;

a first determining unit, configured to: when the receiving unit receives the processor write Cache signal, detect that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache;

a first processing unit, configured to: when the first determining unit detects that the Cache line corresponding to the processor write Cache operation is in the exported part of the Cache, perform a processor write Cache operation;

a first deriving unit, configured to: when the first determining unit detects that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, and writes the content of the write Cache operation into the cache line to be exported;

a second determining unit, configured to: when the receiving unit receives the processor write Cache signal, detect that the cache line corresponding to the processor write Cache operation is in an unexported portion of the Cache;

a second processing unit, configured to: when the second determining unit detects that the Cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache, perform a processor write Cache operation, and pause to export the content in the Cache;

And a third processing unit, configured to: when the receiving unit receives the processor read Cache signal, perform a processor read Cache operation, and suspend exporting the content in the Cache.

In a first possible implementation manner of the second aspect, the device further includes:

a third determining unit, configured to: when the receiving unit receives the processor read Cache signal, detect that the cache line corresponding to the processor read Cache operation is the next exported Cache line;

a fourth processing unit, configured to perform a processor read Cache operation when the third determining unit detects that the Cache line corresponding to the processor read Cache operation is the next exported Cache line;

a second deriving unit, configured to: when the third determining unit detects that the cache line corresponding to the processor read Cache operation is the next exported Cache line, export the content in the Cache line corresponding to the read Cache operation .

With reference to the second aspect, or the first possible implementation of the second aspect, in a second possible implementation, the apparatus further includes:

The control unit is configured to control the address generator to generate the first address by using one end of the Cache line address range.

With reference to the second possible implementation of the second aspect, in a third possible implementation, the process of exporting the content in the Cache row by row is specifically: the control unit controls the address generator to generate the first The content in the cache line corresponding to an address is exported to the compressor for storage. After each cache line is exported, the control unit controls the address generator to change the first address to the next cache line address.

In conjunction with the third possible implementation of the second aspect, in a fourth possible implementation, the first determining unit includes:

a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is configured to compare a cache row address corresponding to the processor write Cache operation with a current first address size;

a first determining subunit, configured to: when the address generator starts generating the first address by the low address end of the Cache line address range, the comparison result received by the receiving subunit is a Cache line corresponding to the processor write Cache operation The address is smaller than the current first address, and the processor is determined to write the Cache operation. The Cache line is in the exported part of the Cache;

a second determining subunit, configured to: when the address generator starts generating the first address by the high address end of the Cache line address range, the comparison result received by the receiving subunit is a Cache line corresponding to the processor write Cache operation The address is greater than the current first address, and it is determined that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache.

In conjunction with the third possible implementation of the second aspect, in a fifth possible implementation, the second determining unit includes:

a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is configured to compare a cache row address corresponding to the processor write Cache operation with a current first address size;

a third determining subunit, configured to: when the address generator starts to generate the first address by the low address end of the Cache line address range, the comparison result received by the receiving subunit is a Cache line corresponding to the processor write Cache operation The address is greater than or equal to the current first address, and the cache line corresponding to the processor write Cache operation is determined to be in the unexported portion of the Cache;

a fourth determining subunit, configured to: when the address generator starts generating the first address by the high address end of the Cache line address range, the comparison result received by the receiving subunit is a Cache line corresponding to the processor write Cache operation The address is less than or equal to the current first address, and the cache line corresponding to the processor write Cache operation is determined to be in the unexported portion of the Cache.

In conjunction with the third possible implementation of the second aspect, in a sixth possible implementation, the third determining unit includes:

a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is further configured to compare a cache line address corresponding to the processor read Cache operation with a current first address size;

a fifth determining subunit, wherein the comparison result received by the receiving subunit is that the cache line address corresponding to the processor read Cache operation is equal to the current first address, and determining that the cache line corresponding to the processor read Cache operation is the next exported Cache line.

In a third aspect, the present invention provides a system for establishing a processor Cache checkpoint, the system comprising:

The export controller is the device for establishing a processor Cache checkpoint according to the second aspect of the present invention;

An address generator, configured to generate a first address according to the control of the export controller;

a comparator, configured to compare a cache row address corresponding to the processor write cache operation with a current first address, compare a cache row address corresponding to the processor read cache operation with a current first address, and send the comparison result Giving the derived controller;

A compressor that stores the contents of the Cache line.

It can be seen that the embodiments of the present invention have the following beneficial effects:

In the process of exporting the content in the Cache row by row, if the detection determines that the processor needs to write the Cache and the Cache line corresponding to the write Cache operation is in the exported part of the Cache, the processor write Cache operation is performed, and at the same time The write cache operation is written to the content in the cache line for export; if the detection determines that the processor needs to write the cache and the cache line corresponding to the write cache operation is in the unexported portion of the cache, the processor write cache operation is performed, and the pause is performed. The content in the Cache is exported; when it is detected that the processor needs to read the Cache, the processor reads the Cache operation, and pauses the content in the Cache to be exported. In the process of exporting the contents of the Cache line by line, when the Cache is not idle, the Cache export process is suspended. When the Cache is updated, the Cache update operation occurs, and the update operation occurs in the exported part of the Cache, and the update is performed. The data needs to be stored in the compressor at the same time, so that the data exported to the compressor is the latest data in each cache line, and the established Cache checkpoint is the Cache state at the end of the establishment process. During the entire Cache checkpoint establishment process, when the processor is always in the normal working state, there is no interruption of the establishment of the Cache checkpoint or any operation of the processor is delayed. The process of establishing the Cache checkpoint does not affect the operation of the processor. The normal operation of the system is guaranteed.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below, obviously, The drawings in the above description are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive labor.

1 is a schematic diagram of a method for establishing a processor Cache checkpoint in the prior art;

2 is a flowchart of Embodiment 1 of a method for establishing a processor Cache checkpoint according to an embodiment of the present invention;

3 is a schematic diagram of an embodiment of a method for establishing a processor Cache checkpoint according to an embodiment of the present invention;

4 is a flowchart of Embodiment 2 of a method for establishing a processor Cache checkpoint according to an embodiment of the present invention;

FIG. 5 is a flowchart of Embodiment 3 of a method for establishing a processor Cache checkpoint according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of Embodiment 1 of an apparatus for establishing a processor Cache checkpoint according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of Embodiment 2 of an apparatus for establishing a processor Cache checkpoint according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of Embodiment 1 of a system for establishing a processor Cache checkpoint according to an embodiment of the present invention; FIG.

FIG. 9 is a structural diagram of Embodiment 2 of a system for establishing a processor Cache checkpoint according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The data processing method provided by the embodiment of the present invention is applied to a data processing system, where the data processing system includes an operating system, and a hardware thread resource pool for executing a task code, where the operating system manages the hardware thread pool. The hardware thread is a physical execution unit for executing a task code, and the specific physical form thereof may be a chip or a processor, and the hardware thread pool includes a plurality of hardware threads.

The method, device and system for establishing a processor Cache checkpoint in the embodiment of the present invention can be applied to the checkpoint establishment of the CPU Cache. CPU Cache is a component used to reduce the average time required for the processor to access memory. Each Cache consists of several cache lines, and each cache line can be It includes an index (Index), a tag (Tag), and a number of flag bits, such as a valid bit, a dirty bit, a use bit, and the like. From the processor's point of view, Cache can be considered as a transparent component, usually can not directly interfere with the operation of the cache, and can not directly read the contents of the Cache through the software method.

In large-scale systems, the design is more and more complex, and the scale is getting bigger and bigger. The failure of some components will affect the operation of the whole system, and even the whole system will be more and more serious. To ensure system reliability, you can use fault recovery technology and state transition technology. In fault migration and state recovery, if the Cache checkpoint can be used to restore the Cache state, the processor does not need to initialize the Cache, which saves a lot of Cache rebuild time and speeds up system fault recovery and state transition. Cache checkpoints can also be used for system error detection, error correction and fault diagnosis, and auxiliary system debugging.

In the prior art, there is a method for establishing a Cache checkpoint offline. When the system needs to establish a checkpoint, it first suspends the operation of the processor, stops the pipeline, and starts the processor after all the cache data is stored in the compressor. However, this method needs to suspend the normal working state of the processor, stop the pipeline, and affect the operation of the system. The processor cannot perform any operations during the establishment of the Cache checkpoint stage, which takes a long time and is costly. At the same time, this technology destroys the real-time performance of the system. For some real-time systems, the processor may not continue to operate normally after the pause.

Therefore, in the prior art, there is another method for establishing a Cache checkpoint, the main idea of which is to derive the Cache state at the start of the setup process into the compressor. As shown in Figure 1, the system derives the contents of the Cache from the time A to the compressor until the end of time B, and the exported Cache content is the Cache state at time A. During this setup process, if the Cache does not have a data update operation, all cache lines are sequentially exported to the compressor in the order of the Cache address. However, if there is an update operation and the content of the updated cache line has not been exported, the pipeline needs to be suspended, the original content of the cache line is first exported to the compressor, and then the pipeline is started, and the cache line is updated. Otherwise, the update operation overwrites the original data, the original data cannot be obtained, and the Cache data at time A cannot be exported.

It can be seen that the prior art affects the operation of the processor, that is, when the data of the unexported area needs to be updated, the original data needs to be saved first, and the operation of updating the data by the processor is delayed, the pipeline is suspended, or the access is suspended. The operation of the memory makes the execution of the processor at the time of data export different from the normal mode, and some operations are delayed, which affects the normal operation of the system.

Therefore, the method for establishing a Cache checkpoint in the prior art affects the normal operation of the processor. For this reason, the embodiment of the present invention provides the following method, device, and system for establishing a processor Cache checkpoint.

As shown in FIG. 2, the first embodiment of the method for establishing a processor cache checkpoint in the embodiment of the present invention may include the following steps:

Step 201: In the process of exporting the content in the Cache row by row, when receiving the processor write Cache signal, detecting that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, executing the processor write Cache The operation is performed, and at the same time, the write cache operation is written to the content in the cache line for export.

The method for establishing a processor Cache checkpoint in the embodiment of the present invention may be performed by a new export controller combined with the processor Cache architecture.

When receiving the external input enable signal, the Cache data content of each row can be exported from low to high or high to low according to the Cache address sequence when the Cache is in the idle state without the Cache read and write operation. In the specific implementation, each row of the output may be returned to continue to determine whether there is a read or write operation to the Cache. If the Cache continues to be idle, the content of the next cache line of the previous exported cache line is exported, that is, the Cache is idle. In the state, the contents of the Cache are exported line by line.

In the process of exporting the contents of the Cache line by line, the entire Cache can be divided into two parts: the exported part and the unexported part.

The data exported each time includes all data of the cache line, that is, Tag, Valid, Dirty, and Data information. The tag information is identification information, and the Cache row address and the offset address are combined to determine the segment address offset of the saved data in the Cache line; the Valid bit is a valid bit information indicating the number According to whether it is valid; the Dirty bit is dirty bit information, in the writeback strategy, it is determined whether the data has been updated; the Data information is the data content of the corresponding address saved in the Cache line.

The compressor can use the lossless compression method to compress according to the correlation between the tag and data information, and store the content in the cache line.

When receiving the processor write Cache signal, the representative processor needs to perform a write Cache operation, and the write operation is an update operation, and the data that needs to be updated is written into the Cache. When receiving the processor write Cache signal, further detecting the location where the write operation occurs is determined, and determining that the write operation occurs in the exported portion of the Cache, the data written to the Cache needs to be simultaneously performed in addition to being written into the Cache. Export the storage to the compressor,

Step 202: When receiving the processor write Cache signal, detecting that the cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache, performing a processor write Cache operation, and suspending exporting the content in the Cache.

When it is determined that the Cache line corresponding to the processor write Cache operation is in the unexported part of the Cache, the processor write Cache operation may be performed normally, and the content in the Cache is suspended. The process of exporting the contents of the Cache line by line after the processor writes the Cache operation.

Step 203: When receiving the processor read Cache signal, perform a processor read Cache operation, and pause to export the content in the Cache.

When the processor reads the Cache signal, that is, the processor needs to perform the read Cache operation, the processor reads the Cache operation normally, and pauses the content in the Cache to be exported. The process of exporting the contents of the Cache line by line after the processor reads the Cache operation.

If all the Cache lines have been exported, a processor Cache checkpoint is established, and the Cache content saved in the compressor is the content in the Cache at the end of the export.

As shown in FIG. 3, in the process of establishing a Cache checkpoint, the Cache is divided into an exported part and an unexported part. When an update operation occurs in the exported part, the updated data is simultaneously saved in the compressor. Having no effect on the processor update Cache operation itself, so that the Cache data derived in the embodiment of the present invention is always the latest content of the Cache, that is, the established The Cache checkpoint is the Cache state at the time of the export end time B. During the entire Cache checkpoint establishment process, when the processor is always in the normal working state, no Cache is established because the Cache checkpoint is interrupted or any operation of the processor is delayed. The process of checking points does not affect the operation of the processor, which ensures the normal operation of the system.

In some embodiments of the present invention, the method for establishing a processor cache checkpoint in the embodiment of the present invention may further include:

When the received processor reads the Cache signal, it is determined that the Cache line corresponding to the processor read Cache operation is the next exported Cache line, and then the processor reads the Cache operation, and simultaneously performs the Cache corresponding to the read Cache operation. The contents of the line are exported.

That is to say, when the read/write operation to the Cache is a read operation on the Cache, in order to speed up the export of the Cache, when the Cache line corresponding to the read operation is exactly the next Cache line, the content in the Cache line is also exported. That is, the Cache read operation originally needs to pause the Cache export, but when the Cache line corresponding to the read operation is the next Cache line to be exported, the content of the line is directly exported. In a special case, the read operation The Cache is also exported, which speeds up the speed and avoids repeated reading of the Cache content.

As shown in FIG. 4, the second embodiment of the method for establishing a processor cache checkpoint in the embodiment of the present invention may include the following steps:

Step 401: When receiving the external input enable signal, proceed to step 403.

When receiving the enable signal of the external input, it starts to determine whether there is a read or write operation to the Cache. That is, when an external enable signal is received, the process of establishing a processor Cache checkpoint is started.

Step 402: Determine whether all the cache lines have been exported. If yes, the processor Cache checkpoint is established. If no, go to step 403.

Step 403: Determine whether there is a read/write operation on the Cache. If yes, go to step 405 or step 408. If no, go to step 404.

Step 404: Export the content in the next cache line of the last exported cache line to the storage in the compressor, and return to step 402.

It should be noted that, after starting to determine whether there is a read/write operation to the Cache, the first time to obtain the judgment result of the read/write operation of the Cache, since there is no previous export cache line, the previous cache line is derived. The next Cache line can be thought of as the first line of Cache lines.

Step 405: When a write operation to the Cache is received when the processor writes the Cache signal, it is detected whether the cache line corresponding to the Cache operation of the processor is in the exported part of the Cache. If yes, go to step 406. If no, go to step 407.

Step 406: Perform a processor write Cache operation, write the content of the processor write Cache operation into the cache line and store it in the compressor, and return to step 402.

Step 407: Perform a processor write Cache operation, suspend the content in the Cache, and return to step 402.

Step 408: When the processor reads the Cache signal, that is, when there is a read operation on the Cache, the detection processor reads whether the cache line corresponding to the Cache operation is the next cache line of the previous export cache line, and if yes, proceeds to step 404. If no, go to step 409.

Step 409: Perform a processor read Cache operation, suspend the content in the Cache, and return to step 402.

The method of the method includes a complete process of establishing a Cache checkpoint. When receiving an enable signal of an external input, the Cache checkpoint is started, and the current state of the Cache is determined in real time after the operation of any Cache row. What happens to the Cache in the future, until the contents of all the cache lines are exported, the export step is stopped, and a Cache checkpoint establishment process is completed.

Specifically, it can be seen from the embodiment of the method that after starting to establish the checkpoint, if the processor is in the following three cases, the export controller allows the data to be saved to the compressor:

First, the processor does not read or write the Cache, that is, the Cache is in an idle state, and the content in the next cache line of the previous exported cache line is exported to the compressor for storage;

Second, the processor is in the read Cache operation, and the cache line read at the same time is the same as the next exported Cache line, then the next exported Cache line is the next one of the previous Cache line. The content in the Cache line is exported to the compressor for storage;

Third, the processor updates the Cache data, and the updated Cache line is the exported Cache line, and the updated data is simultaneously stored in the compressor for storage.

In this way, the method for establishing a processor Cache checkpoint in the embodiment of the present invention enables the Cache checkpoint to be established when the processor is in a normal working state.

In a specific application, the method for establishing a processor Cache checkpoint in order to implement the embodiment of the present invention may further include an address generator and a comparator in combination with the processor Cache architecture. The address generator may be configured to generate a first address according to the control of the export controller, where the first address may be regarded as a cache line address that is to be exported, and the comparator may be used for a cache address corresponding to the cache write operation of the processor. Comparing the size of the current first address, comparing the size of the cache line address corresponding to the processor read Cache operation with the current first address, and sending the comparison result to the export controller to determine whether the update operation occurs in the exported part. Or whether the address for the read operation is the cache line address to be exported, and further, the export controller determines whether to save the data to the compressor according to the comparison result of the comparator, whether the cache is in an idle state, or the like.

Specifically, in some embodiments of the present invention, the method for establishing a processor cache checkpoint in the embodiment of the present invention may further include:

The control address generator generates a first address starting from one end of the Cache line address range.

That is, when the external input enable signal is received, the processor cache detection point is established, and the export controller control address generator starts to generate the first address by the low address end or the high address end of the Cache, where the first address corresponds to The current Cache row address that needs to be exported. Each time the content of the Cache is exported, the control address generator changes the current first address to the address of the next Cache row address, for example, generates a first address from the lower address end, and after each content of the Cache is exported, the first address The self-increase to the next Cache row address, so that the implementation of exporting the contents of the Cache line to the storage in the compressor may be the Cache line content corresponding to the first address after the change is derived.

In this way, in some embodiments of the present invention, the process of exporting the content in the Cache row by row may specifically: export the content in the cache line corresponding to the first address to the compressor, and each After exporting a cache line, the address generator is controlled to change the first address to the next cache line address.

In some embodiments of the present invention, the specific implementation of detecting that the Cache line corresponding to the processor write Cache operation is in the exported part of the Cache may include:

Receiving a comparison result of the comparator, the comparator is configured to compare the size of the cache line address corresponding to the processor write Cache operation with the current first address;

When the address generator starts to generate the first address by the low address end of the Cache line address range, the comparison result is that the cache line address corresponding to the processor write Cache operation is smaller than the current first address, and the cache line corresponding to the processor write Cache operation is determined to be The exported part of the Cache;

When the address generator starts to generate the first address by the high address end of the cache line address range, the comparison result is that the cache line address corresponding to the processor write cache operation is greater than the current first address, and the cache line corresponding to the processor write cache operation is determined to be The exported portion of the Cache.

Taking the address generator from the lower address end of the Cache line address range as an example, if the content of the cache line is exported, the first address is increased to the next one after the Cache line corresponding to the first address is exported. Cache row address, repeat this process, so that the Cache range from the low address of the Cache to the current first address (excluding the current first address) is the exported part, then the Cache row address corresponding to the write operation and the current first address can be determined. The size of the Cache line corresponding to the write operation is smaller than the current first address. The Cache line corresponding to the write operation is in the exported part, and the content written by the write playground to the Cache line needs to be saved to the compressor at the same time. When the address generator starts to generate the first address by the high address end of the Cache line address range, if the Cache line address corresponding to the write operation is greater than the current first address, the Cache line corresponding to the write operation is in the exported part.

Similarly, in some embodiments of the present invention, the specific implementation of detecting that the Cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache may include:

Receiving a comparison result of the comparator, the comparator is configured to compare the size of the cache line address corresponding to the processor write Cache operation with the current first address;

When the address generator starts generating the first address from the low address end of the Cache line address range, The result is that the cache cache address corresponding to the processor write cache operation is greater than or equal to the current first address, and the cache line corresponding to the processor write cache operation is determined to be in the unexported portion of the cache;

When the address generator starts to generate the first address by the high address end of the cache line address range, the comparison result is that the cache cache address corresponding to the processor write cache operation is less than or equal to the current first address, and the cache corresponding to the processor write cache operation is determined. The line is in the unexported portion of the Cache.

Similarly, in some embodiments of the present invention, the specific implementation that detects that the cache line corresponding to the processor read Cache operation is the next exported Cache line may include:

Receiving the comparison result of the comparator, the comparator is further configured to compare the cache line address corresponding to the processor read Cache operation with the current first address size;

The result of the comparison is that the cache cache address corresponding to the processor read cache operation is equal to the current first address, and the cache line corresponding to the processor read cache operation is determined to be the next exported cache line.

As shown in FIG. 5, the third embodiment of the method for establishing a processor cache checkpoint in the embodiment of the present invention may include the following steps:

Step 501: When receiving the external input enable signal, the control address generator starts generating the first address from the low address end of the Cache, and proceeds to step 503.

Step 502: Determine whether all cache lines have been exported. If yes, the processor Cache checkpoint is established. If no, go to step 503.

Step 503: Determine whether there is a read/write operation on the Cache. If yes, go to step 504. If no, go to step 505.

Step 504: Detect the type of the processor read and write Cache operation. If there is a write operation to the Cache, go to step 506. If there is a read operation on the Cache, go to step 507.

Step 505: Export the content in the cache line corresponding to the first address to the storage in the compressor, and control the address generator to increase the first address to the next cache line address, and return to step 502.

Step 506: Receive a comparison result of the comparator, determine whether the comparison result is that the cache line address corresponding to the processor write Cache operation is smaller than the current first address, and if yes, go to step 508, if no, go to step 509.

Step 507: Receive a comparison result of the comparator, determine whether the comparison result is that the cache line address corresponding to the processor read Cache operation is equal to the current first address, and if yes, go to step 505, if no, go to step 510.

Step 508: Perform a processor write Cache operation, and write the write operation to the content of the cache line and store it in the compressor for storage, and return to step 502.

Step 509: Perform a processor write Cache operation, and suspend the export of the Cache line, and return to step 502.

Step 510: Perform a processor read Cache operation, and suspend the export of the Cache line, and return to step 502.

In the embodiment of the method, the address generator generates the first address from the low address end of the Cache as an example, and describes the specific conditions under which the Cache content is exported and the judgment condition. Further, there is no read/write operation on the Cache. That is, when the Cache is idle, the content in the Cache line corresponding to the first address is exported to the compressor for storage; when the comparison result of the comparator is that the Cache row address corresponding to the read operation is equal to the current first address, the first address corresponds to The content in the Cache line is exported to the compressor for storage; when the comparison result of the comparator is that the Cache row address corresponding to the write operation is smaller than the current first address, the write operation is written to the cache line and stored in the compressor. To achieve the establishment of Cache checkpoints.

Similarly, the address generator starts to generate the first address by the high address end of the Cache, and then the content in the cache line corresponding to the first address is exported to the compressor for storage when there is no read/write operation to the Cache, that is, the Cache is idle. When the comparison result of the comparator is that the Cache row address corresponding to the read operation is equal to the current first address, the content in the Cache line corresponding to the first address is exported to the compressor for storage; the comparison result of the comparator is the write operation. When the Cache row address is greater than the current first address, the write operation is written to the cache line and stored in the compressor for storage to implement the Cache checkpoint.

In this way, in the embodiment of the present invention, when the Cache idle state of the Cache is read and written, the Cache content is exported to the compressor in a cache. When not idle, the Cache export process is suspended, but when the Cache update operation occurs when the Cache is written, and the update operation occurs in the exported part of the Cache, the updated data needs to be simultaneously stored in the compressor, thus being exported to the compressor. The data in the cache is the latest data in each cache line, and the established Cache checkpoint is the Cache state at the end of the setup process. During the entire Cache checkpoint establishment process, when the processor is always in the normal working state, there is no interruption of the establishment of the Cache checkpoint or any operation of the processor is delayed. The process of establishing the Cache checkpoint does not affect the operation of the processor. The normal operation of the system is guaranteed.

Correspondingly, referring to FIG. 6, the embodiment 1 of the device for establishing a processor Cache checkpoint according to an embodiment of the present invention may include:

The receiving unit 601 is configured to receive a processor write Cache signal or receive a processor read Cache signal during the process of deriving content in the Cache row by row.

The first determining unit 602 is configured to: when the receiving unit receives the processor write Cache signal, detect that the cache line corresponding to the processor write Cache operation is in the exported portion of the Cache.

The first processing unit 603 is configured to perform a processor write Cache operation when the first determining unit detects that the Cache line corresponding to the processor write Cache operation is in the exported portion of the Cache.

The first deriving unit 604 is configured to: when the first determining unit detects that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, write the content of the write Cache operation into the cache line for export.

The second determining unit 605 is configured to: when the receiving unit receives the processor write Cache signal, detect that the cache line corresponding to the processor write Cache operation is in an unexported portion of the Cache.

The second processing unit 606 is configured to: when the second determining unit detects that the Cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache, perform a processor write Cache operation, and pause to export the content in the Cache.

The third processing unit 607 is configured to: when the receiving unit receives the processor read Cache signal, perform a processor read Cache operation, and suspend exporting the content in the Cache.

In some embodiments of the present invention, the embodiment of the present invention establishes a processor cache checkpoint The return can include:

a third determining unit, configured to: when the receiving unit receives the processor read Cache signal, detect that the cache line corresponding to the processor read Cache operation is the next exported Cache line;

a fourth processing unit, configured to: when the third determining unit detects that the Cache line corresponding to the processor read Cache operation is the next exported Cache line, perform a processor read Cache operation;

The second deriving unit is configured to: when the third determining unit detects that the Cache line corresponding to the processor read Cache operation is the next exported Cache line, export the content in the Cache line corresponding to the read Cache operation.

As shown in FIG. 7, the embodiment 2 of the device for establishing a processor Cache checkpoint in the embodiment of the present invention may include:

The receiving unit 701 is configured to receive a processor write Cache signal or receive a processor read Cache signal.

The first determining unit 702 is configured to determine whether all the Cache lines have been exported. If the judgment result of the first determining unit is that all the Cache lines have been exported, the processor Cache checkpoint is established, if the judgment result of the first determining unit is If the Cache line is not all exported, the second judgment unit is entered to determine whether there is a read/write operation on the Cache.

The second determining unit 703 is configured to determine whether there is a read/write operation on the Cache according to whether the processor writes the Cache signal received by the receiving unit or the receiving processor reads the Cache signal.

The third deriving unit 704 is configured to: if the judgment result of the second judging unit is that there is no read/write operation on the Cache, export the content in the next cache line of the last exported cache line to the compressor, and enter The first judgment unit.

The first determining unit 705, when the receiving unit receives the processor write Cache signal to make the determination result of the second determining unit that there is a write operation to the Cache, detecting that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache .

The first processing unit 706 is configured to perform a processor write Cache operation when the first determining unit detects that the Cache line corresponding to the processor write Cache operation is in the exported portion of the Cache.

The first deriving unit 707 is configured to: when the first determining unit detects that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, write the content of the write Cache operation into the cache line, and enter the first Judging unit

The second determining unit 708 is configured to: when the receiving unit receives the processor write Cache signal, and the determination result of the second determining unit is that there is a write operation to the Cache, detecting that the Cache line corresponding to the processor write Cache operation is in the Cache Export part;

The second processing unit 709 is configured to: when the second determining unit detects that the Cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache, perform a processor write Cache operation, and pause to export the content in the Cache, and Entering the first judgment unit;

The third determining unit 710 is configured to: when the receiving unit receives the processor read Cache signal, and the judgment result of the second determining unit is that there is a read operation on the Cache, detecting that the Cache line corresponding to the processor read Cache operation is the next Exported Cache line;

The fourth processing unit 711 is configured to: when the third determining unit detects that the Cache line corresponding to the processor read Cache operation is the next exported Cache line, perform a processor read Cache operation;

The second deriving unit 712 is configured to: when the third determining unit detects that the Cache line corresponding to the processor read Cache operation is the next exported Cache line, export the content in the Cache line corresponding to the read Cache operation, and enter The first judgment unit.

The fourth determining unit 713 is configured to: when the receiving unit receives the processor read Cache signal to make the determination result of the second determining unit that there is a read operation on the Cache, detecting that the Cache line corresponding to the processor read Cache operation is not the next Exported Cache line;

The third processing unit 714 is configured to detect, by the fourth determining unit, that the Cache line corresponding to the processor read Cache operation is not the next exported Cache line, perform a processor read Cache operation, and pause to export the content in the Cache.

In some embodiments of the present invention, the apparatus for establishing a processor Cache checkpoint may further include:

a control unit for controlling the address generator to be generated by one end of the Cache line address range An address.

In some embodiments of the present invention, the process of exporting the content in the Cache row by row is specifically: the content in the cache line corresponding to the first address generated by the control unit control address generator is exported to the compressor for storage, and each After exporting a Cache line, the control unit controls the address generator to change the first address to the next Cache line address.

In some embodiments of the present invention, the first determining unit may include:

a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is configured to compare a cache line address corresponding to the processor write Cache operation with a current first address size;

a first determining sub-unit, configured to: when the address generator starts to generate the first address by the low address end of the Cache line address range, the comparison result received by the receiving sub-unit is that the Cache line address corresponding to the processor write Cache operation is smaller than the current An address, determining that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache;

a second determining sub-unit, configured to: when the address generator starts generating the first address by the high address end of the Cache line address range, the comparison result received by the receiving sub-unit is that the Cache line address corresponding to the processor write Cache operation is greater than the current An address determines that the cache line corresponding to the processor write Cache operation is in the exported portion of the Cache.

In some embodiments of the present invention, the second determining unit may include:

a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is configured to compare a cache line address corresponding to the processor write Cache operation with a current first address size;

a third determining sub-unit, configured to: when the address generator starts generating the first address by the low address end of the Cache line address range, the comparison result received by the receiving sub-unit is that the Cache line address corresponding to the processor write Cache operation is greater than or equal to The current first address determines that the cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache;

a fourth determining sub-unit, configured to: when the address generator starts generating the first address by the high address end of the Cache line address range, the comparison result received by the receiving sub-unit is that the Cache line address corresponding to the processor write Cache operation is less than or equal to The current first address determines the processor write Cache operation corresponding to The Cache line is in the unexported portion of the Cache.

In some embodiments of the present invention, the third determining unit may include:

a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is further configured to compare a cache line address corresponding to the processor read Cache operation with a current first address size;

The fifth determining subunit, the comparison result received by the receiving subunit is that the cache line address corresponding to the processor read Cache operation is equal to the current first address, and determining that the cache line corresponding to the processor read Cache operation is the next exported Cache line .

In this way, in the embodiment of the present invention, when there is no Cache idle state for the Cache read/write operation, the Cache content is exported to the compressor for storage, and the Cache is suspended when the Cache is not idle. The process, but when the Cache is written, the Cache update operation occurs, and the update operation occurs in the exported part of the Cache, and the updated data needs to be stored in the compressor at the same time, so that the data exported to the compressor is each Cache. The latest data in the line, the established Cache checkpoint is the Cache state at the end of the establishment process. During the entire Cache checkpoint establishment process, when the processor is always in the normal working state, there is no interruption of the establishment of the Cache checkpoint or any operation of the processor is delayed. The process of establishing the Cache checkpoint does not affect the operation of the processor. The normal operation of the system is guaranteed.

Correspondingly, referring to FIG. 8, the embodiment 1 of the system for establishing a processor Cache checkpoint in the embodiment of the present invention may include:

The export controller 801 may be an apparatus embodiment for establishing a processor Cache checkpoint as described above.

An address generator 802, configured to generate a first address according to control of the export controller;

The comparator 803 is configured to compare the size of the cache line address corresponding to the processor write cache operation with the current first address, compare the size of the cache line address corresponding to the processor read cache operation with the current first address, and send the comparison result to the Export controller

The compressor 804 is configured to store the content of the cache line.

The working principle of the embodiment of the system is:

When the export controller receives the enable signal of the external input, the control address generator is controlled by the Cache line. One end of the address range starts to generate a first address, and determines whether there is a read/write operation on the Cache;

If there is no read or write operation to the Cache, the content in the cache line corresponding to the first address is exported to the compressor for storage, and the address generator is controlled to change the first address to the next cache line address, and all caches are determined. Whether the line has been exported; if all the Cache lines have been exported, the processor Cache checkpoint is established. If the Cache line is not all exported, continue to determine whether there is a read or write operation to the Cache; Determine the type of read and write operations;

If the read/write operation on the Cache is a write operation to the Cache, the comparison result of the comparator is received, and the comparison result is determined whether the cache line corresponding to the write operation is the exported cache line; if the read and write operation to the Cache is the Cache The read operation receives the comparison result of the comparator, and determines whether the comparison result of the comparator is the cache address corresponding to the read operation equal to the current first address;

If the comparison result of the comparator is that the cache line corresponding to the write operation is the exported cache line, the write operation writes the content of the cache line to the storage in the compressor, and returns to determine whether all the cache lines have been exported; The comparison result of the device is that the cache line corresponding to the write operation is not the exported cache line, suspends the export of the cache line, and returns to determine whether all the cache lines have been exported;

If the comparison result of the comparator is that the cache line address corresponding to the read operation is equal to the current first address, and the control address generator changes the first address to the next cache line address, it returns to determine whether all the cache lines have been exported; if the comparator The comparison result is that the cache line address corresponding to the read operation is not equal to the current first address, the export of the cache line is suspended, and it is returned to determine whether all the cache lines have been exported.

That is, in the process of exporting the content in the Cache row by row, when receiving the processor write Cache signal, detecting that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, performing processor write Cache operation, and at the same time write the write Cache operation to the contents of the Cache line for export.

When receiving the processor write Cache signal, detecting determines that the processor writes the Cache operation correspondingly If the Cache line is in the unexported part of the Cache, the processor writes the Cache operation and pauses the export of the contents of the Cache.

When the received processor reads the Cache signal, it is determined that the Cache line corresponding to the processor read Cache operation is the next exported Cache line, and then the processor reads the Cache operation, and simultaneously reads the Cache line corresponding to the Cache operation. The content is exported.

When receiving the processor read Cache signal, the detection determines that the Cache line corresponding to the processor read Cache operation is not the next exported Cache line, performs a processor read Cache operation, and suspends exporting the content in the Cache.

In this way, the Cache state at the end of the export can be exported to the compressor for storage.

As shown in FIG. 9 , the system embodiment 2 of the present invention is used to establish a processor Cache checkpoint. In an actual application, in combination with a specific Cache structure, the hardware module added in the embodiment of the present invention includes an address generator, a comparator, and Export controllers, compressors, and several selectors.

In the actual application, when the Dump_enable enable signal is valid, the system enables the Cache checkpoint establishment, starts to establish the Cache checkpoint, and the export controller controls the address generator to start generating the first address (to generate the first address from the low address end as example);

The export controller receives the Valid signal sent by the processor access unit (LSQ) to determine whether there is a read/write operation on the Cache;

When the Valid signal is invalid, the Cache is idle, the export controller sends an enable Dump signal to the compressor, and the first address generated by the address generator is selected by the Addr_sel signal as the Cache read/write address, and the first address generated by the address generator is corresponding. The Cache line content is exported to the compressor, and the exported data includes all data such as Tag, Valid, and Data in the Cache line, and then controls the address generator to increase to the next Cache address. If the Cache is still idle, repeat the above process;

When the Valid signal is valid, it means that the Cache is not idle, the export controller invalid Dump signal, and the export process is suspended. However, when the following two conditions are detected, the export controller enables the Dump signal and derives the corresponding data:

First, receiving the write signal Wr or the read signal Rw sent by the LSQ to determine the read/write operation Type, when the Cache of the exported part is updated for the processor, that is, the Wr signal is valid, and the comparator Cpr_res signal is received, and when the first address is smaller than the read/write address Address of the Cache, the updated data is simultaneously exported to the compressor;

Secondly, when it is a read operation, the comparator Cpr_res signal is received, and when the read/write address Address of the Cache is equal to the first address, the content of the Cache line corresponding to the first address is exported to the compressor for storage;

Specifically, the export controller sends a Dsel signal, selects a data source of the compressor, and when the updated data is stored in the compressor, uses the Dsel signal to control the selection of the ND data stream; when the Cache data is exported to the compressor, Controlling the data stream of the Cache by using the Dsel signal;

When the address generator reaches the address maximum value, the export ends, and the state of the Cache at this time is all stored in the compressor, and a Cache checkpoint establishment process is completed.

The function of the LSQ (load store queue) is to cache the memory access operation of the Cache, and the memory access operation is sent to the Cache. In the embodiment of the present invention, the role of the LSQ is to send and receive to the Cache. The command is to enable the corresponding Wr or Rw signal, and when the Wr write enable signal is valid, the write data is sent, and when the Rw read enable signal is valid, the data is read.

In addition, FSM (Finite State Machine), which is equivalent to the controller module of the Cache, is used to generate various Cache control signals and interact with other modules (LSQ and memory Mem). The Full signal is used to indicate whether the compressor storage space is full. If the storage space is full, the new data cannot be stored.

In this way, the embodiment of the present invention starts from the checkpoint establishment time, when the processor does not have the Cache idle state of the Cache, that is, the Cache idle state, the content in the Cache is exported to the compressor in a row-by-row manner, and is suspended when the Cache is not idle. The Cache export process, but when the Cache update operation occurs when the Cache is written, and the update operation occurs in the exported part of the Cache, the updated data needs to be simultaneously stored in the compressor, so that the data exported to the compressor is The latest data in a Cache line, the Cache checkpoint established is the Cache state at the end of the establishment process. During the entire Cache checkpoint establishment process, when the processor is always in a working state, there is no reason Establishing a Cache checkpoint interrupt or deferring any operation of the processor, the process of establishing a Cache checkpoint does not affect the operation of the processor, ensuring the normal operation of the system.

At the same time, after a system failure (such as a soft error), it is necessary to recover from the failure and roll back to the last trouble-free checkpoint. The saved Cache checkpoint can quickly restore the state of the Cache, so that the system can recover to the normal operation as soon as possible, avoiding a large number of Cache misses and improving the efficiency of memory access. Also in state migration, the state of one processor is migrated to another processor, and the recovery of the Cache state can also enable the processor to quickly restore locality, and can directly obtain the required data from the Cache, thereby improving the efficiency of migration.

The Cache checkpoint stores the most recently used data of the processor, which is important for understanding the running of the program and the state of the system, so it can be used for system error detection, error correction, fault recovery and fault diagnosis.

It should be noted that the various embodiments in the present specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the system or device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

It should also be noted that, in this context, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying such entities or operations. There is any such actual relationship or order between them. Furthermore, the term "comprises" or "comprises" or "comprises" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a plurality of elements includes not only those elements but also Other elements, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.

The steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented directly in hardware, a software module executed by a processor, or a combination of both. Software modules can be placed in random memory Memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form known in the art In the storage medium.

The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but the scope of the invention is to be accorded

Claims (15)

1. A method for establishing a processor Cache checkpoint, the method comprising:

   In the process of exporting the contents of the Cache row by row, when receiving the processor write Cache signal, detecting that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, performing a processor write Cache operation, and At the same time, the write Cache operation is written into the cache line to be exported;

   When receiving the processor write Cache signal, detecting that the cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache, performing a processor write Cache operation, and suspending the content in the Cache;

   When receiving the processor read Cache signal, the processor reads the Cache operation and pauses the export of the content in the Cache.
2. The method of claim 1 further comprising:

   When the received processor reads the Cache signal, it is determined that the Cache line corresponding to the processor read Cache operation is the next exported Cache line, and then the processor reads the Cache operation, and simultaneously performs the Cache corresponding to the read Cache operation. The contents of the line are exported.
3. The method according to claim 1 or 2, wherein the method further comprises:

   The control address generator generates a first address starting from one end of the Cache line address range.
4. The method according to claim 3, wherein the process of exporting the content in the Cache row by row is specifically: exporting the content in the cache line corresponding to the first address to the compressor for storage, each After exporting a cache line, the address generator is controlled to change the first address to the next cache line address.
5. The method according to claim 4, wherein the detecting determines that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, and includes:

   Receiving a comparison result of the comparator, the comparator is configured to compare a cache line address corresponding to the processor write Cache operation with a current first address size;

   Generating the first address when the address generator starts from the lower address end of the Cache line address range The comparison result is that the cache line address corresponding to the processor write cache operation is smaller than the current first address, and the cache line corresponding to the processor write cache operation is determined to be in the exported part of the cache;

   When the address generator starts to generate the first address by the high address end of the Cache line address range, the comparison result is that the Cache line address corresponding to the processor write Cache operation is greater than the current first address, and the processor write Cache operation is determined to be corresponding. The Cache line is in the exported portion of the Cache.
6. The method according to claim 4, wherein the detecting determines that the cache line corresponding to the processor write Cache operation is in an unexported portion of the Cache, and includes:

   Receiving a comparison result of the comparator, the comparator is configured to compare a cache line address corresponding to the processor write Cache operation with a current first address size;

   When the address generator starts to generate the first address by the low address end of the Cache line address range, the comparison result is that the Cache line address corresponding to the processor write Cache operation is greater than or equal to the current first address, and the processor write Cache is determined. The corresponding Cache line of the operation is in the unexported part of the Cache;

   When the address generator starts to generate the first address by the high address end of the cache line address range, the comparison result is that the cache cache address corresponding to the processor write cache operation is less than or equal to the current first address, and the processor write cache is determined. The corresponding Cache line is operated in the unexported part of the Cache.
7. The method according to claim 4, wherein the detecting determines that the cache line corresponding to the processor read Cache operation is the next exported Cache line, and includes:

   Receiving a comparison result of the comparator, the comparator is further configured to compare a cache line address corresponding to the processor read Cache operation with a current first address size;

   The comparison result is that the cache line address corresponding to the processor read Cache operation is equal to the current first address, and the cache line corresponding to the processor read Cache operation is determined to be the next exported cache line.
8. An apparatus for establishing a processor Cache checkpoint, the apparatus comprising:

   a receiving unit, configured to receive a processor during the process of exporting content in the Cache line by line Write a Cache signal or receive a processor read Cache signal;

   a first determining unit, configured to: when the receiving unit receives the processor write Cache signal, detect that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache;

   a first processing unit, configured to: when the first determining unit detects that the Cache line corresponding to the processor write Cache operation is in the exported part of the Cache, perform a processor write Cache operation;

   a first deriving unit, configured to: when the first determining unit detects that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache, and writes the content of the write Cache operation into the cache line to be exported;

   a second determining unit, configured to: when the receiving unit receives the processor write Cache signal, detect that the cache line corresponding to the processor write Cache operation is in an unexported portion of the Cache;

   a second processing unit, configured to: when the second determining unit detects that the Cache line corresponding to the processor write Cache operation is in the unexported portion of the Cache, perform a processor write Cache operation, and pause to export the content in the Cache;

   And a third processing unit, configured to: when the receiving unit receives the processor read Cache signal, perform a processor read Cache operation, and suspend exporting the content in the Cache.
9. The device according to claim 8, wherein the device further comprises:

   a third determining unit, configured to: when the receiving unit receives the processor read Cache signal, detect that the cache line corresponding to the processor read Cache operation is the next exported Cache line;

   a fourth processing unit, configured to perform a processor read Cache operation when the third determining unit detects that the Cache line corresponding to the processor read Cache operation is the next exported Cache line;

   a second deriving unit, configured to: when the third determining unit detects that the cache line corresponding to the processor read Cache operation is the next exported Cache line, export the content in the Cache line corresponding to the read Cache operation .
10. The device according to claim 8 or 9, wherein the device further comprises:

    The control unit is configured to control the address generator to generate the first address by using one end of the Cache line address range.
11. The device according to claim 10, wherein the process of deriving the content in the Cache row by row is specifically: controlling the content in the Cache line corresponding to the first address generated by the address generator by the control unit Exported to the internal storage of the compressor, the control unit controls the address generator to change the first address to the next cache line address after each cache line is exported.
12. The apparatus according to claim 11, wherein the first determining unit comprises:

    a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is configured to compare a cache row address corresponding to the processor write Cache operation with a current first address size;

    a first determining subunit, configured to: when the address generator starts generating the first address by the low address end of the Cache line address range, the comparison result received by the receiving subunit is a Cache line corresponding to the processor write Cache operation The address is smaller than the current first address, and the cache line corresponding to the processor write Cache operation is determined to be in the exported part of the Cache;

    a second determining subunit, configured to: when the address generator starts generating the first address by the high address end of the Cache line address range, the comparison result received by the receiving subunit is a Cache line corresponding to the processor write Cache operation The address is greater than the current first address, and it is determined that the cache line corresponding to the processor write Cache operation is in the exported part of the Cache.
13. The apparatus according to claim 11, wherein the second determining unit comprises:

    a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is configured to compare a cache row address corresponding to the processor write Cache operation with a current first address size;

    a third determining subunit, configured to: when the address generator starts to generate the first address by the low address end of the Cache line address range, the comparison result received by the receiving subunit is a Cache line corresponding to the processor write Cache operation The address is greater than or equal to the current first address, and the cache line corresponding to the processor write Cache operation is determined to be in the unexported portion of the Cache;

    a fourth determining subunit, configured to be used by the address generator by the Cache line address range of the highlands When the address starts to generate the first address, the comparison result received by the receiving subunit is that the cache line address corresponding to the processor write Cache operation is less than or equal to the current first address, and the cache line corresponding to the processor write Cache operation is determined to be in the Cache. Unexported part.
14. The apparatus according to claim 11, wherein the third determining unit comprises:

    a receiving subunit, configured to receive a comparison result of the comparator, where the comparator is further configured to compare a cache line address corresponding to the processor read Cache operation with a current first address size;

    a fifth determining subunit, wherein the comparison result received by the receiving subunit is that the cache line address corresponding to the processor read Cache operation is equal to the current first address, and determining that the cache line corresponding to the processor read Cache operation is the next exported Cache line.
15. A system for establishing a processor Cache checkpoint, the system comprising:

    An export controller, which is the apparatus for establishing a processor Cache checkpoint according to any one of claims 8-14;

    An address generator, configured to generate a first address according to the control of the export controller;

    a comparator, configured to compare a cache row address corresponding to the processor write cache operation with a current first address, compare a cache row address corresponding to the processor read cache operation with a current first address, and send the comparison result Giving the derived controller;

    A compressor that stores the contents of the Cache line.

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