WO2012123995A1

WO2012123995A1 - Gradient voltage generating circuit, and display device

Info

Publication number: WO2012123995A1
Application number: PCT/JP2011/002162
Authority: WO
Inventors: 友和小島; 欣之大谷
Original assignee: パナソニック株式会社
Priority date: 2011-03-15
Filing date: 2011-04-12
Publication date: 2012-09-20
Also published as: JP2012194275A

Abstract

This gradient voltage generating circuit is configured such that a plurality of voltage follower circuits (2_1~2_64) are divided between at least two gradient voltage generating units (12_D1, 12_D2), and the two or more gradient voltage generating units drive the respective voltage follower circuit included therein at different power supply voltages having a lower potential difference than the potential difference between the maximum voltage (γref1) and the minimum voltage (γref64) among a plurality of reference voltages. A plurality of selection circuits (3_1~3_M) are also similarly divided between at least two switch circuits (3_D1, 3_D2), and driven. Furthermore, a pre-charge circuit can be further provided in the output path from the switch circuit to an output terminal, said pre-charge circuit being configured such that, by means of a process for changing the gradient voltage selection, the output terminal voltage is maintained at an intermediate voltage which is between the maximum and minimum voltages among the plurality of reference voltages.

Description

Gradation voltage generation circuit and display device

The present invention relates to a gradation voltage generation circuit and a display device using the same.

In recent years, active matrix type liquid crystal panels using TFTs (Thin Film Transistors), which are becoming smaller and more precise, are required to display images with abundant colors and high image quality through multi-gradation. ing. In order to satisfy such a requirement, the gradation voltage corresponding to the image data is corrected according to the gamma characteristic, and the signal line (also referred to as a source line or data line) of the liquid crystal panel is driven by the corrected gradation voltage. Has been. Note that the correction of the gradation voltage is generally performed by a gradation voltage generation circuit including a ladder resistor configured by connecting a plurality of resistors in series.

FIG. 14 is a diagram showing a configuration of a conventional gradation voltage generation circuit (liquid crystal driving power supply circuit) disclosed in Patent Document 1. In FIG. The gradation voltage generation circuit shown in FIG. 14 is configured to use voltages V1 to V6 divided by frequency dividing resistors R1 to R6 as power supply voltages of the operational amplifiers (voltage followers) 200a to 200d. In particular, the grayscale voltage generation circuit shown in FIG. 14 is configured such that the voltage at the previous stage and the next stage among the voltages divided by the frequency dividing resistors R1 through R6 are used as the power supply voltages of the operational amplifiers 200a through 200d. ing. For example, the voltage V1 and the voltage V3 are supplied as power supply voltages to the operational amplifier 200a to which the voltage V2 is input.

JP-A-5-257121

The configuration of Patent Document 1 has the following problems. As described above, the power supply voltage of each of the plurality of operational amplifiers is configured such that among the voltages divided by the plurality of frequency dividing resistors, the voltages at the previous stage and the next stage with respect to the input voltage of the operational amplifier are used. there. However, in the operation of the liquid crystal panel, when one of a plurality of gradation voltages output from a plurality of operational amplifiers is selected, it is applied to the pixel capacitor via a signal line. For this reason, when the gradation voltage is switched, a potential difference higher than the potential difference between the voltage at the previous stage and the next stage may be applied to each transistor constituting the operational amplifier. Therefore, the configuration of Patent Document 1 may cause breakdown of each transistor constituting the operational amplifier, but there is no suggestion or disclosure about the countermeasure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides a grayscale voltage generation circuit capable of appropriately switching grayscale voltages and a display device using the same, together with downsizing. it is.

In order to solve the above problem, a gradation voltage generating circuit according to one aspect of the present invention is configured to perform gradation of image data by dividing each voltage between a high potential side power source and a low potential side power source. A ladder resistor configured by connecting a plurality of resistors in series so as to generate a plurality of reference voltages in accordance with the reference voltage, and the reference voltage provided for each of the plurality of reference voltages is used as the gradation voltage. A voltage follower circuit group composed of a plurality of voltage follower circuits to be output, and a plurality of gradation voltages output from the voltage follower circuit group and the image data are input, and the gradation of the image data A gradation voltage selection circuit composed of a plurality of selection circuits configured to select and output one gradation voltage corresponding to the plurality of gradation voltages, and each of the plurality of selection circuits. A plurality of connected output terminals, wherein the plurality of voltage follower circuits of the voltage follower circuit group are divided into two or more gray voltage generators, and the two or more gray voltage generators are the plurality of gray voltage generators. The voltage follower circuit included in each of the voltage follower circuits is driven by different power supply voltages having a potential difference lower than the potential difference between the maximum voltage and the minimum voltage of the reference voltage, and the gradation voltage selection circuit The plurality of selection circuits are divided into two or more switch circuits, and the two or more switch circuits include the selection circuits belonging to each with a potential difference lower than a potential difference between a maximum voltage and a minimum voltage of the plurality of reference voltages. Each gray scale voltage selection is switched to an output path from each switch circuit to the output terminal. And a precharge circuit configured to hold the output voltage at an intermediate voltage between a maximum voltage and a minimum voltage of the plurality of reference voltages in the process.

In the gradation voltage generation circuit, the voltage follower circuit is configured by a transistor having a breakdown voltage corresponding to a power supply voltage having a potential difference lower than a potential difference between the maximum voltage and the minimum voltage of the plurality of reference voltages. It is good also as.

In the gradation voltage generation circuit, the switch circuit is configured by a transistor having a withstand voltage corresponding to a power supply voltage having a potential difference lower than a potential difference between the maximum voltage and the minimum voltage of the plurality of reference voltages. it may be.

In the gradation voltage generating circuit, the voltage follower circuit may be configured by an operational amplifier in which an output terminal is connected to an inverting input terminal and the reference voltage is input to a non-inverting input terminal. *

In the gradation voltage generation circuit, there are two gradation voltage generation units, two switch circuits, and the intermediate voltage is an average voltage of the maximum voltage and the minimum voltage of the plurality of reference voltages. There may be.

According to this configuration, the plurality of voltage follower circuits included in the voltage follower circuit group and the plurality of selection circuits included in the gradation voltage selection circuit include the maximum voltage and the minimum voltage of the plurality of reference voltages generated by the ladder resistor. Since it is driven with a potential difference lower than that between and with a different power supply voltage having the lower potential difference, it is configured with a low breakdown voltage transistor as compared with the case where it is not so divided can do. Thereby, the area of the whole gradation voltage generating circuit can be suppressed.

A plurality of voltage follower circuits included in the voltage follower circuit group and a plurality of selection circuits included in the gradation voltage selection circuit are configured by low breakdown voltage transistors, respectively. In some cases, a voltage higher than the withstand voltage is applied to the transistor. However, in the process of switching the grayscale voltage, the precharge circuit temporarily holds the voltage at the output terminal at an intermediate voltage between the maximum reference voltage and the minimum reference voltage generated by the ladder resistor. At most, a potential difference between the maximum reference voltage and the intermediate voltage or a potential difference between the intermediate voltage and the minimum reference voltage is applied. In other words, when the gradation voltage is switched, the low voltage transistor is not required to apply a potential difference between the maximum reference voltage and the minimum reference voltage. Thereby, the breakdown of the breakdown voltage of the low breakdown voltage transistor can be suppressed.

In the grayscale voltage generation circuit, the process of switching the selection of the grayscale voltage is a process of switching between the positive reference voltage and the negative reference voltage, and the selection circuit includes: The output path may further include a short circuit configured to hold the voltage at the output terminal at the ground potential in the process of switching the positive reference voltage and the negative reference voltage to each other. .

According to this configuration, in order to prevent burn-in of the display panel or the like, the voltage at the output terminal is grounded by a short circuit in the process of switching the positive reference voltage or the negative reference voltage to each other (polarity inversion). Since the potential is once held, the low withstand voltage transistor is applied with a potential difference between the maximum positive reference voltage and the ground potential or a potential difference between the ground potential and the minimum negative reference voltage. different. In other words, the potential difference between the positive maximum reference voltage and the negative minimum reference voltage is not applied to the low breakdown voltage transistor during polarity reversal. Thereby, the breakdown of the breakdown voltage of the low breakdown voltage transistor can be suppressed.

In the gradation voltage generation circuit, an operational amplifier that outputs a gradation voltage near a boundary between the plurality of gradation voltage generation units among the plurality of operational amplifiers that respectively constitute the plurality of voltage follower circuits. The regulated voltage may be driven by a power supply voltage different from that of other operational amplifiers in which the regulated voltage is within the operable voltage range of the operational amplifier.

According to this configuration, the operational amplifier that outputs the gradation voltage near the boundary of the plurality of gradation voltage generation units among the plurality of operational amplifiers included in the voltage follower circuit group is driven within the operable voltage range. Normal output can be obtained.

In order to solve the above problems, a display device according to another aspect of the present invention includes a plurality of pixels arranged in a matrix and a plurality of pixels connected to the plurality of pixels for each column or row. A display panel comprising: a signal line; and a plurality of scanning lines for selecting, for each row or column, a pixel to which the gradation voltage is to be applied among the plurality of pixels, via the plurality of scanning lines A scanning line driving circuit for selecting the pixel, the gradation voltage generating circuit in which the plurality of output terminals are connected to the plurality of signal lines, and a gradation voltage corresponding to the image data are the plurality of pixels. A timing controller that controls output of the grayscale voltage from the plurality of output terminals by the grayscale voltage generation circuit and selection of the pixel by the scanning line driving circuit so as to be applied to it is.

According to the present invention, it is possible to provide a gradation voltage generating circuit capable of appropriately switching gradation voltages together with downsizing and a display device using the same.

FIG. 1 is a diagram showing a configuration example of a display device according to Embodiment 1 of the present invention. FIG. 2 is a diagram schematically showing the configuration of each pixel shown in FIG. FIG. 3 is a graph showing the relationship between image data and gradation voltage. FIG. 4 is a block diagram showing a configuration example of the gradation voltage generating circuit according to the first embodiment of the present invention. FIG. 5 is a diagram showing a configuration example of a selection circuit included in the gradation voltage selection circuit shown in FIG. FIG. 6 is a diagram showing another configuration example of the selection circuit included in the gradation voltage selection circuit shown in FIG. FIG. 7 is a waveform diagram for explaining the operation of the selection circuit shown in FIG. FIG. 8 is a block diagram showing a configuration example of a gradation voltage generating circuit configured by connecting a positive circuit and a negative circuit. FIG. 9 is a block diagram showing a configuration example of a selection circuit included in the gradation voltage selection circuit shown in FIG. FIG. 10 is a waveform diagram for explaining an operation example of the selection circuit shown in FIG. FIG. 11 is a block diagram showing a configuration example of the gradation voltage generating circuit according to the second embodiment of the present invention. FIG. 12 is a circuit diagram showing a configuration example of a general operational amplifier. FIG. 13 is a diagram for explaining an operable voltage range of the operational amplifier shown in FIG. FIG. 14 is a diagram showing a configuration of a conventional gradation voltage generation circuit (liquid crystal drive power supply circuit).

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout the drawings, and redundant description thereof is omitted.

(Embodiment 1)
[Display device]
FIG. 1 is a diagram showing a configuration example of a display device according to Embodiment 1 of the present invention. Note that throughout all of the following embodiments, a liquid crystal display device is cited as an example of a display device according to the present invention, but the present invention is not limited to this, and an active matrix (active matrix) in which gradation voltages are corrected according to gamma characteristics. ) Type display device. FIG. 2 is a diagram schematically showing the configuration of each pixel shown in FIG. FIG. 3 is a graph showing the relationship between image data and gradation voltage.

The liquid crystal display device of FIG. 1 includes a liquid crystal panel 100, a backlight 110, a scanning line driving circuit 10, a signal line driving circuit 20, and a timing controller 30. there. Scanning line driving is performed so that display light is incident on the liquid crystal panel 100 from the backlight 110 and the display light is transmitted with a transmittance according to image data DATA (gradation data, display data) commanded from the outside. By driving the circuit 10 and the signal line driving circuit 20, an image corresponding to the image data DATA is displayed on the liquid crystal panel 100.

The liquid crystal panel 100 has a structure in which a liquid crystal layer 103 is sandwiched between a counter substrate 101 and an array substrate 102. A deflection plate 105 is disposed on the surface of the array substrate 102 and the counter substrate 101 opposite to the liquid crystal layer 103, and a light distribution film (not shown) is disposed on the surface of the array substrate 102 and the counter substrate 101 on the liquid crystal layer 103 side. Is arranged.

On the inner surface of the array substrate 102, N × M pixels PIX_ij (i = 1) arranged in a matrix (here, N rows × M columns, where N and M are natural numbers, and so on). N, j = 1 to M), N signal lines Y_i (i = 1 to N) connected to the pixel PIX_ij for each column or row, and a pixel to which the gradation voltage is to be applied among the pixels PIX_ij M scanning lines G_j (j = 1 to M) are selected for selecting for each row or column. The scanning line G_j is driven by the scanning line driving circuit 10, and the signal line Y_i is driven by the signal line driving circuit 20.

In the pixel PIX_ij, a thin film transistor (TFT) W and a pixel electrode PIX are formed at the intersection of the scanning line G_j and the signal line Y_i. The thin film transistor (transistor) W has a gate connected to one scanning line G_j, a source connected to one signal line Y_i, and a drain connected to the pixel electrode PIX. Has been.

The counter substrate 101 includes a color filter (not shown) disposed on the glass substrate and a common electrode VCOM disposed on the color filter so as to face the pixel electrode PIX of the array substrate 102. A liquid crystal capacitor C (including parasitic capacitance) is formed between the common electrode VCOM and the pixel electrode PIX facing the common electrode VCOM. The transmittance of the pixel PIX_ij is a difference voltage between the gradation voltage (pixel voltage) supplied to the pixel electrode PIX of the array substrate 102 and the common voltage supplied to the common electrode VCOM of the counter substrate 101 in the liquid crystal layer 103. It is controlled according to the applied driving voltage. The common electrode VCOM is connected to a power source for applying a common voltage via a common line (not shown) formed on the counter substrate 101.

The signal line drive circuit 20 includes a gradation voltage generation circuit 40 and an output circuit 50. The gradation voltage generation circuit 40 generates a plurality of gradation voltages based on a power supply voltage supplied from a power supply circuit (not shown). For example, when the image data DATA per pixel is 6 bits, 64 (= 2 to the sixth power) types of gradation voltages γ1 to γ64 are generated (see FIG. 3). Further, the gradation voltage generation circuit 40 selects one of the plurality of gradation voltages based on the plurality of bits of image data DATA and outputs the selected signal line Y_i to the output circuit 50. The output circuit 50 buffers the grayscale voltage supplied from the grayscale voltage generation circuit 40 for each signal line Y_i, and outputs it to each signal line Y_i. Thereby, each of the plurality of signal lines Y_i is driven.

The timing controller 30 outputs the grayscale voltage outputs γ1 to γ64 from the grayscale voltage generation circuit 40 and the pixels from the scanning line drive circuit 10 so that the grayscale voltages γ1 to γ64 corresponding to the image data DATA are applied to the pixels PIX_ij. Controls selection of PIX_ij. For example, the control signal CTG for sequentially selecting the scanning lines G_1 to G_N every one vertical scanning period (1V) and the analog for the pixel PIX_ij for one line included in the image data DATA every one horizontal scanning period (1H). A control signal CTY for assigning the image data DATA to each of the signal lines Y_1 to Y_M is generated.

The control signal CTG includes a vertical start signal which is a pulse generated every one vertical scanning period (1V), a vertical clock signal which is a pulse generated for the number of scanning lines G_j in one vertical scanning period (1V), and the like. And is supplied from the timing controller 30 to the scanning line driving circuit 10. The control signal CTY includes a horizontal start signal STH which is a pulse generated every horizontal scanning period (1H), a horizontal clock signal CKH which is a pulse generated by the number of signal lines in each horizontal scanning period, and pixels for one line. In order to drive the signal line Y_i corresponding to the image data DATA for PIX_ij, a strobe signal STB which is a pulse generated with a predetermined time delay from the start signal STH every horizontal scanning period (1H), and every horizontal scanning period (1H) and a polarity signal POL for setting the polarity of the pixel voltage with respect to the common voltage VCOM every vertical scanning period (1V). The control signal CTY is supplied from the timing controller 30 to the signal line driving circuit 20 together with the image data DATA. The image data DATA includes gradation data for correcting gradation characteristics (gamma characteristics) of the liquid crystal panel 100. *

[Grayscale voltage generator]
=== Lower pressure of ladder resistor and voltage follower circuit group ===
FIG. 4 is a block diagram showing a configuration example of the gradation voltage generation circuit according to the first embodiment of the present invention.

4 includes a ladder resistor 1, a voltage follower circuit group 2, and a gradation voltage selection circuit 3. The gradation voltage generation circuit 40 shown in FIG. In the example shown in the figure, the image data DATA has 6 bits, and the gradation level has voltage levels corresponding to 64 types of gradations, which is the sixth power of 2.

The ladder resistor 1 includes 65 resistors R1 to R65 between a high-potential-side power supply VDD and a low-potential-side power supply VSS generated based on a power supply voltage supplied from a power supply circuit (not shown). It is configured to be connected in series. The ladder resistor 1 divides the potential difference between the high-potential-side power supply VDD and the low-potential-side power supply VSS by the resistors R1 to R65, thereby taking out the reference voltages γref1 to γref64 from the connection points of the resistors R1 to R65. . The reference voltage γref1 is the maximum reference voltage, and the reference voltage γref64 is the minimum reference voltage.

In the voltage follower circuit group 2, one operational amplifier (2_1 to 2_64) is provided for each of the reference voltages γref1 to γref64 generated by the ladder resistor 1. Each of the operational amplifiers 2_1 to 2_64 is configured to be a voltage follower circuit. That is, the operational amplifiers 2_1 to 2_64 receive the reference voltages γref1 to γref64 from the ladder resistor 1, and output the gradation voltages γ1 to γ64 by impedance conversion so that the loss can be suppressed even when the input impedance of the external load is low. Is configured to do. Note that the plurality of voltage follower circuits of the voltage follower circuit group 2 may be configured by a transistor amplifier circuit such as a source follower in addition to the operational amplifier.

The gradation voltage selection circuit 3 is configured such that one selection circuit (3_1 to 3_M) is provided for each of the output terminals OUT1 to OUTM corresponding to the number of signal lines Y_i. The selection circuits 3_1 to 3_M are configured to select only one voltage to be applied to the pixels PIX_ij connected to the output terminals OUT1 to OUTM from the gradation voltages γ1 to γ64. Specifically, the selection circuits 3_1 to 3_M receive the gradation voltages γ1 to γ64 from the voltage follower circuit group 2 and the 6-bit image data DATA from the timing controller 6, and the 6-bit image data. Based on the result of decoding DATA, one of the gradation voltages γ1 to γ64 is selected and output.

In addition to the above-described configuration, the grayscale voltage generation circuit 40 shown in FIG. 4 makes the ladder resistor 1 and the voltage follower circuit group 2 at least two lower than the potential difference between the maximum reference voltage γref1 and the minimum reference voltage γref64. It is configured to be divided into two power systems. In the present embodiment, the gradation voltage generation circuit 40 includes a first gradation voltage generation unit 12_D1 that outputs any one of the gradation voltages γ1 (for example, 9.8 V) to γ32 (for example, 5.05 V), The second gradation voltage generator 12_D2 that outputs any one of the regulated voltages γ33 (for example, 5V) to γ64 (for example, 0.2V) is configured.

In the first gradation voltage generator 12_D1, the first power supply voltage (for example, 10V) and the second power supply for generating the gradation voltages γ1 (9.8V above) to γ32 (5.05V above) A voltage (for example, 4V) is used. The first power supply voltage and the second power supply voltage are generated based on a predetermined node voltage (VDD, γref1 to γref64, or VSS) of the ladder resistor 1 and drive the operational amplifiers 2_1 to 2_32. Used as

In the second gradation voltage generator 12_d2, the third power supply voltage (for example, 6V) and the fourth power supply voltage (for example, 0V) for generating the gradation voltages γ33 (5V) to γ64 (0.2V) are provided. It is used. The third power supply voltage and the fourth power supply voltage are generated based on a predetermined node voltage (VDD, γref1 to γref64, or VSS) of the ladder resistor 1 and drive the operational amplifiers 2_33 to 2_64. Used as

Here, when the maximum gradation voltage γ1 is 9.8V, the voltage follower circuit group 2 needs to be configured using, for example, a 10V withstand voltage transistor exceeding 9.8V. However, as in the present embodiment, the voltage follower circuit group 2 is divided into a first grayscale voltage generator 12_D1 and a second grayscale voltage generator 12_d2 each using a 6V power supply system. . For this reason, the voltage follower circuit group 2 can be composed of transistors having a 6V breakdown voltage lower than the 10V breakdown voltage, and the area of the voltage follower circuit group 2 can be reduced accordingly.

=== Lowering the breakdown voltage of the selection circuit ===
FIG. 5 is a diagram showing a configuration example of one selection circuit 3_1 included in the gradation voltage selection circuit 3 shown in FIG. The other selection circuits 3_2 to 3_M have the same configuration.

The selection circuit 3_1 is configured by arranging a switch composed of a P-type transistor or an N-type transistor so as to realize a tournament-type selection algorithm. Here, the tournament method selection algorithm is to repeatedly select two adjacent gradation voltages out of 64 gradation voltages based on the bit value of the image data DATA. It means an algorithm that finally selects one gradation voltage. “L: ON” in FIG. 5 represents a P-type transistor that is turned on when the corresponding bit of the image data DATA is Low (= 0) and is turned off when the corresponding bit is High (= 1). there. “H: ON” in FIG. 5 represents an N-type transistor that is turned on when the corresponding bit of the image data DATA is High (= 1) and turned off when the corresponding bit is Low (= 0). there.

For example, when the 6-bit image data DATA is “111111”, among the paths from 64 input terminals γ1 to γ64 to one output terminal OUT1, the path where all the switches are ON is the input terminal. There is only a path from γ64 to the output terminal OUT1. In this case, the selection circuit 3_1 selects the gradation voltage γ64 input to the input terminal 64 and outputs it from the output terminal OUT1.

Furthermore, the selection circuit 3_1 is configured to be divided into at least two power supply voltage systems according to the potential difference between the maximum reference voltage γref1 and the minimum reference voltage γref64. In the present embodiment, the selection circuit 3_1 includes a first switch circuit 3_D1 that outputs any one of gradation voltages γ1 (for example, 9.8V) to γ32 (for example, 5.05V), and a gradation voltage γ33 (for example, 5V). ) To γ64 (for example, 0.2V), and the second switch circuit 3_D2 that outputs any one of them is configured.

In the first switch circuit 3_D1, the first power supply voltage (for example, 10V) and the second power supply voltage (for example, 10V) for generating the gradation voltages γ1 (9.8V described above) to γ32 (5.05V described above) are provided. 4V) is used. The first power supply voltage and the second power supply voltage are generated based on a predetermined node voltage (VDD, γref1 to γref64, or VSS) of the ladder resistor 1 and used as a power supply voltage for driving the switch. . Specifically, the first power supply voltage is applied to the back gate of the P-type transistor used in the first switch circuit 3_D1, and the second gate is applied to the back gate of the N-type transistor used in the first switch circuit 3_D1. The power supply voltage is applied.

In the second switch circuit 3_d2, a third power supply voltage (for example, 6V) and a fourth power supply voltage (for example, 0V) for generating the gradation voltages γ33 (5V above) to γ64 (0.2V above) are provided. Is used. The third power supply voltage and the fourth power supply voltage are generated based on a predetermined node voltage (VDD, γref1 to γref64, or VSS) of the ladder resistor 1 and used as a power supply voltage for driving the switch. . Specifically, the third power supply voltage is applied to the back gate of the P-type transistor used in the second switch circuit 3_D2, and the fourth gate is applied to the back gate of the N-type transistor used in the second switch circuit 3_D2. The power supply voltage is applied.

Here, when the maximum gradation voltage γ1 is 9.8V, the selection circuit 3_1 needs to be configured using, for example, a 10V withstand voltage transistor exceeding 9.8V. However, as in this embodiment, the selection circuit 3_1 is divided into a first switch circuit 3_D1 and a second switch circuit 3_d2 each using a 6V power supply system. Therefore, the selection circuit 3_1 can be formed of a transistor with a 6V breakdown voltage that is lower than the 10V breakdown voltage, and its area can be reduced.

=== Precharge of pixel capacity at the time of gradation voltage switching ===
By the way, when the voltage follower circuit group 2 is constituted by low-voltage transistors, it is necessary to take the following points into consideration. That is, when driving the liquid crystal panel 100, the voltage charged one line before the pixel capacitance C of a certain signal line Y_i is the gradation voltage γ1 output from the operational amplifier 2_1. In this case, the maximum gradation voltage γ1 is charged in the pixel capacitor C of a certain signal line Y_i. When the minimum gradation voltage γ64 newly output from the operational amplifier 2_64 is charged to the pixel capacitance C of a certain signal line Y_i, the maximum gradation voltage γ1 is connected between the source and drain of the output transistor of the operational amplifier 2_64. And a potential difference between the minimum gradation voltage γ64 is applied. For example, in the above example, since the maximum gradation voltage γ1 is 9.8V and the minimum gradation voltage γ64 is 0.2V, the output transistor of the operational amplifier 2_64 has 9.6V ( = 9.8V-0.2V) is applied. As described above, with the breakdown voltage of the voltage follower circuit group 2, there is a risk that the output transistor of the voltage follower circuit group 2 is broken down when the grayscale voltage is switched.

Therefore, in the gradation voltage selection circuit 3, as a stage before charging the pixel capacitor C of a certain signal line Y_i, the pixel capacitor C is divided into the maximum gradation voltage γ1 (9.8V) and the minimum gradation voltage γ64 (0. A method of once precharging to an intermediate voltage between 2V) is adopted. In the following, when the intermediate voltage is 9.8V for the maximum gradation voltage γ1 and 0.2V for the minimum gradation voltage γ64, the intermediate voltage is the average voltage of the maximum gradation voltage γ1 and the minimum gradation voltage γ64. The description will be made assuming that 5V is (= (γ1 + γ64) / 2).

FIG. 6 is a diagram showing another configuration example of one selection circuit 3_1 included in the gradation voltage selection circuit 3 shown in FIG. 4, that is, a configuration example for realizing the precharge of the pixel capacitor C. The selection circuit 3_1 shown in FIG. 6 is different from the selection circuit 3_1 shown in FIG. 5 in that precharge switches (precharge switches) 3_SW1 and 3_SW3 for temporarily holding the voltage at the output terminal OUT1 at an intermediate voltage when the grayscale voltage is switched. Is added.

Here, the complementary switch of the first switch circuit 3_D1 corresponding to the fifth bit of the 6-bit image data DATA is represented by 3_D1_SW1 (P-type transistor) and 3_D1_SW2 (N-type transistor), and is also 5 of the image data DATA. The complementary switch of the second switch circuit 3_D2 corresponding to the bit number is represented as 3_D2_SW1 (P-type transistor) and 3_D2_SW2 (N-type transistor). Further, complementary switches corresponding to the sixth bit of the image data DATA are represented as 3_SW2 (P-type transistor) and 3_SW4 (N-type transistor).

One end of the precharge switch 3_SW1 is connected between the output end of the fifth bit complementary switch 3_D1_SW1, 3_D1_SW2 on the first switch circuit 3_D1 side and the input end of the sixth bit switch 3_SW2, and the other end. Is configured so that an intermediate voltage is applied thereto.

One end of the precharge switch 3_SW3 is connected between the output end of the fifth bit complementary switch 3_D2_SW1, 3_D2_SW2 on the second switch circuit 3_D2 side and the input end of the sixth bit switch 3_SW4, and the other end. Is configured so that an intermediate voltage is applied thereto.

FIG. 7 is a waveform diagram for explaining the operation of the selection circuit 3_1 shown in FIG. The example of FIG. 6 illustrates an example in which the selection circuit 3_1 in FIG. 6 selects the minimum gradation voltage γ64 output from the operational amplifier 2_64 from the state where the maximum gradation voltage γ1 output from the operational amplifier 2_1 has been selected. ing.

First, when the operational amplifier 2_1 outputs the maximum gradation voltage γ1, on the first switch circuit 3_D1 side, the fifth bit switch 3_D1_SW1 is ON, the switch 3_D1_SW2 is OFF, the precharge switch 3_SW1 is OFF, In addition, it is assumed that the 6th bit switch 3_SW2 is in the ON state. On the second switch circuit 3_D2 side, it is assumed that the 5th bit switch 3_D2_SW1 and the switch 3_D2_SW2 are both OFF, the precharge switch 3_SW3 is ON, and the 6th bit switch 3_SW4 is OFF.

Next, on the first switch circuit 3_D1, the 5th bit switch 3_D1_SW1 is switched from the ON state to the OFF state, and the precharge switch 3_SW1 is switched from the OFF state to the ON state. As a result, the pixel capacitor C of the signal line Y_i connected to the output terminal OUT1 is charged to an intermediate voltage via the precharge switch 3_SW1 and the sixth bit switch 3_SW2.

Next, on the first switch circuit 3_D1, the 6th bit switch 3_SW2 switches from the ON state to the OFF state, and on the second switch circuit 3_D2 side, the precharge switch 3_SW3 switches from the ON state to the OFF state. The bit switch 3_SW4 is switched from the OFF state to the ON state. Then, on the second switch circuit 3_D2 side, when the fifth bit switch 3_D2_SW2 is switched from the OFF state to the ON state, the gradation voltage γ64 output from the operational amplifier 2_64 is changed to the fifth bit switch 3_D2_SW2, the sixth bit. Output from the output terminal OUT1 via the switch 3_SW4.

In summary, when the driving voltage of the signal line Y_i is switched from the maximum gradation voltage γ1 to the minimum gradation voltage γ64, the pixel connected to the signal line Y_i is charged before the minimum gradation voltage γ64 is charged from the operational amplifier 2_64. The capacitor C is charged with an intermediate voltage of 5 V via the precharge switch 3_SW1. On the second switch circuit 3_D2 side, when the switch 3_D2_SW2 of the fifth bit is switched from the OFF state to the ON state, an intermediate voltage of 5 V is applied to the drain, and the source of the gradation voltage γ64 is 0. .2V is applied. As a result, the second switch circuit 3_D2, which is composed of a 6V withstand voltage transistor, and thus the operational amplifier 2_64 are reliably protected. Also for the switches 3_D1_SW1 and 3_D1_SW2, the precharge switch 3_SW1 continues to be ON while the minimum gradation voltage γ64 is output, so that the switches 3_D1_SW1 and 3_D1_SW2 are reliably protected.

=== Precharge of pixel capacitance at polarity inversion ===
In order to prevent burn-in of the liquid crystal panel 100, the liquid crystal display device is normally configured to alternately perform positive output that is positive with respect to the common voltage VCOM or negative output that is negative with respect to the common voltage VCOM. Has been.

FIG. 8 is a block diagram showing a configuration example of a gradation voltage generation circuit configured by connecting a positive circuit and a negative circuit. 8 includes a first gradation voltage generator 12_D1, a second gradation voltage generator 12D2, and a gradation voltage selection circuit 3, and these components are illustrated in FIG. 4 are the same as those shown in FIG. The negative electrode circuit of FIG. 8 includes a first negative gradation voltage generation unit N12_D1, a second negative gradation voltage generation unit N12_D2, and a negative gradation voltage selection circuit N3. With the voltage VCOM as a reference, a reverse polarity voltage that is line-symmetric with respect to the output terminals OUT1 to OUNM of the positive circuit is output. As shown in FIG. 8, the output terminals OUT1 to OUTM of the positive circuit and the output terminals OUT1 to OUTM of the negative circuit are short-circuited.

FIG. 9 is a block diagram showing a configuration example of the selection circuit 3_1 included in the gradation voltage selection circuits 3 and N3 shown in FIG. The other selection circuits 3_2 to 3_M have the same configuration.

As described above, the transistors (particularly the switches 3_SW1 to SW4_SW4) constituting the gradation voltage selection circuits 3 and N3 are low breakdown voltage (for example, 10V breakdown voltage) transistors, so that the gradation voltage selection circuits 3 and N3 The area is reduced. However, when the voltages before and after the polarity reversal collide, the low breakdown voltage transistor may break down. For example, when the pixel capacitance C of the signal line of the liquid crystal panel 100 is charged with −9.8 V (Nγ64) at the time of negative electrode driving, +9.8 V (γ1) at the time of positive electrode driving is newly added to the pixel capacitance C. When charged, in the switch 3_SW2 of the 6th bit, −9.8V (Nγ64) at the time of negative electrode driving is applied to its drain, and + 9.8V (γ64) at the time of positive electrode driving is applied to its source. It will be. Therefore, the source-drain voltage of the switch 3_SW2 is 19.6V, and if the switch 3_SW2 is formed of, for example, a 10V breakdown voltage transistor, the breakdown voltage may be destroyed.

Therefore, in order to employ the method of driving via the ground potential GND in the gradation voltage selection circuit 3, the selection circuit 3 uses a short switch (short switch) 3_SW5 to short-circuit the output path to the ground potential GND. 6 has been added.

FIG. 10 is a waveform diagram for explaining an operation example of the selection circuit 3_1 shown in FIG.

In the example of FIG. 10, the case is switched from negative drive of −9.8 V (Nγ64) to positive drive of +9.8 V (γ1).

First, when the negative circuit is driven (when -9.8V (Nγ64) is output), on the positive circuit side, the short switch 3_SW5 is in the ON state and the open switch (open switch) 3_SW6 is in the OFF state. Suppose that

Next, on the negative circuit side, the output is switched from −9.8 V to the ground potential GND, and the charging voltage of the pixel capacitor C of the signal line Y_i of the liquid crystal panel 100 becomes 0 V.

Next, on the negative circuit side, the open switch 3_SW6 is switched from the ON state to the OFF state.

Next, on the positive electrode circuit side, the short switch 3_SW5 is switched from the ON state to the OFF state, and the open switch 3_SW6 is switched from the OFF state to the ON state.

Next, on the positive electrode circuit side, when the switch 3_SW2 of the sixth bit is switched from the OFF state to the ON state, 9.8V (γ1) output from the operational amplifier 2_1 is selected and output.

In summary, the charging voltage of the pixel capacitor C is once maintained at 0 V as a stage before the gradation voltage γ1 output from the operational amplifier 2_1 is charged to the pixel capacitor C at the time of polarity inversion. That is, immediately after the switch 3_SW2 is turned on, 0 V is applied to its drain and 9.8 V (γ1) is applied to its source. Therefore, the source-drain voltage of the switch 3_SW2 is suppressed from 19.6V to 9.8V, and when the switch 3_SW2 is formed of, for example, a 10V breakdown voltage transistor, there is no possibility of breakdown breakdown.

(Embodiment 2)
=== Separate power supply for operational amplifier that outputs grayscale voltage near the boundary of power supply system ===
FIG. 11 is a block diagram showing a configuration example of the gradation voltage generating circuit according to the second embodiment of the present invention. The grayscale voltage generation circuit shown in FIG. 11 is different from the configuration of the grayscale voltage generation circuit 40 shown in FIG. 4 in that the first of the plurality of grayscale voltages γ1 to γ64 is selected from the voltage follower circuit group 2A. Grayscale voltage close to the second power supply voltage of the second grayscale voltage generator 12D1A and the third power supply voltage of the second grayscale voltage generator 12_D2A (close to the boundary between the two power supply systems) One or a plurality of operational amplifiers (hereinafter referred to as boundary operational amplifiers) that output a regulated voltage are extracted, and the power supply voltage of the boundary operational amplifier is made independent of the voltage follower circuit group 2A. In other words, in the first embodiment, the boundary operational amplifier that outputs the boundary gradation voltage is operated near the power supply voltage, and there is a possibility that the operable voltage range may be out of range. Therefore, in the second embodiment, a boundary gradation voltage generation unit 12_D3A configured by a boundary operational amplifier whose power supply voltage is independent from the voltage follower circuit group 2A is newly added.

The boundary gradation voltage generator 12_D3A generates a boundary gradation voltage close to the second power supply voltage and the third power supply voltage, and includes a boundary voltage follower circuit group 2A2. The boundary voltage follower circuit group 2A2 is composed of a plurality of boundary operational amplifiers (2_32, 2_33, etc.) that output boundary gradation voltages (γ32, γ33, etc.). The boundary operational amplifiers include first to fourth power supply voltages. A fifth power supply voltage and a sixth power supply voltage that are independent from each other are supplied. The fifth power supply voltage is a voltage near the middle between the first power supply voltage and the second power supply voltage, and the sixth power supply voltage is a voltage near the middle between the third power supply voltage and the fourth power supply voltage. It is said. For this reason, the gradation voltage output from the boundary voltage follower circuit group 2A2 falls within the voltage near the center of the operable voltage range, and the operation of the boundary voltage follower circuit group 2A2 is stabilized. Note that the fifth power supply voltage and the sixth power supply voltage are not provided with a new ladder resistor, but reference voltages (γref5 (7.4 V), γref59 (2) generated by the existing ladder resistor 1 are used. .7V) etc.) is used effectively. Thereby, an increase in the area of the gradation voltage generation circuit can be suppressed.

FIG. 12 is a circuit diagram showing a configuration example of a general operational amplifier, and FIG. 13 is a diagram for explaining an operable voltage range of the operational amplifier shown in FIG.

As shown in FIG. 12, a general operational amplifier has, as its differential amplifying unit, P-type transistors P1 and P2 constituting a current mirror, and N-type transistors N1 and N2 provided on the current discharge side of the current mirror. And an N-type transistor N3 connected in common with the N-type transistors N1 and N2. In addition, a general operational amplifier has a P-type transistor P3 and an N-type transistor N4 connected in series as its output section. Here, the ON voltage of the N-type transistor N3 is Ov1, the ON voltage of the N-type transistor N1 is Ov2, the ON voltage of the N-type transistor N4 is Ov3, the ON voltage of the P-type transistor P3 is Ov4, and the input bias voltage is VT2. it is assumed that.

As shown in FIG. 13, in order to operate the transistors constituting the operational amplifier in the saturation region, a voltage range in which the operational amplifier can operate is determined. The input potential difference of the operational amplifier configured as shown in FIG. 12 is in the range of [Ov1 + VT2 + Ov2 to AVDD]. Even if a voltage within the range of [AVSS to Ov1 + VT2 + Ov2] deviating from the input potential difference is input to the operational amplifier, the transistors constituting the operational amplifier operate in the non-saturated region, so that the operational amplifier cannot operate normally. Further, the output potential difference of the operational amplifier configured as shown in FIG. 12 is in the range [AVSS + Ov3 to AVDD−Ov4], and the voltage within the range [AVSS to Ov3] or [AVDD−Ov4 to Even if a voltage within the range of [AVDD] is output from the operational amplifier, the transistors constituting the operational amplifier operate in a non-saturated region, and thus the operational amplifier cannot operate normally. If AVSS = 0V, AVDD = 3V, Ov1 = 0.2V, VT2 = 0.7V, Ov2 = 0.2V, Ov3 = 0.2V, Ov4 = 0.2V, the operable voltage range is [1 .1V to 2.8V]. *

Therefore, the boundary gradation voltages close to the second power supply voltage and the third power supply voltage are the boundary levels to which the fifth power supply voltage and the sixth power supply voltage independent of the first to fourth power supply voltages are applied. It was made to generate in the regulated voltage generator 12_D3A. The fifth power supply voltage may be approximately 7.5 V in the vicinity of the middle between the first power supply voltage and the second power supply voltage, and the sixth power supply voltage is the same as the third power supply voltage. What is necessary is just to give the voltage of about 2.5V in the middle of the fourth power supply voltage.

From the above description, many modifications and other embodiments of the present invention are apparent to persons skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.

The gradation voltage circuit and the display device using the same according to the present invention are particularly useful for a liquid crystal display device used in an electronic device such as a notebook personal computer that is required to be compact and have high performance.

DESCRIPTION OF SYMBOLS 10 ... Scanning line drive circuit 20 ... Signal line drive circuit 30 ... Timing controller 40 ... Gradation voltage generation circuit 50 ... Output circuit 100 ... Liquid crystal panel 101 ... Counter substrate 102 ... Array substrate 103 ... Liquid crystal layer 105 ... Deflection plate 110 ... Back Lights OUT1 to OUTM ... Output terminals Y_1 to Y_N ... Signal lines G_1 to G_N ... Scanning lines 12_D1, N12_D1 ... First gradation voltage generators 12_D2, N12_D2 ... Second gradation voltages generator 1 ... Ladder resistors R1 to R65: frequency dividing resistors γref1 to γref64:

reference voltage

2, 2A: voltage follower circuit group 3, N3: gradation voltage selection circuit γ1 to γ64: gradation voltage (positive output)
Nγ1 to Nγ64 ... gradation voltage (negative output)
3_1 to 3_M... Selection circuit 3_D1... First switch circuit 3_D2... Second switch circuit 3_SW1, 3_SW2... Precharge switch 3_SW5.

Claims

A ladder resistor constructed by connecting a plurality of resistors in series so as to generate a plurality of reference voltages corresponding to the gradation of image data by dividing each voltage between a high potential side power source and a low potential side power source. When,
A voltage follower circuit group including a plurality of voltage follower circuits provided for each of the plurality of reference voltages and outputting the input reference voltage as the gradation voltage;
The plurality of gradation voltages output from the voltage follower circuit group are input and the image data is input, and one gradation voltage corresponding to the gradation of the image data is set to the plurality of gradation voltages. A gradation voltage selection circuit composed of a plurality of selection circuits configured to select and output from among;
A plurality of output terminals respectively connected to the plurality of selection circuits,
The plurality of voltage follower circuits of the voltage follower circuit group are divided into two or more gradation voltage generators, and the two or more gradation voltage generators are between a maximum voltage and a minimum voltage of the plurality of reference voltages. Each of the voltage follower circuits included in each of the voltage follower circuits included in different power supply voltages having a potential difference lower than the potential difference of
The plurality of selection circuits of the gradation voltage selection circuit are divided into two or more switch circuits, and the two or more switch circuits have a potential difference lower than a potential difference between a maximum voltage and a minimum voltage of the plurality of reference voltages. The selection circuits belonging to each of the switching circuits are respectively driven, and in the process of switching the selection of the gradation voltage, the voltage at the output terminal is applied to the output path from each switch circuit to the output terminal. A grayscale voltage generation circuit further comprising a precharge circuit configured to hold an intermediate voltage between a maximum voltage and a minimum voltage of a plurality of reference voltages.
2. The floor according to claim 1, wherein the voltage follower circuit includes a transistor having a withstand voltage corresponding to a power supply voltage having a potential difference lower than a potential difference between a maximum voltage and a minimum voltage of the plurality of reference voltages. Regulated voltage generation circuit.
2. The gradation according to claim 1, wherein the switch circuit includes a transistor having a withstand voltage corresponding to a power supply voltage having a potential difference lower than a potential difference between a maximum voltage and a minimum voltage of the plurality of reference voltages. Voltage generation circuit.
2. The gradation voltage generating circuit according to claim 1, wherein the voltage follower circuit includes an operational amplifier in which an output terminal is connected to an inverting input terminal and the reference voltage is input to a non-inverting input terminal.
The number of the gradation voltage generation units is two, the number of the switch circuits is two, and the intermediate voltage is an average voltage of the maximum voltage and the minimum voltage of the plurality of reference voltages. A gradation voltage generation circuit.
The process of switching the selection of the gradation voltage is a process of switching between the positive reference voltage and the negative reference voltage.
The selection circuit is configured to hold the voltage at the output terminal at the ground potential in the process of switching the positive reference voltage and the negative reference voltage to the output path of the switch circuit. The gradation voltage generating circuit according to claim 1, further comprising a short circuit.
Of the plurality of operational amplifiers constituting each of the plurality of voltage follower circuits, an operational amplifier that outputs a gradation voltage near the boundary of the plurality of gradation voltage generation units can operate with the gradation voltage near the boundary. The gradation voltage generation circuit according to claim 4, wherein the gradation voltage generation circuit is driven by a power supply voltage different from that of another operational amplifier that falls within a certain voltage range.
A plurality of pixels arranged in a matrix, a plurality of signal lines connected to the plurality of pixels for each column or row, and a pixel to which the gradation voltage is applied among the plurality of pixels are arranged in rows or columns. A display panel comprising a plurality of scanning lines for selecting each;
A scanning line driving circuit for selecting the pixel through the plurality of scanning lines;
The gradation voltage generation circuit according to claim 1, wherein the plurality of output terminals are connected to the plurality of signal lines, respectively.
The gradation voltage output from the plurality of output terminals by the gradation voltage generation circuit and the pixel by the scanning line driving circuit so that the gradation voltage corresponding to the image data is applied to the plurality of pixels. And a timing controller for controlling selection of the display device.