WO2012001788A1

WO2012001788A1 - Multicore processor system, restoration program, and method of restoration

Info

Publication number: WO2012001788A1
Application number: PCT/JP2010/061192
Authority: WO
Inventors: 浩一郎山下; 宏真山内; 鈴木　貴久; 康志栗原
Original assignee: 富士通株式会社
Priority date: 2010-06-30
Filing date: 2010-06-30
Publication date: 2012-01-05
Also published as: JPWO2012001788A1; JP5454686B2

Abstract

In (D), an encryption engine (104) compresses block data (MC51) and generates compressed data (mc51) according to an instruction from a privilege mode program (H). Further, a hash value (h51) is generated for the compressed data (mc51). A hash value (h5) and the hash value (h51) are compared. Because a block data (MC5) is modified by the block data (MC51) in response to a fault, the compressed data (mc51) and the hash value (h51) are saved. In this case, the master CPU is stalling, so, of the compressed data (mc5, mc51), the compressed data (mc5) before modification as a result of the fault is expanded and a block data (MC5) is generated. Then, in (E) the faulty block data (MC51) is replaced by the expanded block data (MC5), and thereby a master context MC (block data (MC12), (MC2) - (MC8)) is restored.

Description

Multi-core processor system, restoration program, and restoration method

The present invention relates to a multicore processor system, a restoration program, and a restoration method that cause a plurality of processors (multicore processors) to execute a program.

Conventionally, the OS initialization data is saved to the main memory write-protected area at the initial startup of the OS (Operating System), and the OS is restarted from a specific address and the saved initialization data is used when the OS is restarted when a failure is detected. Thus, a technique for restoring the main memory is disclosed. Also disclosed is a technique for saving the contents of the main memory to a storage area of the main memory after the initial startup of the OS and restoring the contents of the storage area to the main memory upon restart (for example,

Patent Documents

1 and 2 below). See).

Japanese Patent Laid-Open No. 11-24936 JP 2002-258971 A

However, if it is attempted to operate in an embedded system such as a mobile phone to which a multi-core processor system is applied by the above-described conventional software control, the memory image is protected every moment during operation, which causes an overhead factor. There is. In addition, if the operation state is stored on the memory in a multiple manner, the required memory amount increases, and there is a problem that portability is impaired due to an increase in size.

An object of the present invention is to provide a multi-core processor system, a restoration program, and a restoration method capable of efficiently realizing a warm start during operation in order to solve the above-described problems caused by the prior art.

In order to solve the above-described problem and achieve the object, the first processor executing the master process among the multi-core processors accessing the shared memory detects that the context related to the master process in the shared memory is accessed, Each time access to the context is detected, a combination of difference data before and after detection in a section including the access destination in the context is stored, and when the first processor is stalled, the first of the multi-core processors A second processor selected from a group of processors other than one processor restores the context before the stall based on the combination of the difference data for each partition before the stall, and the first processor If the second processor stalls, the second program A multi-core processor system, a restoration program, which creates the master process to be executed by a second processor by the second processor, and associates the restored pre-stall context with the created master process by the second processor; The restoration method is provided as an example.

According to the above multi-core processor system, restoration program, and restoration method, it is possible to efficiently realize a warm start during operation.

It is a block diagram which shows the system configuration example of a multi-core processor system. It is explanatory drawing which shows the example of an update of the compression information in a protection area. It is a flowchart which shows the update process procedure of compression information. It is a flowchart which shows a restoration process procedure. It is a block diagram which shows the system state after decompression | restoration.

Hereinafter, embodiments of a multi-core processor system, a restoration program, and a restoration method according to the present invention will be described in detail with reference to the accompanying drawings.

In the embodiment described below, the master function of the OS is protected by using a cryptographic engine that is standardly installed in an embedded terminal, particularly many portable terminals, and a snoop controller that is mounted in a multi-core processor. Continue system operation without a cold start when a failure occurs.

(Example of system configuration)
FIG. 1 is a block diagram illustrating a system configuration example of a multi-core processor system. In FIG. 1, a multicore processor system 100 includes a multicore processor 101, a snoop controller 102, a watchdog timer 103, a cryptographic engine 104, and a shared memory 105 that are communicably connected via a bus 106.

The multi-core processor 101 is composed of a plurality of CPUs (Central Processing Units) (four in the figure as an example). Each of the CPUs # 0 to # 3 is provided with a cache memory (hereinafter simply referred to as “cache”) C. Each of the CPUs # 0 to # 3 executes the privileged mode program H. The privileged mode program H is, for example, a hypervisor, and is a program that can directly access each of the CPUs # 0 to # 3 by privilege.

Further, each of the CPUs # 0 to # 3 executes a kernel K, a master process MP, and a slave process SP. The kernel K is a program that is the core of the OS, and executes memory management, file management, and management of the multi-core processor 101. Further, the kernel K generates a master process MP.

The master process MP is a program that manages the slave process SP. The master process MP is generated and executed only by one CPU of the multi-core processor 101 (CPU # 0 as an example in FIG. 1). A CPU that executes the master process MP is referred to as a master CPU. At the time of initial startup, the master CPU is set to CPU # 0. However, migration may be performed according to the present embodiment, or other existing load distribution may be performed to shift to another CPU # 1 to CPU # 3. is there. Further, the remaining CPUs other than the master CPU in the multi-core processor 101 are referred to as slave CPUs.

The slave process SP is a program executed by the multi-core processor 101. Specific examples of the slave process SP include system processes such as thread generation (scheduling), interrupt processing, and system resource access (driver). As described above, information management of these slave processes SP is held by the master process MP, and the master process MP monitors these resource managements using the master context written in the system management area on the shared memory 105. To do.

In addition, the slave process SP notifies the master process MP of a change in its own state. If there is no response to the master process MP, a timeout occurs because a resource failure has occurred. After that, conventionally, the multi-core processor system 100 is hung or reset operation is performed through the watchdog timer 103. In this embodiment, the master process MP is restored.

Note that a kernel K and a process (including at least the master process MP) in which the master process MP is operating are referred to as a master OS. The kernel K and the slave process SP are referred to as a slave OS. The OS includes a library common to application software (hereinafter simply referred to as “application”) AP, but is omitted here for the sake of simplicity. Various applications AP operate on the master OS and the slave OS.

The snoop controller 102 is connected to the multi-core processor 101 and monitors the cache C of each CPU # 0 to CPU # 3. When a value in a certain cache C is updated, the snoop controller 102 performs a coherent process on another cache C. Specifically, the snoop controller 102 detects all memory accesses that pass through the cache C. Therefore, when the detected memory access is a memory access to the coherent corresponding area in the cache C, the snoop controller 102 executes the above-described coherent processing.

The watchdog timer 103 periodically checks the survival state of the multi-core processor 101, and responds to the non-responsive CPUs # 0 to # 3 in order to recover from the stop or runaway state of the program counter for illegal segment access. Issue a reset signal.

The cryptographic engine 104 is hardware that executes encryption processing of target data and decryption processing of encrypted data. The cryptographic engine 104 is hardware that is provided as standard in the portable terminal. The cryptographic engine 104 is a unit that is installed on the bus 106 to which the shared memory 105 is connected for the purpose of concealing personal data, and performs encryption / decryption.

For encryption, AES (Advanced Encryption Standard), DES (Data Encryption Standard), etc. are used, but usually a data reversible compression function such as Huffman coding is installed.

In this embodiment, the encryption and decryption processes in the encryption engine 104 are omitted. However, the compressed data is encrypted, the encrypted data is decrypted into the compressed data, and then decompressed. Shall be. Also, the encryption process and the decryption process need not be executed only by compression and decompression.

During operation, when the memory rewrite is detected by the snoop controller 102 or when the privileged mode program H detects a process change (update of the system management area by the master process MP), the reversible compression of the cryptographic engine 104 is performed on the updated data. Data is backed up in a protected area in the shared memory 105 as compressed data by compressing using the function.

Also, the cryptographic engine 104 calculates a hash value of the compressed data. Thereby, when the data is updated and the compressed data and the hash value thereof are obtained, it is understood that the compressed data is the same before and after the update if it matches the stored hash value. On the other hand, if the hash values do not match, the compressed data differs before and after the update.

When the compressed data is different before and after the update, the cryptographic engine 104 stores the old compressed data before the update and its hash value, and the new compressed data after the update and the hash value in the protected area in the shared memory 105. If the compressed data is the same before and after the update, the new compressed data after the update and its hash value are not saved. As a result, the latest two compressed data and their hash values are always stored. Since the cryptographic engine 104 is hardware, there is no influence on performance.

The shared memory 105 is a storage area shared by the multi-core processor 101, and includes a system management area 151, a protection area 152, and a general area 153. The system management area 151 is an area where the master OS, slave OS, and privileged mode program H can read and write. In the system management area 151, a master context MC related to the master process MP is stored.

The master context MC is unique information obtained by the master process MP such as a stack pointer and a register value managed by the master process MP, a value of a program counter, a type of the generated slave process SP, and a generation destination CPU number of the slave process SP. is there. The master context MC is divided into a plurality of sections. Specifically, for example, the data is stored separately for each unit area such as a cache line, a page, and a bank.

The protected area 152 is an area for storing the compressed data compressed by the privileged mode program H and its hash value. In this embodiment, a double buffer method is adopted. The double buffer method is a method of storing two pieces of compressed data and hash values of data at the same location in time series.

Since the master context MC is divided for each unit area, when data of a certain unit area in the master context MC is updated, compressed data (old compressed data) before the update and its hash are obtained as the compression information 160. The value (old hash value), the updated compressed data (new compressed data), and the hash value (new hash value) are stored.

General area 153 is an area where the master OS, slave OS, and application AP store data. Specifically, the master OS and the slave OS store data other than data to be stored in the system management area 151 in the general area 153. The application AP stores the calculation result in the general area 153.

(Update example of protected area 152)
FIG. 2 is an explanatory diagram showing an example of updating the compression information 160 in the protection area 152. In FIG. 2, as an example, it is assumed that the master context MC is divided into eight and stored in the system management area 151 as partition data MC1 to MC8.

(A) shows the state when the system is started. At the time of system startup, since all the storage areas of the master context MC are accessed, a difference occurs in all the storage areas. Therefore, the partition data MC1 to MC8 are stored as the master context MC. Then, according to an instruction from the privileged mode program H, the cryptographic engine 104 compresses the divided data MC1 to MC8 to generate compressed data mc1 to mc8. Also, the cryptographic engine 104 generates hash values h1 to h8 of the compressed data mc1 to mc8. The cryptographic engine 104 stores the generated compressed data mc1 to mc8 and their hash values h1 to h8 in the protected area 152.

In (B), it is assumed that the partition data MC1 in the master context MC is updated from the state of (A) to become partition data MC11. That is, it is assumed that the memory access destination is an address in the partition data MC1. In this case, the cryptographic engine 104 compresses the partition data MC11 according to an instruction from the privileged mode program H to generate compressed data mc11. Further, the cryptographic engine 104 generates a hash value h11 of the compressed data mc11.

Then, the hash value h1 is compared with the hash value h11. When h1 = h11, the compressed data mc11 and its hash value h11 are not stored. On the other hand, when h1 ≠ h11, there is a difference between the partition data MC1 and the partition data MC11, and the compressed data mc11 and its hash value h11 are stored. In (B), it is assumed that the compressed data mc11 and its hash value h11 are stored as h1 ≠ h11. Also, for the partition data MC2 to MC8 that have not been updated this time, the cryptographic engine 104 does not compress or calculate a hash value.

In (C), it is assumed that the partition data MC11 in the master context MC is updated to the partition data MC12 from the state of (B). That is, it is assumed that the memory access destination is an address in the partition data MC12. In this case, the cryptographic engine 104 compresses the partition data MC12 according to an instruction from the privileged mode program H to generate compressed data mc12. Further, the cryptographic engine 104 generates a hash value h12 of the compressed data mc12.

Then, the hash value h11 and the hash value h12 are compared. When h11 = h12, the compressed data mc12 and its hash value h12 are not stored. On the other hand, when h11 ≠ h12, there is a difference between the partition data MC11 and the partition data MC12, and the compressed data mc12 and its hash value h12 are stored. In (C), it is assumed that the compressed data mc12 and its hash value h12 are stored as h11 ≠ h12. Also, for the partition data MC2 to MC8 that have not been updated this time, the cryptographic engine 104 does not compress or calculate a hash value.

In (D), it is assumed that the partition data MC5 of the master context MC is updated due to a failure from the state of (C) to become partition data MC51. That is, it is assumed that the memory access destination is an address in the partition data MC51. In this case, the cryptographic engine 104 compresses the partition data MC51 according to an instruction from the privileged mode program H to generate compressed data mc51. Further, the cryptographic engine 104 generates a hash value h51 of the compressed data mc51.

Then, the hash value h5 is compared with the hash value h51. Due to the failure, the partition data MC5 is updated to the partition data MC51. Therefore, h5 ≠ h51, and there is a difference between the partition data MC5 and the partition data MC51, and the compressed data mc51 and its hash value h51 are stored. In this case, since the master CPU is stalled, the encryption engine 104 causes the compressed data mc5 and mc51 stored in the protection area 152 for the partition data MC51 that is the failure location according to an instruction from the privileged mode program H of the slave CPU. Among them, the compressed data mc5 before update due to the failure is expanded to generate partition data MC5.

Then, in (E), the master context MC at the time of failure, specifically, the partition data MC5, MC2 to MC4, MC51, MC6 to MC8, which is the master context MC of (D), is the partition data that becomes a failure. The master context MC (partition data MC12, MC2 to MC8) is restored by replacing the MC51 with the expanded partition data MC5. The restored master context MC is in the state before the failure occurrence in (D), that is, the state (C). Also, the updated compressed data mc51 and its hash value h51 in (D) are also deleted from the protected area 152 and restored to the same state as in (C).

(Compressed data and hash value update processing)
FIG. 3 is a flowchart showing a procedure for updating the compression information 160. First, the snoop controller 102 detects a memory access passing through the cache C from the kernel K, master process MP, and slave process SP (step S301). Note that the memory access is also performed from the application AP via the kernel K, the master process MP, and the slave process SP.

Next, when detecting the memory access, the snoop controller 102 determines whether or not the memory access is a coherent corresponding area in the cache C (step S302). If it is not a coherent area (step S302: No), the process returns to step S301. On the other hand, when it is a coherent corresponding area (step S302: Yes), the snoop controller 102 performs cache coherent (step S303), and returns to step S301.

The privileged mode program H monitors memory access by the snoop controller 102. In step S301, when the snoop controller 102 detects memory access of the target data, the privileged mode program H waits for memory access to the system management area 151 in the shared memory 105 (step S304: No). If the memory access of the target data is a memory access to the system management area 151 (step S304: Yes), the privileged mode program H performs a cache flush of the target data (step S305).

In this case, the target data written to the cache C is also written to the shared memory 105 by write-through. For example, when the master context MC in the system management area 151 by the master process MP is updated, the target data is written in the non-coherent corresponding area of the cache C and is also written in the master context MC. Then, the non-coherent corresponding area of the cache C is cache flushed. Thereafter, the privileged mode program H activates the cryptographic engine 104 and gives an instruction to compress the target data (step S306).

Further, the same processing is performed even when access is made from another program, for example, the application AP, instead of access to the system management area 151 by the master process MP. That is, the privileged mode program H executes the processing of steps S304 to S306 regardless of what program the memory access source is.

When receiving the compression instruction from the privileged mode program H, the cryptographic engine 104 compresses the target data written in the access destination (step S307). For example, as shown in FIG. 2, when the partition data MC1 of the master context MC is the target data, the partition data MC1 is updated to the partition data MC11. Therefore, the cryptographic engine 104 compresses and compresses the partition data MC11. The data is mc11.

Next, the cryptographic engine 104 calculates a hash value of the compressed data (step S308). Then, the cryptographic engine 104 determines whether or not there is a difference between the compressed data compressed last time and the compressed data compressed this time for the partitioned data that is the access destination (step S309). Specifically, it is determined whether or not the hash value of the old compressed data and the hash value of the new compressed data are the same. If they are the same, there is no difference.

On the other hand, if they are not identical, there will be a difference. If there is no difference (step S309: No), the processing of the cryptographic engine 104 is terminated. On the other hand, if there is a difference (step S309: Yes), the cryptographic engine 104 stores the new compressed data and its hash value in the protected area 152 as shown in FIG. 2 (step S310).

As described above, in the flowchart shown in FIG. 3, regardless of whether the memory access to the system management area 151 is a normal update process or a memory access that disturbs the system management area 151, When the data is updated, the latest compressed data and its hash value at the access destination, the previous previous compressed data and its hash value are stored.

(Restore process)
FIG. 4 is a flowchart showing the restoration processing procedure. First, the watchdog timer 103 monitors the master CPU (step S401: No). When the watchdog timer 103 detects an abnormality due to a stall or hang of the master CPU (step S401: Yes), the privileged mode program H receives the notification of the abnormality detection of the master CPU and temporarily stops the slave OS to the slave CPU. An instruction is notified (step S402). The slave CPU that has received the temporary stop instruction temporarily stops the slave OS.

After that, since the master CPU has stalled (hereinafter, the stalled master CPU is referred to as “stall CPU”), the privileged mode program H can execute the stall from among the slave CPUs that have received an instruction to pause the slave OS. A restoration source CPU for restoring the CPU is selected (step S403). Specifically, for example, a CPU having a lower CPU number among the slave CPUs is selected as the restoration source CPU. In the example of FIG. 1, since CPU # 0 becomes a stall CPU, CPU # 1 becomes a restoration source CPU. Further, the CPU having the lowest load among the slave CPUs is selected as the restoration source CPU. The CPU load can be obtained by monitoring the slave OS or the privileged mode program H of the slave CPU.

Then, when the restoration source CPU is selected, the privileged mode program H of the restoration source CPU specifies partition data that becomes a failure location in the master context MC (step S404). Specifically, the privileged mode program H of the restoration source CPU does not specify whether or not the failure has occurred due to the stall, and it is not necessary. When an abnormality is detected by the watchdog timer 103, as shown in FIG. 2, the partition data having the master context MC is compressed by memory access detection, and the new compressed data and its hash value are stored.

The privileged mode program H of the restoration source CPU identifies the compression source partition data of the new compression data saved at this time as the failure location. The privileged mode program H of the restoration source CPU extracts the old compressed data from the new and old compressed data of the partition data that is the specified failure location, to the cryptographic engine 104 (step S405), and extracts the extracted old compressed data. Extend (step S406). For example, as shown in FIG. 2D, when the failure location is the partition data MC51, the previous old compressed data mc5 is extracted instead of the new compressed data mc51.

The privileged mode program H of the restoration source CPU restores the master context MC to the state before the stall by overwriting the failed portion of the master context MC with the expanded partition data (step S407). For example, as shown in FIG. 2D, the extracted compressed data mc5 is expanded to partition data MC5, and the partition data MC5 expanded to partition data MC51 of the master context MC in FIG. Overwriting (see (E) of FIG. 2).

Thereafter, the privileged mode program H of the restoration source CPU updates the process table held by the kernel K in the slave OS that is temporarily stopped by the restoration source CPU (step S408). Specifically, an address specifying the restored master context MC is added to the process table. The process table is stored in the cache C in the restoration source CPU or the system management area.

Then, the privileged mode program H of the restoration source CPU releases the suspension only for the slave OS of the restoration source CPU, and notifies the generation instruction of the master process MP to the kernel K of the slave OS of the restoration source CPU (step S409). Thereby, since the master process MP is generated by the restoration source CPU, it is associated with an address that designates the restored master context MC in the updated process table. In this way, the master process MP is migrated to the restoration source CPU.

After this, the privileged mode program H of the restoring source CPU notifies the instruction to cancel the suspension of the slave OS of the remaining remaining slave CPU (step S410). As a result, the operation of the OS is resumed by the slave CPU other than the stall CPU. Further, when the operation of the OS is resumed, the operation of the upper application AP is also resumed.

Thus, after the migration of the master process MP is completed, the privileged mode program H of the restoration source CPU reboots the stall CPU (step S411). Thereby, the restoration process ends.

FIG. 5 is a block diagram showing the system state after restoration. In FIG. 5, since the CPU # 1 is the restoration source CPU, the master process MP is migrated to the CPU # 1. The CPU # 0, which is a stall CPU, does not execute the OS and the application AP immediately after rebooting, but the CPU # 1, which is the master CPU after restoration, instructs the activation of the slave OS, so that the CPU # When 0, kernel K is started. Thereafter, the load of the multi-core processor 101 can be balanced by allocating the slave process SP and the application AP by a known load balancing technique.

Many technologies for protecting the master process MP and the master CPU have been developed, but all of them store the initial state, and during operation, the overhead of storing the dynamic change state every moment is large. It cannot be restored efficiently.

On the other hand, according to the present embodiment, when an abnormality occurs in the master CPU during the operation of the multi-core processor system 100, the master context MC is restored to the state before the stall and the master CPU is set to the slave CPU. Process MP can be migrated. Therefore, it is not necessary to cold start the entire system, and warm start is possible. Further, not only the master process MP but also when the master context MC is rewritten due to an illegal operation or abnormal operation of the application AP, the warm start can be similarly performed.

Particularly, since the multi-core processor system 100 has a large number of CPUs, the chip area is inevitably widened. Therefore, gamma rays are easily irradiated, and bit inversion may occur in the CPU. Even when the value in the master context MC is changed due to such bit inversion, since the stall of the master CPU is detected by the watchdog timer 103, the warm start by the high-speed transition of the master process MP can be realized.

Further, each time the master context MC is updated, the master context MC can be restored by storing the old and new compressed data and the hash value thereof only for the updated partition data. Therefore, since the size of the protection area 152 can be reduced, the system management area 151 and the general area 153 can be increased accordingly.

Further, when the multi-core processor system 100 is mounted on a mobile terminal, the mobile terminal inevitably requires a high-speed startup as compared with a stationary terminal. Therefore, it is not necessary to restart the entire system due to a warm start after the master CPU stall. Therefore, the convenience of the mobile terminal can be improved.

The cryptographic engine 104 is hardware that is provided as standard equipment for communication authentication and data protection in portable terminals such as mobile phones, smartphones, game machines, and tablets. By diverting the encryption engine 104 provided as a standard for restoration, it is not necessary to install hardware dedicated for restoration. Therefore, the number of parts of the mobile terminal can be reduced, and an increase in size due to an increase in functions can be prevented.

100 Multi-core processor system 101 Multi-core processor 102 Snoop controller 103 Watchdog timer 104 Cryptographic engine 105 Shared memory 106 Bus 151 System management area 152 Protected area 153 General area 160 Compressed information AP Application C Cache H Privileged mode program MC Master context MP Master process SP Slave process

Claims

Detecting means for detecting that a first processor executing a master process among multi-core processors accessing a shared memory accesses a context relating to the master process in the shared memory;
Each time the access to the context is detected by the detection means, a storage means for storing a combination of difference data before and after detection in a section including the access destination in the context;
When the first processor is stalled, the second processor selected from a group of processors other than the first processor among the multi-core processors causes the difference data for each partition before the stall to be stored. Restoring means for restoring the context before the stall based on the combination;
Generating means for generating, by the second processor, the master process executed by the second processor when the first processor is stalled;
Association means for associating, by the second processor, the pre-stall context restored by the restoration means and the master process created by the creation means;
A multi-core processor system comprising:
The detection means includes
The access to a context related to the master process is detected based on a detection result of a memory access to the shared memory by a cache coherency mechanism that performs coherent processing of each cache in the multi-core processor. Item 4. The multi-core processor system according to Item 1.
Compression means for compressing the difference data;
Calculating means for calculating a hash value of the compressed differential data compressed by the compressing means;
Determining means for determining whether or not the hash values of the compressed difference data in the same location before and after accessing the context calculated by the calculating means match;
Decompression means for decompressing the compressed differential data,
The storage means includes
If it is determined that there is a mismatch by the determination unit, the combination of the compressed difference data determined as a mismatch is stored,
The restoration means includes
3. The multi-core processor system according to claim 1, wherein the context before the stall is restored based on the differential data decompressed from the compressed differential data before the stall by the decompression unit.
Determining means for determining the second processor from the other processor group based on the load of each of the other processor group;
The restoration means includes
2. The context before the stall is restored based on the difference data before the stall by the second processor determined by the determination unit when the first processor is stalled. Or the multi-core processor system of 2.
3. The multi-core processor system according to claim 1, further comprising a reboot unit configured to reboot the first processor by the second processor after the first processor is stalled.
A detecting step of detecting that a first processor executing a master process among multi-core processors accessing the shared memory has accessed a context relating to the master process in the shared memory;
Each time the access to the context is detected by the detection step, a storage step of storing a combination of difference data before and after detection in a section including the access destination in the context;
When the first processor is stalled, the second processor selected from a group of processors other than the one of the multi-core processors, and the combination of the difference data for each partition before the stall Based on the restoration process of restoring the context before the stall; and
When the first processor is stalled, a generation step of generating the master process executed by the second processor by the second processor;
An association step of associating, by the second processor, the pre-stall context restored by the restoration step and the master process created by the creation step;
Is executed by the multi-core processor.
A detecting step of detecting that a first processor executing a master process among multi-core processors accessing the shared memory has accessed a context relating to the master process in the shared memory;
Each time the access to the context is detected by the detection step, a storage step of storing a combination of difference data before and after detection in a section including the access destination in the context;
When the first processor is stalled, the second processor selected from a group of processors other than the one of the multi-core processors, and the combination of the difference data for each partition before the stall Based on the restoration process of restoring the context before the stall; and
When the first processor is stalled, a generation step of generating the master process executed by the second processor by the second processor;
An association step of associating, by the second processor, the pre-stall context restored by the restoration step and the master process created by the creation step;
Is performed by the multi-core processor.