WO2022193768A1

WO2022193768A1 - Method for executing memory read-write instruction, and computing device

Info

Publication number: WO2022193768A1
Application number: PCT/CN2021/140505
Authority: WO
Inventors: 吴平宇; 潘伟
Original assignee: 华为技术有限公司
Priority date: 2021-03-16
Filing date: 2021-12-22
Publication date: 2022-09-22
Also published as: CN115080223A

Abstract

The present application belongs to the field of computers. Provided are a method for executing a memory read-write instruction, and a computing device. According to the present application, in a page table entry corresponding to a virtual address, a field is enabled to carry mirror indication information, so as to indicate that mirror protection has been enabled for a memory space identified by the virtual address. When a memory read-write instruction is received, if it is discovered that there is mirror indication information in a page table entry corresponding to a virtual address that is carried in the memory read-write instruction, a read-write operation is performed on both two memory spaces corresponding to a master address and a standby address, such that a dynamic memory mirror function is supported, and the limitation of an existing memory mirror solution can be solved to a certain extent.

Description

Execution method and computing device of memory read and write instructions

This application claims the priority of the Chinese patent application with the application number 202110281668.8 filed on March 16, 2021 and the invention title is "Memory Read and Write Instruction Execution Method and Computing Device", the entire contents of which are incorporated into this application by reference .

technical field

The present application relates to the field of computers, and in particular, to a method for executing memory read and write instructions and a computing device.

Background technique

Memory mirroring is a memory protection technology. Memory mirroring-enabled memory spaces include main memory space and mirrored memory space. The main memory space is used for the memory controller to read data, and the mirror memory space is used to save the backup of the data in the main memory space. When the main memory space fails, the computer can recover data from the mirrored memory space, improving memory stability and availability.

Nowadays, administrators pre-set parameters such as the memory space for enabling memory mirroring, the size of the mirrored memory space, and software modules based on memory mirroring protection. After the computer starts, it will implement memory mirroring through the preset memory space.

However, if the preset memory size for enabling memory mirroring in the above solution is too small, the demand for mirrored memory may not be satisfied, resulting in out of memory (OOM). If the memory space is too large, it will lead to a waste of memory space. It can be seen that the above scheme has certain limitations.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a method and a computing device for executing a memory read and write instruction, which help to support the function of dynamic memory mirroring and thus solve the limitation of the existing memory mirroring scheme to a certain extent. The technical solution is as follows.

A first aspect provides a method for executing a memory read/write instruction, the method comprising: receiving a memory read/write instruction, the memory read/write instruction carrying a virtual address of a target memory space; responding to a page corresponding to the virtual address The table entry includes mirroring indication information, the main address and mirroring address are determined according to the virtual address, the mirroring indication information is used to identify that memory mirroring has been enabled in the target memory space, and the main address is the main memory in the target memory space The physical address of the space, the mirror address is the physical address of the mirror memory space in the target memory space; according to the main address and the mirror address, execute the memory on the main memory space and the mirror memory space Operations corresponding to read and write instructions.

The above method enables the field in the page table entry corresponding to the virtual address to carry the mirroring indication information, thereby indicating that mirroring protection has been enabled in the memory space identified by the virtual address. When a memory read/write command is received, if it is found that the page table entry corresponding to the virtual address carried by the memory read/write command has mirror indication information, the two memory spaces corresponding to the primary address and the standby address are both read and written, thus supporting The dynamic memory mirroring function can solve the limitations of the existing memory mirroring scheme to a certain extent.

Optionally, the mirrored memory space and the main memory space are located in different channels.

In this way, multiple channels can be used to parallelize the mirrored memory space and the main memory space, thereby improving read and write performance.

Optionally, the mirrored memory space is separated from the main memory space by a distance of at least one cache line size.

In this way, the address calculation method is made as simple as possible, and the implementation complexity is reduced.

Optionally, the offset address included in the main address is determined according to the size of the cache line and the offset address included in the virtual address.

In this way, the main address can be determined according to the virtual address carried by the memory read and write instructions and the size of the cache line, and the computational complexity is low.

Optionally, performing an operation corresponding to the memory read/write instruction on the main memory space and the mirrored memory space according to the main address and the mirrored address includes: responding to the main memory corresponding to the main address. Both the ECC space and the ECC space corresponding to the mirror address include the mirror indication information, and according to the main address and the mirror address, execute the memory read and write instructions corresponding to the main memory space and the mirror memory space. operation.

In this way, it helps to avoid mirrored read and write operations in non-mirrored memory space, and ensures that mirror-protected pages are only used for mirrored read and write operations.

Optionally, before the receiving a memory read/write instruction, the method further includes: receiving a memory allocation request for a specified object; in response to setting a mirror flag of the specified object to a set value, allocating the specified object to the specified object. The target memory space; wherein, when the mirror flag is set to a set value, it indicates to allocate memory space including the main memory space and the mirror memory space for the specified object.

In the above manner, mirror protection is adopted for the memory actually requested to be allocated when the specified object is running, so as to avoid the waste of memory resources caused by the preset mirror memory that is too large, and avoid the service interruption caused by insufficient mirror memory.

Optionally, after receiving the memory allocation request for the specified object, the method further includes: sending the page table entry corresponding to the virtual address, the ECC space corresponding to the main address, and the ECC space corresponding to the mirror address, respectively. Write the mirroring indication information.

In the above manner, mirroring indication information is set in the page table entry corresponding to the specified object and the ECC space, so that each hardware of the computer can identify that the memory of the specified object is protected by mirroring.

Optionally, before the receiving the memory allocation request of the specified object, the method further includes: in response to a memory mirroring instruction, modifying the mirroring flag of the specified object to the set value, the memory mirroring instruction indicating that The memory space required by the specified object enables memory mirroring.

In the above manner, it is convenient to trigger an instruction through the programming interface to define which object to enable mirror protection, so as to meet the custom requirements and improve the flexibility.

Optionally, each virtual page identified by the virtual address corresponds to two adjacent physical pages.

Optionally, the method further includes: in response to a failure of the mirrored memory space, isolating the mirrored memory space; reallocating the mirrored memory space for the virtual address, and writing the data stored in the main memory space to a Reallocated mirrored memory space.

In the above manner, the influence of the memory failure on the system is reduced, and the reliability is improved.

In a second aspect, a device for executing memory read and write instructions is provided, and the device has the function of implementing the first aspect or any optional manner of the first aspect. The apparatus includes at least one unit, and the at least one unit is configured to implement the method provided in the first aspect or any optional manner of the first aspect. In some embodiments, the elements in the apparatus are implemented in software, and the elements in the apparatus are program modules. In other embodiments, the units in the apparatus are implemented by hardware or firmware. For specific details of the apparatus provided in the second aspect, reference may be made to the foregoing first aspect or any optional manner of the first aspect, which will not be repeated here.

In a third aspect, a computing device is provided, the computing device includes a processor and a memory, the memory stores at least one piece of program code, the program code is loaded and executed by the processor to implement the above-mentioned first aspect or The method provided in any optional manner of the first aspect.

A fourth aspect provides a computer-readable storage medium, where at least one instruction is stored in the storage medium, and when the instruction is executed on a computer, causes the computer to execute the above-mentioned first aspect or any optional manner of the first aspect. provided method.

In a fifth aspect, a computer program product is provided, the computer program product includes one or more computer program instructions, when the computer program instructions are loaded and executed by a computer, cause the computer to execute the first aspect or the first aspect above. A method provided by any of the alternatives on the one hand.

In a sixth aspect, a chip is provided, including a memory and a processor, the memory is used to store computer instructions, and the processor is used to call and run the computer instructions from the memory to execute the above-mentioned first aspect and any possible possible aspects of the first aspect. method in the implementation.

A seventh aspect, a computing device is provided, the computing device includes a memory management unit (memory management unit, MMU), a memory controller (memory controller, MC) and a memory; the MMU is used for receiving memory read and write instructions , the memory read-write instruction carries the virtual address of the target memory space; the MMU is further configured to determine the main address and the mirror address according to the virtual address in response to the page table entry corresponding to the virtual address including the mirroring indication information, The mirroring indication information is used to identify that memory mirroring has been enabled in the target memory space, the main address is the physical address of the main memory space in the target memory space, and the mirroring address is the mirrored memory space in the target memory space The physical address of the MC; the MC is configured to perform operations corresponding to the memory read and write instructions on the main memory space in the memory and the mirror memory space in the memory according to the main address and the mirror address.

Description of drawings

FIG. 1 is a schematic structural diagram of a computing device provided by an embodiment of the present application;

2 is a schematic diagram of a read-write memory provided by an embodiment of the present application;

3 is a flowchart of a method for executing a memory read/write instruction provided by an embodiment of the present application;

4 is a schematic diagram of a relationship between a primary address and a mirror address provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a device for executing a memory read/write instruction provided by an embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Some terms and concepts involved in the embodiments of the present application are explained below.

(1) channel (channel)

A channel refers to the physical path between the memory controller and the storage medium. There is optionally one or more channels between the memory controller and the storage medium. Different channels can work serially or in parallel. In the case of multiple channels working in parallel, it can improve the bandwidth and throughput of the memory.

(2) Memory address interleaving (channel interleave or interleaved memory)

Memory address interleaving refers to an addressing method that evenly distributes memory addresses across a group of channels. For example, there are 2 channels, channel 0 and channel 1. With memory address interleaving enabled, if virtual address 32 belongs to channel 0, then virtual address 33 belongs to channel 1, virtual address 34 belongs to channel 0, and virtual address 35 belongs to channel 1, and so on. By enabling memory address interleaving, each channel can be used in parallel or in turn to perform continuous memory reading and writing, thereby reducing the time consuming of memory reading and writing and improving the efficiency of memory reading and writing.

(3) Enable memory space for memory mirroring

A memory space with memory mirroring enabled consists of two separate physical memory spaces. One physical memory space acts as the main memory space, and the other physical memory space acts as the mirror memory space. When a process, kernel, or other object initiates a write data command to a memory space with memory mirroring enabled, the data will be written to the main memory space and the mirrored memory space at the same time, so that the same two copies of the data exist in memory. Typically, the main memory space is used for reading and writing, while the mirror memory space is used to hold backups of data. If the main memory space fails, memory data can be recovered from the mirrored memory space. Typically, the mirrored memory space has the same capacity as the main memory space. For example, the capacity of the main memory space is N pages, and the capacity of the mirror memory space is also N pages.

(4) Mirror indication information (mirror indicator)

The mirroring indication information is the indication information provided by this embodiment for identifying whether to enable memory mirroring. Through the mirroring indication information, it is possible to distinguish whether the memory space to be accessed is a memory space with memory mirroring enabled or a memory space without memory mirroring enabled. Specifically, in the memory allocation process, if the allocated memory space A is a memory space with memory mirroring enabled, the corresponding mirroring indication information is marked for the memory space A; in the memory read-write process, when the memory management unit (memory management unit) unit, MMU) detects the mirroring indication information, the MMU will calculate the physical address of the main memory space according to the address calculation method provided in this embodiment, and when the memory controller (memory controller, MC) detects the mirroring indication information, the MC will follow the The address calculation method provided in this embodiment calculates the physical address of the mirrored memory space, so as to correctly convert the virtual address to the physical address of the main memory space and the physical address of the mirrored memory space. Optionally, the mirroring indication information occupies one bit in the reserved field. A bit occupied by the mirroring indication information can be called the mirroring indication information field. If the bit position is set (that is, the value is 1), it indicates that the mirroring indication information is available. If the bit is not set (that is, the value is 0), it indicates that the mirroring indication information is not available. .

(5) Mirror flag (mirror flag)

The mirroring flag is a flag provided in this embodiment for identifying whether to allocate a memory space for enabling memory mirroring. For example, when the mirroring flag is set to a set value (such as 1), it indicates that the allocation of memory space includes enabling memory mirroring. When the mirror flag is not set to the set value, it means that only the memory space of the size specified by the request is allocated. For example, process A sends a memory allocation request indicating that process A is allocated a page of memory space. If the mirror flag of process A is 1, two physical pages are allocated for process A, one physical page is the main memory space, and the other physical page is the mirror memory space. If process A's mirroring flag is 0, process A is allocated a physical page.

The mirror flag is, for example, an input parameter of a memory allocation function. The mirroring flag instructs memory space to be allocated with memory mirroring enabled when the memory allocation function is executed. For example, the memory allocation function is the kmalloc function, and the mirror flag is a get free page (get free pages, GFP) allocation flag (also called the memory allocation flag or the flags parameter) of the kmalloc function. For another example, the memory allocation function is the vmalloc function, and the image flag is a virtual address space (virtual memory area, VMA) flag in the vmalloc function.

(6) cache line (cache line)

A cache is hardware that caches the contents of memory. A cache line is the basic unit of a cache. Cache line size refers to the size of a cache line. When the computer accesses the memory, it will migrate the data in the memory to the cache according to the size of the cache line. For example, the cache line size is N bytes, and when the computer accesses the memory, at least N bytes of data in the memory are migrated to the cache at a time.

(7) Error checking and correction (Error Correcting Code, ECC) space

ECC space refers to the area in memory where checksums in ECC technology are kept. ECC is an instruction error correction technique. The basic principle of ECC is that each time data is written into the memory, the ECC code uses a special algorithm to calculate the data, and the result is called check bits. Then add all the check bits together to get the checksum (checksum), and the checksum is stored in memory along with the data. When the data is read from the memory, the same algorithm is used to calculate the checksum again and compare it with the previous calculation result. If the result is the same, it means that the data is correct, otherwise it means that there is an error, then the error is logically separated and notified. system. When only a single-bit error occurs, ECC can correct the error without affecting system operation.

If the memory failure is mild, the application process will be terminated or crashed abnormally, and some services will be interrupted. In severe cases, the operating system (OS) will be down, and all services will be interrupted. At present, in addition to using memory ECC and other reliability, availability and diagnostic (Reliability, Availability and Serviceability, RAS) technologies for fault detection and error correction, mission critical also requires memory mirroring technology to further reduce memory failures and business interruptions possibility. In the case of enabling memory mirroring, the memory space is organized in the manner of the main memory space and the mirrored memory space, and is allocated to the application in units of a main memory space and a mirrored memory space. When one memory space in the main memory space and the mirrored memory space fails, the system can restore data from another memory space, thereby avoiding application or system downtime.

However, the cost of the current memory mirroring technology is relatively high, and when the preset mirror memory space is insufficient, OOM will still occur, resulting in service interruption. Modifying the mirror space must be restarted (reboot) to take effect, and will also interrupt services. Some researches try to implement memory mirroring using full mirror mode, partial mirror mode, address range mirroring, etc. However, the memory mirroring relationship in these modes is fixed, which cannot meet the software's dynamic mirroring management requirements for key business memory modules. Specifically, when the preset image memory cannot meet the needs of the kernel, OOM occurs, and the preset image is too large, which leads to a waste of memory; moreover, OS support is required to fully utilize the address range image; and, firmware-OS (Firmware-OS) needs to be provided. interface, the OS must interact with the Basic Input Output System (BIOS) to determine the mirror region information; and, to modify the mirror region size (region size), the operating system must be restarted to take effect; and the application process cannot obtain the mirror image Protect.

In view of this, the embodiment of the present application provides a dynamic memory mirroring scheme, which only adopts mirror protection for the memory actually allocated by the OS or key business processes, and can avoid the preset memory under the condition that the memory failure will not lead to interruption of the business. Excessive mirroring memory leads to waste of expensive memory resources, and it can also avoid the serious consequences of insufficient mirroring space in the preset memory, failure of mirroring protection, or service interruption caused by OOM. In addition, the existing mirroring solution cannot solve the problem of allocating new mirroring space after the mirroring memory fails, resulting in that the business continuity cannot be well guaranteed; while in the embodiment of the present application, when the dynamic mirroring memory fails, the system can additionally allocate a new mirroring space. Mirror memory and isolate faulty memory to ensure business continuity.

The basic hardware structure of the computing device involved in the embodiments of the present application is illustrated below with an example.

FIG. 1 is a schematic structural diagram of a computing device provided by an embodiment of the present application. The computing device 100 shown in FIG. 1 is used to execute the method provided by the embodiment of the present application.

Computing device 100 includes processor 101 , memory 102 , and network interface 103 .

The processor 101 includes a CPU, an MMU, and an MC. The CPU includes a CPU execution unit and an MMU.

A CPU execution unit refers to a hardware unit in a CPU that processes data or computer program instructions. For example, a CPU execution unit is one or more CPU cores. In the process of executing mirrored memory read and write, the CPU execution unit is used to generate and send memory read and write instructions.

The MMU is used to translate virtual addresses to physical addresses. Specifically, as shown in FIG. 2 , after the CPU execution unit sends the memory read and write instructions, the MMU intercepts the memory read and write instructions, and performs address conversion, that is, converts the virtual addresses in the memory read and write instructions into physical addresses. After that, the MMU sends the address-translated instruction to the MC. The action of MMU address translation is also called translation. The MMU uses page tables to implement virtual to physical address translation. In this embodiment of the present application, the physical address obtained by the MMU address conversion includes at least one of a main address or a mirror address. For example, in some embodiments, as shown in FIG. 2, the MMU sends the main address and the mirror address to the MC; the MC receives the main address and the mirror address sent by the MMU, and performs mirror read and write operations on the memory according to the main address and the mirror address . In other embodiments, the MMU sends the main address and the virtual address to the MC, the MC receives the main address and the virtual address sent by the MMU, and the MC determines the mirror address according to the main address and the virtual address. After that, the MC performs mirrored read and write operations on the memory according to the main address and the mirrored address. The MMU is usually set up inside the CPU.

The page table is stored in memory. Each row in the page table corresponds to a page in the virtual storage space. The row contains the address of the physical memory page corresponding to the virtual memory page, the access authority of the page, and the buffering characteristics of the page. . Each entry in the page table is called a page table entry.

The MC is used to control the memory, and the data exchange between the memory and the CPU is realized through the MC. Specifically, the MC is used to access the memory according to the physical address carried by the instruction sent by the MMU. In the case of reading data, the MC obtains the data from the location corresponding to the physical address in the memory, and returns the data to the CPU. In the case of writing data, the MC writes the data to the location corresponding to the physical address. When the MC receives the memory read/write command sent by the MMU, the MC judges whether the memory read/write command is a mirror read/write command, and judges whether the mirror indication information field in the ECC is set; if the memory read/write command is a mirror read/write command and the ECC If the medium mirror indication information field is set, the MC performs mirror read and write operations, that is, perform read data operations or write data operations on the main memory space and the mirror memory space at the same time. If the memory read/write command is not a mirror read/write command and the mirroring indication information field in the ECC is set, the MC refuses to execute the memory read/write command, thereby preventing the mirrored memory from being illegally accessed.

The positional relationship between the MC and the CPU includes various cases. Optionally, the MC is provided inside the CPU, that is, the MC is integrated with the CPU. Alternatively, the MC is provided outside the CPU, that is, the MC is provided separately from the CPU. For example, in FIG. 2, the MC in the processor 101 is arranged inside the CPU, and the MC in the processor 105 is arranged outside the CPU.

The memory 102 includes memory. Memory includes ECC space. The memory 102 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or a device that can store information and instructions. Other types of dynamic storage devices, such as electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, optical disks storage (including compact discs, laser discs, compact discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium accessed by a computer without limitation.

In some embodiments, computing device 100 also includes bus 104 . Optionally, bus 104 is a memory bus or a system bus. The processor 101 , the memory 102 and the network interface 103 are connected through a bus 104 . The bus 104 is used to transfer information between the aforementioned components.

In some embodiments, computing device 100 also includes an input-output interface 106 . An input-output interface 106 is connected to the bus 104 .

In some embodiments, the input-output interface 106 is used for connecting with an input device, and receiving commands or data involved in the following method embodiments input by a user through the input device, such as memory mirroring instructions. Input devices include, but are not limited to, keyboards, touch screens, microphones, mice, or sensing devices, among others.

In some embodiments, the input-output interface 106 is also used to interface with output devices. The input-output interface 106 outputs the intermediate results and/or final results generated by the processor 301 by executing the following method embodiments, such as data read from the memory, through the output device. Output devices include, but are not limited to, displays, printers, projectors, and the like.

Optionally, the processor 101 implements the methods in the above embodiments by reading program codes stored in the memory 102, or the processor 101 implements the methods in the above embodiments by using internally stored program codes. When the processor 101 implements the method in the above embodiment by reading the program code stored in the memory 102, the memory 102 stores the program code for implementing the method provided by the embodiment of the present application.

For more details of the above-mentioned functions implemented by the processor 101, please refer to the descriptions in the foregoing method embodiments, which will not be repeated here.

The method flow of the embodiment of the present application is illustrated below with an example.

FIG. 3 is a flowchart of a method for executing a memory read/write instruction provided by an embodiment of the present application. The method shown in FIG. 3 includes the following steps S301 to S303.

Step S301, the computing device receives a memory read and write instruction.

The memory read and write instructions are used to instruct a data read operation or a write data operation to the target memory space. The target memory space refers to the space that needs to be accessed currently in the memory of the computing device. Memory read and write instructions carry the virtual address of the target memory space. For example, a memory read/write instruction includes a destination address field, and the content of the destination address field includes a virtual address of the target memory space.

The virtual address of the target memory space includes the base address and the offset address. The base address in the virtual address, also called the page number, is used to identify the corresponding virtual page. The offset address in the virtual address, also called the page offset, is used to identify the location inside the virtual page. Among them, a virtual page is also called a logical page, which is a concept relative to a physical page.

Step S302, in response to the page table entry (page table entry, PTE) corresponding to the virtual address including the mirroring indication information, the computing device determines the main address and the mirroring address according to the virtual address.

The page table is used to record the physical address corresponding to the virtual address, and the page table also includes a reserved field.

The mirroring indication is used to identify that the target memory space has memory mirroring enabled. The mirroring indication information in the page table entry is located in the reserved field of the page table entry. For example, one or more bits are enabled in the reserved field of the page table entry as the mirror indication information field. If the mirroring indication information field in the page table entry is set (that is, the page table entry includes mirroring indication information), it means that memory mirroring is enabled in the target memory space. If the mirroring indication information field in the page table entry is not set (that is, the page table entry does not include mirroring indication information), it means that memory mirroring is not enabled in the target memory space. For example, the PTE of the ARM architecture includes an upper attribute field, an output block address field, and a lower attribute field, and the upper attribute field includes a reserved for software use field, A bit in a field reserved for software use is enabled as a mirror indication field.

By enabling the field in the page table entry to carry the mirroring indication information, the MMU can identify whether dynamic mirroring is enabled for the virtual address through whether the page table entry carries the mirroring indication information, thereby solving the problem that the MMU does not support translating virtual addresses into real mirroring addresses.

The main address is the physical address (Physical Address, PA) of the main memory space in the target memory space. The main address includes the base address and the offset address. The base address corresponds to the page number of the physical page. For example, referring to FIG. 4, a specific main address is simplified in the form of “Pri+number” in FIG. 4, for example, each of Pri0, Pri1...Pri4095 in FIG. 4 represents a specific main address. Among them, Pri is the abbreviation of "Primary (main, referring to the main memory space)".

The mirror address is the physical address of the mirror memory space in the target memory space. The mirror address includes the base address and the offset address. For example, referring to FIG. 4 , a specific mirror address is simplified in the form of “Sec+number” in FIG. 4 . For example, each of Sec0 , Sec1 . . . Sec4095 in FIG. 4 represents a specific mirror address. Among them, Sec is the abbreviation of "Secondary (standby, referring to the mirrored memory space)".

In some embodiments, the mirrored memory space is separated from the main memory space by a distance of one or more cache line sizes. Optionally, the mirrored memory space is separated from the main memory space by a distance of one cache line size.

In some embodiments, the primary address is separated from the mirrored address by a distance of at least one cache line size. Optionally, the primary address is separated from the mirrored address by a distance of one cache line size. For example, referring to FIG. 4, the primary address Pri0 and the backup address Sec0 have a mirror relationship, the primary address Pri63 and the backup address Sec63 have a mirror relationship, the primary address Pri0 and the backup address Sec0 are separated by a distance of a cache line size, and the primary address Pri63 and the backup address Sec63 is one cache line size apart. In this way, the address calculation method is made as simple as possible, and the implementation complexity is reduced.

In some embodiments, the relationship between the mirror address and the master address satisfies Equation 1 below.

Secondary_PA=Primary_PA+CacheLine_Size; Formula 1

In the above formula 1, Secondary_PA represents the mirror address, Primary_PA represents the primary address, and CacheLine_Size represents a cache line size. For example, referring to Figure 4, when the cache line size is 64B, the main address Pri0 is in the first byte of Cache Line0, and the mirror address Sec0 corresponding to the main address Pri0 is in the first byte of Cache Line1, so Sec0=Pr0 +0x40. Through the above formula 1, it is ensured that the MC can calculate the mirror address through the destination address field of the memory read and write instructions.

In some embodiments, the offset address included in the main address is determined according to the cache line size and the offset address included in the virtual address. Specifically, when the dynamic memory mirroring function is not enabled, the physical address obtained by translating the virtual address through the page table is the actual memory address, that is, PA=Page_Base_PA+Offset_In_VA. Among them, PA represents the physical address, Page_Base_PA represents the base address of the physical page, and Offset_In_VA represents the offset address in the physical page. After the dynamic mirroring function is enabled, the physical address translated by the virtual address through the page table (ie Page_Base_PA+Offset_in_VA) is no longer equal to the actual main address (ie Page_Base_PA+Offset in Memory). Assuming that the size of a page is 4 kilobytes (Kilobyte, KB), and the size of the cache line is 64 bytes (byte, B), as shown in Figure 4, the offset address of the actual main address and the offset of the virtual address The address (that is, the offset in the page table) satisfies the following relationship:

Offset_In_Memory=Offset_In_VA+Cache_Line_Size*[INT(Offset_In_VA/Cache_Line_Size)];

Among them, Offset_In_Memory represents the offset address of the main address, Offset_In_VA represents the offset address in the virtual address, Cache_Line_Size represents the size of the cache line, and INT represents the rounding operation.

According to the above relationship, the calculation formula of the master address is shown in the following formula 2.

Primary_PA=Page_Base_PA+Offset_In_VA+Cache_Line_Size*[INT(Offset_In_VA/Cache_Line_Size)]; Formula 2

In the above formula 2, Primary_PA represents the main address, Page_Base_PA represents the base address of the physical page, Offset_In_VA represents the offset address in the virtual address, Cache_Line_Size represents the cache line size, and INT represents the rounding operation. Through the above formula 2, it is ensured that the MMU can correctly translate the virtual address to the main address of the mirrored memory.

In some embodiments, each virtual page identified by the virtual address corresponds to two adjacent physical pages. Wherein, two adjacent physical pages are, for example, the address of the last position in one physical page is adjacent to the address of the first position in another physical page. Specifically, the OS allocates a block of memory space with contiguous addresses in units of pages. In order to implement dynamic mirroring, this embodiment performs memory mirroring in units of pages. When allocating mirrored memory, memory space is allocated in units of two adjacent consecutive physical pages. For example, referring to FIG. 4, the size of a page is 4KB, the virtual page is a page identified by virtual address 0 to virtual address 4095, and the target memory space is physical page 1 identified by physical address 0 to physical address 4095, physical address 4096 to Physical page 2 identified by physical address 8191.

In some embodiments, a physical page includes one or more main memory spaces and one or more mirrored memory spaces. For example, referring to FIG. 4, physical page 1 includes both main memory space (cache line 0 main, cache line 2 main) and mirror memory space (cache line 1 mirror, cache line 3 mirror).

In some embodiments, the main memory space and the mirror memory space are interleaved in a physical page. The distance between the main memory space and the mirror memory space that are mirrored to each other in a physical page is one cache line size.

Step S303: The computing device performs operations corresponding to the memory read and write instructions on the main memory space and the mirrored memory space according to the main address and the mirrored address.

In some embodiments, memory address interleaving is enabled while the dynamic mirroring function is enabled. For example, enable 2way Channel Interleave. The mirrored memory space and the main memory space are in different channels. For example, referring to FIG. 4 , the memory space identified by the mirror address primary0 and the memory space identified by the primary address primary0 are located in different channels.

In this way, on the one hand, since the mirrored memory space and the main memory space are located in different channels, the mirrored memory space and the main memory space are physically independent of each other, and the memory controller can use multiple channels to Mirror memory space and main memory space to improve read and write performance. For example, the above memory read and write instructions are write instructions, the main memory space is located in channel 0, and the mirror memory space is located in channel 1. When the memory controller writes data to the main memory space in channel 0, it writes data to the mirror memory space in channel 1. data input. Obviously, compared to accessing the mirrored memory space and the main memory space successively through the same channel, the read and write performance is higher. On the other hand, since the mirrored memory space and the main memory space can read and write data at the same time, it is ensured that the mirrored memory space and the main memory space data are kept synchronized, and errors caused by inconsistent data saved in the mirrored memory space and the main memory space are avoided.

In some embodiments, after determining the primary address and the secondary address, the computing device determines whether the ECC space corresponding to the primary address includes mirroring indication information, and determines whether the ECC space corresponding to the mirroring address includes mirroring indication information; in response to the ECC corresponding to the primary address Both the space and the ECC space corresponding to the mirrored address include mirroring indication information, and the computing device performs operations corresponding to the memory read and write instructions on the main memory space and the mirrored memory space according to the main address and the mirrored address.

Optionally, the action of judging whether the ECC space includes mirroring indication information is specifically performed by the MC in the computing device. Specifically, when the MC receives the memory read/write command, it determines whether the memory read/write command is a mirror read/write command. If the memory read/write command is a mirror read/write command, the MC determines the mirror address, and accesses the ECC space corresponding to the main address and For the ECC space corresponding to the mirror address, the MC judges whether the ECC space corresponding to the main address and the ECC space corresponding to the mirror address both include mirror indication information. If both the ECC space corresponding to the main address and the ECC space corresponding to the mirror address include mirror indication information, the MC performs mirror read and write operations, that is, perform read data operations or write data operations on the main memory space and the mirror memory space at the same time. If the ECC space corresponding to the primary address does not include mirroring indication information, or the ECC space corresponding to the mirroring address does not include mirroring indication information, the MC determines that the access to the mirrored memory is illegal, and the MC refuses to perform mirroring read and write operations.

In some embodiments, one or more bits are enabled in the ECC space as a mirror indication information field for the MC to identify a memory space in which mirror memory is enabled. If the mirroring indication information field in the ECC space is set (that is, the ECC space includes mirroring indication information), it means that memory mirroring is enabled in the target memory space. If the mirroring indication information field in the ECC space is not set (that is, the ECC space does not include mirroring indication information), it means that memory mirroring is not enabled in the target memory space. For example, referring to FIG. 4, the primary address Pri0 is located in the cache line CacheLine0, and the mirror address Sec0 is located in the cache line CacheLine1. If the ECC space corresponding to CacheLine0 and the ECC space corresponding to CacheLine1 both include mirroring indication information, mirroring read and write operations (such as simultaneous data writing) are allowed to the memory space marked by the primary address Pri0 and the memory space marked by the mirror address Sec0.

In the method provided by this embodiment, the enabling field in the page table entry corresponding to the virtual address carries mirroring indication information, thereby indicating that mirroring protection has been enabled in the memory space identified by the virtual address. When a memory read/write command is received, if it is found that the page table entry corresponding to the virtual address carried by the memory read/write command has mirror indication information, the two memory spaces corresponding to the primary address and the standby address are both read and written, thus supporting The dynamic memory mirroring function can solve the limitations of the existing memory mirroring scheme to a certain extent.

In some embodiments, the above-mentioned processing flow of reading and writing the mirrored memory is implemented by the MMU and the MC. Specifically, the MMU is used to perform a translation process flow from a virtual address to a physical address on the dynamic mirror memory. When the MMU detects that the mirror indication information field in the page table entry corresponding to the virtual address is 1, the MMU calculates the physical address of the main memory space according to the above formula 2.

The processing flow of the MC performing mirror memory read and write includes the following steps 1 to 3.

Step 1. Reject non-"mirror read and write" commands.

Specifically, when the MC receives the memory read/write instruction sent by the MMU, the MC detects whether the content of the mirror indication information field in the ECC corresponding to the destination address of the memory read/write instruction is 1. When the mirror indication information field is 1, if the MC receives a non-mirrored read/write command, the MC refuses to execute the command and returns an illegal access, thereby ensuring that mirror-protected pages can only be used for mirror-protected operations.

Among them, the page allocated as mirrored memory, the corresponding ECC mirroring indication information is 1; the page fault interrupt function of the OS initiates the ECC mirroring indication information field setting operation when the physical page is allocated; when the physical page is released , the physical page recovery function of the OS initiates the zero-clearing operation of the mirror indication information field of the ECC. The MC identifies whether the dynamic mirroring function is enabled in the physical memory through the mirroring instruction information field of the ECC, and can distinguish between ordinary memory read and write instructions and mirrored memory read and write instructions, thus solving the problem that the MC cannot support dynamic memory mirroring.

Step 2. The MC executes normal mirror read/write commands.

The destination address in the "mirror read and write" command received by the MC is the primary address Pri_PA translated by the MMU through formula 2. The MC calculates the mirror address Sec_PA according to formula 1, and simultaneously initiates an operation (read/write) specified by the instruction to the main memory space and the mirror memory space, thereby ensuring the consistency of the main address and mirror address writing. When the mirror address Sec_PA and the primary address Pri_PA do not belong to the same channel controlled by the MC, the MC that receives the command is responsible for interacting with the MC to which the mirror address Sec_PA belongs to complete the corresponding command operation.

Step 3. If the MC encounters an error when executing the memory read/write command, follow steps 3, 4, 5, 6, and 7 in the following dynamic mirror memory fault handling process.

The above describes the processing flow of mirror memory read and write, and the following describes the dynamic mirror memory allocation processing flow.

In some embodiments, before receiving the memory read/write instruction, the computing device receives a memory allocation request for the specified object; in response to the specified object's mirroring flag being set to a set value, the computing device allocates the target memory space for the specified object.

Specified objects refer to software modules that are allowed to occupy memory space in the computer. For example, specified objects include, but are not limited to, a process, a kernel, a portion of a VMA segment of a process, a portion of a module in the kernel, and the like. A memory allocation request indicates to allocate memory space for the specified object. In some embodiments, different types of designated objects have different mirror marks. For example, the kernel's mirror flag is different from the process' mirror flag.

In some embodiments, after receiving the memory allocation request for the specified object, the computing device writes mirror indication information to the page table entry corresponding to the virtual address, the ECC space corresponding to the main address, and the ECC space corresponding to the mirror address, respectively. For example, in the process of allocating mirrored memory, the computing device uses the mirroring indication information field in the page table entry corresponding to the virtual address, the mirroring indication information field in the ECC space corresponding to the main address, and the mirroring indication in the ECC space corresponding to the mirror address. Information fields are all set to 1.

In some embodiments, the dynamic mirror memory allocation process flow is implemented by modifying the memory management module of the OS. Specifically, modify the memory allocation function of the OS memory management module. In the memory allocation function, add a module that sets the mirroring indication information of the PTE to 1 when processing mirrored memory allocation, indicating that mirroring protection is enabled for this memory space. Modify the page fault interrupt processing function of the OS memory management module, and add a module for mirroring memory allocation to physical pages in the page fault interrupt processing function. When the page fault interrupt processing function detects that the mirroring indication information of the PTE is 1, it also sets the mirroring indication information of the ECC corresponding to the actually allocated physical page to 1, so that the memory controller can identify and process according to the requirements of dynamic mirroring memory.

Exemplarily, the processing flow for allocating virtual addresses by the dynamic mirror memory allocation function includes the following steps 1 to 3.

Step 1. The OS allocates a new virtual address space for the process.

Among them, GFP_MIRROR (kernel mode) is added to the gfp allocation flag and VM_MIRROR (user mode) is added to the vma flag. GFP_MIRROR (kernel state) is a GFP allocation flag. GFP_MIRROR applies to kernel mode processes. VM_MIRROR is a VMA flag. VM_MIRROR applies to user-mode processes. Added GFP_MIRROR (kernel mode) and vma new flag VM_MIRROR (user mode) through the gfp allocation flag to solve the problem that the memory allocation function cannot support the management of memory dynamic mirroring, and support the dynamic mirroring programming interface.

When a memory allocation function such as malloc needs to add a new virtual address space, the system calls the brk or do_map function to allocate a new virtual address space.

Step 2: The OS adds a page table entry corresponding to the virtual address in the process page table.

Among them, in the unit of page, a page table entry is allocated for the newly added address space in the page table. At this time, the base address of the page is recorded in the page table entry, and the corresponding physical page base address is empty.

Step 3. The OS sets the mirroring indication information field of the newly added PTE to 1.

When the mirror indication information field is 1, the MMU calls formula 2 to correctly translate the virtual address to the main address; at the same time, the page fault interrupt handler also allocates two consecutive physical pages for this virtual address, the base of the first physical page. The address is recorded into the physical address of the page table entry.

Exemplarily, the processing flow of allocating physical pages by the dynamic mirroring memory function includes the following steps 1 to 3.

Step 1. The OS determines whether the mirror indication information field of the page table entry corresponding to the virtual address is 1.

Wherein, when the image indication information field of the page table entry is 1, indicating that the virtual address corresponds to a dynamic memory image, the OS allocates two consecutive physical pages. When the mirror indication information field of the page table entry is 0, the OS allocates a physical page according to the original process.

Step 2. The OS allocates two consecutive physical pages to the virtual address.

Specifically, two consecutive physical pages are searched in the free physical page space, and the base address of the first physical page in the two consecutive physical pages is recorded in the physical address of the page table entry corresponding to the virtual address. If there are not two contiguous physical pages, try to move the data held in some physical pages, thus constructing two contiguous physical pages, and allocate the constructed two contiguous physical pages.

Step 3. The OS sets the mirror indication information field corresponding to the ECC to 1.

The OS records the base address of the newly allocated physical page into the physical address field of the page table entry. The underlying interface is called to set the mirror indication information field of the ECC corresponding to the newly allocated physical page to 1, to ensure that the MC also manages the physical page according to the dynamic mirror memory. In addition, the allocated two physical pages are marked as reserved (Reserved) at the same time to avoid repeated allocation.

The following describes the process of reclaiming physical pages of dynamic mirrored memory. In some embodiments, a module for reclaiming physical pages of mirrored memory is added to the memory reclamation processing function of OS memory management. Specifically, the processing flow of the dynamic mirror memory recycling function includes the following steps 1 to 3.

Step 1. Determine whether the mirror indication information field of the page table entry corresponding to the virtual address is 1.

When the mirror indication information field of the page table entry is 1, indicating that dynamic memory mirroring is enabled in the memory space corresponding to the virtual address, two consecutive physical pages corresponding to the physical address field are reclaimed. When the mirror indication information field of the page table entry is 0, a physical page corresponding to the physical address field in the page table entry is reclaimed according to the original process.

Step 2. The page recycling function sets the mirror indication information field corresponding to the ECC to 0.

Specifically, the value carried by the physical address field of the corresponding page table entry is obtained according to the virtual address. The underlying interface is called to set the mirroring indication information field of the ECC of two consecutive physical pages corresponding to the physical address to 0, so as to ensure that the MC manages the physical pages according to ordinary memory.

Step 3. The page reclaim function reclaims the home page and the mirror page corresponding to the physical address.

The page recycling function clears the physical address field of the page table entry corresponding to the virtual address; puts the two physical pages back into the free page linked list for allocation.

The following describes the configuration and command flow of dynamic memory mirroring management. In some embodiments, before receiving the memory allocation request for the specified object, the method further includes: in response to the memory mirroring instruction, the computing device modifies the mirroring flag of the specified object to a set value. Among them, the memory mirroring instruction instructs to enable memory mirroring for the memory space required by the specified object. The memory mirroring instruction is triggered, for example, by the operation of the administrator. Memory mirroring instructions include the identification of the specified object. For example, in the case where the specified object is a process, the memory mirroring instruction includes the process ID (Process ID, PID) of the process. By adding a memory mirroring instruction, you can specify which objects enable memory mirroring protection, and the computer can modify the mirroring flag of the process when the process starts or runs, so as to meet the dynamic mirroring management requirements of the process.

In some embodiments, the configuration and command flow includes a kernel image protection flow and a process memory image protection flow.

The kernel image protection process refers to adding new configuration items to the existing system configuration file, or defining a new configuration file, which is used to define those parts of the kernel to enable dynamic memory image protection. During the OS startup process, image protection is allocated to the kernel according to the configuration. physical page, the process includes the following steps 1 to 3.

Step 1. The operating system starts (OS Boot) and parses the configuration about the protection of the kernel image in the configuration file.

Step 2. According to the configuration file, allocate mirrored physical pages to modules in the kernel that need mirroring protection.

Step 3. Allocate mirrored physical pages for the kernel during operation.

Among them, the mirrored physical pages are allocated for the new memory requirements of the kernel; or, when the memory fails, the faulty pages are isolated and new mirrored physical pages are allocated.

The process memory image protection process includes the following steps 1 to 3. The following mirrorable commands are the above memory mirroring commands.

Step 1. Start the process with the mirrorable command and mirror the memory of the process.

MML: #mirroable program;

mirroable sets task_struct->mirrorable to true (True), the process memory enables mirror protection, and the mirror indication information fields of the page table entries corresponding to the allocated virtual addresses are all set to 1. Call the execX() function to start the target process, the target inherits all mirror memory settings, and the subsequently allocated memory also automatically starts mirror protection.

Step 2. After the process starts, run the mirrorable command to mirror the memory of the process.

MML: #mirroable pid;

The mirroable command suspends the pid process first; modifies the pid process task_struct->mirrorable to be true (True); sets all the mirror indication information fields of the page table entries corresponding to all virtual addresses of the pid process to 1; allocates physical pages for the pid process Create a new mirrored physical page, copy the existing physical page data to the mirrored physical page, refresh the physical address corresponding to the virtual address with the physical address of the mirrored physical page; release the original unmirrored physical page; activate the pid process to continue running.

Step 3. Manage process memory mirroring through the programming interface

Check whether the current version of the operating system supports dynamic memory mirroring, and whether the CPU and MC support dynamic memory mirroring. If the operating system, CPU, and MC support dynamic memory mirroring, call the functions that support mirrored memory to apply for memory space, and the related functions automatically complete the mirroring protection page. The virtual address of the corresponding page table entry is all set to 1; Allocate and reclaim mirrored physical pages.

It should be noted that, through the mirrorable command, all memory modules of the process are mirrored, and some VMA segments of the process can also be selected for mirror protection. If a specific page needs to be protected, it can be done by the programmer through the programming interface.

In addition, if the OS can support dual kernels, you can start a memory mirror to protect the new kernel through the mirrorable command, and then hand over all the business to the new kernel for management, and release the old kernel without mirror protection, so that you can run ) switches the kernel to an image-protected state.

The following describes the processing flow of the physical page fault of the dynamic mirror memory.

During operation, the computing device isolates the mirrored memory space in response to the above-mentioned fault in the mirrored memory space; the computing device reallocates the mirrored memory space for the virtual address, and the computing device writes the data stored in the main memory space to the reallocated mirrored memory space .

For example, the computing device selects a memory space with the same capacity as the main memory space from the free and available memory space in the memory as the reallocated mirror memory space.

In addition, the computing device also tags the failed mirrored memory space. Flags are used to indicate that the mirrored memory space is in a failed state. When the computer subsequently allocates memory, it will not allocate the marked memory space, thereby avoiding problems caused when the faulty mirrored memory space is allocated. The dynamic mirror memory fault handling process includes the following steps 1 to 7.

Step 1. When the system is running normally, faults are found through automatic memory inspection, or faults are encountered when accessing memory.

Step 2: The hardware of the computing device determines the faulty page in the memory, triggers an interrupt, and proceeds to Step 3 and Step 4. Specifically, when the MC encounters an uncorrectable error (Uncorrectable Error, UCE) while executing the mirror read/write instruction, it notifies the OS through an interrupt to perform data recovery and fault page isolation.

Step 3. The computing device restores data from the normal page.

Step 4. The OS or virtual machine monitor (Virtual Machine Monitor, VMM) of the computing device isolates the fault page, proceeds to step 5, and proceeds to step 6 or step 7.

Step 5. The OS or VMM of the computing device reallocates the mirror page.

Step 6. If the number of exceptions is lower than the threshold or the available memory is higher than the threshold, the computing device generates an exception alarm.

Step 7. If the number of exceptions is higher than the threshold or the available memory is lower than the threshold, the computing device generates a fault alarm.

The interface of the dynamic mirror memory provided by this embodiment is introduced below. The interface of dynamic mirror memory includes data structure definition, user mode interface, kernel mode interface and so on. Through the application programming interface (Application Programming Interface, API) of dynamic memory mirroring, a refined dynamic memory management development interface can be provided. The following describes the API provided by this embodiment from the data structure definition, the user-mode interface, and the kernel-mode interface.

1. Data structure definition

1.1 defines the feature configuration: CONFIG_ACPI_MIRROR_MEMORY.

1.2 defines the management structure: mirror_info.

1.3 Define vm_stat reference count, new: NR_FREE_MIRROR_PAGES.

1.4 Programming interface: Added GFP_MIRROR (kernel mode) to the gfp allocation flag.

1.5 Programming interface: VM_MIRROR (user mode) is added to vma.

1.6 Non-programming interface: task_struct->mirrorable, global variable mirrorable.

2. User mode interface (programming/non-programming)

2.1 mmap(MAP_MIRROR)->vma(VM_MIRROR)->alloc_page(GFP_MIRROR).

2.2 malloc(xx)->madvise(MAP_MIRROR)->vma(VM_MIRROR)->alloc_page(GFP_MIRRO R).

2.3 syscall->task_struct->mirrorable.

2.4 The new command mirrorable is used to modify the mirror configuration at runtime: /proc/pid/mirrorable.

3. Kernel mode interface (programming/non-programming)

3.1 alloc_page(GFP_MIRROR);

3.2 /proc/sys/vm/mirrorable->global variable mirrorable.

In this embodiment, by providing the above-mentioned dynamic memory mirroring programming interface, dynamic memory mirroring in units of pages can be implemented.

FIG. 5 is a schematic structural diagram of a device for executing a memory read/write instruction provided by an embodiment of the present application. The apparatus 500 shown in FIG. 5 , for example, implements the functions of the computing device in the method shown in FIG. 3 .

Referring to FIG. 5 , the apparatus 500 includes a receiving unit 501 , a determining unit 502 and a reading and writing unit 503 . Each unit in the apparatus 500 is implemented in whole or in part by software, hardware, firmware or any combination thereof. The receiving unit 501 is configured to support the apparatus 500 to execute S301. The determining unit 502 is configured to support the apparatus 500 to perform S302. The read/write unit 503 is used to support the device 500 to execute S303.

Optionally, the apparatus 500 further includes an allocation unit configured to support the apparatus 500 to perform the step of allocating memory space.

Optionally, the read-write unit 503 is further configured to support the apparatus 500 to perform the steps of writing the mirroring indication information and modifying the mirroring flag of the specified object to a set value.

Optionally, the apparatus 500 further includes an isolation unit configured to support the apparatus 500 to perform the step of isolating the faulty memory space.

The apparatus embodiment described in FIG. 5 is only schematic, for example, the division of the above-mentioned units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components may be combined or Integration into another system, or some features can be ignored, or not implemented. Each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned units in FIG. 5 can be implemented in the form of hardware, and can also be implemented in the form of software functional units. For example, when implemented in software, the above determination unit 502 and read/write unit 503 may be implemented by software functional units generated after the processor 101 or the processor 105 in FIG. 1 reads the program code stored in the memory 102 . The above units in FIG. 5 can also be implemented by different hardware in the computing device, for example, the determination unit 502 is determined by a part of the processing resources (for example, one core or two of the multi-core processors 101 in the at least one processor 101 in FIG. 1 ). The read/write unit 503 is implemented by the rest of the processing resources in the processor 101 in FIG. 1 (such as other cores in the multi-core processor), or by using a field-programmable gate array (FPGA, FPGA). ), or programmable devices such as coprocessors. The receiving unit 501 is realized by the network interface 103 in FIG. 1 . Obviously, the above-mentioned functional units can also be realized by a combination of software and hardware. For example, the determination unit 502 is realized by a hardware programmable device, and the read-write unit 503 is a software functional unit generated after the CPU reads the program code stored in the memory. .

In the embodiments of the present application, unless otherwise specified, the meaning of "at least one" refers to one or more.

The above-described embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented in whole or in part in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present application are generated in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable device. Computer instructions may be stored on or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server, or data center over a wire (e.g. coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.) to another website site, computer, server, or data center. A computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that includes an integration of one or more available media. Useful media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)), among others.

Above, the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the above-mentioned embodiments, those of ordinary skill in the art should understand that: it can still be used for the above-mentioned implementations The technical solutions described in the examples are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

A method for executing memory read and write instructions, wherein the method comprises:

receiving a memory read and write instruction, where the memory read and write instruction carries the virtual address of the target memory space;

In response to the page table entry corresponding to the virtual address including mirroring indication information, the main address and the mirroring address are determined according to the virtual address, the mirroring indication information being used to identify that the target memory space has enabled memory mirroring, and the main address is is the physical address of the main memory space in the target memory space, and the mirrored address is the physical address of the mirrored memory space in the target memory space;

According to the main address and the mirror address, an operation corresponding to the memory read/write instruction is performed on the main memory space and the mirror memory space.
The method according to claim 1, wherein the mirrored memory space and the main memory space are located in different channels.
The method according to claim 1 or 2, wherein the mirrored memory space is separated from the main memory space by a distance of at least one cache line size.
The method according to any one of claims 1 to 3, wherein the offset address included in the main address is determined according to the size of the cache line and the offset address included in the virtual address.
The method according to any one of claims 1 to 4, wherein the memory read/write is performed on the main memory space and the mirrored memory space according to the main address and the mirrored address The operations corresponding to the instructions, including:

In response to the error checking and correction ECC space corresponding to the main address and the ECC space corresponding to the mirror address including the mirror indication information, according to the main address and the mirror address, the main memory space and the mirror address are compared. The mirrored memory space executes operations corresponding to the memory read and write instructions.
The method according to any one of claims 1 to 5, wherein before the receiving a memory read and write instruction, the method further comprises:

Receive a memory allocation request for the specified object;

Allocate the target memory space for the specified object in response to the mirroring flag of the specified object being set to a set value;

Wherein, when the mirror flag is set to a set value, it indicates to allocate a memory space including a main memory space and a mirror memory space for the specified object.
The method according to claim 6, wherein after receiving the memory allocation request of the specified object, the method further comprises:

The mirroring indication information is written into the page table entry corresponding to the virtual address, the ECC space corresponding to the main address, and the ECC space corresponding to the mirroring address, respectively.
The method according to claim 6 or 7, wherein before the receiving a memory allocation request for the specified object, the method further comprises:

In response to a memory mirroring instruction, the mirroring flag of the specified object is modified to the set value, the memory mirroring instruction instructing to enable memory mirroring for the memory space required by the specified object.
The method according to any one of claims 1 to 8, wherein each virtual page identified by the virtual address corresponds to two adjacent physical pages.
The method according to any one of claims 1 to 9, wherein the method further comprises:

In response to the mirrored memory space failing, isolating the mirrored memory space;

The mirrored memory space is reallocated for the virtual address, and the data stored in the main memory space is written into the reallocated mirrored memory space.
A device for executing memory read and write instructions, wherein the device comprises:

a receiving unit, configured to receive a memory read/write instruction, where the memory read/write instruction carries a virtual address of the target memory space;

a determining unit, configured to determine a main address and a mirror address according to the virtual address in response to the page table entry corresponding to the virtual address including mirroring indication information, where the mirroring indication information is used to identify that memory mirroring has been enabled in the target memory space , the main address is the physical address of the main memory space in the target memory space, and the mirror address is the physical address of the mirrored memory space in the target memory space;

A read-write unit, configured to perform an operation corresponding to the memory read-write instruction on the main memory space and the mirrored memory space according to the main address and the mirror address.
The apparatus according to claim 11, wherein the mirrored memory space and the main memory space are located in different channels.
The apparatus according to claim 11 or 12, wherein the mirrored memory space is separated from the main memory space by a distance of at least one cache line size.
The apparatus according to any one of claims 11 to 13, wherein the offset address included in the main address is determined according to the size of the cache line and the offset address included in the virtual address.
The device according to any one of claims 11 to 14, wherein the read-write unit is configured to check and correct the ECC space corresponding to the main address and the ECC space corresponding to the mirror address in response to the error Both include the mirroring indication information, and according to the main address and the mirroring address, perform operations corresponding to the memory read and write instructions on the main memory space and the mirrored memory space.
The device according to any one of claims 11 to 15, wherein the receiving unit is further configured to receive a memory allocation request for a specified object;

The device also includes: an allocation unit configured to allocate the target memory space for the specified object in response to the mirroring flag of the specified object being set to a set value;

Wherein, when the mirror flag is set to a set value, it indicates to allocate a memory space including a main memory space and a mirror memory space for the specified object.
The device according to claim 16, wherein the read/write unit is further configured to send a page table entry corresponding to the virtual address, an ECC space corresponding to the main address, and an ECC space corresponding to the mirror address Write the mirroring indication information respectively.
The device according to claim 16 or 17, wherein the read-write unit is further configured to, in response to a memory mirroring instruction, modify the mirroring flag of the specified object to the set value, and the memory mirroring The instructions instruct to enable memory mirroring for the memory space required by the specified object.
The apparatus according to any one of claims 11 to 18, wherein each virtual page identified by the virtual address corresponds to two adjacent physical pages.
The device according to any one of claims 11 to 19, characterized in that:

an isolation unit, configured to isolate the mirrored memory space in response to a failure of the mirrored memory space;

The apparatus further includes: an allocation unit, configured to reallocate a mirrored memory space for the virtual address, and the read-write unit, further configured to write the data stored in the main memory space into the reallocated mirrored memory space.
A computing device, characterized in that the computing device comprises a processor and a memory, the memory stores at least one piece of program code, and the program code is loaded and executed by the processor to implement claims 1 to 6 The method of any one of Claims 10.
A computing device, characterized in that the computing device comprises a memory management unit MMU, a memory controller MC and a memory;

The MMU is configured to receive memory read and write instructions, where the memory read and write instructions carry the virtual address of the target memory space;

The MMU is further configured to determine the main address and the mirror address according to the virtual address in response to the page table entry corresponding to the virtual address including mirror indication information, where the mirror indication information is used to identify that the target memory space is enabled memory mirroring, the main address is the physical address of the main memory space in the target memory space, and the mirroring address is the physical address of the mirrored memory space in the target memory space;

The MC is configured to, according to the main address and the mirror address, perform operations corresponding to the memory read and write instructions on the main memory space in the memory and the mirror memory space in the memory.
A computer-readable storage medium, wherein at least one piece of program code is stored in the storage medium, and the program code is loaded and executed by a processor to implement the method according to any one of claims 1 to 10. method.