WO2011073466A1 - Modular converter based on multi-level distributed circuits with a capacitive mid-point - Google Patents

Modular converter based on multi-level distributed circuits with a capacitive mid-point Download PDF

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Publication number
WO2011073466A1
WO2011073466A1 PCT/ES2009/070606 ES2009070606W WO2011073466A1 WO 2011073466 A1 WO2011073466 A1 WO 2011073466A1 ES 2009070606 W ES2009070606 W ES 2009070606W WO 2011073466 A1 WO2011073466 A1 WO 2011073466A1
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WO
WIPO (PCT)
Prior art keywords
switches
subsystem
switch
junction
capacities
Prior art date
Application number
PCT/ES2009/070606
Other languages
Spanish (es)
French (fr)
Inventor
Sergio Aurtenetxea Larrinaga
Igor Larrazabal Bengoetxea
Josu Elorriaga Llanos
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Ingeteam Technology, S.A.
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Application filed by Ingeteam Technology, S.A. filed Critical Ingeteam Technology, S.A.
Priority to PCT/ES2009/070606 priority Critical patent/WO2011073466A1/en
Publication of WO2011073466A1 publication Critical patent/WO2011073466A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/49—Combination of the output voltage waveforms of a plurality of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4837—Flying capacitor converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters

Definitions

  • the object of this invention is to define a modular converter circuit composed of at least one phase module that integrates an upper and lower part or assembly containing at least one upper and lower subsystem respectively, based on a multilevel electrical circuit with midpoint capacitive linked by diodes.
  • the upper assembly is connected at one of its ends to a positive conductor or pole and the other to the alternating current phase or central point of the phase module.
  • the lower assembly is arranged symmetrically to the alternating current phase or central point of the phase module and the other end is connected to a negative conductor or pole.
  • the potential between the positive and negative poles establishes the continuous voltage of the phase module of the converter circuit.
  • the generic type modular converter has been raised in various patents such as DE 101 03 031 A1, US 7577008 B2, WO 2009115124 A1 and in recent international publications such as (The Future of High Power Electronics in Transmission and Distribution Power Systems, Col ⁇ n C Davison and Bryan de Préville, EPE2009 - Barcelona).
  • the simplified general circuit of a phase module (100) is shown in Figure 1.
  • the conversion structure is based on a set or upper part (95) and a set or lower part (96) that they integrate one or several upper (90) and lower (91) subsystems arranged in series.
  • the upper assembly (95) is connected at one of its ends to a positive conductor or pole (P) and in the other to the alternating current phase (L) or center point of the phase module.
  • the lower assembly (96) is arranged symmetrically to the alternating current phase (L) or central point of the phase module and the other end is connected to a negative conductor or pole (N).
  • the use of electromagnetic elements (30) that facilitate the connection of the upper and lower assemblies (95, 96) to points (P), (N) and (L) can optionally be contemplated.
  • the potential between both poles (PN) establishes the continuous voltage of the phase module (100) of the converter circuit.
  • the connection of several phases (100) in parallel allows to develop more complex converter circuits such as the three-phase converter of Figure 2.
  • the subsystems (90, 91) known in accordance with the prior art are usually based on semiconductor devices of the IGBT (Insulated Gate Bipolar Transistors) type, MOS field effect transistors (MOSFETs), GTO thyristors, integrated gate switched thyristors (IGCTs) ), etc. all of which have the ability to be controlled both on and off.
  • IGBT Insulated Gate Bipolar Transistors
  • MOSFETs MOS field effect transistors
  • GTO thyristors GTO thyristors
  • IGCTs integrated gate switched thyristors
  • These subsystems comprise two switches (1, 3) and (5, 7) connected in series and based on semiconductors that can be controlled both in its on and off, two diodes (2, 4) and (6, 8) electrically connected in Antiparalle it with each switch (1, 3) and (5, 7) and a unipolar capacity (9) and (10) arranged in parallel with the serial switches (1, 3) and (5, 7) respectively.
  • the unipolar storage capacity (9) and (10) of each of these subsystems may be composed of one or a set of capacitors that provide a given capacity. The interconnection of this subsystem is done through the terminals (y1 and y2).
  • the terminal (y1) is connected to the emitter of the switches (1 and 5) and the anode of the diodes (2 and 6) in the subsystems (1 1 and 12) respectively.
  • the terminal (y2) is connected to the collector of the switches (1 and 5) and the cathode of the diodes (2 and 6) in the subsystems (1 1 and 12) respectively. It should be noted that this interconnection does not have to be done in this way.
  • WO 20091 15124 A1 the same electrical diagrams of the subsystems (1 1 and 12) are used but alternative connections are proposed, defining other structures for the general converter circuit.
  • control I and I I have two states or modes of operation called control I and I I:
  • switches (1) or (5) are on and the respective complementary switches (3) or (7) are off.
  • the voltage or potential (Uy21) between the terminals (y2, y1) of the subsystems (1 1 and 12) is equal to 0.
  • the subsystem (13) of Figure 4 consists of four switches based on semiconductor devices (21, 23, 25 and 27) that can be controlled both on and off, four diodes (22, 24, 26 and 28) , two unipolar capacities (29 and 30) and an electronic circuit (32).
  • the four switches (21, 23, 25 and 27) are electrically connected in series.
  • Each of the diodes (22, 24, 26 and 28) is electrically connected in antiparallel with each of these switches (21, 23, 25 and 27).
  • the unipolar capacities (29 or 30) are electrically connected in parallel with each pair of switches (21, 23 or 25, 27) respectively.
  • the unipolar capacities (29 or 30) of this subsystem (13) can be composed of one or a set of capacitors that provide a given capacity.
  • the terminal (y2) of the subsystem (13) is connected at the junction between the emitter and collector of the switches (21 and 23) and the anode and cathode of the diodes (22 and 24).
  • the terminal (y1) of the subsystem (13) is connected at the junction between the emitter and collector of the switches (25 and 27) and the anode and cathode of the diodes (26 and 28).
  • the junction between the emitter of the switch (23), the collector of the switch (25), the anode of the diode (24), the cathode of the diode (26), the negative terminal of the unipolar capacity (29) and the terminal Positive unipolar capacity (30) defines a common potential (P0), which is electrically connected to a potential (M) used as a reference by the electronic module (32).
  • P0 common potential
  • M potential
  • the electronic circuits that are part of this module are at a suitable potential to act on the switches (21, 23, 25 and 27).
  • This electronic module (32) is linked to a higher control that governs the converter circuit by means of two optical fibers (34 and 36).
  • control I The subsystem (13) of Figure 4 has four states or modes of operation called control I, I I, I I I and IV:
  • the diodes (22, 24, 26 and 28) are electrically connected in antiparallel with each switch (21, 23, 25 and 27).
  • the respective unipolar capacities (29 and 30) are electrically connected in parallel with each pair of switches respectively.
  • the junction between the emitter of the switch (23), the anode of the diode (24) and the negative terminal of the unipolar capacity (29) is electrically connected between the junction of the emitter and collector of the switches (25 and 27). This junction forms a common potential (P0), which is considered as a reference potential for the terminal (M) of the electronic module (32).
  • the junction between the emitter of the switch (27), the anode of the diode (28) and the negative terminal of the unipolar capacity (30) is connected to the terminal (y1) of the subsystem (14).
  • the junction between the emitter and collector of the switches (21 and 23), the anode of the diode (22) and the cathode of the diode (24) establishes the terminal (y2) of the subsystem (14).
  • this subsystem (14) remains equivalent to subsystem (13) and functionally amounts to the serial connection of the two subsystems (1 1) in DE 101 03 031 A1.
  • Figure 6 shows a third subsystem mode where, unlike the subsystem (14), the connection between the emitter and collector of the switches (21 and 23) electrically connected in series is performed between the collector of the switch (25), the diode cathode (26) and the positive terminal of unipolar capacity (30).
  • the connection between the emitter and collector of the two switches (25 and 27) electrically connected in series now constitutes the connection terminal (y1), while the connection between the switch collector (21), the cathode of the diode (22) and the positive terminal of the unipolar capacity (29) constitutes the connection terminal (y2) of this subsystem (15).
  • this new subsystem (15) remains similar to subsystem (13) and functionally amounts to serial connection of the two subsystems (12) proposed in DE 101 03 031 A1.
  • Figure 7 shows a fourth subsystem modality related to Figures 5 and 6.
  • the switch pairs (21, 23) and (25, 27) are electrically connected in series and each of the diodes (22, 24, 26, 28) are arranged in antiparallel with these switches (21, 23, 25, 27) respectively.
  • Each of the unipolar capacities (29 and 30) is electrically connected in parallel with each pair of switches (21, 23) and (25, 27).
  • the connection between the transmitter and collector of the switches (21 and 23) is linked to the connection between the transmitter and collector of the switches (25 and 27).
  • the junction between the switch collector (21), the cathode of the diode (22) and the positive terminal of the unipolar capacity (29) establishes the connection terminal (y2) of the subsystem (16).
  • the junction between the emitter of the switch (27), the anode of the diode (28) and the negative terminal of the unipolar capacity (30) establishes the terminal (y1) of the subsystem (16).
  • the operation of the subsystem (16) remains equivalent to that detailed for the subsystem (13).
  • this subsystem (16) is equivalent to the serial connection of the subsystem (12) with the subsystem (1 1) proposed in DE 101 03 031 A1.
  • Each of the diodes (42, 44, 46 and 48) is electrically arranged in antiparallel with each of these switches (41, 43, 45 and 47).
  • the unipolar capacity (49) is electrically connected in parallel with each pair of switches (21, 23) and (25, 27).
  • control I I I, I I I and IV:
  • Control I I I the switches (23 and 25) are on and the switches (21 and 27) off.
  • the resulting voltage (Uy21) at the terminals (y2, y1) of the subsystem (17) is equal to zero.
  • the object of this invention is a converter circuit comprising novel two-terminal subsystems that simplify the size and complexity of the converter.
  • a diode may comprise several diodes or a switch based on semiconductor devices may comprise a combination of switches.
  • the invention relates to a converter circuit composed of at least one phase module comprising an upper and lower part or assembly, each of which is formed by at least one subsystem of two upper and lower terminals respectively.
  • the upper assembly is connected at one of its ends to a positive conductor or pole and the other to the alternating current phase or central point of the phase module.
  • the lower assembly is arranged symmetrically to the alternating current phase or central point of the phase module and the other end is connected to a negative conductor or pole.
  • the potential between the positive and negative pole sets the continuous voltage of the phase module of the converter circuit.
  • the first group of subsystems proposed in this invention is characterized by an electrical circuit consisting of four switches based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes, each connected electrically in antiparallel with each switch, two unipolar storage capacities electrically connected in series with each other and in parallel with the four switches and two additional link or clamp diodes called first diode and second diode.
  • the cathode of the first link diode is connected at the junction between the emitter and collector of the two upper switches and the anode at the junction between the capacities arranged in series.
  • the anode of the second link diode is connected between the junction between the emitter and collector of the two lower switches and the cathode at the junction between the capacities arranged in series.
  • the unipolar capabilities of this subsystem can be composed of one or a set of capacitors that provide a certain total capacity.
  • each of the proposed subsystems integrates an electronic management system correctly associated with its reference potential that allows the correct operation of the subsystem and its communication with one or more higher order control systems.
  • the second group of subsystems proposed in this invention is characterized by an electrical circuit consisting of four switches based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes, each connected electrically in antiparallel with each switch, two unipolar storage capacities electrically connected in series with each other and in parallel with the four switches and two additional link or clamp switches, called first link switch and second link switch, each with its respective diode in antiparallel.
  • the collector of the first link switch connects the junction between the emitter and collector of the two upper switches while its emitter is connected at the junction between the capacities arranged in series.
  • the emitter of the second link switch connects the junction between the emitter and collector of the two lower switches while its collector is connected at the junction between the capacities arranged in series.
  • the unipolar capabilities of the subsystem can be composed of one or a set of capacitors that provide a given total capacity.
  • each of the proposed subsystems integrates an electronic management system correctly associated with its reference potential that allows the correct operation of the subsystem and its communication with one or more higher order control systems.
  • the third group of subsystems proposed in this invention is characterized by an electrical circuit consisting of four switches based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes, each connected electrically in antiparallel with each switch, two unipolar storage capacities electrically connected in series with each other and in parallel with the four switches and a first and second additional link or clamp switches oppositely connected in series with their respective antiparallel diodes.
  • the collector of the first link switch connects the junction between the emitter and collector of the two central switches while its emitter is connected to the emitter of the second link switch.
  • the collector of this second link switch is connected between the capacities arranged in series by means of its collector.
  • the unipolar capabilities of the subsystem may be composed of one or a set of capacitors that provide a given total capacity.
  • each of the proposed subsystems integrates an electronic management system correctly associated with its reference potential that allows the correct operation of the subsystem and its communication with one or more higher order control systems.
  • the fourth group of subsystems proposed in this invention is characterized by an electrical circuit consisting of four switches based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes, each electrically connected in antiparallel with each switch, two capacities of Unipolar storage electrically connected in series with each other and in parallel with the four switches and an additional floating capacity that is connected in parallel with the central switches.
  • the unipolar capabilities of the subsystem may be composed of one or a set of capacitors that provide a given total capacity.
  • each of the proposed subsystems integrates an electronic management system correctly associated with its reference potential that allows the correct operation of the subsystem and its communication with one or more higher order control systems.
  • the set of subsystems that integrate the upper and lower part of the phase module into the four proposed configurations differ in the location of the electrical circuit connection terminals.
  • the connection between the central switches and the emitter of the lower switch respectively defines each of the two terminals of the upper subsystem and the collector of the upper switch and the connection between the two central switches defines each of the two terminals of the lower subsystem.
  • the location of these terminals can also be made between the central switches and the capacitive midpoint, resulting in a compatible subsystem for both the top and bottom.
  • Figure 1 shows the general diagram of a phase of a converter circuit composed of a set of N distributed subsystems
  • Figure 2 shows a three-phase converter circuit composed of a set of N distributed subsystems
  • FIGS. 3a, 3b, 4, 5, 6, 7, 8 show the known electrical circuits for distributed subsystems
  • Figures 9a, 9b, 10a, 10b, 1 1 a, 1 1 b, 12a and 12b detail the multi-level electrical capacitive mid-circuit circuit sets proposed in this invention for distributed subsystems.
  • Figures 9a and 9b show in detail a first set of electrical diagrams proposed in this invention for the subsystems (90 and 91) corresponding to the converter circuit, consisting of at least one phase module (100) that integrates an upper part or assembly (95 ) and a lower part or assembly (96) formed at least by a subsystem of two upper terminals (90) and a lower one (91) respectively.
  • the upper assembly (95) is connected at one of its ends to a positive conductor or pole (P) and in the other to the alternating current phase (L) or center point of the phase module.
  • the Lower assembly (96) is arranged symmetrically to the alternating current phase (L) or center point of the phase module and the other end is connected to a negative conductor or pole (N).
  • Figure 9a are characterized by an electrical circuit consisting of four switches (57, 55, 53 and 51) based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes (58 , 56, 54 and 52), each electrically connected in antiparallel with each switch (57, 55, 53 and 51), two unipolar storage capacities (76 and 75) electrically connected in series with each other and in parallel with the four switches (57, 55, 53 and 51) and two additional link or clamp diodes (70a and 68a).
  • the diode cathode (70a) is connected between the switch emitter junction (57) and the switch manifold (55) and the anode at the junction (Po) between the capacities (76 and 75).
  • This junction point between both capacities (76 and 75) is defined as (Po) or capacitive midpoint.
  • the diode anode (68a) is connected between the switch emitter junction (53) and the switch manifold (51) and the cathode in the junction (Po) between the capacities (76 and 75).
  • the positive capacity terminal (76) is connected to the switch manifold (57) and the negative capacity terminal (75) is connected to the emitter of the switch (51).
  • the terminal (y2) is connected at the junction between the switch emitter (55), the switch manifold (53), the diode anode (56) and the diode cathode (54) .
  • the terminal (y1) is connected at the junction between the emitter of the switch (51), the negative terminal of the unipolar capacity (75) and the anode of the diode (52).
  • each of the lower subsystems (91) detailed in Figure 9b is characterized by an electrical circuit consisting of four switches (59, 61, 63 and 65) based on semiconductor devices, which can be controlled both when switched on as in the shutdown and four diodes (60, 62, 64 and 66) are connected electrically in series, each electrically connected in antiparallel with each switch (59, 61, 63 and 65), two unipolar storage capacities (77 and 78) electrically connected in series with each other and in parallel with the four switches (59, 61, 63 and 65) and two additional link or clamp diodes (72a and 74a).
  • the diode cathode (72a) is connected between the switch emitter junction (59) and the switch manifold (61) and the anode at the junction (Po) between the capacities (77 and 78).
  • the anode of the diode (74a) is connected between the switch emitter junction (63) and the switch manifold (65) and the cathode in the junction (Po) between the capacities (77 and 78).
  • This junction point between both capacities (77 and 78) is defined as (Po) or capacitive midpoint.
  • the positive capacity terminal (77) is connected to the switch manifold (59) and the negative capacity terminal (78) is connected to the emitter of the switch (65).
  • the terminal (y2) is connected at the junction between the switch collector (59), the positive terminal of the unipolar capacity (77) and the diode cathode (60).
  • the terminal (y1) is connected at the junction between the emitter of the switch (61), the collector of the switch (63), the anode of the diode (62) and the cathode of the diode (64).
  • the unipolar capacities of both subsystems (76, 75) and (77, 78) may be composed of one or a set of capacitors that provide a given total capacity.
  • each of the proposed subsystems (90 and 91) integrates an electronic management system (80 and 81) correctly associated with its reference potential (Po) that allows the correct operation of the subsystem and its communication (83 and 84) ( 85 and 86) with one or more higher order control systems.
  • This communication (83 and 84) (85 and 86) can be performed using optical fibers or other technologies that allow isolation and proper functionality between the subsystems and the upper control devices.
  • the electrical circuits that are part of the subsystems (90 and 91) detailed in Figures 9a and 9b have the following states or modes of operation:
  • switches (53 and 55) or (61 and 63) are on, while switches (51 and 57) or (59 and 65) are off.
  • the voltage or potential (UC) corresponding to that of the capacity (75) or (77) between the terminals (y2, y1) of the subsystems (90 and 91) respectively is established.
  • the capacities (76 and 75) or (77 and 78) receive or release energy depending on the direction of the current flowing through the subsystem terminals
  • Each of the upper subsystems (90) detailed in Figure 10a is characterized by an electrical circuit consisting of four switches (57, 55, 53 and 51) based on semiconductor devices, which can be controlled both on and off. and four diodes (58, 56, 54 and 52) are electrically connected in series, each electrically connected in antiparallel with each switch (57, 55, 53 and 51), two unipolar storage capacities (76 and 75) connected electrically in series with each other and in parallel with the four switches (57, 55, 53 and 51) and some first and second additional link or clamp switches (69b and 67b) with their respective antiparallel diodes (70b and 68b).
  • the junction between the diode cathode (70b) and the switch manifold (69b) is connected between the switch emitter junction (57) and the switch manifold (55) and the junction between the diode anode (70b) and the emitter of the switch (69b) at the junction (Po) between the capacities (76 and 75).
  • This junction point between both capacities (76 and 75) is defined as (Po) or capacitive midpoint.
  • the junction between the diode anode (68b) and the switch emitter (67b) is connected between the switch emitter junction (53) and the switch manifold (51) and the junction between the diode cathode (68b) and the switch manifold (67b) at the junction (Po) between the capacities (76 and 75).
  • the positive capacity terminal (76) is connected to the switch manifold (57) and the negative capacity terminal (75) is connected to the emitter of the switch (51).
  • the terminal (y2) is connects at the junction between the emitter of the switch (55), the collector of the switch (53), the anode of the diode (56) and the cathode of the diode (54).
  • the terminal (y1) is connected at the junction between the emitter of the switch (51), the negative terminal of the unipolar capacity (75) and the anode of the diode (52).
  • each of the lower subsystems (91) detailed in Figure 10b are characterized by an electrical circuit consisting of four switches (59, 61, 63 and 65) based on semiconductor devices, which can be controlled both in their ignition as in the shutdown and four diodes (60, 62, 64 and 66) are connected electrically in series, each electrically connected in antiparallel with each switch (59, 61, 63 and 65), two unipolar storage capacities (77 and 78) electrically connected in series with each other and in parallel with the four switches (59, 61, 63 and 65) and two additional link or clamp switches (71 b and 73b) with their respective diodes in antiparallel (72b and 74b).
  • junction between the diode cathode (72b) and the switch manifold (71 b) is connected between the switch emitter junction (59) and the switch manifold (61) and the junction between the diode anode (72) and the emitter of the switch (71 b) on the junction (Po) between the capacities (77 and 78).
  • This junction point between both capacities (77 and 78) is defined as (Po) or capacitive midpoint.
  • the junction between the anode of the diode (74b) and the emitter of the switch (73b) is connected between the junction of the emitter of the switch (63) and the collector of the switch (65) and the junction between the cathode of the diode (74b) and the switch manifold (73b) at the junction (Po) between the capacities (77 and 78).
  • the positive capacity terminal (77) is connected to the switch manifold (59) and the negative capacity terminal (78) is connected to the emitter of the switch (65).
  • the terminal (y2) is connected at the junction between the switch collector (59), the positive terminal of the unipolar capacity (77) and the diode cathode (60).
  • the terminal (y1) is connects at the junction between the emitter of the switch (61), the collector of the switch (63), the anode of the diode (62) and the cathode of the diode (64).
  • each of the proposed subsystems (90 and 91) integrates an electronic management system (80 and 81) correctly associated with its reference potential (Po) that allows the correct operation of the subsystem and its communication (83 and 84 ) (85 and 86) with one or more higher order control systems.
  • This communication (83 and 84) (85 and 86) can be performed using optical fibers or other technologies that allow isolation and proper functionality between the subsystems and the upper control devices.
  • - Control III the switches (51, 55 and 69b) or (59, 63 and 73b) are on, while the switches (53, 57 and 67b) or (61, 65 and 71 b) are off.
  • - Control IV the switches (55 and 69) or (63 and 73) are on, while the switches (51, 53, 57 and 67b) or (59, 61, 65 and 71 b) are off.
  • switches (55, 57 and 67b) or (63, 65 and 71 b) are on and switches (51, 53 and 69b) or (59, 61 and 73b) are off.
  • the resulting voltage (Uy21) at the terminals (y2, y1) of the subsystems (90 and 91) corresponds to the sum of the voltages or potentials (UC) of each of the capacities (76 and 75) or (77 and 78 ) respectively.
  • control states II, III, IV, V and VI the energy store formed by the capacities (76 and 75) or (77 and 78) receives or releases energy depending on the direction of the current flowing through of the subsystem terminals.
  • the energy in the capacities (76 and 75) or (77 and 78) remains constant.
  • FIGs 1 1 a and 1 1 b show in detail a third set of electrical diagrams proposed in this invention for the subsystems (90 and 91) corresponding to the converter circuit specified initially.
  • Each of the upper subsystems (90) detailed in Figure 1 1 a are characterized by an electrical circuit consisting of four switches (57, 55, 53 and 51) based on semiconductor devices, which can be controlled both on and on the shutdown and are connected electrically in series, four diodes (58, 56, 54 and 52), each electrically connected in antiparallel with each switch (57, 55, 53 and 51), two unipolar storage capacities (76 and 75) electrically connected in series with each other and in parallel with the four switches (57, 55, 53 and 51) and two additional link or clamp switches (67c and 69c) arranged opposite in series with their respective antiparallel diodes (70c and 68c).
  • the junction between the diode cathode (70c) and the switch manifold (67c) is connected between the switch emitter junction (55) and the switch manifold (53) and the junction between the diode anode (70c) and the emitter of the switch (67c) at the junction between the anode of the diode (68c) and the emitter of the switch (69c).
  • the junction between the diode cathode (68c) and the switch manifold (69c) is connected at the junction (Po) between the capacities (76 and 75). This link point between both capacities (76 and 75) is defined as (Po) or capacitive midpoint.
  • the positive capacity terminal (76) is connected to the switch manifold (57) and the negative capacity terminal (75) is connected to the emitter of the switch (51).
  • the terminal (y2) is connected at the junction between the switch emitter (55), the switch manifold (53), the switch manifold (67c), the diode anode (56), diode cathode (70c) and diode cathode (54).
  • the terminal (y1) is connected at the junction between the emitter of the switch (51), the negative terminal of the unipolar capacity (75) and the anode of the diode (52).
  • each of the lower subsystems (91) detailed in Figure 1 1 b is characterized by an electrical circuit consisting of four switches (59, 61, 63 and 65) based on semiconductor devices, which can be controlled both in their ignition as in the off and four diodes (60, 62, 64 and 66) are connected electrically in series, each electrically connected in antiparallel with each switch (59, 61, 63 and 65), two unipolar storage capacities (77 and 78) connected electrically in series with each other and in parallel with the four switches (59, 61, 63 and 65) and two additional link or clamp switches (71 c and 73c) arranged opposite in series with their respective antiparallel diodes (72c and 74c).
  • the junction between the diode cathode (72c) and the switch manifold (71 c) is connected between the switch emitter junction (61) and the switch manifold (63) and the junction between the diode anode (72c) and the emitter of the switch (71 c) is connected at the junction between the anode of the diode (74c) and the emitter of the switch (73c).
  • the junction of the switch manifold (73c) and the diode cathode (74c) is connected at the junction (Po) between the capacities (77 and 78). This link point between both capacities (77 and 78) is defined as (Po) or capacitive midpoint.
  • the positive capacity terminal (77) is connected to the switch manifold (59) and the negative capacity terminal (78) is connected to the emitter of the switch (65).
  • the terminal (y2) is connected at the junction between the switch manifold (59), the positive terminal of the unipolar capacity (77) and the diode cathode (60 ).
  • the terminal (y1) is connected at the junction between the emitter of the switch (61), the collector of the switch (63), the collector of the switch (71 c), the anode of the diode (62), the cathode of the diode (72c ) and the cathode of the diode (64).
  • the unipolar capacities of both subsystems (76, 75) and (77, 78) represented in Figures 1 1 a and 1 1 b may be composed of one or a set of capacitors that provide a certain total capacity.
  • each of the proposed subsystems (90 and 91) integrates an electronic management system (80 and 81) correctly associated with its reference potential (Po) that allows the correct operation of the subsystem and its communication (83 and 84 ) (85 and 86) with one or more higher order control systems.
  • This communication (83 and 84) (85 and 86) can be done using optical fibers or other technologies that allow isolation and proper functionality between subsystems and superior control devices.
  • the electrical circuits that are part of the subsystems (90 and 91) detailed in Figures 1 1 a and 1 1 b have essentially three operating states:
  • the switches (55 and 57) or (63 and 65) are on and the switches (51, 53, 67c and 69c) or (59, 61, 71 c and 73c) off.
  • the resulting voltage (Uy21) at the terminals (y2, y1) of the subsystems (90 and 91) corresponds to the sum of the voltages or potentials (UC) of each of the capacities (76 and 75) or (77 and 78 ) respectively.
  • the energy store formed by the capacities (76 and 75) or (77 and 78) receives or releases energy depending on the direction of the current flowing through the terminals of the subsystem .
  • FIGS. 12a and 12b show in detail a fourth set of electrical diagrams proposed in this invention for the subsystems (90 and 91) corresponding to the initially specified converter circuit.
  • Each of the upper subsystems (90) detailed in Figure 12a is characterized by an electrical circuit consisting of four switches (57, 55, 53 and 51) based on semiconductor devices, which can be controlled both on and off.
  • diodes 58, 56, 54 and 52 are electrically connected in series, each electrically connected in antiparallel with each switch (57, 55, 53 and 51), two unipolar storage capacities (76 and 75) connected electrically in series with each other and in parallel with the four switches (57, 55, 53 and 51) and an additional floating capacity (74d) arranged in parallel with the switches (55 and 53).
  • the positive capacity terminal (76) is connected to the switch manifold (57) and the negative capacity terminal (75) is connected to the emitter of the switch (51).
  • the link point between both capacities (75 and 76) is defined as (Po) or capacitive midpoint.
  • the Positive Capacity Terminal (74d) is connected at the junction between the switch emitter (57) and the switch manifold (55), while the Negative Terminal is connected at the junction between the switch emitter (53) and the switch manifold (51).
  • the terminal (y2) is connected at the junction between the switch emitter (55), the switch manifold (53), the diode anode (56) and the cathode of the diode (54).
  • the terminal (y1) is connected at the junction between the emitter of the switch (51), the negative terminal of the unipolar capacity (75) and the anode of the diode (52).
  • each of the lower subsystems (91) detailed in Figure 12b is characterized by an electrical circuit consisting of four switches (59, 61, 63 and 65) based on semiconductor devices, which can be controlled both on and off and are electrically connected in series, four diodes (60, 62, 64 and 66), each electrically connected in antiparallel with each switch (59, 61, 63 and 65), two unipolar storage capacities (77 and 78) electrically connected in series with each other and in parallel with the four switches (59, 61, 63 and 65) and an additional floating capacity (79d) arranged in parallel with the switches ( 61 and 63).
  • the positive capacity terminal (77) is connected to the switch manifold (59) and the negative capacity terminal (78) is connected to the emitter of the switch (65).
  • the link point between both capacities (77 and 78) is defined as (Po) or capacitive midpoint.
  • the Positive Capacity Terminal (79d) is connected at the junction between the switch emitter (59) and the switch manifold (61), while the Negative Terminal is connected at the junction between the switch emitter (63) and the switch manifold (65).
  • the terminal (y2) is connected at the junction between the switch collector (59), the positive terminal of the unipolar capacity (77) and the diode cathode (60).
  • the terminal (y1) is connected at the junction between the emitter of the switch (61), the collector of the switch (63), the anode of the diode (62) and the cathode of the diode (64).
  • the unipolar capacities that are part of these subsystems (74d, 76 and 75) and (77, 78 and 79d) represented in Figures 12a and 12b may be composed of one or a set of capacitors that provide a certain total capacity.
  • each of the proposed subsystems (90 and 91) integrates an electronic management system (80 and 81) correctly associated with its reference potential (Po) that allows the correct operation of the subsystem and its communication (83 and 84 ) (85 and 86) with one or more higher order control systems.
  • This communication (83 and 84) (85 and 86) can be performed using optical fibers or other technologies that allow isolation and proper functionality between subsystems and superior control devices.
  • the electrical circuits that are part of the subsystems (90 and 91) detailed in Figures 12a and 12b have the following four operating states:
  • the switches (51 and 55) or (59 and 63) are on, while the switches (53 and 57) or (61 and 65) are off.
  • the voltage or potential (UC) corresponding to that of the capacity (74d) or (79d) between the terminals (y2, y1) of the subsystems (90 and 91) respectively is established.
  • the energy store formed by the capacities (74d) or (79d) receives or releases energy depending on the direction of the current flowing through the terminals of the subsystem, while the energy in the capacities (75 and 76) or (77 and 78) remains constant.
  • the switches (53 and 57) or (61 and 65) are on, while the switches (51 and 55) or (59 and 63) are off.
  • the voltage or potential (UC) is established between the terminals (y2, y1) corresponding to the result of the subtraction between the potentials that group the capacities (76 and 75) or (77 and 78) and their potentials inversely related (74d) or (79d) respectively.
  • the resulting energy store between capacities (74d, 75 and 76) or (77, 78 and 79d) receives or releases energy in function of the direction of the current flowing through the subsystem terminals.
  • switches (55 and 57) or (63 and 65) are on and switches (51 and 53) or (59 and 61) off.
  • the resulting voltage (Uy21) at the terminals (y2, y1) of the subsystems (90 and 91) corresponds to the sum of the voltages or potentials (UC) of each of the capacities (76 and 75) or (77 and 78 ) respectively.
  • the resulting energy store between capacities (75 and 76) or (77 and 78) receives or releases energy depending on the direction of the current flowing through the terminals of the subsystem, while the energy in The capacities (74d) or (79d) remain constant.

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Abstract

The invention relates to a converter circuit composed of at least one phase module which incorporates an upper part or assembly and a lower part or assembly formed by at least one upper subsystem of two terminals and a lower subsystem, respectively. Each of these subsystems is based on a multi-level electrical circuit with a capacitive mid-point which is specified in great detail in this invention. One of the ends of the resultant upper assembly is connected to a positive conductor or pole and the other end is connected to the AC phase or central point of the phase module. Moreover, the lower assembly is arranged in a symmetrical manner with respect to the AC phase or central point of the phase module and the other end is connected to a negative conductor or pole. It is optionally necessary to use one or more electromagnetic elements at the connection points with the positive conductor or pole, the negative conductor or pole and the central point or the AC phase. The potential between the positive and negative poles establishes the DC voltage of the phase module of the converter circuit.

Description

CONVERTIDOR MODULAR BASADO EN CIRCUITOS DISTRIBUIDOS ULTI NIVEL DE PUNTO MEDIO CAPACITIVO  MODULAR CONVERTER BASED ON DISTRIBUTED CIRCUITS ULTI LEVEL OF CAPACITIVE MIDDLE POINT
OBJETO DE LA INVENCIÓN OBJECT OF THE INVENTION
El objeto de esta invención es definir un circuito convertidor modular compuesto al menos de un módulo de fase que integra una parte o conjunto superior y otra inferior que contienen por lo menos un subsistema superior e inferior respectivamente, basados en un circuito eléctrico multinivel con punto medio capacitivo enlazado mediante diodos. El conjunto superior se conecta en uno de sus extremos a un conductor o polo positivo y el otro a la fase de corriente alterna o punto central del modulo de fase. Por otro lado el conjunto inferior se dispone de forma simétrica a la fase de corriente alterna o punto central del modulo de fase y el otro extremo se conecta a un conductor o polo negativo. Opcionalmente es necesaria la utilización de uno o varios elementos electromagnéticos en los puntos de conexión con el conductor o polo positivo, el conductor o polo negativo y el punto central o la fase de corriente alterna. El potencial entre los polos positivo y negativo establece la tensión continua del modulo de fase del circuito convertidor. The object of this invention is to define a modular converter circuit composed of at least one phase module that integrates an upper and lower part or assembly containing at least one upper and lower subsystem respectively, based on a multilevel electrical circuit with midpoint capacitive linked by diodes. The upper assembly is connected at one of its ends to a positive conductor or pole and the other to the alternating current phase or central point of the phase module. On the other hand, the lower assembly is arranged symmetrically to the alternating current phase or central point of the phase module and the other end is connected to a negative conductor or pole. Optionally, it is necessary to use one or more electromagnetic elements at the connection points with the positive conductor or pole, the negative conductor or pole and the central point or the alternating current phase. The potential between the positive and negative poles establishes the continuous voltage of the phase module of the converter circuit.
ANTECEDENTES DE LA INVENCIÓN BACKGROUND OF THE INVENTION
El convertidor modular del tipo genérico se ha planteado en diversas patentes como DE 101 03 031 A1 , US 7577008 B2, WO 2009115124 A1 y en recientes publicaciones internacionales como (The Future of High Power Electronics in Transmission and Distribution Power Systems, Colín C Davison and Guillaume de Préville, EPE2009 - Barcelona). En la Figura 1 se muestra el circuito general simplificado de un modulo de fase (100). La estructura de conversión se basa en un conjunto o parte superior (95) y un conjunto o parte inferior (96) que integran uno o varios subsistemas superiores (90) e inferiores (91 ) dispuestos en serie. El conjunto superior (95) se conecta en uno de sus extremos a un conductor o polo positivo (P) y en el otro a la fase de corriente alterna (L) o punto central del modulo de fase. Por otro lado el conjunto inferior (96) se dispone de forma simétrica a la fase de corriente alterna (L) o punto central del modulo de fase y el otro extremo se conecta a un conductor o polo negativo (N). En esta configuración puede contemplarse opcionalmente la utilización de elementos electromagnéticos (30) que faciliten la conexión de los conjuntos superiores e inferiores (95, 96) a los puntos (P), (N) y (L). El potencial entre ambos polos (P-N) establece la tensión continua del modulo de fase (100) del circuito convertidor. La conexión de varias fases (100) en paralelo permite desarrollar circuitos convertidores más complejos como es el caso del convertidor trifásico de la Figura 2. The generic type modular converter has been raised in various patents such as DE 101 03 031 A1, US 7577008 B2, WO 2009115124 A1 and in recent international publications such as (The Future of High Power Electronics in Transmission and Distribution Power Systems, Colín C Davison and Guillaume de Préville, EPE2009 - Barcelona). The simplified general circuit of a phase module (100) is shown in Figure 1. The conversion structure is based on a set or upper part (95) and a set or lower part (96) that they integrate one or several upper (90) and lower (91) subsystems arranged in series. The upper assembly (95) is connected at one of its ends to a positive conductor or pole (P) and in the other to the alternating current phase (L) or center point of the phase module. On the other hand, the lower assembly (96) is arranged symmetrically to the alternating current phase (L) or central point of the phase module and the other end is connected to a negative conductor or pole (N). In this configuration, the use of electromagnetic elements (30) that facilitate the connection of the upper and lower assemblies (95, 96) to points (P), (N) and (L) can optionally be contemplated. The potential between both poles (PN) establishes the continuous voltage of the phase module (100) of the converter circuit. The connection of several phases (100) in parallel allows to develop more complex converter circuits such as the three-phase converter of Figure 2.
Los subsistemas (90, 91 ) conocidos de acuerdo con la técnica anterior normalmente están basados en dispositivos semiconductores del tipo IGBT (Insulated Gate Bipolar Transistors), transistores de efecto de campo MOS (MOSFETs), tiristores GTO, tiristores conmutados de puerta integrada (IGCTs), etc. todos los cuales poseen la capacidad de ser controlados tanto en el encendido como en el apagado. A continuación se describen algunas configuraciones particulares conocidas de estos subsistemas (90, 91 ) haciendo referencia a las Figuras 3-8. Las Figuras 3a y 3b muestran los diagramas eléctricos propuestos en DE 101 03 031 A1 para los subsistemas (90) y (91 ) respectivamente. Estos subsistemas, a los que se hace referencia en las Figuras 3a y 3b respectivamente como (1 1 y 12), comprenden dos interruptores (1 , 3) y (5, 7) conectados en serie y basados en semiconductores que pueden ser controlados tanto en su encendido como en el apagado, dos diodos (2, 4) y (6, 8) conectados eléctricamente en antiparalelo con cada interruptor (1 , 3) y (5, 7) y una capacidad unipolar (9) y (10) dispuesta en paralelo con los interruptores serie (1 , 3) y (5, 7) respectivamente. La capacidad de almacenamiento unipolar (9) y (10) de cada uno de estos subsistemas puede estar compuesta por uno o un conjunto de condensadores que proporcionen una capacidad determinada. La interconexión de este subsistema se realiza a través de los terminales (y1 e y2). El terminal (y1 ) se encuentra conectado con en el emisor de los interruptores (1 y 5) y el ánodo de los diodos (2 y 6) en los subsistemas (1 1 y 12) respectivamente. El terminal (y2) se encuentra conectado con en el colector de los interruptores (1 y 5) y el cátodo de los diodos (2 y 6) en los subsistemas (1 1 y 12) respectivamente. Cabe destacar que esta interconexión no tiene por que realizarse de este modo. Por ejemplo en WO 20091 15124 A1 se utilizan los mismos diagramas eléctricos de los subsistemas (1 1 y 12) pero se plantean conexiones alternativas, definiendo otras estructuras para el circuito convertidor general. The subsystems (90, 91) known in accordance with the prior art are usually based on semiconductor devices of the IGBT (Insulated Gate Bipolar Transistors) type, MOS field effect transistors (MOSFETs), GTO thyristors, integrated gate switched thyristors (IGCTs) ), etc. all of which have the ability to be controlled both on and off. Some particular known configurations of these subsystems (90, 91) are described below with reference to Figures 3-8. Figures 3a and 3b show the electrical diagrams proposed in DE 101 03 031 A1 for subsystems (90) and (91) respectively. These subsystems, referred to in Figures 3a and 3b respectively as (1 1 and 12), comprise two switches (1, 3) and (5, 7) connected in series and based on semiconductors that can be controlled both in its on and off, two diodes (2, 4) and (6, 8) electrically connected in Antiparalle it with each switch (1, 3) and (5, 7) and a unipolar capacity (9) and (10) arranged in parallel with the serial switches (1, 3) and (5, 7) respectively. The unipolar storage capacity (9) and (10) of each of these subsystems may be composed of one or a set of capacitors that provide a given capacity. The interconnection of this subsystem is done through the terminals (y1 and y2). The terminal (y1) is connected to the emitter of the switches (1 and 5) and the anode of the diodes (2 and 6) in the subsystems (1 1 and 12) respectively. The terminal (y2) is connected to the collector of the switches (1 and 5) and the cathode of the diodes (2 and 6) in the subsystems (1 1 and 12) respectively. It should be noted that this interconnection does not have to be done in this way. For example in WO 20091 15124 A1 the same electrical diagrams of the subsystems (1 1 and 12) are used but alternative connections are proposed, defining other structures for the general converter circuit.
Los subsistemas (1 1 , 12) de las Figuras 3a y 3b tienen dos estados o modos de operación denominados control I y I I: The subsystems (1 1, 12) of Figures 3a and 3b have two states or modes of operation called control I and I I:
- Control I: los interruptores (1 ) o (5) están encendidos y los interruptores complementarios respectivos (3) o (7) apagados. Como resultado, la tensión o el potencial (Uy21 ) entre los terminales (y2, y1 ) de los subsistemas (1 1 y 12) es igual a 0.  - Control I: switches (1) or (5) are on and the respective complementary switches (3) or (7) are off. As a result, the voltage or potential (Uy21) between the terminals (y2, y1) of the subsystems (1 1 and 12) is equal to 0.
- Control I I: los interruptores complementarios (3) o (7) se encienden y los interruptores (1 ) o (5) se apagan. De este modo, la tensión o potencial (Uy21 ) entre los terminales (y2, y1 ) corresponde con el potencial almacenado el la capacidad (9) o (10) del subsistema (1 1 o 12) correspondiente. Por otro lado, las Figuras 4, 5, 6 y 7 muestran diversos diagramas eléctricos propuestos en US 7577008 B2 para los subsistemas (90 y 91 ). Como se describe a continuación, estas propuestas equivalen funcionalmente hablando a diversas combinaciones de los subsistemas (1 1 y 12) descritos en DE 101 03 031 A1 y representados en las Figuras 3a y 3b. - Control II: the complementary switches (3) or (7) turn on and the switches (1) or (5) turn off. Thus, the voltage or potential (Uy21) between the terminals (y2, y1) corresponds to the potential stored in the capacity (9) or (10) of the corresponding subsystem (1 1 or 12). On the other hand, Figures 4, 5, 6 and 7 show various electrical diagrams proposed in US 7577008 B2 for the subsystems (90 and 91). As described below, these proposals are functionally equivalent to various combinations of the subsystems (1 1 and 12) described in DE 101 03 031 A1 and represented in Figures 3a and 3b.
El subsistema (13) de la Figura 4 consta de cuatro interruptores basados en dispositivos semiconductores (21 , 23, 25 y 27) que pueden ser controlados tanto en su encendido como en su apagado, cuatro diodos (22, 24, 26 y 28), dos capacidades unipolares (29 y 30) y un circuito electrónico (32). Los cuatro interruptores (21 , 23, 25 y 27) se encuentran conectados eléctricamente en serie. Cada uno de los diodos (22, 24, 26 y 28) se encuentra conectado eléctricamente en antiparalelo con cada uno de estos interruptores (21 , 23, 25 y 27). Las capacidades unipolares (29 o 30), están conectadas eléctricamente en paralelo con cada par de interruptores (21 , 23 o 25, 27) respectivamente. Asimismo, las capacidades unipolares (29 o 30) de este subsistema (13) pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad determinada. El terminal (y2) del subsistema (13) se conecta en la unión entre el emisor y colector de los interruptores (21 y 23) y el ánodo y cátodo de los diodos (22 y 24). Por otro lado, el terminal (y1 ) del subsistema (13) se conecta en la unión entre el emisor y colector de los interruptores (25 y 27) y el ánodo y cátodo de los diodos (26 y 28). Además, la unión entre el emisor del interruptor (23), el colector del interruptor (25), el ánodo del diodo (24), el cátodo del diodo (26), el terminal negativo de la capacidad unipolar (29) y el terminal positivo de la capacidad unipolar (30) define un potencial común (P0), que está conectado eléctricamente a un potencial (M) utilizado como referencia por el módulo electrónico (32). De esta manera, los circuitos electrónicos que forman parte de este modulo se encuentran a un potencial adecuado para actuar sobre los interruptores (21 , 23, 25 y 27). Este módulo electrónico (32) se encuentra vinculado a un control superior que gobierna el circuito convertidor mediante dos fibras ópticas (34 y 36). The subsystem (13) of Figure 4 consists of four switches based on semiconductor devices (21, 23, 25 and 27) that can be controlled both on and off, four diodes (22, 24, 26 and 28) , two unipolar capacities (29 and 30) and an electronic circuit (32). The four switches (21, 23, 25 and 27) are electrically connected in series. Each of the diodes (22, 24, 26 and 28) is electrically connected in antiparallel with each of these switches (21, 23, 25 and 27). The unipolar capacities (29 or 30), are electrically connected in parallel with each pair of switches (21, 23 or 25, 27) respectively. Likewise, the unipolar capacities (29 or 30) of this subsystem (13) can be composed of one or a set of capacitors that provide a given capacity. The terminal (y2) of the subsystem (13) is connected at the junction between the emitter and collector of the switches (21 and 23) and the anode and cathode of the diodes (22 and 24). On the other hand, the terminal (y1) of the subsystem (13) is connected at the junction between the emitter and collector of the switches (25 and 27) and the anode and cathode of the diodes (26 and 28). In addition, the junction between the emitter of the switch (23), the collector of the switch (25), the anode of the diode (24), the cathode of the diode (26), the negative terminal of the unipolar capacity (29) and the terminal Positive unipolar capacity (30) defines a common potential (P0), which is electrically connected to a potential (M) used as a reference by the electronic module (32). In this way, the electronic circuits that are part of this module are at a suitable potential to act on the switches (21, 23, 25 and 27). This electronic module (32) is linked to a higher control that governs the converter circuit by means of two optical fibers (34 and 36).
El subsistema (13) de la Figura 4 tiene cuatro estados o modos de operación denominados control I, I I, I I I y IV: The subsystem (13) of Figure 4 has four states or modes of operation called control I, I I, I I I and IV:
- Control I: los interruptores (21 y 25) están encendidos, y los interruptores (23 y 27) están apagados. Como resultado, se establece la tensión o potencial (UC) correspondiente a la de la capacidad (29) entre los terminales (y2, y1 ) del subsistema (13). En este estado, la capacidad (29) recibe o libera energía en función de la dirección de la corriente que circula a través de los terminales.  - Control I: the switches (21 and 25) are on, and the switches (23 and 27) are off. As a result, the voltage or potential (UC) corresponding to that of the capacity (29) between the terminals (y2, y1) of the subsystem (13) is established. In this state, the capacity (29) receives or releases energy depending on the direction of the current flowing through the terminals.
- Control I I: los interruptores (21 y 27) están encendidos, mientras que los interruptores (23 y 25) están apagados. En este estado, la tensión (Uy21 ) en los terminales (y2, y1 ) del subsistema (13) es igual a la suma de las tensiones (UC) de cada una de las capacidades unipolares (29 y 30). En consecuencia, ambas capacidades (29 y 30) dispuestas en serie y reciben o liberan energía en función de la dirección de la corriente que circula a través de los terminales (y2, y1 )  - Control I I: the switches (21 and 27) are on, while the switches (23 and 25) are off. In this state, the voltage (Uy21) at the terminals (y2, y1) of the subsystem (13) is equal to the sum of the voltages (UC) of each of the unipolar capacities (29 and 30). Consequently, both capacities (29 and 30) arranged in series and receive or release energy depending on the direction of the current flowing through the terminals (y2, y1)
- Control I I I: los interruptores (23 y 25) están encendidos y los interruptores (21 y 27) apagados. En este caso, la tensión resultante - Control I I I: the switches (23 and 25) are on and the switches (21 and 27) off. In this case, the resulting tension
(Uy21 ) en los terminales (y2, y1 ) del subsistema (13) es igual a cero. La energía en las capacidades (29 y 30) se mantiene constante. (Ou21) at the terminals (y2, y1) of the subsystem (13) is equal to zero. The energy in the capacities (29 and 30) remains constant.
- Control IV: los interruptores (23 y 27) están encendidos, mientras los interruptores (21 y 25) se encuentran apagados. Como resultado, la tensión (Uy21 ) en los terminales (y2, y1 ) del subsistema (13) equivale a la tensión (UC) establecida en la capacidad unipolar (30), y la capacidad (30) recibe o libera energía en función de la dirección de la corriente Por lo tanto, en términos de funcionalidad este subsistema (13) es equivalente a la conexión en serie de los subsistemas (1 1 y 12) presentados en DE 101 03 031 A1 . La Figura 5 muestra un nuevo subsistema (14) que difiere del subsistema presentado en la Figura 4 en el que sólo los pares de interruptores (21 , 23) y (25, 27) se encuentran conectados eléctricamente en serie. Al igual que en el subsistema (14), los diodos (22, 24, 26 y 28) están conectados eléctricamente en antiparalelo con cada interruptor (21 , 23, 25 y 27). Por otro lado las capacidades unipolares respectivas (29 y 30) están conectadas eléctricamente en paralelo con cada par de interruptores respectivamente. La unión entre el emisor del interruptor (23), el ánodo del diodo (24) y el terminal negativo de la capacidad unipolar (29) se conecta eléctricamente entre la unión del emisor y colector de los interruptores (25 y 27). Esta unión forma un potencial común (P0), que se considera como potencial de referencia para el terminal (M) del módulo electrónico (32). Además, la unión entre el emisor del interruptor (27), el ánodo del diodo (28) y el terminal negativo de la capacidad unipolar (30) se conecta al terminal (y1 ) del subsistema (14). La unión entre el emisor y colector de los interruptores (21 y 23), el ánodo del diodo (22) y el cátodo del diodo (24) establece el terminal (y2) del subsistema (14). - Control IV: the switches (23 and 27) are on, while the switches (21 and 25) are off. As a result, the voltage (Uy21) at the terminals (y2, y1) of the subsystem (13) is equivalent to the voltage (UC) established in the unipolar capacity (30), and the capacity (30) receives or releases energy as a function of the direction of the current Therefore, in terms of functionality this subsystem (13) is equivalent to the serial connection of the subsystems (1 1 and 12) presented in DE 101 03 031 A1. Figure 5 shows a new subsystem (14) that differs from the subsystem presented in Figure 4 in which only the switch pairs (21, 23) and (25, 27) are electrically connected in series. As in the subsystem (14), the diodes (22, 24, 26 and 28) are electrically connected in antiparallel with each switch (21, 23, 25 and 27). On the other hand the respective unipolar capacities (29 and 30) are electrically connected in parallel with each pair of switches respectively. The junction between the emitter of the switch (23), the anode of the diode (24) and the negative terminal of the unipolar capacity (29) is electrically connected between the junction of the emitter and collector of the switches (25 and 27). This junction forms a common potential (P0), which is considered as a reference potential for the terminal (M) of the electronic module (32). In addition, the junction between the emitter of the switch (27), the anode of the diode (28) and the negative terminal of the unipolar capacity (30) is connected to the terminal (y1) of the subsystem (14). The junction between the emitter and collector of the switches (21 and 23), the anode of the diode (22) and the cathode of the diode (24) establishes the terminal (y2) of the subsystem (14).
En consecuencia, en términos de operación este subsistema (14) sigue siendo equivalente al subsistema (13) y funcionalmente equivale a la conexión en serie de los dos subsistemas (1 1 ) en DE 101 03 031 A1 . Consequently, in terms of operation this subsystem (14) remains equivalent to subsystem (13) and functionally amounts to the serial connection of the two subsystems (1 1) in DE 101 03 031 A1.
La Figura 6 muestra una tercera modalidad de subsistema donde, a diferencia del subsistema (14), la unión entre el emisor y colector de los interruptores (21 y 23) conectados eléctricamente en serie se realiza entre el colector del interruptor (25), el cátodo del diodo (26) y el terminal positivo de la capacidad unipolar (30). En este caso, la unión entre el emisor y colector de los dos interruptores (25 y 27) conectados eléctricamente en serie constituye ahora el terminal de conexión (y1 ), mientras que la unión entre el colector del interruptor (21 ), el cátodo del diodo (22) y el terminal positivo de la capacidad unipolar (29) constituye el terminal de conexión (y2) de este subsistema (15). Figure 6 shows a third subsystem mode where, unlike the subsystem (14), the connection between the emitter and collector of the switches (21 and 23) electrically connected in series is performed between the collector of the switch (25), the diode cathode (26) and the positive terminal of unipolar capacity (30). In this case, the connection between the emitter and collector of the two switches (25 and 27) electrically connected in series now constitutes the connection terminal (y1), while the connection between the switch collector (21), the cathode of the diode (22) and the positive terminal of the unipolar capacity (29) constitutes the connection terminal (y2) of this subsystem (15).
Por lo tanto, en términos de operación este nuevo subsistema (15) sigue siendo similar al subsistema (13) y funcionalmente equivale a conexión en serie de los dos subsistemas (12) propuestos en DE 101 03 031 A1 . Therefore, in terms of operation this new subsystem (15) remains similar to subsystem (13) and functionally amounts to serial connection of the two subsystems (12) proposed in DE 101 03 031 A1.
La Figura 7 presenta una cuarta modalidad de subsistema relacionada con la Figuras 5 y 6. Los pares de interruptores (21 , 23) y (25, 27) se conectan eléctricamente en serie y cada uno de los diodos (22, 24, 26, 28) se disponen en antiparalelo con de estos interruptores (21 , 23, 25, 27) respectivamente. Cada una de las capacidades unipolares (29 y 30) se conectan eléctricamente en paralelo con cada par de interruptores (21 , 23) y (25, 27). La unión entre el emisor y colector de los interruptores (21 y 23) se vincula a la unión entre el emisor y colector de los interruptores (25 y 27). La unión entre el colector del interruptor (21 ), el cátodo del diodo (22) y el terminal positivo de la capacidad unipolar (29) establece el terminal de conexión (y2) del subsistema (16). Por otro lado, la unión entre el emisor del interruptor (27), el ánodo del diodo (28) y el terminal negativo de la capacidad unipolar (30) establece el terminal (y1 ) del subsistema (16). De forma análoga a los subsistemas (14 y 15), la operación del subsistema (16) sigue siendo equivalente a la detallada para el subsistema (13). Desde el punto de vista funcional, este subsistema (16) es equivalente a la conexión en serie del subsistema (12) con el subsistema (1 1 ) propuesto en DE 101 03 031 A1 . Por último, se ha presentado recientemente en (The Future ofFigure 7 shows a fourth subsystem modality related to Figures 5 and 6. The switch pairs (21, 23) and (25, 27) are electrically connected in series and each of the diodes (22, 24, 26, 28) are arranged in antiparallel with these switches (21, 23, 25, 27) respectively. Each of the unipolar capacities (29 and 30) is electrically connected in parallel with each pair of switches (21, 23) and (25, 27). The connection between the transmitter and collector of the switches (21 and 23) is linked to the connection between the transmitter and collector of the switches (25 and 27). The junction between the switch collector (21), the cathode of the diode (22) and the positive terminal of the unipolar capacity (29) establishes the connection terminal (y2) of the subsystem (16). On the other hand, the junction between the emitter of the switch (27), the anode of the diode (28) and the negative terminal of the unipolar capacity (30) establishes the terminal (y1) of the subsystem (16). Similarly to the subsystems (14 and 15), the operation of the subsystem (16) remains equivalent to that detailed for the subsystem (13). From the functional point of view, this subsystem (16) is equivalent to the serial connection of the subsystem (12) with the subsystem (1 1) proposed in DE 101 03 031 A1. Finally, he has recently performed in (The Future of
High Power Electronics in Transmission and Distribution Power Systems, Colín C Davison and Guillaume de Préville, EPE2009 - Barcelona) otro diagrama eléctrico alternativo a los subsistemas propuestos en DE 101 03 031 A1 y US 7577008 B2 basado en las patentes US3909685 y US3867643. La Figura 8 detalla el circuito eléctrico propuesto en este documento. Este subsistema (17) se caracteriza por cuatro interruptores basados en dispositivos semiconductores (41 , 43, 45 y 47) que pueden ser controlados tanto en su encendido como en su apagado, cuatro diodos (42, 44, 46 y 48) y una capacidad unipolar (49). Los interruptores (41 , 43) y (45, 47) se conectan eléctricamente en serie y los pares resultantes (41 , 43) y (45 y 47) se conectan eléctricamente en paralelo. Cada uno de los diodos (42, 44, 46 y 48) se dispone eléctricamente en antiparalelo con cada uno de estos interruptores (41 , 43, 45 y 47). La capacidad unipolar (49) se conecta eléctricamente en paralelo con cada par de interruptores (21 , 23) y (25, 27). High Power Electronics in Transmission and Distribution Power Systems, Colín C Davison and Guillaume de Préville, EPE2009 - Barcelona) another alternative electrical diagram to the subsystems proposed in DE 101 03 031 A1 and US 7577008 B2 based on US3909685 and US3867643. Figure 8 details the electrical circuit proposed in this document. This subsystem (17) is characterized by four switches based on semiconductor devices (41, 43, 45 and 47) that can be controlled both on and off, four diodes (42, 44, 46 and 48) and a capacity unipolar (49). The switches (41, 43) and (45, 47) are electrically connected in series and the resulting pairs (41, 43) and (45 and 47) are electrically connected in parallel. Each of the diodes (42, 44, 46 and 48) is electrically arranged in antiparallel with each of these switches (41, 43, 45 and 47). The unipolar capacity (49) is electrically connected in parallel with each pair of switches (21, 23) and (25, 27).
En términos de operación, el subsistema (17) presenta fundamentalmente cuatro estados o modos de operación denominados control I, I I, I I I y IV: In terms of operation, the subsystem (17) presents essentially four states or modes of operation called control I, I I, I I I and IV:
- Control I: los interruptores (41 y 45) están encendidos y los interruptores complementarios (23 y 27) apagados. Como resultado, se establece la tensión o potencial (UC) correspondiente a la capacidad (49) entre los terminales (y2, y1 ) del subsistema (17).  - Control I: the switches (41 and 45) are on and the complementary switches (23 and 27) are off. As a result, the voltage or potential (UC) corresponding to the capacity (49) between the terminals (y2, y1) of the subsystem (17) is established.
- Control I I: los interruptores (21 y 27) están encendidos, mientras que los interruptores (23 y 25) se encuentran apagados. En este estado, la tensión (Uy21 ) en los terminales (y2, y1 ) del subsistema (17) es cero. - Control II: the switches (21 and 27) are on, while the switches (23 and 25) are off. In this state, the voltage (Uy21) at the terminals (y2, y1) of the subsystem (17) is zero.
- Control I I I: los interruptores (23 y 25) están encendidos y los interruptores (21 y 27) apagados. Al igual que en el estado de control II, la tensión (Uy21 ) resultante en los terminales (y2, y1 ) del subsistema (17) es igual a cero.  - Control I I I: the switches (23 and 25) are on and the switches (21 and 27) off. As in the control state II, the resulting voltage (Uy21) at the terminals (y2, y1) of the subsystem (17) is equal to zero.
- Control IV: los interruptores (23 y 27) están encendidos, mientras que los interruptores (21 y 25) se encuentran apagados. Como resultado, la tensión (Uy21 ) en los terminales (y2, y1 ) del subsistema (17) equivale a la tensión inversa establecida en la capacidad unipolar (49). Consecuentemente, este subsistema (17) presenta un grado de libertad adicional con respecto a los subsistemas anteriores ya que funcionalmente le permite operar con tensiones negativas en sus terminales (y2, y1 ).  - Control IV: the switches (23 and 27) are on, while the switches (21 and 25) are off. As a result, the voltage (Uy21) at the terminals (y2, y1) of the subsystem (17) is equivalent to the inverse voltage established at the unipolar capacity (49). Consequently, this subsystem (17) presents an additional degree of freedom with respect to the previous subsystems since it functionally allows it to operate with negative voltages in its terminals (y2, y1).
El desarrollo de convertidores de media-alta potencia en niveles de media-alta tensión, utilizando semiconductores controlados tanto en el encendido como en el apagado requiere disponer en serie varios subsistemas como los propuestos en DE 101 03 031 A1 , US 7577008 B2 y (The Future of High Power Electronics in Transmission and Distribution Power Systems, Colín C Davison and Guillaume de Préville, EPE2009 - Barcelona). El número depende fundamentalmente de la tensión continua entre los terminales (P) y (N), la potencia del circuito convertidor y la capacidad de bloqueo de los semiconductores seleccionados. Por lo tanto, un mayor requerimiento en potencia para una determinada tecnología de semiconductor implica directamente un aumento en el número de subsistemas necesarios. Esto implica a su vez que el número de circuitos electrónicos de control asociados a estos subsistemas, tales como sistemas de supervisión, medida, etc. que deben encontrarse aislados, tienden a incrementarse, aumentando la complejidad y coste final del sistema en su conjunto. El documento US 7577008 B2 detalla este hecho y propone reducir el número de subsistemas combinando diversos circuitos simples como los de las Figuras 4, 5, 6 y 7. De este modo el número de subsistemas disminuye a costa de aumentar el número de elementos que forman parte ellos. Así, un convertidor complejo compuesto por varios subsistemas simples puede ser reemplazado por un convertidor simple que integre unos pocos subsistemas complejos. Por otro lado, la solución abordada en The Future of High Power Electronics in Transmission and Distribution Power Systems, Colín C Davison and Guillaume de Préville, EPE2009 - Barcelona) describe un subsistema complejo y requiere tantos subsistemas como los necesarios en DE 101 03 031 A1 . No obstante, las características operativas de este circuito eléctrico permiten disminuir el tamaño de la capacidad de cada uno de los subsistemas que lo integran, reduciendo su tamaño y volumen. The development of medium-high power converters at medium-high voltage levels, using controlled semiconductors both on and off requires several series of subsystems such as those proposed in DE 101 03 031 A1, US 7577008 B2 and (The Future of High Power Electronics in Transmission and Distribution Power Systems, Colín C Davison and Guillaume de Préville, EPE2009 - Barcelona). The number depends mainly on the continuous voltage between terminals (P) and (N), the power of the converter circuit and the blocking capacity of the selected semiconductors. Therefore, a higher power requirement for a given semiconductor technology directly implies an increase in the number of necessary subsystems. This in turn implies that the number of electronic control circuits associated with these subsystems, such as monitoring systems, measurement, etc. which must be isolated, tend to increase, increasing the complexity and final cost of the system as a whole. Document US 7577008 B2 details this fact and proposes to reduce the number of subsystems by combining various simple circuits such as those in Figures 4, 5, 6 and 7. In this way the number of subsystems decreases at the cost of increasing the number of elements that are part of them. Thus, a complex converter composed of several simple subsystems can be replaced by a simple converter that integrates a few complex subsystems. On the other hand, the solution addressed in The Future of High Power Electronics in Transmission and Distribution Power Systems, Colín C Davison and Guillaume de Préville, EPE2009 - Barcelona) describes a complex subsystem and requires as many subsystems as necessary in DE 101 03 031 A1 . However, the operational characteristics of this electrical circuit make it possible to reduce the size of the capacity of each of the subsystems that integrate it, reducing its size and volume.
DESCRIPCIÓN DE LA INVENCIÓN DESCRIPTION OF THE INVENTION
El objeto de esta invención es un circuito convertidor que comprende unos novedosos subsistemas de dos terminales que permiten simplificar el tamaño y complejidad del convertidor. The object of this invention is a converter circuit comprising novel two-terminal subsystems that simplify the size and complexity of the converter.
En el presente documento, se entiende que cada elemento descrito, reivindicado o representado en las figuras hace también referencia a combinaciones de ese mismo elemento que puedan llevar a cabo una función equivalente. Así, por ejemplo, cuando se menciona una capacidad se entiende que es equivalente emplear uno o varios condensadores conectados en paralelo. De igual modo, un diodo puede comprender varios diodos o un interruptor basado en dispositivos semiconductores puede comprender una combinación de interruptores. La invención se refiere a un circuito convertidor compuesto por al menos un módulo de fase que comprende una parte o conjunto superior y otro inferior, cada uno de los cuales está formado por al menos un subsistema de dos terminales superior y otro inferior respectivamente. El conjunto superior se conecta en uno de sus extremos a un conductor o polo positivo y el otro a la fase de corriente alterna o punto central del modulo de fase. Por otro lado el conjunto inferior se dispone de forma simétrica a la fase de corriente alterna o punto central del modulo de fase y el otro extremo se conecta a un conductor o polo negativo. Opcionalmente es necesaria la utilización de uno o varios elementos electromagnéticos en los puntos de conexión con el conductor o polo positivo, el conductor o polo negativo y el punto central o la fase de corriente alterna. El potencial entre el polo positivo y negativo establece la tensión continua del modulo de fase del circuito convertidor. In this document, it is understood that each element described, claimed or represented in the figures also refers to combinations of that same element that can perform an equivalent function. Thus, for example, when a capacity is mentioned, it is understood that it is equivalent to use one or several capacitors connected in parallel. Similarly, a diode may comprise several diodes or a switch based on semiconductor devices may comprise a combination of switches. The invention relates to a converter circuit composed of at least one phase module comprising an upper and lower part or assembly, each of which is formed by at least one subsystem of two upper and lower terminals respectively. The upper assembly is connected at one of its ends to a positive conductor or pole and the other to the alternating current phase or central point of the phase module. On the other hand, the lower assembly is arranged symmetrically to the alternating current phase or central point of the phase module and the other end is connected to a negative conductor or pole. Optionally, it is necessary to use one or more electromagnetic elements at the connection points with the positive conductor or pole, the negative conductor or pole and the central point or the alternating current phase. The potential between the positive and negative pole sets the continuous voltage of the phase module of the converter circuit.
El primer grupo de subsistemas propuestos en esta invención se caracteriza por un circuito eléctrico compuesto por cuatro interruptores basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos, cada uno conectado eléctricamente en antiparalelo con cada interruptor, dos capacidades de almacenamiento unipolar conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores y dos diodos adicionales de enlace o clamp denominados primer diodo y segundo diodo. El cátodo del primer diodo de enlace se conecta en la unión entre el emisor y colector de los dos interruptores superiores y el ánodo en la unión entre las capacidades dispuestas en serie. Por otro lado, el ánodo del segundo diodo de enlace se conecta entre la unión entre el emisor y colector de los dos interruptores inferiores y el cátodo en la unión entre las capacidades dispuestas en serie. Las capacidades unipolares de este subsistema pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad total determinada. Además, cada uno de los subsistemas propuestos integra un sistema electrónico de gestión correctamente asociado a su potencial de referencia que permite la correcta operación del subsistema y su comunicación con uno o varios sistemas de control de orden superior. The first group of subsystems proposed in this invention is characterized by an electrical circuit consisting of four switches based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes, each connected electrically in antiparallel with each switch, two unipolar storage capacities electrically connected in series with each other and in parallel with the four switches and two additional link or clamp diodes called first diode and second diode. The cathode of the first link diode is connected at the junction between the emitter and collector of the two upper switches and the anode at the junction between the capacities arranged in series. On the other hand, the anode of the second link diode is connected between the junction between the emitter and collector of the two lower switches and the cathode at the junction between the capacities arranged in series. The unipolar capabilities of this subsystem can be composed of one or a set of capacitors that provide a certain total capacity. In addition, each of the proposed subsystems integrates an electronic management system correctly associated with its reference potential that allows the correct operation of the subsystem and its communication with one or more higher order control systems.
El segundo grupo de subsistemas propuestos en esta invención se caracteriza por un circuito eléctrico compuesto por cuatro interruptores basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos, cada uno conectado eléctricamente en antiparalelo con cada interruptor, dos capacidades de almacenamiento unipolar conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores y dos interruptores adicionales de enlace o clamp, denominados primer interruptor de enlace y segundo interruptor de enlace, cada uno con su respectivo diodo en antiparalelo. De forma general, el colector del primer interruptor de enlace se conecta la unión entre el emisor y colector de los dos interruptores superiores mientras que su emisor se conecta en la unión entre las capacidades dispuestas en serie. Por otro lado, el emisor del segundo interruptor de enlace se conecta la unión entre el emisor y colector de los dos interruptores inferiores mientras que su colector se conecta en la unión entre las capacidades dispuestas en serie. Al igual que el primer conjunto de subsistemas propuesto en esta invención, las capacidades unipolares del subsistema pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad total determinada. Asimismo, cada uno de los subsistemas propuestos integra un sistema electrónico de gestión correctamente asociado a su potencial de referencia que permite la correcta operación del subsistema y su comunicación con uno o varios sistemas de control de orden superior. El tercer grupo de subsistemas propuestos en esta invención se caracteriza por un circuito eléctrico compuesto por cuatro interruptores basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos, cada uno conectado eléctricamente en antiparalelo con cada interruptor, dos capacidades de almacenamiento unipolar conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores y un primer y segundo interruptores adicionales de enlace o clamp opuestamente conectados en serie con sus respectivos diodos en antiparalelo. De forma general, el colector del primer interruptor de enlace se conecta la unión entre el emisor y colector de los dos interruptores centrales mientras que su emisor se conecta al emisor del segundo interruptor de enlace. El colector de este segundo interruptor de enlace se conecta entre las capacidades dispuestas en serie por medio de su colector. The second group of subsystems proposed in this invention is characterized by an electrical circuit consisting of four switches based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes, each connected electrically in antiparallel with each switch, two unipolar storage capacities electrically connected in series with each other and in parallel with the four switches and two additional link or clamp switches, called first link switch and second link switch, each with its respective diode in antiparallel. In general, the collector of the first link switch connects the junction between the emitter and collector of the two upper switches while its emitter is connected at the junction between the capacities arranged in series. On the other hand, the emitter of the second link switch connects the junction between the emitter and collector of the two lower switches while its collector is connected at the junction between the capacities arranged in series. Like the first set of subsystems proposed in this invention, the unipolar capabilities of the subsystem can be composed of one or a set of capacitors that provide a given total capacity. Likewise, each of the proposed subsystems integrates an electronic management system correctly associated with its reference potential that allows the correct operation of the subsystem and its communication with one or more higher order control systems. The third group of subsystems proposed in this invention is characterized by an electrical circuit consisting of four switches based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes, each connected electrically in antiparallel with each switch, two unipolar storage capacities electrically connected in series with each other and in parallel with the four switches and a first and second additional link or clamp switches oppositely connected in series with their respective antiparallel diodes. In general, the collector of the first link switch connects the junction between the emitter and collector of the two central switches while its emitter is connected to the emitter of the second link switch. The collector of this second link switch is connected between the capacities arranged in series by means of its collector.
De forma similar a los conjuntos de subsistemas propuestos anteriormente, las capacidades unipolares del subsistema pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad total determinada. Además, cada uno de los subsistemas propuestos integra un sistema electrónico de gestión correctamente asociado a su potencial de referencia que permite la correcta operación del subsistema y su comunicación con uno o varios sistemas de control de orden superior. Similar to the sets of subsystems proposed above, the unipolar capabilities of the subsystem may be composed of one or a set of capacitors that provide a given total capacity. In addition, each of the proposed subsystems integrates an electronic management system correctly associated with its reference potential that allows the correct operation of the subsystem and its communication with one or more higher order control systems.
Por último, el cuarto grupo de subsistemas propuestos en esta invención se caracteriza por un circuito eléctrico compuesto por cuatro interruptores basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos, cada uno conectado eléctricamente en antiparalelo con cada interruptor, dos capacidades de almacenamiento unipolar conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores y una capacidad adicional flotante que se conecta en paralelo con los interruptores centrales. De forma similar a los conjuntos de subsistemas propuestos anteriormente, las capacidades unipolares del subsistema pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad total determinada. Asimismo, cada uno de los subsistemas propuestos integra un sistema electrónico de gestión correctamente asociado a su potencial de referencia que permite la correcta operación del subsistema y su comunicación con uno o varios sistemas de control de orden superior. Finally, the fourth group of subsystems proposed in this invention is characterized by an electrical circuit consisting of four switches based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes, each electrically connected in antiparallel with each switch, two capacities of Unipolar storage electrically connected in series with each other and in parallel with the four switches and an additional floating capacity that is connected in parallel with the central switches. Similar to the sets of subsystems proposed above, the unipolar capabilities of the subsystem may be composed of one or a set of capacitors that provide a given total capacity. Likewise, each of the proposed subsystems integrates an electronic management system correctly associated with its reference potential that allows the correct operation of the subsystem and its communication with one or more higher order control systems.
El conjunto de subsistemas que integran la parte superior e inferior del módulo de fase en las cuatro configuraciones propuestas se diferencian en la ubicación de los terminales de conexión del circuito eléctrico. De forma general, la unión entre los interruptores centrales y el emisor del interruptor inferior definen, respectivamente, cada uno de los dos terminales del subsistema superior y el colector del interruptor superior y la unión entre los dos interruptores centrales definen cada uno de los dos terminales del subsistema inferior. No obstante, la ubicación de estos terminales también puede realizarse entre los interruptores centrales y el punto medio capacitivo, resultando un subsistema compatible tanto para la parte superior como inferior. The set of subsystems that integrate the upper and lower part of the phase module into the four proposed configurations differ in the location of the electrical circuit connection terminals. In general, the connection between the central switches and the emitter of the lower switch respectively defines each of the two terminals of the upper subsystem and the collector of the upper switch and the connection between the two central switches defines each of the two terminals of the lower subsystem. However, the location of these terminals can also be made between the central switches and the capacitive midpoint, resulting in a compatible subsystem for both the top and bottom.
BREVE DESCRIPCIÓN DE LAS FIGURAS BRIEF DESCRIPTION OF THE FIGURES
Las siguientes figuras permiten mostrar con un mayor detalle las soluciones conocidas así como nuevas las propuestas presentadas en esta invención. La Figura 1 muestra el diagrama general de una fase de un circuito convertidor compuesto por un conjunto de N subsistemas distribuidos La Figura 2 muestra un circuito convertidor trifásico compuesto por un conjunto de N subsistemas distribuidos The following figures allow to show in greater detail the known solutions as well as new the proposals presented in this invention. Figure 1 shows the general diagram of a phase of a converter circuit composed of a set of N distributed subsystems Figure 2 shows a three-phase converter circuit composed of a set of N distributed subsystems
Las Figuras 3a, 3b, 4, 5, 6, 7, 8 muestran los circuitos eléctricos conocidos para los subsistemas distribuidos Figures 3a, 3b, 4, 5, 6, 7, 8 show the known electrical circuits for distributed subsystems
Las Figuras 9a, 9b, 10a, 10b, 1 1 a, 1 1 b, 12a y 12b detallan los conjuntos de circuitos eléctricos multinivel de punto medio capacitivo propuestos en esta invención para los subsistemas distribuidos. EJEMPLOS DE REALIZACIÓN DE LA INVENCIÓN Figures 9a, 9b, 10a, 10b, 1 1 a, 1 1 b, 12a and 12b detail the multi-level electrical capacitive mid-circuit circuit sets proposed in this invention for distributed subsystems. EXAMPLES OF EMBODIMENT OF THE INVENTION
Se describen a continuación con mayor detalle las diferentes topologías de subsistemas superior e inferior propuestas en el presente documento haciendo referencia a las figuras adjuntas. En ellas, se ha utilizado la misma numeración para hacer referencia a elementos iguales o equivalentes. The different top and bottom subsystem topologies proposed in this document are described in greater detail with reference to the attached figures. In them, the same numbering has been used to refer to equal or equivalent elements.
Las Figuras 9a y 9b muestran detalladamente un primer conjunto de diagramas eléctricos propuestos en esta invención para los subsistemas (90 y 91 ) correspondientes al circuito convertidor, compuesto por al menos un módulo de fase (100) que integra una parte o conjunto superior (95) y una parte o conjunto inferior (96) formados al menos por un subsistema de dos terminales superior (90) y otro inferior (91 ) respectivamente. El conjunto superior (95) se conecta en uno de sus extremos a un conductor o polo positivo (P) y en el otro a la fase de corriente alterna (L) o punto central del modulo de fase. Por otro lado el conjunto inferior (96) se dispone de forma simétrica a la fase de corriente alterna (L) o punto central del modulo de fase y el otro extremo se conecta a un conductor o polo negativo (N). En esta configuración puede contemplarse opcionalmente la utilización de elementos electromagnéticos (30) que faciliten la conexión de los conjuntos superiores e inferiores (95, 96) a los puntos (P), (N) y (L). El potencial entre ambos polos (P-N) establece la tensión continua del modulo de fase (100) de circuito convertidor. Cada uno de los subsistemas superiores (90) detallados en laFigures 9a and 9b show in detail a first set of electrical diagrams proposed in this invention for the subsystems (90 and 91) corresponding to the converter circuit, consisting of at least one phase module (100) that integrates an upper part or assembly (95 ) and a lower part or assembly (96) formed at least by a subsystem of two upper terminals (90) and a lower one (91) respectively. The upper assembly (95) is connected at one of its ends to a positive conductor or pole (P) and in the other to the alternating current phase (L) or center point of the phase module. On the other hand the Lower assembly (96) is arranged symmetrically to the alternating current phase (L) or center point of the phase module and the other end is connected to a negative conductor or pole (N). In this configuration, the use of electromagnetic elements (30) that facilitate the connection of the upper and lower assemblies (95, 96) to points (P), (N) and (L) can optionally be contemplated. The potential between both poles (PN) establishes the continuous voltage of the phase module (100) of the converter circuit. Each of the upper subsystems (90) detailed in the
Figura 9a se caracterizan por un circuito eléctrico compuesto por cuatro interruptores (57, 55, 53 y 51 ) basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos (58, 56, 54 y 52), cada uno conectado eléctricamente en antiparalelo con cada interruptor (57, 55, 53 y 51 ), dos capacidades de almacenamiento unipolar (76 y 75) conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores (57, 55, 53 y 51 ) y dos diodos adicionales de enlace o clamp (70a y 68a). El cátodo del diodo (70a) se conecta entre la unión del emisor del interruptor (57) y el colector del interruptor (55) y el ánodo en la unión (Po) entre las capacidades (76 y 75). Este punto de unión entre ambas capacidades (76 y 75) se define como (Po) o punto medio capacitivo. Por otro lado, el ánodo del diodo (68a) se conecta entre la unión del emisor del interruptor (53) y el colector del interruptor (51 ) y el cátodo en la unión (Po) entre las capacidades (76 y 75). El terminal positivo de la capacidad (76) se conecta al colector del interruptor (57) y el terminal negativo de la capacidad (75) se conecta al emisor del interruptor (51 ). En los subsistemas (90) superiores, el terminal (y2) se conecta en la unión entre el emisor del interruptor (55), el colector del interruptor (53), el ánodo del diodo (56) y el cátodo del diodo (54). El terminal (y1 ) se conecta en la unión entre el emisor del interruptor (51 ), el terminal negativo de la capacidad unipolar (75) y el ánodo del diodo (52). Figure 9a are characterized by an electrical circuit consisting of four switches (57, 55, 53 and 51) based on semiconductor devices, which can be controlled both on and off and are connected electrically in series, four diodes (58 , 56, 54 and 52), each electrically connected in antiparallel with each switch (57, 55, 53 and 51), two unipolar storage capacities (76 and 75) electrically connected in series with each other and in parallel with the four switches (57, 55, 53 and 51) and two additional link or clamp diodes (70a and 68a). The diode cathode (70a) is connected between the switch emitter junction (57) and the switch manifold (55) and the anode at the junction (Po) between the capacities (76 and 75). This junction point between both capacities (76 and 75) is defined as (Po) or capacitive midpoint. On the other hand, the diode anode (68a) is connected between the switch emitter junction (53) and the switch manifold (51) and the cathode in the junction (Po) between the capacities (76 and 75). The positive capacity terminal (76) is connected to the switch manifold (57) and the negative capacity terminal (75) is connected to the emitter of the switch (51). In the upper subsystems (90), the terminal (y2) is connected at the junction between the switch emitter (55), the switch manifold (53), the diode anode (56) and the diode cathode (54) . The terminal (y1) is connected at the junction between the emitter of the switch (51), the negative terminal of the unipolar capacity (75) and the anode of the diode (52).
De forma similar, cada uno de los subsistemas inferiores (91 ) detallados en la Figura 9b se caracterizan por un circuito eléctrico compuesto por cuatro interruptores (59, 61 , 63 y 65) basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos (60, 62, 64 y 66), cada uno conectado eléctricamente en antiparalelo con cada interruptor (59, 61 , 63 y 65), dos capacidades de almacenamiento unipolar (77 y 78) conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores (59, 61 , 63 y 65) y dos diodos adicionales de enlace o clamp (72a y 74a). El cátodo del diodo (72a) se conecta entre la unión del emisor del interruptor (59) y el colector del interruptor (61 ) y el ánodo en la unión (Po) entre las capacidades (77 y 78). Por otro lado, el ánodo del diodo (74a) se conecta entre la unión del emisor del interruptor (63) y el colector del interruptor (65) y el cátodo en la unión (Po) entre las capacidades (77 y 78). Este punto de unión entre ambas capacidades (77 y 78) se define como (Po) o punto medio capacitivo. El terminal positivo de la capacidad (77) se conecta al colector del interruptor (59) y el terminal negativo de la capacidad (78) se conecta al emisor del interruptor (65). No obstante, en los subsistemas (91 ) inferiores, el terminal (y2) se conectan en la unión entre el colector del interruptor (59), el terminal positivo de la capacidad unipolar (77) y el cátodo del diodo (60). El terminal (y1 ) se conecta en la unión entre el emisor del interruptor (61 ), el colector del interruptor (63), el ánodo del diodo (62) y el cátodo del diodo (64). Similarly, each of the lower subsystems (91) detailed in Figure 9b is characterized by an electrical circuit consisting of four switches (59, 61, 63 and 65) based on semiconductor devices, which can be controlled both when switched on as in the shutdown and four diodes (60, 62, 64 and 66) are connected electrically in series, each electrically connected in antiparallel with each switch (59, 61, 63 and 65), two unipolar storage capacities (77 and 78) electrically connected in series with each other and in parallel with the four switches (59, 61, 63 and 65) and two additional link or clamp diodes (72a and 74a). The diode cathode (72a) is connected between the switch emitter junction (59) and the switch manifold (61) and the anode at the junction (Po) between the capacities (77 and 78). On the other hand, the anode of the diode (74a) is connected between the switch emitter junction (63) and the switch manifold (65) and the cathode in the junction (Po) between the capacities (77 and 78). This junction point between both capacities (77 and 78) is defined as (Po) or capacitive midpoint. The positive capacity terminal (77) is connected to the switch manifold (59) and the negative capacity terminal (78) is connected to the emitter of the switch (65). However, in the lower subsystems (91), the terminal (y2) is connected at the junction between the switch collector (59), the positive terminal of the unipolar capacity (77) and the diode cathode (60). The terminal (y1) is connected at the junction between the emitter of the switch (61), the collector of the switch (63), the anode of the diode (62) and the cathode of the diode (64).
Las capacidades unipolares de ambos subsistemas (76, 75) y (77, 78) pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad total determinada. Asimismo, cada uno de los subsistemas (90 y 91 ) propuestos integra un sistema electrónico de gestión (80 y 81 ) correctamente asociado a su potencial de referencia (Po) que permita la correcta operación del subsistema y su comunicación (83 y 84) (85 y 86) con uno o varios sistemas de control de orden superior. Esta comunicación (83 y 84) (85 y 86) puede realizarse utilizando fibras ópticas u otras tecnologías que permitan el aislamiento y la funcionalidad adecuada entre los subsistemas y los dispositivos de control superior. Los circuitos eléctricos que forman parte de los subsistemas (90 y 91 ) detallados en las Figuras 9a y 9b presentan los estados o modos de operación siguientes: The unipolar capacities of both subsystems (76, 75) and (77, 78) may be composed of one or a set of capacitors that provide a given total capacity. Likewise, each of the proposed subsystems (90 and 91) integrates an electronic management system (80 and 81) correctly associated with its reference potential (Po) that allows the correct operation of the subsystem and its communication (83 and 84) ( 85 and 86) with one or more higher order control systems. This communication (83 and 84) (85 and 86) can be performed using optical fibers or other technologies that allow isolation and proper functionality between the subsystems and the upper control devices. The electrical circuits that are part of the subsystems (90 and 91) detailed in Figures 9a and 9b have the following states or modes of operation:
- Control I: los interruptores (51 y 53) o (59 y 61 ) de los subsistemas (90 y 91 ) respectivamente están encendidos, y los interruptores (55 y 57) o (63 y 65) apagados. Como resultado, la tensión (Uy21 ) resultante en los terminales (y2 y y1 ) es igual a cero. _En este estado la energía en las capacidades (76 y 75) o (77 y 78) se mantiene constante.  - Control I: the switches (51 and 53) or (59 and 61) of the subsystems (90 and 91) respectively are on, and the switches (55 and 57) or (63 and 65) off. As a result, the resulting voltage (Uy21) at terminals (y2 and y1) is equal to zero. _In this state the energy in the capacities (76 and 75) or (77 and 78) remains constant.
- Control I I: los interruptores (53 y 55) o (61 y 63) están encendidos, mientras que los interruptores (51 y 57) o (59 y 65) se encuentran apagados. En este caso, se establece la tensión o potencial (UC) correspondiente a la de la capacidad (75) o (77) entre los terminales (y2, y1 ) de los subsistemas (90 y 91 ) respectivamente. En este estado, las capacidades (76 y 75) o (77 y 78) reciben o liberan energía en función de la dirección de la corriente que circula a través de los terminales del subsistema  - Control I I: switches (53 and 55) or (61 and 63) are on, while switches (51 and 57) or (59 and 65) are off. In this case, the voltage or potential (UC) corresponding to that of the capacity (75) or (77) between the terminals (y2, y1) of the subsystems (90 and 91) respectively is established. In this state, the capacities (76 and 75) or (77 and 78) receive or release energy depending on the direction of the current flowing through the subsystem terminals
- Control I I I, los interruptores (55 y 57) o (65 y 63) se encuentran encendidos y los interruptores (51 y 53) o (59 y 61 ) apagados. La tensión resultante (Uy21 ) en los terminales (y2, y1 ) de los subsistemas (90 y 91 ) corresponde con la suma de las tensiones o potenciales (UC) de cada una de las capacidades (76 y 75) o (77 y 78) respectivamente. En este estado, las capacidades (76 y 75) o (77 y 78) reciben o liberan energía en función de la dirección de la corriente que circula a través de los terminales del subsistema De forma similar, las Figuras 10a y 10b muestran detalladamente un segundo conjunto de diagramas eléctricos propuestos en esta invención para los subsistemas (90 y 91 ) correspondientes al circuito convertidor especificado anteriormente. Cada uno de los subsistemas superiores (90) detallados en la Figura 10a se caracterizan por un circuito eléctrico compuesto por cuatro interruptores (57, 55, 53 y 51 ) basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos (58, 56, 54 y 52), cada uno conectado eléctricamente en antiparalelo con cada interruptor (57, 55, 53 y 51 ), dos capacidades de almacenamiento unipolar (76 y 75) conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores (57, 55, 53 y 51 ) y unos primer y segundo interruptores adicionales de enlace o clamp (69b y 67b) con sus respectivos diodos en antiparalelo (70b y 68b). La unión entre el cátodo del diodo (70b) y el colector del interruptor (69b) se conecta entre la unión del emisor del interruptor (57) y el colector del interruptor (55) y la unión entre el ánodo del diodo (70b) y el emisor del interruptor (69b) en la unión (Po) entre las capacidades (76 y 75). Este punto de unión entre ambas capacidades (76 y 75) se define como (Po) o punto medio capacitivo. Por otro lado, la unión entre el ánodo del diodo (68b) y el emisor del interruptor (67b) se conecta entre la unión del emisor del interruptor (53) y el colector del interruptor (51 ) y la unión entre el cátodo del diodo (68b) y el colector del interruptor (67b) en la unión (Po) entre las capacidades (76 y 75). El terminal positivo de la capacidad (76) se conecta al colector del interruptor (57) y el terminal negativo de la capacidad (75) se conecta al emisor del interruptor (51 ). En los subsistemas (90) superiores de la Figura 10a, el terminal (y2) se conecta en la unión entre el emisor del interruptor (55), el colector del interruptor (53), el ánodo del diodo (56) y el cátodo del diodo (54). El terminal (y1 ) se conecta en la unión entre el emisor del interruptor (51 ), el terminal negativo de la capacidad unipolar (75) y el ánodo del diodo (52). - Control III, the switches (55 and 57) or (65 and 63) are on and the switches (51 and 53) or (59 and 61) are off. The resulting voltage (Uy21) at the terminals (y2, y1) of the subsystems (90 and 91) corresponds to the sum of the voltages or potentials (UC) of each of the capacities (76 and 75) or (77 and 78 ) respectively. In this state, the capacities (76 and 75) or (77 and 78) receive or release energy depending on the direction of the current flowing through the subsystem terminals Similarly, Figures 10a and 10b show in detail a second set of diagrams electrical systems proposed in this invention for the subsystems (90 and 91) corresponding to the converter circuit specified above. Each of the upper subsystems (90) detailed in Figure 10a is characterized by an electrical circuit consisting of four switches (57, 55, 53 and 51) based on semiconductor devices, which can be controlled both on and off. and four diodes (58, 56, 54 and 52) are electrically connected in series, each electrically connected in antiparallel with each switch (57, 55, 53 and 51), two unipolar storage capacities (76 and 75) connected electrically in series with each other and in parallel with the four switches (57, 55, 53 and 51) and some first and second additional link or clamp switches (69b and 67b) with their respective antiparallel diodes (70b and 68b). The junction between the diode cathode (70b) and the switch manifold (69b) is connected between the switch emitter junction (57) and the switch manifold (55) and the junction between the diode anode (70b) and the emitter of the switch (69b) at the junction (Po) between the capacities (76 and 75). This junction point between both capacities (76 and 75) is defined as (Po) or capacitive midpoint. On the other hand, the junction between the diode anode (68b) and the switch emitter (67b) is connected between the switch emitter junction (53) and the switch manifold (51) and the junction between the diode cathode (68b) and the switch manifold (67b) at the junction (Po) between the capacities (76 and 75). The positive capacity terminal (76) is connected to the switch manifold (57) and the negative capacity terminal (75) is connected to the emitter of the switch (51). In the upper subsystems (90) of Figure 10a, the terminal (y2) is connects at the junction between the emitter of the switch (55), the collector of the switch (53), the anode of the diode (56) and the cathode of the diode (54). The terminal (y1) is connected at the junction between the emitter of the switch (51), the negative terminal of the unipolar capacity (75) and the anode of the diode (52).
Por otro lado, cada uno de los subsistemas inferiores (91 ) detallados en la Figura 10b se caracterizan por un circuito eléctrico compuesto por cuatro interruptores (59, 61 , 63 y 65) basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos (60, 62, 64 y 66), cada uno conectado eléctricamente en antiparalelo con cada interruptor (59, 61 , 63 y 65), dos capacidades de almacenamiento unipolar (77 y 78) conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores (59, 61 , 63 y 65) y dos interruptores adicionales de enlace o clamp (71 b y 73b) con sus respectivos diodos en antiparalelo (72b y 74b). La unión entre el cátodo del diodo (72b) y el colector del interruptor (71 b) se conecta entre la unión del emisor del interruptor (59) y el colector del interruptor (61 ) y la unión entre el ánodo del diodo (72) y el emisor del interruptor (71 b) el en la unión (Po) entre las capacidades (77 y 78). Este punto de unión entre ambas capacidades (77 y 78) se define como (Po) o punto medio capacitivo. Por otro lado, la unión entre el ánodo del diodo (74b) y el emisor del interruptor (73b) se conecta entre la unión del emisor del interruptor (63) y el colector del interruptor (65) y la unión entre el cátodo del diodo (74b) y el colector del interruptor (73b) en la unión (Po) entre las capacidades (77 y 78). El terminal positivo de la capacidad (77) se conecta al colector del interruptor (59) y el terminal negativo de la capacidad (78) se conecta al emisor del interruptor (65). En los subsistemas (91 ) inferiores de la Figura 10b, el terminal (y2) se conectan en la unión entre el colector del interruptor (59), el terminal positivo de la capacidad unipolar (77) y el cátodo del diodo (60). El terminal (y1 ) se conecta en la unión entre el emisor del interruptor (61 ), el colector del interruptor (63), el ánodo del diodo (62) y el cátodo del diodo (64). On the other hand, each of the lower subsystems (91) detailed in Figure 10b are characterized by an electrical circuit consisting of four switches (59, 61, 63 and 65) based on semiconductor devices, which can be controlled both in their ignition as in the shutdown and four diodes (60, 62, 64 and 66) are connected electrically in series, each electrically connected in antiparallel with each switch (59, 61, 63 and 65), two unipolar storage capacities (77 and 78) electrically connected in series with each other and in parallel with the four switches (59, 61, 63 and 65) and two additional link or clamp switches (71 b and 73b) with their respective diodes in antiparallel (72b and 74b). The junction between the diode cathode (72b) and the switch manifold (71 b) is connected between the switch emitter junction (59) and the switch manifold (61) and the junction between the diode anode (72) and the emitter of the switch (71 b) on the junction (Po) between the capacities (77 and 78). This junction point between both capacities (77 and 78) is defined as (Po) or capacitive midpoint. On the other hand, the junction between the anode of the diode (74b) and the emitter of the switch (73b) is connected between the junction of the emitter of the switch (63) and the collector of the switch (65) and the junction between the cathode of the diode (74b) and the switch manifold (73b) at the junction (Po) between the capacities (77 and 78). The positive capacity terminal (77) is connected to the switch manifold (59) and the negative capacity terminal (78) is connected to the emitter of the switch (65). In the lower subsystems (91) of Figure 10b, the terminal (y2) is connected at the junction between the switch collector (59), the positive terminal of the unipolar capacity (77) and the diode cathode (60). The terminal (y1) is connects at the junction between the emitter of the switch (61), the collector of the switch (63), the anode of the diode (62) and the cathode of the diode (64).
Al igual que en las Figuras 9a y 9b, las capacidades unipolares de ambos subsistemas (76, 75) y (77, 78) representados en las Figuras 10a y 10b, pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad total determinada. De forma equivalente, cada uno de los subsistemas (90 y 91 ) propuestos integra un sistema electrónico de gestión (80 y 81 ) correctamente asociado a su potencial de referencia (Po) que permita la correcta operación del subsistema y su comunicación (83 y 84) (85 y 86) con uno o varios sistemas de control de orden superior. Esta comunicación (83 y 84) (85 y 86) puede realizarse utilizando fibras ópticas u otras tecnologías que permitan el aislamiento y la funcionalidad adecuada entre los subsistemas y los dispositivos de control superior. As in Figures 9a and 9b, the unipolar capacities of both subsystems (76, 75) and (77, 78) represented in Figures 10a and 10b, may be composed of one or a set of capacitors that provide a total capacity determined. Equivalently, each of the proposed subsystems (90 and 91) integrates an electronic management system (80 and 81) correctly associated with its reference potential (Po) that allows the correct operation of the subsystem and its communication (83 and 84 ) (85 and 86) with one or more higher order control systems. This communication (83 and 84) (85 and 86) can be performed using optical fibers or other technologies that allow isolation and proper functionality between the subsystems and the upper control devices.
Los circuitos eléctricos que forman parte de los subsistemas (90 y 91 ) detallados en las Figuras 10a y 10b presentan al menos los seis estados de operación siguientes: The electrical circuits that are part of the subsystems (90 and 91) detailed in Figures 10a and 10b have at least the following six operating states:
- Control I: los interruptores (51 , 53 y 69b) o (59, 61 y 73b) de los subsistemas (90 y 91 ) respectivamente están encendidos, y los interruptores (55, 57 y 67b) o (63, 65 y 71 b) apagados. Como resultado, la tensión (Uy21 ) resultante en los terminales (y2 y y1 ) es igual a cero.  - Control I: the switches (51, 53 and 69b) or (59, 61 and 73b) of the subsystems (90 and 91) respectively are on, and the switches (55, 57 and 67b) or (63, 65 and 71 b) off. As a result, the resulting voltage (Uy21) at terminals (y2 and y1) is equal to zero.
- Control I I: los interruptores (53 y 67b) o (61 y 71 b) están encendidos, mientras que los interruptores (51 , 55, 57 y 69b) o (59, 63, 65 y 73b) se encuentran apagados.  - Control I I: the switches (53 and 67b) or (61 and 71 b) are on, while the switches (51, 55, 57 and 69b) or (59, 63, 65 and 73b) are off.
- Control I I I: los interruptores (51 , 55 y 69b) o (59, 63 y 73b) están encendidos, mientras que los interruptores (53, 57 y 67b) o (61 , 65 y 71 b) se encuentran apagados. - Control IV: los interruptores (55 y 69) o (63 y 73) están encendidos, mientras que los interruptores (51 , 53, 57 y 67b) o (59, 61 , 65 y 71 b) se encuentran apagados. - Control III: the switches (51, 55 and 69b) or (59, 63 and 73b) are on, while the switches (53, 57 and 67b) or (61, 65 and 71 b) are off. - Control IV: the switches (55 and 69) or (63 and 73) are on, while the switches (51, 53, 57 and 67b) or (59, 61, 65 and 71 b) are off.
- Control V: los interruptores (53, 57 y 67b) o (61 , 65 y 71 b) están encendidos, mientras que los interruptores (51 , 55, y 69b) o (59, 63 y 73b) se encuentran apagados. En estos cuatro últimos casos, se establece la tensión o potencial (UC) correspondiente a la de la capacidad (75) o (77) entre los terminales (y2, y1 ) de los subsistemas (90 y 91 ) respectivamente.  - Control V: the switches (53, 57 and 67b) or (61, 65 and 71 b) are on, while the switches (51, 55, and 69b) or (59, 63 and 73b) are off. In these last four cases, the voltage or potential (UC) corresponding to the capacity (75) or (77) between the terminals (y2, y1) of the subsystems (90 and 91) respectively is established.
- Control VI: los interruptores (55, 57 y 67b) o (63, 65 y 71 b) se encuentran encendidos y los interruptores (51 , 53 y 69b) o (59, 61 y 73b) apagados. La tensión resultante (Uy21 ) en los terminales (y2, y1 ) de los subsistemas (90 y 91 ) corresponde con la suma de las tensiones o potenciales (UC) de cada una de las capacidades (76 y 75) o (77 y 78) respectivamente.  - Control VI: switches (55, 57 and 67b) or (63, 65 and 71 b) are on and switches (51, 53 and 69b) or (59, 61 and 73b) are off. The resulting voltage (Uy21) at the terminals (y2, y1) of the subsystems (90 and 91) corresponds to the sum of the voltages or potentials (UC) of each of the capacities (76 and 75) or (77 and 78 ) respectively.
En los estados de control I I, I I I, IV, V y VI, el almacén de energía formado por las capacidades (76 y 75) o (77 y 78) recibe o libera energía en función de la dirección de la corriente que circula a través de los terminales del subsistema. En el estado de control I, la energía en las capacidades (76 y 75) o (77 y 78) se mantiene constante. In control states II, III, IV, V and VI, the energy store formed by the capacities (76 and 75) or (77 and 78) receives or releases energy depending on the direction of the current flowing through of the subsystem terminals. In the control state I, the energy in the capacities (76 and 75) or (77 and 78) remains constant.
Las Figuras 1 1 a y 1 1 b muestran detalladamente un tercer conjunto de diagramas eléctricos propuestos en esta invención para los subsistemas (90 y 91 ) correspondientes al circuito convertidor especificado inicialmente. Cada uno de los subsistemas superiores (90) detallados en la Figura 1 1 a se caracterizan por un circuito eléctrico compuesto por cuatro interruptores (57, 55, 53 y 51 ) basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos (58, 56, 54 y 52), cada uno conectado eléctricamente en antiparalelo con cada interruptor (57, 55, 53 y 51 ), dos capacidades de almacenamiento unipolar (76 y 75) conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores (57, 55, 53 y 51 ) y dos interruptores adicionales de enlace o clamp (67c y 69c) dispuestos opuestamente en serie con sus respectivos diodos en antiparalelo (70c y 68c). La unión entre el cátodo del diodo (70c) y el colector del interruptor (67c) se conecta entre la unión del emisor del interruptor (55) y el colector del interruptor (53) y la unión entre el ánodo del diodo (70c) y el emisor del interruptor (67c) en la unión entre el ánodo del diodo (68c) y el emisor del interruptor (69c). Por otro lado, la unión entre el cátodo del diodo (68c) y el colector del interruptor (69c) se conecta en la unión (Po) entre las capacidades (76 y 75). Este punto de enlace entre ambas capacidades (76 y 75) se define como (Po) o punto medio capacitivo. El terminal positivo de la capacidad (76) se conecta al colector del interruptor (57) y el terminal negativo de la capacidad (75) se conecta al emisor del interruptor (51 ). En los subsistemas (90) superiores de la Figura 1 1 a, el terminal (y2) se conecta en la unión entre el emisor del interruptor (55), el colector del interruptor (53), el colector del interruptor (67c), el ánodo del diodo (56), el cátodo del diodo (70c) y el cátodo del diodo (54). El terminal (y1 ) se conecta en la unión entre el emisor del interruptor (51 ), el terminal negativo de la capacidad unipolar (75) y el ánodo del diodo (52). Figures 1 1 a and 1 1 b show in detail a third set of electrical diagrams proposed in this invention for the subsystems (90 and 91) corresponding to the converter circuit specified initially. Each of the upper subsystems (90) detailed in Figure 1 1 a are characterized by an electrical circuit consisting of four switches (57, 55, 53 and 51) based on semiconductor devices, which can be controlled both on and on the shutdown and are connected electrically in series, four diodes (58, 56, 54 and 52), each electrically connected in antiparallel with each switch (57, 55, 53 and 51), two unipolar storage capacities (76 and 75) electrically connected in series with each other and in parallel with the four switches (57, 55, 53 and 51) and two additional link or clamp switches (67c and 69c) arranged opposite in series with their respective antiparallel diodes (70c and 68c). The junction between the diode cathode (70c) and the switch manifold (67c) is connected between the switch emitter junction (55) and the switch manifold (53) and the junction between the diode anode (70c) and the emitter of the switch (67c) at the junction between the anode of the diode (68c) and the emitter of the switch (69c). On the other hand, the junction between the diode cathode (68c) and the switch manifold (69c) is connected at the junction (Po) between the capacities (76 and 75). This link point between both capacities (76 and 75) is defined as (Po) or capacitive midpoint. The positive capacity terminal (76) is connected to the switch manifold (57) and the negative capacity terminal (75) is connected to the emitter of the switch (51). In the upper subsystems (90) of Figure 1 1 a, the terminal (y2) is connected at the junction between the switch emitter (55), the switch manifold (53), the switch manifold (67c), the diode anode (56), diode cathode (70c) and diode cathode (54). The terminal (y1) is connected at the junction between the emitter of the switch (51), the negative terminal of the unipolar capacity (75) and the anode of the diode (52).
De forma análoga, cada uno de los subsistemas inferiores (91 ) detallados en la Figura 1 1 b se caracterizan por un circuito eléctrico compuesto por cuatro interruptores (59, 61 , 63 y 65) basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos (60, 62, 64 y 66), cada uno conectado eléctricamente en antiparalelo con cada interruptor (59, 61 , 63 y 65), dos capacidades de almacenamiento unipolar (77 y 78) conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores (59, 61 , 63 y 65) y dos interruptores adicionales de enlace o clamp (71 c y 73c) dispuestos opuestamente en serie con sus respectivos diodos en antiparalelo (72c y 74c). La unión entre el cátodo del diodo (72c) y el colector del interruptor (71 c) se conecta entre la unión del emisor del interruptor (61 ) y el colector del interruptor (63) y la unión entre el ánodo del diodo (72c) y el emisor del interruptor (71 c) se conecta en la unión entre el ánodo del diodo (74c) y el emisor del interruptor (73c). Por otro lado, la unión del colector del interruptor (73c) y el cátodo del diodo (74c) se conecta en la unión (Po) entre las capacidades (77 y 78). Este punto de enlace entre ambas capacidades (77 y 78) se define como (Po) o punto medio capacitivo. El terminal positivo de la capacidad (77) se conecta al colector del interruptor (59) y el terminal negativo de la capacidad (78) se conecta al emisor del interruptor (65). En los subsistemas (91 ) inferiores de la Figura 1 1 b, el terminal (y2) se conectan en la unión entre el colector del interruptor (59), el terminal positivo de la capacidad unipolar (77) y el cátodo del diodo (60). El terminal (y1 ) se conecta en la unión entre el emisor del interruptor (61 ), el colector del interruptor (63), el colector del interruptor (71 c), el ánodo del diodo (62), el cátodo del diodo (72c) y el cátodo del diodo (64). Similarly, each of the lower subsystems (91) detailed in Figure 1 1 b is characterized by an electrical circuit consisting of four switches (59, 61, 63 and 65) based on semiconductor devices, which can be controlled both in their ignition as in the off and four diodes (60, 62, 64 and 66) are connected electrically in series, each electrically connected in antiparallel with each switch (59, 61, 63 and 65), two unipolar storage capacities (77 and 78) connected electrically in series with each other and in parallel with the four switches (59, 61, 63 and 65) and two additional link or clamp switches (71 c and 73c) arranged opposite in series with their respective antiparallel diodes (72c and 74c). The junction between the diode cathode (72c) and the switch manifold (71 c) is connected between the switch emitter junction (61) and the switch manifold (63) and the junction between the diode anode (72c) and the emitter of the switch (71 c) is connected at the junction between the anode of the diode (74c) and the emitter of the switch (73c). On the other hand, the junction of the switch manifold (73c) and the diode cathode (74c) is connected at the junction (Po) between the capacities (77 and 78). This link point between both capacities (77 and 78) is defined as (Po) or capacitive midpoint. The positive capacity terminal (77) is connected to the switch manifold (59) and the negative capacity terminal (78) is connected to the emitter of the switch (65). In the lower subsystems (91) of Figure 1 1 b, the terminal (y2) is connected at the junction between the switch manifold (59), the positive terminal of the unipolar capacity (77) and the diode cathode (60 ). The terminal (y1) is connected at the junction between the emitter of the switch (61), the collector of the switch (63), the collector of the switch (71 c), the anode of the diode (62), the cathode of the diode (72c ) and the cathode of the diode (64).
Al igual que en los conjuntos previos propuestos en esta invención, las capacidades unipolares de ambos subsistemas (76, 75) y (77, 78) representados en las Figuras 1 1 a y 1 1 b, pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad total determinada. Del mismo modo, cada uno de los subsistemas (90 y 91 ) propuestos integra un sistema electrónico de gestión (80 y 81 ) correctamente asociado a su potencial de referencia (Po) que permita la correcta operación del subsistema y su comunicación (83 y 84) (85 y 86) con uno o varios sistemas de control de orden superior. Esta comunicación (83 y 84) (85 y 86) puede realizarse utilizando fibras ópticas u otras tecnologías que permitan el aislamiento y la funcionalidad adecuada entre los subsistemas y los dispositivos de control superior. Los circuitos eléctricos que forman parte de los subsistemas (90 y 91 ) detallados en las Figuras 1 1 a y 1 1 b presentan fundamentalmente tres estados de operación: As in the previous sets proposed in this invention, the unipolar capacities of both subsystems (76, 75) and (77, 78) represented in Figures 1 1 a and 1 1 b, may be composed of one or a set of capacitors that provide a certain total capacity. Similarly, each of the proposed subsystems (90 and 91) integrates an electronic management system (80 and 81) correctly associated with its reference potential (Po) that allows the correct operation of the subsystem and its communication (83 and 84 ) (85 and 86) with one or more higher order control systems. This communication (83 and 84) (85 and 86) can be done using optical fibers or other technologies that allow isolation and proper functionality between subsystems and superior control devices. The electrical circuits that are part of the subsystems (90 and 91) detailed in Figures 1 1 a and 1 1 b have essentially three operating states:
- Control I: los interruptores (51 y 53) o (59 y 61 ) de los subsistemas (90 y 91 ) respectivamente están encendidos, y los interruptores (55, 57, 67c y 69c) o (63, 65, 71 c y 73c) apagados. Como resultado, la tensión (Uy21 ) resultante en los terminales (y2 y y1 ) es igual a cero.  - Control I: the switches (51 and 53) or (59 and 61) of the subsystems (90 and 91) respectively are on, and the switches (55, 57, 67c and 69c) or (63, 65, 71 c and 73c ) off. As a result, the resulting voltage (Uy21) at terminals (y2 and y1) is equal to zero.
- Control I I: los interruptores (67c y 69c) o (71 c y 73c) están encendidos, mientras que los interruptores (51 , 53, 55 y 57) o (59, 61 , 63 y 65) se encuentran apagados. En este caso, se establece la tensión o potencial (UC) correspondiente a la de la capacidad (75) o (77) entre los terminales (y2, y1 ) de los subsistemas (90 y 91 ) respectivamente.  - Control I I: the switches (67c and 69c) or (71 c and 73c) are on, while the switches (51, 53, 55 and 57) or (59, 61, 63 and 65) are off. In this case, the voltage or potential (UC) corresponding to that of the capacity (75) or (77) between the terminals (y2, y1) of the subsystems (90 and 91) respectively is established.
- Control I I I, los interruptores (55 y 57) o (63 y 65) se encuentran encendidos y los interruptores (51 , 53, 67c y 69c) o (59, 61 , 71 c y 73c) apagados. La tensión resultante (Uy21 ) en los terminales (y2, y1 ) de los subsistemas (90 y 91 ) corresponde con la suma de las tensiones o potenciales (UC) de cada una de las capacidades (76 y 75) o (77 y 78) respectivamente. En los estados de control I I y II I, el almacén de energía formado por las capacidades (76 y 75) o (77 y 78) recibe o libera energía en función de la dirección de la corriente que circula a través de los terminales del subsistema. En el estado de control I, la energía en las capacidades (76 y 75) o (77 y 78) se mantiene constante. Por último, las Figuras 12a y 12b muestran detalladamente un cuarto conjunto de diagramas eléctricos propuestos en esta invención para los subsistemas (90 y 91 ) correspondientes al circuito convertidor especificado inicialmente. Cada uno de los subsistemas superiores (90) detallados en la Figura 12a se caracterizan por un circuito eléctrico compuesto por cuatro interruptores (57, 55, 53 y 51 ) basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos (58, 56, 54 y 52), cada uno conectado eléctricamente en antiparalelo con cada interruptor (57, 55, 53 y 51 ), dos capacidades de almacenamiento unipolar (76 y 75) conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores (57, 55, 53 y 51 ) y una capacidad adicional flotante (74d) dispuesta en paralelo con los interruptores (55 y 53). Concretamente, el terminal positivo de la capacidad (76) se conecta al colector del interruptor (57) y el terminal negativo de la capacidad (75) se conecta al emisor del interruptor (51 ). El punto de enlace entre ambas capacidades (75 y 76) se define como (Po) o punto medio capacitivo. Por otro lado, el Terminal positivo de la capacidad (74d) se conecta en la unión entre el emisor del interruptor (57) y el colector del interruptor (55), mientras que el Terminal negativo se conecta en la unión entre el emisor del interruptor (53) y el colector del interruptor (51 ). En los subsistemas (90) superiores de la Figura 12a, el terminal (y2) se conecta en la unión entre el emisor del interruptor (55), el colector del interruptor (53), el ánodo del diodo (56) y el cátodo del diodo (54). El terminal (y1 ) se conecta en la unión entre el emisor del interruptor (51 ), el terminal negativo de la capacidad unipolar (75) y el ánodo del diodo (52). - Control III, the switches (55 and 57) or (63 and 65) are on and the switches (51, 53, 67c and 69c) or (59, 61, 71 c and 73c) off. The resulting voltage (Uy21) at the terminals (y2, y1) of the subsystems (90 and 91) corresponds to the sum of the voltages or potentials (UC) of each of the capacities (76 and 75) or (77 and 78 ) respectively. In control states II and II I, the energy store formed by the capacities (76 and 75) or (77 and 78) receives or releases energy depending on the direction of the current flowing through the terminals of the subsystem . In the control state I, the energy in the capacities (76 and 75) or (77 and 78) remains constant. Finally, Figures 12a and 12b show in detail a fourth set of electrical diagrams proposed in this invention for the subsystems (90 and 91) corresponding to the initially specified converter circuit. Each of the upper subsystems (90) detailed in Figure 12a is characterized by an electrical circuit consisting of four switches (57, 55, 53 and 51) based on semiconductor devices, which can be controlled both on and off. and four diodes (58, 56, 54 and 52) are electrically connected in series, each electrically connected in antiparallel with each switch (57, 55, 53 and 51), two unipolar storage capacities (76 and 75) connected electrically in series with each other and in parallel with the four switches (57, 55, 53 and 51) and an additional floating capacity (74d) arranged in parallel with the switches (55 and 53). Specifically, the positive capacity terminal (76) is connected to the switch manifold (57) and the negative capacity terminal (75) is connected to the emitter of the switch (51). The link point between both capacities (75 and 76) is defined as (Po) or capacitive midpoint. On the other hand, the Positive Capacity Terminal (74d) is connected at the junction between the switch emitter (57) and the switch manifold (55), while the Negative Terminal is connected at the junction between the switch emitter (53) and the switch manifold (51). In the upper subsystems (90) of Figure 12a, the terminal (y2) is connected at the junction between the switch emitter (55), the switch manifold (53), the diode anode (56) and the cathode of the diode (54). The terminal (y1) is connected at the junction between the emitter of the switch (51), the negative terminal of the unipolar capacity (75) and the anode of the diode (52).
Simétricamente, cada uno de los subsistemas inferiores (91 ) detallados en la Figura 12b se caracterizan por un circuito eléctrico compuesto por cuatro interruptores (59, 61 , 63 y 65) basados en dispositivos semiconductores, que pueden ser controlados tanto en su encendido como en el apagado y se encuentran conectados eléctricamente en serie, cuatro diodos (60, 62, 64 y 66), cada uno conectado eléctricamente en antiparalelo con cada interruptor (59, 61 , 63 y 65), dos capacidades de almacenamiento unipolar (77 y 78) conectados eléctricamente en serie entre si y en paralelo con los cuatro interruptores (59, 61 , 63 y 65) y una capacidad adicional flotante (79d) dispuesta en paralelo los interruptores (61 y 63). El terminal positivo de la capacidad (77) se conecta al colector del interruptor (59) y el terminal negativo de la capacidad (78) se conecta al emisor del interruptor (65). El punto de enlace entre ambas capacidades (77 y 78) se define como (Po) o punto medio capacitivo. Por otro lado, el Terminal positivo de la capacidad (79d) se conecta en la unión entre el emisor del interruptor (59) y el colector del interruptor (61 ), mientras que el Terminal negativo se conecta en la unión entre el emisor del interruptor (63) y el colector del interruptor (65). En los subsistemas (91 ) inferiores de la Figura 12b, el terminal (y2) se conectan en la unión entre el colector del interruptor (59), el terminal positivo de la capacidad unipolar (77) y el cátodo del diodo (60). El terminal (y1 ) se conecta en la unión entre el emisor del interruptor (61 ), el colector del interruptor (63), el ánodo del diodo (62) y el cátodo del diodo (64). Symmetrically, each of the lower subsystems (91) detailed in Figure 12b is characterized by an electrical circuit consisting of four switches (59, 61, 63 and 65) based on semiconductor devices, which can be controlled both on and off and are electrically connected in series, four diodes (60, 62, 64 and 66), each electrically connected in antiparallel with each switch (59, 61, 63 and 65), two unipolar storage capacities (77 and 78) electrically connected in series with each other and in parallel with the four switches (59, 61, 63 and 65) and an additional floating capacity (79d) arranged in parallel with the switches ( 61 and 63). The positive capacity terminal (77) is connected to the switch manifold (59) and the negative capacity terminal (78) is connected to the emitter of the switch (65). The link point between both capacities (77 and 78) is defined as (Po) or capacitive midpoint. On the other hand, the Positive Capacity Terminal (79d) is connected at the junction between the switch emitter (59) and the switch manifold (61), while the Negative Terminal is connected at the junction between the switch emitter (63) and the switch manifold (65). In the lower subsystems (91) of Figure 12b, the terminal (y2) is connected at the junction between the switch collector (59), the positive terminal of the unipolar capacity (77) and the diode cathode (60). The terminal (y1) is connected at the junction between the emitter of the switch (61), the collector of the switch (63), the anode of the diode (62) and the cathode of the diode (64).
De forma equivalente a los conjuntos propuestos en esta invención, las capacidades unipolares que forman parte de estos subsistemas (74d, 76 y 75) y (77, 78 y 79d) representados en las Figuras 12a y 12b, pueden estar compuestas por uno o un conjunto de condensadores que proporcionen una capacidad total determinada. Del mismo modo, cada uno de los subsistemas (90 y 91 ) propuestos integra un sistema electrónico de gestión (80 y 81 ) correctamente asociado a su potencial de referencia (Po) que permita la correcta operación del subsistema y su comunicación (83 y 84) (85 y 86) con uno o varios sistemas de control de orden superior. Esta comunicación (83 y 84) (85 y 86) puede realizarse utilizando fibras ópticas u otras tecnologías que permitan el aislamiento y la funcionalidad adecuada entre los subsistemas y los dispositivos de control superior. Los circuitos eléctricos que forman parte de los subsistemas (90 y 91 ) detallados en las Figuras 12a y 12b presentan los cuatro estados de operación siguientes: Equivalent to the assemblies proposed in this invention, the unipolar capacities that are part of these subsystems (74d, 76 and 75) and (77, 78 and 79d) represented in Figures 12a and 12b, may be composed of one or a set of capacitors that provide a certain total capacity. Similarly, each of the proposed subsystems (90 and 91) integrates an electronic management system (80 and 81) correctly associated with its reference potential (Po) that allows the correct operation of the subsystem and its communication (83 and 84 ) (85 and 86) with one or more higher order control systems. This communication (83 and 84) (85 and 86) can be performed using optical fibers or other technologies that allow isolation and proper functionality between subsystems and superior control devices. The electrical circuits that are part of the subsystems (90 and 91) detailed in Figures 12a and 12b have the following four operating states:
- Control I, los interruptores (51 y 53) o (59 y 61 ) de los subsistemas (90 y 91 ) respectivamente están encendidos, y los interruptores (55 y 57) o (63 y 65) apagados. Como resultado, la tensión (Uy21 ) resultante en los terminales (y2 y y1 ) es igual a cero. En este estado, la energía en las capacidades (74d, 75 y 76) o (77, 78 y 79d) se mantiene constante.  - Control I, the switches (51 and 53) or (59 and 61) of the subsystems (90 and 91) respectively are on, and the switches (55 and 57) or (63 and 65) off. As a result, the resulting voltage (Uy21) at terminals (y2 and y1) is equal to zero. In this state, the energy in the capacities (74d, 75 and 76) or (77, 78 and 79d) remains constant.
- Control I I, los interruptores (51 y 55) o (59 y 63) están encendidos, mientras que los interruptores (53 y 57) o (61 y 65) se encuentran apagados. En este caso, se establece la tensión o potencial (UC) correspondiente a la de la capacidad (74d) o (79d) entre los terminales (y2, y1 ) de los subsistemas (90 y 91 ) respectivamente. En este estado, el almacén de energía formado por las capacidades (74d) o (79d) recibe o libera energía en función de la dirección de la corriente que circula a través de los terminales del subsistema, mientras que la energía en las capacidades (75 y 76) o (77 y 78) se mantiene constante.  - Control I I, the switches (51 and 55) or (59 and 63) are on, while the switches (53 and 57) or (61 and 65) are off. In this case, the voltage or potential (UC) corresponding to that of the capacity (74d) or (79d) between the terminals (y2, y1) of the subsystems (90 and 91) respectively is established. In this state, the energy store formed by the capacities (74d) or (79d) receives or releases energy depending on the direction of the current flowing through the terminals of the subsystem, while the energy in the capacities (75 and 76) or (77 and 78) remains constant.
- Control I II, los interruptores (53 y 57) o (61 y 65) están encendidos, mientras que los interruptores (51 y 55) o (59 y 63) se encuentran apagados. En este caso, se establece la tensión o potencial (UC) entre los terminales (y2, y1 ) correspondiente a la resultante de la resta entre los potenciales que agrupan las capacidades (76 y 75) o (77 y 78) y sus potenciales inversamente relacionados (74d) o (79d) respectivamente. En este estado, el almacén de energía resultante entre las capacidades (74d, 75 y 76) o (77, 78 y 79d) recibe o libera energía en función de la dirección de la corriente que circula a través de los terminales del subsistema. - Control I II, the switches (53 and 57) or (61 and 65) are on, while the switches (51 and 55) or (59 and 63) are off. In this case, the voltage or potential (UC) is established between the terminals (y2, y1) corresponding to the result of the subtraction between the potentials that group the capacities (76 and 75) or (77 and 78) and their potentials inversely related (74d) or (79d) respectively. In this state, the resulting energy store between capacities (74d, 75 and 76) or (77, 78 and 79d) receives or releases energy in function of the direction of the current flowing through the subsystem terminals.
- Control IV, los interruptores (55 y 57) o (63 y 65) se encuentran encendidos y los interruptores (51 y 53) o (59 y 61 ) apagados. La tensión resultante (Uy21 ) en los terminales (y2, y1 ) de los subsistemas (90 y 91 ) corresponde con la suma de las tensiones o potenciales (UC) de cada una de las capacidades (76 y 75) o (77 y 78) respectivamente. En este estado, el almacén de energía resultante entre las capacidades (75 y 76) o (77 y 78) recibe o libera energía en función de la dirección de la corriente que circula a través de los terminales del subsistema, mientras que la energía en las capacidades (74d) o (79d) se mantiene constante.  - Control IV, switches (55 and 57) or (63 and 65) are on and switches (51 and 53) or (59 and 61) off. The resulting voltage (Uy21) at the terminals (y2, y1) of the subsystems (90 and 91) corresponds to the sum of the voltages or potentials (UC) of each of the capacities (76 and 75) or (77 and 78 ) respectively. In this state, the resulting energy store between capacities (75 and 76) or (77 and 78) receives or releases energy depending on the direction of the current flowing through the terminals of the subsystem, while the energy in The capacities (74d) or (79d) remain constant.

Claims

REIVINDICACIONES
Un circuito convertidor que comprende al menos un módulo de fase (100) formado por un conjunto superior (95), que comprende al menos un subsistema superior (90) dotado de un par de terminales de conexión, y un conjunto inferior (96), que comprende al menos un subsistema inferior (91 ) dotado de otro par de terminales de conexión, caracterizado porque cada subsistema (90; 91 ) comprende: cuatro interruptores (51 , 53, 55, 57; 59, 61 , 63, 65) basados en dispositivos semiconductores que pueden ser controlados tanto en su encendido como en el apagado, conectados eléctricamente en serie, donde la unión entre los interruptores centrales (53, 55) y el emisor del interruptor inferior (51 ) constituyen los terminales de conexión del subsistema superior (90), y donde el colector del interruptor superior (59) y la unión entre los dos interruptores centrales (61 , 63) constituyen los terminales de conexión del subsistema inferior (91 ); cuatro diodos (52, 54, 56, 58; 60, 62, 64, 66), cada uno conectado eléctricamente en antiparalelo con cada interruptor (51 , 53, 55, 57; 59, 61 , 63, 65), dos capacidades (75, 76; 77, 78) de almacenamiento unipolar conectadas eléctricamente en serie entre si y en paralelo con los cuatro interruptores (51 , 53, 55, 57; 59, 61 , 63, 65); unos primer y segundo diodos de enlace (68a, 70a; 72a, 74a) , donde el primer diodo de enlace (70a; 72a) tiene el cátodo conectado entre la unión del emisor y colector de los dos interruptores superiores (55, 57; 59; 61 ) y el ánodo en la unión entre las dos capacidades (75, 76; 77, 78), y donde el segundo diodo de enlace (68a; 74a) tiene el ánodo conectado entre la unión del emisor y el colector de los dos interruptores inferiores (51 , 53; 63; 65) y el cátodo en la unión entre las dos capacidades (75, 76; 77, 78); y un sistema electrónico de gestión (80; 81 ) asociado a un potencial de referencia (Po) situado entre las dos capacidades (75, 76; 77, 78), que controla el funcionamiento del subsistema (90; 91 ) y permite su comunicación con un sistema de control de orden superior. A converter circuit comprising at least one phase module (100) formed by an upper assembly (95), comprising at least one upper subsystem (90) provided with a pair of connection terminals, and a lower assembly (96), comprising at least one lower subsystem (91) provided with another pair of connection terminals, characterized in that each subsystem (90; 91) comprises: four switches (51, 53, 55, 57; 59, 61, 63, 65) based in semiconductor devices that can be controlled both on and off, electrically connected in series, where the junction between the central switches (53, 55) and the emitter of the lower switch (51) constitute the connection terminals of the upper subsystem (90), and where the collector of the upper switch (59) and the junction between the two central switches (61, 63) constitute the connection terminals of the lower subsystem (91); four diodes (52, 54, 56, 58; 60, 62, 64, 66), each electrically connected in antiparallel with each switch (51, 53, 55, 57; 59, 61, 63, 65), two capacities ( 75, 76; 77, 78) of unipolar storage electrically connected in series with each other and in parallel with the four switches (51, 53, 55, 57; 59, 61, 63, 65); first and second link diodes (68a, 70a; 72a, 74a), where the first link diode (70a; 72a) has the cathode connected between the emitter and collector junction of the two upper switches (55, 57; 59; 61) and the anode at the junction between the two capacities (75, 76; 77, 78), and where the second link diode (68a; 74a) has the anode connected between the junction of the emitter and the collector of the two lower switches (51, 53; 63; 65) and the cathode at the junction between the two capacities (75, 76; 77, 78); and an electronic management system (80; 81) associated with a reference potential (Po) located between the two capacities (75, 76; 77, 78), which controls the operation of the subsystem (90; 91) and allows its communication With a higher order control system.
El circuito convertidor de la reivindicación 1 , que además comprende al menos un elemento electromagnético (30) que facilita la conexión entre los conjuntos superior (95) e inferior (96) y el polo positivo (P), el polo negativo (N) y/o el punto central (L). The converter circuit of claim 1, further comprising at least one electromagnetic element (30) that facilitates the connection between the upper (95) and lower (96) assemblies and the positive pole (P), the negative pole (N) and / or the center point (L).
El circuito convertidor de cualquiera de las reivindicaciones 1 -2, donde los interruptores (51 , 53, 55, 57; 59, 61 , 63, 65) están implementados mediante IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Integrated Gate Commutated Tyristor), GTOs (Gate turn-off Tyristor) y/o transistores de efecto de campo MOS. The converter circuit of any one of claims 1-2, wherein the switches (51, 53, 55, 57; 59, 61, 63, 65) are implemented by IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Integrated Gate Commutated Tyristor) , GTOs (Gate turn-off Tyristor) and / or MOS field effect transistors.
El circuito convertidor de cualquiera de las reivindicaciones 1 -3, que además comprende al menos una conexión (83, 84; 85, 86) de fibra óptica para la comunicación del sistema electrónico de gestión (80, 81 ) con el sistema de control de orden superior. The converter circuit of any one of claims 1-3, further comprising at least one fiber optic connection (83, 84; 85, 86) for communication of the electronic management system (80, 81) with the control system of higher order
Un circuito convertidor que comprende al menos un módulo de fase (100) formado por un conjunto superior (95), que comprende al menos un subsistema superior (90) dotado de un par de terminales de conexión, y un conjunto inferior (96), que comprende al menos un subsistema inferior (91 ) dotado de otro par de terminales de conexión, caracterizado porque cada subsistema (90; 91 ) comprende: cuatro interruptores (51 , 53, 55, 57; 59, 61 , 63, 65) basados en dispositivos semiconductores que pueden ser controlados tanto en su encendido como en el apagado, conectados eléctricamente en serie, donde la unión entre los interruptores centrales (53, 55) y el emisor del interruptor inferior (51 ) constituyen los terminales de conexión del subsistema superior (90), y donde el colector del interruptor superior (59) y la unión entre los dos interruptores centrales (61 , 63) constituyen los terminales de conexión del subsistema inferior (91 ); cuatro diodos (52, 54, 56, 58; 60, 62, 64, 66), cada uno conectado eléctricamente en antiparalelo con cada interruptor (51 , 53, 55, 57; 59, 61 , 63, 65), dos capacidades (75, 76; 77, 78) de almacenamiento unipolar conectadas eléctricamente en serie entre si y en paralelo con los cuatro interruptores (51 , 53, 55, 57; 59, 61 , 63, 65); unos primer y segundo interruptores de enlace (67b, 69b; 71 b,A converter circuit comprising at least one phase module (100) formed by an upper assembly (95), comprising the less an upper subsystem (90) provided with a pair of connection terminals, and a lower assembly (96), comprising at least one lower subsystem (91) provided with another pair of connection terminals, characterized in that each subsystem (90; 91) comprises: four switches (51, 53, 55, 57; 59, 61, 63, 65) based on semiconductor devices that can be controlled both on and off, electrically connected in series, where the union between the central switches (53, 55) and the transmitter of the lower switch (51) constitute the connection terminals of the upper subsystem (90), and where the collector of the upper switch (59) and the junction between the two central switches (61, 63 ) constitute the connection terminals of the lower subsystem (91); four diodes (52, 54, 56, 58; 60, 62, 64, 66), each electrically connected in antiparallel with each switch (51, 53, 55, 57; 59, 61, 63, 65), two capacities ( 75, 76; 77, 78) of unipolar storage electrically connected in series with each other and in parallel with the four switches (51, 53, 55, 57; 59, 61, 63, 65); first and second link switches (67b, 69b; 71b,
73b), donde el colector del primer interruptor de enlace (69b; 71 b) está conectado entre la unión del emisor y colector de los dos interruptores superiores (55, 57; 59, 61 ) y el emisor en la unión entre las capacidades (75, 76; 77, 78), y donde que el emisor del segundo interruptor de enlace (67b; 73b) está conectado entre la unión del emisor y el colector de los dos interruptores inferiores (51 , 53; 63, 65) y el colector en la unión entre las capacidades (75, 76; 77, 78); dos diodos (68b, 70b; 72b, 74b), cada uno conectado eléctricamente en antiparalelo con cada interruptor de enlace (67b, 69b; 71 b, 73b), y un sistema electrónico de gestión (80; 81 ) asociado a un potencial de referencia (Po) situado entre las dos capacidades (75, 76; 77, 78) que controla el funcionamiento del subsistema (90; 91 ) y su comunicación con un sistema de control de orden superior. 73b), where the collector of the first link switch (69b; 71 b) is connected between the transmitter and collector junction of the two upper switches (55, 57; 59, 61) and the transmitter in the junction between the capacities ( 75, 76; 77, 78), and where the emitter of the second link switch (67b; 73b) is connected between the transmitter junction and the collector of the two lower switches (51, 53; 63, 65) and the collector at the junction between the capacities (75, 76; 77, 78); two diodes (68b, 70b; 72b, 74b), each electrically connected in antiparallel with each link switch (67b, 69b; 71b, 73b), and an electronic management system (80; 81) associated with a potential reference (Po) located between the two capacities (75, 76; 77, 78) that controls the operation of the subsystem (90; 91) and its communication with a higher order control system.
El circuito convertidor de la reivindicación 5, que además comprende al menos un elemento electromagnético (30) que facilita la conexión entre los conjuntos superior (95) e inferior (96) y el polo positivo (P), el polo negativo (N) y/o el punto central (L). The converter circuit of claim 5, further comprising at least one electromagnetic element (30) that facilitates the connection between the upper (95) and lower (96) assemblies and the positive pole (P), the negative pole (N) and / or the center point (L).
El circuito convertidor de cualquiera de las reivindicaciones 5-6, donde los interruptores (51 , 53, 55, 57; 59, 61 , 63, 65) están implementados mediante IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Integrated Gate Commutated Tyristor), GTOs (Gate turn-off Tyristor) y/o transistores de efecto de campo MOS. The converter circuit of any one of claims 5-6, wherein the switches (51, 53, 55, 57; 59, 61, 63, 65) are implemented by IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Integrated Gate Commutated Tyristor) , GTOs (Gate turn-off Tyristor) and / or MOS field effect transistors.
El circuito convertidor de cualquiera de las reivindicaciones 5-7, que además comprende al menos una conexión (83, 84; 85, 86) de fibra óptica para la comunicación del sistema electrónico de gestión (80, 81 ) con el sistema de control de orden superior. The converter circuit of any one of claims 5-7, further comprising at least one fiber optic connection (83, 84; 85, 86) for communication of the electronic management system (80, 81) with the control system of higher order
Un circuito convertidor que comprende al menos un módulo de fase (100) formado por un conjunto superior (95), que comprende al menos un subsistema superior (90) dotado de un par de terminales de conexión, y un conjunto inferior (96), que comprende al menos un subsistema inferior (91 ) dotado de otro par de terminales de conexión, caracterizado porque cada subsistema (90; 91 ) comprende: cuatro interruptores (51 , 53, 55, 57; 59, 61 , 63, 65) basados en dispositivos semiconductores que pueden ser controlados tanto en su encendido como en el apagado, conectados eléctricamente en serie, donde la unión entre los interruptores centrales (53, 55) y el emisor del interruptor inferior (51 ) constituyen los terminales de conexión del subsistema superior (90) y donde el colector del interruptor superior (59) y la unión entre los dos interruptores centrales (61 , 63) constituyen los terminales de conexión del subsistema inferior (91 ); cuatro diodos (52, 54, 56, 58; 60, 62, 64, 66), cada uno conectado eléctricamente en antiparalelo con cada interruptor (51 , 53, 55, 57; 59, 61 , 63, 65), dos capacidades (75, 76; 77, 78) de almacenamiento unipolar conectadas eléctricamente en serie entre si y en paralelo con los cuatro interruptores (51 , 53, 55, 57; 59, 61 , 63, 65); un primer y segundo interruptores de enlace (67c, 69c; 71 c, 73c) dispuestos opuestamente en serie, donde el colector del primer interruptor está conectado entre la unión del emisor y colector de los dos interruptores centrales (53, 55; 61 , 63) y el emisor está conectado al emisor del segundo interruptor de enlace (69c, 73c), y donde el colector del segundo interruptor de enlace (69c, 73c) está conectado a la unión entre las capacidades (75, 76; 77, 78); dos diodos adicionales (70c, 68c; 72c, 74c), cada uno conectado eléctricamente en antiparalelo con cada interruptor de enlace (67c, 69c; 71 c, 73c), y un sistema electrónico de gestión (80; 81 ) asociado a un potencial de referencia (Po) situado entre las dos capacidades (75, 76; 77, 78) que controla el funcionamiento del subsistema (90; 91 ) y su comunicación con un sistema de control de orden superior. A converter circuit comprising at least one phase module (100) formed by an upper assembly (95), comprising at least one upper subsystem (90) provided with a pair of terminals of connection, and a lower assembly (96), comprising at least one lower subsystem (91) provided with another pair of connection terminals, characterized in that each subsystem (90; 91) comprises: four switches (51, 53, 55, 57; 59, 61, 63, 65) based on semiconductor devices that can be controlled both on and off, electrically connected in series, where the junction between the central switches (53, 55) and the lower switch emitter (51) constitute the connection terminals of the upper subsystem (90) and where the collector of the upper switch (59) and the junction between the two central switches (61, 63) constitute the connection terminals of the lower subsystem (91); four diodes (52, 54, 56, 58; 60, 62, 64, 66), each electrically connected in antiparallel with each switch (51, 53, 55, 57; 59, 61, 63, 65), two capacities ( 75, 76; 77, 78) of unipolar storage electrically connected in series with each other and in parallel with the four switches (51, 53, 55, 57; 59, 61, 63, 65); a first and second link switches (67c, 69c; 71 c, 73c) opposite each other in series, where the collector of the first switch is connected between the transmitter and collector junction of the two central switches (53, 55; 61, 63 ) and the transmitter is connected to the transmitter of the second link switch (69c, 73c), and where the collector of the second link switch (69c, 73c) is connected to the junction between the capacities (75, 76; 77, 78) ; two additional diodes (70c, 68c; 72c, 74c), each electrically connected in antiparallel with each link switch (67c, 69c; 71c, 73c), and an electronic management system (80; 81) associated with a potential reference (Po) located between the two capacities (75, 76; 77, 78) that controls the operation of the subsystem (90; 91) and its communication with a higher order control system.
El circuito convertidor de la reivindicación 9, que además comprende al menos un elemento electromagnético que facilita la conexión entre los conjuntos superior (95) e inferior (96) y el polo positivo (P), el polo negativo (N) y/o el punto central (L). 11 . El circuito convertidor de cualquiera de las reivindicaciones 9-10, donde los interruptores (51 , 53, 55, 57; 59, 61 , 63, 65) están implementados mediante IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Integrated Gate Commutated Tyristor), GTOs (Gate turn-off Tyristor) y/o transistores de efecto de campo MOS. The converter circuit of claim 9, further comprising at least one electromagnetic element that facilitates the connection between the upper (95) and lower (96) assemblies and the positive pole (P), the negative pole (N) and / or the center point (L). eleven . The converter circuit of any one of claims 9-10, wherein the switches (51, 53, 55, 57; 59, 61, 63, 65) are implemented by IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Integrated Gate Commutated Tyristor) , GTOs (Gate turn-off Tyristor) and / or MOS field effect transistors.
12. El circuito convertidor de cualquiera de las reivindicaciones 9-1 1 , que además comprende al menos una conexión (83, 84; 85, 86) de fibra óptica para la comunicación del sistema electrónico de gestión (80; 81 ) con el sistema de control de orden superior. 12. The converter circuit of any one of claims 9-1 1, further comprising at least one fiber optic connection (83, 84; 85, 86) for communication of the electronic management system (80; 81) with the system of higher order control.
13. Un circuito convertidor que comprende al menos un módulo de fase (100) formado por un conjunto superior (95), que comprende al menos un subsistema superior (90) dotado de un par de terminales de conexión, y un conjunto inferior (96), que comprende al menos un subsistema inferior (91 ) dotado de otro par de terminales de conexión, caracterizado porque cada subsistema (90; 91 ) comprende: cuatro interruptores (51 , 53, 55, 57; 59, 61 , 63, 65) basados en dispositivos semiconductores que pueden ser controlados tanto en su encendido como en el apagado, conectados eléctricamente en serie, donde la unión entre los interruptores centrales (53, 55) y el emisor del interruptor inferior (51 ) constituyen los terminales de conexión del subsistema superior (90), y donde el colector del interruptor superior (59) y la unión entre los dos interruptores centrales (61 , 63) constituyen los terminales de conexión del subsistema inferior (91 ); cuatro diodos (52, 54, 56, 58; 60, 62, 64, 66), cada uno conectado eléctricamente en antiparalelo con cada interruptor (51 , 53, 55, 57; 59, 61 , 63, 65), dos capacidades (75, 76; 77, 78) de almacenamiento unipolar conectadas eléctricamente en serie entre si y en paralelo con los cuatro interruptores (51 , 53, 55, 57; 59, 61 , 63, 65); una capacidad flotante (74d; 79d) conectada eléctricamente en paralelo con los dos interruptores centrales (53, 55; 61 , 63); y un sistema electrónico de gestión (80; 81 ) asociado a un potencial de referencia (Po) situado entre las dos capacidades (75, 76; 77, 78), que controla el funcionamiento del subsistema (90, 91 ) y permite su comunicación con un sistema de control de orden superior. El circuito convertidor de la reivindicación 13, que además comprende al menos un elemento electromagnético (30) que facilita la conexión entre los conjuntos superior (95) e inferior (96) y el polo positivo (P), el polo negativo (N) y punto central (L). 13. A converter circuit comprising at least one phase module (100) formed by an upper assembly (95), comprising at least one upper subsystem (90) provided with a pair of connection terminals, and a lower assembly (96 ), comprising at least one lower subsystem (91) provided with another pair of terminals connection, characterized in that each subsystem (90; 91) comprises: four switches (51, 53, 55, 57; 59, 61, 63, 65) based on semiconductor devices that can be controlled both on and off, connected electrically in series, where the junction between the central switches (53, 55) and the emitter of the lower switch (51) constitute the connection terminals of the upper subsystem (90), and where the collector of the upper switch (59) and the junction between the two central switches (61, 63) constitute the connection terminals of the lower subsystem (91); four diodes (52, 54, 56, 58; 60, 62, 64, 66), each electrically connected in antiparallel with each switch (51, 53, 55, 57; 59, 61, 63, 65), two capacities ( 75, 76; 77, 78) of unipolar storage electrically connected in series with each other and in parallel with the four switches (51, 53, 55, 57; 59, 61, 63, 65); a floating capacity (74d; 79d) electrically connected in parallel with the two central switches (53, 55; 61, 63); and an electronic management system (80; 81) associated with a reference potential (Po) located between the two capacities (75, 76; 77, 78), which controls the operation of the subsystem (90, 91) and allows its communication With a higher order control system. The converter circuit of claim 13, further comprising at least one electromagnetic element (30) that facilitates the connection between the upper (95) and lower (96) assemblies and the positive pole (P), the negative pole (N) and center point (L).
El circuito convertidor de cualquiera de las reivindicaciones 13-14, donde los interruptores (51 , 53, 55, 57; 59, 61 , 63, 65) son implementados mediante IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Integrated Gate Commutated Tyristor), GTOs (Gate turn-off Tyristor) y/o transistores de efecto de campo MOS. The converter circuit of any of claims 13-14, wherein the switches (51, 53, 55, 57; 59, 61, 63, 65) are implemented by IGBTs (Insulated Gate Bipolar Transistor), IGCTs (Integrated Gate Commutated Tyristor) , GTOs (Gate turn-off Tyristor) and / or MOS field effect transistors.
El circuito convertidor de cualquiera de las reivindicaciones 13-15, que además comprende al menos una conexión (83, 83; 85, 86) de fibra óptica para la comunicación del sistema electrónico de gestión (80; 81 ) con el sistema de control de orden superior. The converter circuit of any one of claims 13-15, further comprising at least one fiber optic connection (83, 83; 85, 86) for communication of the electronic management system (80; 81) with the control system of higher order
Un circuito convertidor que comprende al menos un módulo de fase (100) formado por un conjunto superior (95) y otro inferior (96), compuestos por cualquier combinación de los subsistemas de las reivindicaciones 1 , 5, 9 o 13, caracterizado porque los terminales de conexión de los subsistemas superiores e inferiores (90 y 91 ) son equivalentes y se realizan entre los dos interruptores centrales y el punto medio capacitivo. 18. Un circuito convertidor híbrido que comprende al menos un módulo de fase (100) formado por un conjunto superior (95), que comprende al menos dos subsistemas superiores (90), y un conjunto inferior (96), que comprende al menos dos subsistemas inferiores (91 ), caracterizado porque los subsistemas comprenden cualquier combinación de los subsistemas de las reivindicaciones 1 , 5, 9, 13 oA converter circuit comprising at least one phase module (100) formed by an upper assembly (95) and a lower one (96), composed of any combination of the subsystems of claims 1, 5, 9 or 13, characterized in that the connection terminals of the upper and lower subsystems (90 and 91) are equivalent and are made between the two central switches and the capacitive midpoint. 18. A hybrid converter circuit comprising at least one phase module (100) formed by an upper assembly (95), comprising at least two upper subsystems (90), and a lower assembly (96), comprising at least two lower subsystems (91), characterized in that the subsystems comprise any combination of the subsystems of claims 1, 5, 9, 13 or
17. 17.
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