WO2010086077A1

WO2010086077A1 - Method for assigning a target to a configurable oscillator of a phase-locked loop

Info

Publication number: WO2010086077A1
Application number: PCT/EP2009/067880
Authority: WO
Inventors: Serge Defrance; Emmanuel Jolly; Thierry Tapie
Original assignee: Thomson Licensing
Priority date: 2009-01-30
Filing date: 2009-12-23
Publication date: 2010-08-05

Abstract

The present invention relates to, a method for assigning a target (CSG) to a configurable oscillator (VCO) of a phase-locked loop (PLL), the phase-locked loop (PLL) receiving samples (PCRr, PCR1r, PCR2r) of a first signal realised according to a sampling clock (CLKech) and producing local samples (PCR_Loc, PCR_Loc1, PCR_Loc2) of a second signal, said phase-locked loop (PLL) also producing the second signal from a reconstituted clock (CLK_out) delivered by the configurable oscillator (VCO), the target (CSG) of the phase-locked loop (PLL) having by default a value equal to CSGinit. According to the invention, at the start-up of said phase-locked loop (PLL), it comprises: - a step (10) to memorise a value of a sample (PCR1r) received and a local sample value (PCR_Loc1) produced at a time t1 where the sample (PCR1r) is valid and the value of the target (CSG) is set at a value CSGinit, - a step (20) to memorise a sample value (PCR2r) received following the sample (PCR1r) and a local sample value (PCR_Loc2) produced at a time t2 where the sample (PCR2r) is valid and the value of the target (CSG) is set at the value 20 CSGinit, - a step (30) to evaluate and assign a value of CSGacc = CSGinit.(PCR_Loc2 -PCR_Loc1)/(PCRr2 -PCRr1) - a step (60) to assign to an accumulation corrector (COR) of the phase-locked loop (PLL) an initialisation value COR INIT the value CSG acc and to assign to the target (CSG) a corrected difference (ERC) delivered by the accumulation corrector (COR) in response to a difference (ERR) between a received sample (PCRr) and a local sample (PCR_Loc).

Description

Method for assigning a target to a configurable oscillator of a phase-locked loop

Scope of the invention

The present invention relates to the domain of synchronization of items of equipment connected by a packet switching network. The present invention relates to a reception device connected by such a network to a synchronization signal transmission device. The invention also relates to a method for determining the reduction of a phase difference amplitude between them. It also relates to a synchronization signals reception device implementing such a method.

Prior art

In the prior art, video synchronisation systems are known to reconstruct at the level of a camera, a timing clock for this camera that is perfectly synchronous with timing clocks reconstructed at the levels of other cameras connected to the same network. These different clocks enable guarantying that an image generated by a camera is rigorously in phase with all of the images generated by neighbouring cameras connected to the same network.

Examples of such video synchronisation systems are described in the international PCT application FR2007/050918, they act on Program Clock Reference (PCR) signals that represent reference clock signals. Figures 1 to 4 detail the functioning of such a system.

In Figure 1 , a "transmission" block is constituted of a master module MGE that is connected to an IP/Analogue interface I AIP. The master module MGE sends a Genlock signal SGO to the interfaces I_AIP. A "reception" block is comprised of two cameras (CAM1 , CAM2) each connected to an IP/Analogue interface IJPA. The interfaces IJPA that will eventually be included in the cameras themselves are responsible for reconstructing the Genlock signals SG1 , SG2 synchronous with the SGO signal intended for cameras CAM1 , CAM2. The cameras CAM1 , CAM2 each produce a video signal SV1 , SV2 that must be synchronised perfectly. The transmission and reception sides are linked together by a packet switching network that is the source of a jitter occurring in the Genlock signal SGO.

A sampling clock, CLKech, with a T_eCh period, is generated from a first synchronisation layer, for example IEEE1588, is sent to the "transmission" and "reception" blocks. In fact, the PTP protocol (Precision Time Protocol) based on IEEE1588 enables synchronisation to be obtained between the equipment connected on the Ethernet network to an order of microseconds. In other words, the time bases of each item of equipment progress at the same time with a precision close to the order of microseconds. Each of these time bases can be used in this case to generate its own sampling clock CLKech with a period T_eCh- Use of the IEEE1588 layer is not a required route. Any system capable of providing a sampling clock CLKech of period T_eCh on the different items of equipment connected on a network could be suitable. Figure 2 details the processing of the Genlock signal SGO from the MGE, within the interface I AIP. A module EXS extracts synchronisation information from the signal SGO in order to recover a video timing clock (noted as CIk video on figure 2). More specifically, the module EXS is responsible for the generation of a pulse (or "image cue") at the beginning of each image. Furthermore, the module EXS comprises an image counter, for example a 40 ms counter, which is not shown on figure 2. The output of this image counter progresses according to a counting ramp, crossing 0 at each image start, that is every 40 ms in the case of the image counter cited in the aforementioned example.

"Counting ramp" designates a stair-step signal. The steps have a unitary height. The "counting ramp range" is the term applied to the difference in level between the highest steps and the lowest steps. All of the steps have an equal duration that corresponds to the period 1/F_0Ut of the video timing clock CIk video. For example the counting ramp range delivered by the image counter is equal to 40ms. F_out, where F_out is the frequency of the clock CLK video. The image counter delivers successively all the integer values from 0 to 40 ms.F_0Ut -1. The video timing clock is used to determine the timing of a counter CPT_PCR. The output of the counter CPT_PCR is a counting ramp, CSE_PCR whose period is m image periods. Every "m" image, the counter CPT_PCR is reset, that is to say that the counting ramp CSE_PCR is reset to 0. The range of the counting ramp delivered by the image counter is equal to m.40ms.F_out. The counter CPT_PCR delivers successively each of the integer values from 0 to m.40 ms.F_0Ut -1. Next, a module LCH samples the counting ramp CSE_PCR at a rate provided by the sampling clock CLKech, that is to say with a period T_eCh and thus produces the samples PCR_e that are sent on the network in the form of synchronisation packets and circulate via an interface with the network (block INTE) to the reception side. Figure 3 shows the reception side according to the prior art. The interface IJPA extracts the samples PCR_e of received synchronisation packets. These samples PCR_e reach a network interface (module INTR) with a delay linked to the transport between the transmission device and the reception device: the module INTR produces the samples PCR_r. The samples PCR_e, which are produced at regular intervals defined by the sampling clock CLK_eCh on the transmission side, arrive at irregular intervals on the reception side: this is largely due to the jitter introduced during transport on the network. The samples PCR_r are taken into account at regular T_eCh intervals and hence, the majority of the jitter introduced during packet transport is eliminated. The imprecision between the transmission and reception sampling times is absorbed by a phase-locked loop PLL whose bandwidth is appropriated. The characteristics of the phase-locked loop PLL guarantee a reconstituted clock generation CLK_out with a reduced jitter.

The phase-locked loop PLL acts as a system receiving PCR_r samples and delivering:

- a reconstituted clock CLK_out,

- a counting ramp CSR_PCR and,

- local samples PCRJoc.

When the loop PLL operates in a steady state, the samples PCR_r are noticeably equal to the samples PCRJoc. The reconstituted clock CLK_out determines the timing of a CPT image counter similar to the image counter on the transmission side, for example a 40 ms counter. The image counter CPT is reset each time the counting ramp CSR_PCRi crosses 0. Between two successive initialisations, the image counter CPT progresses freely and produces an image cue that supplies a local Genlock generator, GEG to produce a reconstructed Genlock signal SG1 , SG2 designed to synchronise the cameras CAM1 , CAM2. The reconstructed Genlock signal SG1 , SG2 that is generated from the counting ramp CSR_PCR and the reconstituted clock CLK_out is in phase with the Genlock signal SGO on the transmission side, to the nearest clock pulse. Figure 4 diagrammatically shows a phase-locked loop PLL architecture used in an IJPA interface according to the prior art. As shown in figure 4, the phase- locked loop PLL comprises:

- a sample comparator CMP that compares the samples PCR_r and local samples delivering a comparison result of the samples , or an error signal ERR, - a corrector COR receiving the signal ERR and delivering a corrected difference ERC,

The loop PLL also comprises a set GEN comprising:

- a configurable oscillator VCO receiving as target CSG the corrected difference ERC and delivering a reconstituted clock CLK_out, the clock CLK_out has a frequency F_out that depends on the corrected difference ERC,

- a counter CPT_PCR that produces a counting ramp CSR_PCR according to a rate that is printed by the reconstituted clock CLK_out and having a range of m.40

- a LATCH value maintenance system that generates local samples PCRJoc from values of the counting ramp CSR_PCR at the instants defined by the sampling

ClOCk CLKech-

Usually, two phases are distinguished in the functioning of the loop PLL:

- a first phase, known as the "acquisition phase", during which the phase- locked loop PLL internally produces local samples PCRJoc that are very different from the received samples PCR_r. This phase begins, with the start-up of the phase- locked loop PLL with a reception of samples PCR_r and ends when the local samples PCRJoc produced by the loop PLL are very similar to the received samples PCR_R. During this functioning phase, the synchronisation signal reconstructed on the reception side by means of the phase-locked loop PLL presents a non-null phase difference with the synchronisation signal on the transmission side,

- a second phase, known as the "continuation phase" that corresponds to the steady state, begins at the end of the acquisition phase and ends when a difference of reduced amplitude between the local samples PCRJoc and the received samples PCR_r is detected. The criteria according to which a difference is considered to have a reduced amplitude can for example take the form of an amplitude threshold value. During this functioning phase, a reconstructed synchronisation signal on the reception side is perfectly in phase with the synchronisation signal on the transmission side. A disadvantage if reception devices of the prior art described in figures 3 and

4 is due to the fact that during the acquisition phase, the phase difference between the reconstructed counting ramp CSR_PCR on the reception side and the produced counting ramp CSE_PCR on the transmission side has a heightened amplitude: this amplitude is particularly heightened at the start-up of the acquisition phase and decreases with time. This phase difference creates an imprecision between the synchronization signals that is further heightened as its amplitude is heightened. It is therefore of great interest to be able to reduce the amplitude of phase difference, in particular immediately after the start-ups of the phase locked loop as this enables the imprecision between the synchronization signals to be greatly reduced. At the start-up of a reception device according to the prior art, the frequency of the reconstituted clock CLK_out is not automatically strictly equal to the frequency of the video timing clock CIk video on the transmission side, where the slightest difference between these frequencies has the effect of inducing a phase difference between the counting ramps CSE_PCR and CSR_PCR. In general, the amplitude of the phase difference follows an initial oscillation whose duration depends on the regulation speed of the phase-locked loop PLL. The regulation speed is in principle a fixed parameter that is preferably not adjusted as its value is a compromise between the frequency and the amplitude of the jitter that must be filtered and the frequency of low frequency oscillations that must be respected. The amplitude of the oscillation depends on the distance between the initial frequency of the reconstituted clock CLK_out at the start of the acquisition phase and the value of this same frequency in the continuation phase, this last frequency being equal to that on the transmission side. The more the initial frequency (on the reception side) is close the transmission frequency, the more the amplitude of the start oscillation will be low. If a sufficiently precise evaluation of the frequency on the transmission side is achieved, the amplitude of the oscillation will be less than the phase difference tolerance range in steady state and it can then be assumed that the reception device is immediately operational.

Summary of the invention

The technical problem that the present invention proposes to overcome is to determine on the reception side the frequency on the transmission side.

For this purpose, the present invention relates to, according to a first aspect, a method for assigning a target CSG to a configurable oscillator VCO of a phase- locked loop PLL, the phase-locked loop PLL receiving samples PCRr, PCRI r, PCR2r of a first signal realised according to a sampling clock CLKech and producing local samples PCR_Loc, PCR_Loc1 , PCR_Loc2 of a second signal, said phase- locked loop PLL also producing the second signal from a reconstituted clock CLK_out delivered by the configurable oscillator VCO, the target CSG of the phase- locked loop PLL having by default a value equal to CSGinit. According to the invention, at the start-up of said phase-locked loop PLL, it comprises:

- a step 10 to memorise a sample value PCRI r received and a local sample value PCR_Loc1 produced at a time t1 where PCRI r is valid and the target CSG value is set at a value CSGinit,

- a step 20 to memorise a sample value PCR2r received following the sample PCRI r and a local sample value PCR_Loc2 produced at a time t2 where the sample PCR2r is valid and the target CSG value is set at the value CSGinit,

- a step (30) to evaluate and assign a value of CSGacc = CSGinit. (PCR_Loc2 - PCRJ-od )/(PCRr2 - PCRrI )

- a step 60 to assign to an accumulation corrector COR of the phase-locked loop PLL an initialisation value COR_INIT the value CSG_aCc snd to assign to the target CSG a corrected difference ERC delivered by the accumulation corrector COR in response to a difference ERR between a received sample PCRr and a local sample PCRJ-oα

The present invention relates to, according to a second aspect, a reception device able to receive packets transmitted in a packet switching communication network, said device comprising:

- means to receive packets containing samples PCRI r, PCR2r, said samples PCRI r, PCR2r coming from data sampled according to a main sampling clock

CLKech of period Tech, where the sampling clock CLKech is from a time base synchronised on all the devices connected to said network,

- a phase-locked loop PLL receiving said samples PCRI r, PCR2r delivering a counting ramp CSR_PCR, local samples PCR_Loc1 , PCR_Loc2, said phase-locked loop PLL comprising a configurable oscillator (VCO) delivering, in response to a target CSG, a reconstituted clock (CLK_out) of frequency equal to K. CSG, K being a known real number.

According to the invention, it also comprises:

- means MEM to memorise values of two consecutive received samples PCRI r, PCR2r received after a start-up of said phase-locked loop PLL,

- means MEM to memorise values of two local samples PCR_Loc1 , PCR_Loc2 at timestamps t1 , t2 where the received samples PCRI r, PCR2r are valid whereas the value of the target CSG is set at a value CSGinit,

- means CALC to evaluate the value CSGacc = CSGinit.(PCR_Loc2 - PCRJ-od )/ (PCRr2 - PCRrI ), - means CALC to assign the value of the target CSG evaluated to the configurable oscillator VCO.

A first advantage of the invention resides in the capacity that it offers to rapidly reduce the phase difference amplitude between the counting ramps CSE_PCR and CSR_PCR without modifying fundamentally the architecture of the reception devices according to the prior art.

A second advantage of the invention is the compatibility of the functioning of the reception devices according to the invention with the reception devices according to the prior art: the former are easily substituted for the latter. A third advantage linked to the two advantages cited above, lies in that the invention is localised within the phase-locked loop PLL of the reception device which is most frequently realised by means of a VHDL (Very High Speed Integrated Circuit Hardware Description Language) code. An upgrade of a reception device according to the prior art can thus be implemented by a simple replacement of the VHDL code synthesizing the phase-locked loop PLL.

Brief description of the drawings

The invention will be better understood from the following description of an embodiment of the invention provided as an example by referring to the annexed figures, wherein: - Figure 1 , already described, shows the transmission of Genlock information between two cameras linked via an IP/Ethernet network,

- Figure 2, already described, shows the interfacing between the analogue domain and the IP/Ethernet network,

- Figure 3, already described, shows the regeneration of the Genlock signal on the reception side according to the prior art,

- Figure 4, already described, diagrammatically shows a phase-locked loop architecture of a reception device according to the prior art,

- Figure 5 diagrammatically shows a phase-locked loop architecture of a reception device according to the invention, - Figure 6 shows a flowchart of a method according to the invention.

Detailed description of the embodiments of the invention

Figure 5 shows a phase-locked loop architecture PLL₁ employed in a reception device according to the invention. In the comparator CMP are found, the accumulation corrector COR and the system GEN that groups the digital configurable oscillator VCO, the counter PPT_PCR and the LATCH value maintenance system.

The phase-locked loop PLL shown in figure 5 differs from that shown in figure 4 in that it also comprises means MEM to memorise received sample values PCRI r,

PCR2r or local sample values PCR1_Loc, PCR2_Loc and means CALC to evaluate the value CSGacc = CSGinit.(PCR_Loc2 - PCR_Loc1 )/ (PCRr2 - PCRM ). The means CALC receive the samples stored in the means MEM and receive a value

CSGinit. They deliver the evaluated value CSGacc to the corrector COR that considers it as an initialisation value for the accumulator, not shown, that it comprises.

The block CPL interposed between the corrector COR and the system GEN assign as target CSG to the configurable oscillator VCO either the values CSGinit or the corrected difference delivered by the corrector COR. Figure 6 shows a flowchart of the method according to the invention specifying the interactions between the different modules constituting the phase-locked loop PLL shown in figure 5.

The method according to the invention can be broken down into two main phases: a first phase during which the phase-locked loop PLL is used in "open loop" mode. This first phase begins with the start-up of the phase-locked loop PLL: it corresponds to a situation where it is the value CSGinit that is considered as the target for the configurable oscillator VCO.

It is possible to break down the first phase into a succession of three steps: During a first step 10, a first received sample PCRI r is memorised in the means MEM. For example, PCRI r is the first sample received after the start-up of the phase-locked loop PLL. During this same step 10, a first local sample PCR1_Loc is memorised in the means MEM: the first local sample PCR1_Loc is produced by the system GEN at a time t1 where the sample PCRI r is valid. For example at the first pulse of the sampling clock CLKech following the reception of the sample PCRI r.

This double memorisation is repeated during a step 20 for the sample PCR2r received consecutive to the sample PCRI r and for a second local sample PCR2_Loc produced by the system GEN at a time t2 where the sample PCR2r is valid. The first phase ends following a third step 30 during which the means CALC evaluate the value CSGacc and transmit it to the corrector COR that treats it as an initialisation value COR_mιt

The second phase of the method according to the invention includes a single step 60 that corresponds to a functioning in a closed loop of the phase-locked loop PLL: it corresponds to a situation where it is the corrected difference value ERC that is sent as the target of the oscillator VCO.

At the start-up of the second phase, the frequency of the reconstituted clock CLK_out is very close to the frequency of the timing clock CLk video on the transmission side.

At each reception of a new sample PCRr, a new value is determined for the accumulator of the corrector COR.

The configurable oscillator (VCO) delivers a reconstituted clock (CLK_out) of frequency F_out such that Fout = K.CSG, K being a known real number. Advantageously, the step 30 to evaluate the value of the expression CSGacc consists in approximating determination of a target value CSG to be assigned using the following expression CSGacc = CSGinit + ((PCRr2 - PCRrI ) - (PCR_Loc2 - PCRJ-od )). K . Tech

The invention is described in the preceding text as an example. It is understood that those skilled in the art are capable of producing variants of the invention without leaving the scope of the patent.

Claims

1. Method for assigning a target (CSG) to a configurable oscillator (VCO) of a phase-locked loop (PLL), the phase-locked loop (PLL) receiving samples (PCRr,

PCRI r, PCR2r) of a first signal realised according to a sampling clock (CLKech) and producing local samples (PCR_Loc, PCR_Loc1 , PCR_Loc2) of a second signal, said phase-locked loop (PLL) also producing the second signal from a reconstituted clock (CLK_out) delivered by the configurable oscillator (VCO), the target (CSG) of the phase-locked loop (PLL) having by default a value equal to CSGinit, characterized in that, during the start-up of said phase-locked loop (PLL), it comprises:

- a step (10) to memorise a value of a sample (PCRI r) received and a local sample value (PCR_Loc1 ) produced at a time t1 where the sample (PCRI r) is valid and the value of the target (CSG) is set at a value CSGinit,

- a step (20) to memorise a sample value (PCR2r) received following the sample (PCRI r) and a local sample value (PCR_Loc2) produced at a time t2 where the sample (PCR2r) is valid and the value of the target (CSG) is set at the value CSGinit,

- a step (30) to evaluate and assign a value of CSGacc = CSGinit.(PCR_Loc2 - PCR_Loc1 )/(PCRr2 - PCRrI ) - a step (60) to assign to an accumulation corrector (COR) of the phase- locked loop (PLL) an initialisation value COR_IN_IT the value CSG_acc and to assign to the target (CSG) a corrected difference (ERC) delivered by the accumulation corrector (COR) in response to a difference (ERR) between a received sample (PCRr) and a local sample (PCR_Loc).

2. Method according to claim 1 , the configurable oscillator (VCO) delivering a reconstituted clock (CLK_out) of frequency F_out such that Fout = K.CSG, K being a known real number, the sampling clock (CLKech) having a period Tech, characterized in that the step (30) to evaluate the value of the expression CSGacc consists in approximating determination of a target value (CSG) to be assigned by the following expression CSGacc = CSGinit + ((PCRr2 - PCRrI ) - (PCR_Loc2 - PCRJ-od )). K . Tech.

3. Reception device able to receive packets transmitted in a packet switching network, said device comprising:

- means to receive packets containing samples (PCRI r, PCR2r), said samples (PCRI r, PCR2r) coming from data sampled according to a main sampling clock (CLKech) of period Tech, where the main sampling clock (CLKech) is from a time base synchronised on all the devices connected to said network,

- a phase-locked loop (PLL) receiving said samples (PCRI r, PCR2r) delivering a counting ramp (CSR_PCR), local samples (PCR_Loc1 , PCR_Loc2), said phase- locked loop (PLL) comprising a configurable oscillator (VCO) delivering, in response to a target (CSG), a reconstituted clock (CLK_out) of frequency equal to K. CSG, K being a known real number. characterized in that it also comprises:

- means (MEM) to memorise values of two consecutive received samples (PCRI r, PCR2r) received after a start-up of said phase-locked loop (PLL), - means (MEM) to memorise values of two local samples (PCR_Loc1 ,

PCR_Loc2) at timestamps (t1 , t2) where the received samples (PCRI r, PCR2r) are valid whereas the value of the target (CSG) is set at a value CSGinit,

- means (CALC) to evaluate the value CSGacc = CSGinit.(PCR_Loc2 - PCRJ-od )/ (PCRr2 - PCRrI ), - means (CALC) to assign the value of the target (CSG) evaluated to the configurable oscillator (VCO).