WO2009030745A1 - Fine compensation of a packet transport time for a synchronisation of equipment linked by an ip network - Google Patents

Fine compensation of a packet transport time for a synchronisation of equipment linked by an ip network Download PDF

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Publication number
WO2009030745A1
WO2009030745A1 PCT/EP2008/061766 EP2008061766W WO2009030745A1 WO 2009030745 A1 WO2009030745 A1 WO 2009030745A1 EP 2008061766 W EP2008061766 W EP 2008061766W WO 2009030745 A1 WO2009030745 A1 WO 2009030745A1
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WIPO (PCT)
Prior art keywords
pcr
samples
value
determining
image
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PCT/EP2008/061766
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French (fr)
Inventor
Thierry Tapie
Serge Defrance
Catherine Serre
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Thomson Licensing
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Publication of WO2009030745A1 publication Critical patent/WO2009030745A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator

Definitions

  • the present invention relates to the domain of video equipment .
  • the present invention relates more particularly to a device for the reception of a synchronisation signal on a packet switching network, for example of the IP type, whether the network is wired (for example Ethernet (IEEE802.3)) or wireless (for example IEEE 802.16 D- 2004) .
  • a packet switching network for example of the IP type, whether the network is wired (for example Ethernet (IEEE802.3)) or wireless (for example IEEE 802.16 D- 2004) .
  • IP networks have made it possible to use these networks as the "backbone" architecture for video studios. Of capital importance to this evolution is therefore having a single infrastructure for the transport of data. Whereas in the past, several media were necessary to transport different signal types, the multiplexing properties offered by the IP layer enable a reduction in the number of media necessary: an IP network that links the different equipment .
  • the synchronisation of items of video equipment (cameras, etc.) in a studio is carried out by the transmission of a synchronisation signal commonly called "Genlock” or "Black burst” .
  • the Genlock signal comprises two synchronisation signals, one is repeated every 40 ms and indicates the start of the video frame, the other is repeated every 64 ⁇ s (for a standard format and less for an HD format) and indicates the start of lines in the video frame.
  • the waveforms of synchronisation signals are a function of the format of the image transmitted on the network. For example, for a high definition image, the signal synchronisation has a tri-level form (-30OmV, OV, +300 mV) .
  • a synchronisation signal When a synchronisation signal is routed to different equipment to be synchronised by a dedicated coaxial cable, a constant transmission time, without jitter is ensured. From such a signal, all items of equipment are able to reconstruct a timing clock that is specific to its functioning, which guarantees that its functioning is rigorously in phase with all the equipment connected to the same network. For example, two cameras synchronised by a Genlock signal circulating on a dedicated coaxial cable each generate a video with different contents but rigorously in frequency and in phase with one another.
  • a known disadvantage presented by an IP/Ethernet network is that it introduces a strong jitter in a transmission of signals, and particularly for the transmission of a synchronisation signal.
  • a signal is routed by an IP/Ethernet connection to different items of equipment for synchronising, this jitter results in fluctuations in the length of time required for the information carried by the synchronisation signal to reach the equipment.
  • the reception device comprises means for:
  • the phase- locked loop PLL 1 of the reception device acts as a low-pass filter that partially attenuates the jitter present in the samples received PCR r that have circulated on the network.
  • this international patent request does not mention the problem of a reduction or an elimination of a residual delay in the synchronisation of two items of equipment caused by a prior correction of the effects of a network latency.
  • reception devices it is considered that the information transport time between the two items of equipment is fixed and corresponds to a T ech period of the sampling clock. This hypothesis is correct in the first order; however it does not take into account the variations in the T ech period of the sampling clock both at the level of transmission and reception.
  • a fixed value OFFSET that corresponds to the theoretical difference between two consecutive samples is added on a flat rate basis to each sample received PCR r .
  • the invention relates to a fine compensation of the delay linked to the information transport time and requires a prior measurement of these effects .
  • the present invention relates to a device able to receive packets in a packet switching network comprising at least two stations, the said device comprising means for:
  • PLL 1 phase- locked loop
  • - means for generating image cues at every zero- crossing of said image counter CPT, and - means for reconstituting a synchronisation signal from said image cues characterized in that it comprises: means for determining a difference value AE 1 between two consecutive received samples PCR r i+1 and PCR r x ,
  • FIG. 1 shows the transmission of genlock information between two cameras linked via an IP/Ethernet network
  • figure 2 shows the interfacing between the analogue domain and the IP/Ethernet network
  • figure 3 shows the regeneration of the Genlock signal on the reception side according to the prior art
  • - figure 4 diagrammatically shows a phase- locked loop architecture of a reception device according to the prior art
  • - figure 5 diagrammatically shows a phase- locked loop architecture of a reception device according to the invention.
  • the current analogue domain is interfaced with the IP/Ethernet network on the transmission side, and the IP/Ethernet network is interfaced with the analogue domain on the reception side, as illustrated in figure 1.
  • the transmission side comprises a "Genlock master" MGE that is connected to an IP/Analogue interface I_AIP.
  • the Genlock master MGE sends a Genlock signal SGO to the interfaces I_AIP.
  • the reception side is constituted by two cameras (CAMl, CAM2) each connected to an IP/Analogue interface I_IPA.
  • the interfaces I_IPA that will eventually be included in the cameras themselves are responsible for reconstructing the Genlock signals SGl, SG2 intended for cameras CAMl, CAM2.
  • the cameras CAMl, CAM2 each produce a video signal SVl, SV2 that is required to be synchronised perfectly.
  • the transmission and reception sides are linked together by a packet switching network that is the source of a jitter occurring in the Genlock signal SGO.
  • a sampling pulse, in the T ech , period, is generated from a first synchronisation layer, for example IEEE1588, and is sent to the transmission and reception sides.
  • a first synchronisation layer for example IEEE1588
  • the PTP protocol Precision Time Protocol
  • IEEE1588 enables synchronisation to be obtained between the equipment connected on the Ethernet network to an order of microseconds.
  • all the time bases of every item of equipment progress at the same time with a precision close to the order of microseconds.
  • Each of these time bases can be used in this case to generate its own sampling pulse in the T ech , period.
  • Use of the IEEE1588 layer is not a required route. Any system capable of providing sampling pulses to the various items of equipment on the network in the T ech period could be suitable. For example, a 5 ms sampling pulse from a wireless transmission physical layer can be used.
  • Figure 2 details the processing of the Genlock signal SGO from MGE within the interface I_AIP.
  • a module EXS extracts the synchronisation information from the signal SGO in order to recover a video timing clock (noted as CIk on figure 2) . More specifically, the module EXS is responsible for the generation of an image cue at the beginning of each image. Furthermore, the module EXS comprises an image counter, for example a 40 ms counter, which is not shown on figure 2. The output of this image counter progresses according to the counting ramp, crossing 0 at each image period, that is every 40 ms in the case of the image counter cited in the aforementioned example. The image counter delivers a stair-step signal whose steps are a unitary height.
  • the signal range value that is to say the height corresponding to the difference in level between the highest step and the lowest step is equal to 40ms.
  • F out is the frequency of the clock CIk video.
  • the counter CPT successively delivers all of the integer values from 0 to 40 ms.F out -l.
  • the timing video clock is used to determine the rhythm of a counter CPT_PCR.
  • the output of the counter CPT_PCR is a counting ramp, whose period is m image periods. Every "m" image, the counter CPT_PCR is reset, that is to say that the counting ramp CSE_PCR is reset to 0.
  • Countering ramp designates a stair-step signal .
  • the steps have a unitary height (or count increment ⁇ C) .
  • the signal range value that is to say the height corresponding to the difference in level between the lowest step and the highest step is equal to m.40ms.F out .
  • the counter CPT-PCR 1 delivers successively all of the integer values from 0 to m.40 ms.F out -l.
  • a module LCH samples the counting ramp
  • FIG. 3 shows the reception side according to the prior art.
  • the interface I_IPA recovers the PCR samples that have been sent on the network.
  • These samples PCR e are received by a network interface (module INTR) with a delay linked to the transport between the transmission device and the reception device: the module INTR produces samples PCR r .
  • the samples PCR e which are produced at regular T ech intervals on the transmission side, arrive at irregular intervals on the reception side: this is largely due to the jitter introduced during transport on the network.
  • the samples PCR r are taken into account at regular T ech intervals and hence, the majority of the jitter introduced during packet transport is eliminated.
  • phase-locked loop PLL 1 The imprecision between the transmission and reception sampling times is absorbed by a phase-locked loop PLL 1 whose bandwidth is appropriated.
  • the characteristics of the phase-locked loop PLL 1 guarantee a reconstituted clock generation CLK-OUt 1 with a reduced jitter.
  • the phase- locked loop PLL 1 acts as a system receiving PCR r samples and delivering: - a reconstituted clock CLK-OUt 1 ,
  • the counting ramp CSR-PCR 1 has a range value PCR-Modulus .
  • the samples PCR r are noticeably equal to the samples PCR-IoC 1 .
  • the reconstituted clock CLK-OUt 1 determines the rhythm of a CPT image counter similar to the image counter on the transmission side, for example a 40 ms counter.
  • the image counter CPT is reset each time the counting ramp CSR-PCR 1 crosses 0. Between two successive initialisations, the image counter CPT progresses freely and produces an image cue that supplies a local Genlock generator, GEG to produce a reconstructed Genlock signal
  • Genlock signal SGl, SG2 designed to synchronise the cameras CAMl, CAM2.
  • the reconstructed Genlock signal SGl, SG2 that is generated from the counting ramp CSR-PCR 1 and the reconstituted clock CLK-OUt 1 is in phase with the Genlock signal SGO on the transmission side, to the nearest clock pulse.
  • Figure 4 diagrammatically shows a PLL 1 phase- locked loop architecture used in an I_IPA interface according to the prior art . As shown in figure 4, the phase locking loop
  • PLL 1 comprises:
  • a sample comparator CMP 1 that compares the samples PCR r and local samples delivering a comparison result of the samples , or an error signal ERR, - a corrector COR 1 receiving the signal ERR and delivering a corrected error signal ERC, a configurable oscillator VCO 1 receiving the corrected error signal ERC and delivering a reconstituted clock CLK-OUt 1 , the clock CLK-OUt 1 has a frequency F out that depends on the signal ERC,
  • Figure 5 illustrates a sample locking loop PLL 1 of a reception device PLL 1 according to the invention.
  • the loop PLL 1 comprises, furthermore, the means for: determining the difference value AE 1 between two consecutive received samples PCR r I ,
  • the loop PLL 1 comprises a device REC 1 that receives the different samples received PCR r x .
  • the means for determining a difference value AE 1 between two consecutive received samples deliver a result which is modulo PCR_Modulus . That is to say that for each index i, the device REC 1 determines AE 1 from the expression PCR r i+1 - PCR r x if (PCR 11+1 - PCR 11 ) is positive and determines AE 1 from the expression PCR_Modulus + (PCR 11+1 - PCR r J if (PCR 11+1 - PCR r J is negative.
  • the device REC 1 stores the difference value AE 1 then delivers a mean value of the difference AE 1 .
  • the means for determining a mean value ( ⁇ E>J deliver a value which is a linear combination of consecutive difference values.
  • the means for determining a mean value ⁇ E> x deliver a value equal to 0.1 AE 1 1 + 0.9 AE 1 .
  • the mean value ⁇ E> x is added to the received samples PCR 11 .

Abstract

The present invention relates to the domain of video equipment. More specifically, it relates to a device able to receive packets in a packet switching network. The device comprises: - means for regenerating a counting ramp CSR_PCR1 having a range value PCR_Modulus using a phase-locked loop PLL1 receiving the samples PCRr,i and also delivering local samples PCR_loc1,i every Tech period and a reconstituted clock CLK_out1, - means for initialising, at every zero-crossing of the counting ramp CSR_PCR1, an image counter CPT that is determined by the reconstituted clock CLK_out1, - means for generating image cues at every zero- crossing of said image counter CPT, and - means for reconstituting a synchronisation signal from said image cues. According to the invention, the device comprises: - means for determining a difference value ΔE i between two consecutive received samples PCRr,i+1 and PCRr,i, - means for storing the difference values ΔE i, - means for determining a mean value <Δ E> i of the difference values ΔE i, - means for adding the mean value <Δ E> i to the received samples PCRr,i.

Description

FINE COMPENSATION OF A PACKET TRANSPORT TIME FOR A SYNCHRONISATION OF EQUIPMENT LINKED BY AN IP NETWORK
Scope of the invention
The present invention relates to the domain of video equipment .
The present invention relates more particularly to a device for the reception of a synchronisation signal on a packet switching network, for example of the IP type, whether the network is wired (for example Ethernet (IEEE802.3)) or wireless (for example IEEE 802.16 D- 2004) .
Prior art
Progress in the ability of IP networks to transport all types of signal (data or video) has made it possible to use these networks as the "backbone" architecture for video studios. Of capital importance to this evolution is therefore having a single infrastructure for the transport of data. Whereas in the past, several media were necessary to transport different signal types, the multiplexing properties offered by the IP layer enable a reduction in the number of media necessary: an IP network that links the different equipment .
In the prior art, the synchronisation of items of video equipment (cameras, etc.) in a studio is carried out by the transmission of a synchronisation signal commonly called "Genlock" or "Black burst" . For example, the Genlock signal comprises two synchronisation signals, one is repeated every 40 ms and indicates the start of the video frame, the other is repeated every 64 μs (for a standard format and less for an HD format) and indicates the start of lines in the video frame. The waveforms of synchronisation signals are a function of the format of the image transmitted on the network. For example, for a high definition image, the signal synchronisation has a tri-level form (-30OmV, OV, +300 mV) .
When a synchronisation signal is routed to different equipment to be synchronised by a dedicated coaxial cable, a constant transmission time, without jitter is ensured. From such a signal, all items of equipment are able to reconstruct a timing clock that is specific to its functioning, which guarantees that its functioning is rigorously in phase with all the equipment connected to the same network. For example, two cameras synchronised by a Genlock signal circulating on a dedicated coaxial cable each generate a video with different contents but rigorously in frequency and in phase with one another.
A known disadvantage presented by an IP/Ethernet network is that it introduces a strong jitter in a transmission of signals, and particularly for the transmission of a synchronisation signal. When such a signal is routed by an IP/Ethernet connection to different items of equipment for synchronising, this jitter results in fluctuations in the length of time required for the information carried by the synchronisation signal to reach the equipment.
In the prior art, devices are known for reconstructing, for each camera, a timing clock specific to this camera enabling the jitter to be overcome. The underlying principle of these devices is a high attenuation of the synchronisation signal jitter amplitude at the level of reception. In such a way, it can be guaranteed that an image generated by a camera is rigorously in phase with all of the images generated by neighbouring cameras connected to the same network. Examples of such devices for jitter attenuation are described in international PCT application FR2007/050918 , and they act on program clock reference (PCR) signals that represent very accurate reference clock signals. These digital signals are sent to cameras across a network so that they can locally reconstruct clock signals that are in phase with the reference clock.
According to the prior art, the reception device comprises means for:
- receiving packets containing samples of the network coming from data sampled every Tech period,
- regenerating a counting ramp CSR-PCR1 using a phase-locked loop PLL1,
- initialising a second counter CPT at every zero-crossing of said first counter CSR-PCR1, generating image cues at every zero-crossing of said second counter, and - reconstituting a synchronisation signal from said image cues .
The phase- locked loop PLL1 of the reception device acts as a low-pass filter that partially attenuates the jitter present in the samples received PCRr that have circulated on the network.
However, this international patent request does not mention the problem of a reduction or an elimination of a residual delay in the synchronisation of two items of equipment caused by a prior correction of the effects of a network latency. Indeed, in reception devices according to the prior art, it is considered that the information transport time between the two items of equipment is fixed and corresponds to a Tech period of the sampling clock. This hypothesis is correct in the first order; however it does not take into account the variations in the Tech period of the sampling clock both at the level of transmission and reception.
Thus, in the reception devices according to the prior art, in order to compensate for the information transport time on the network, a fixed value OFFSET that corresponds to the theoretical difference between two consecutive samples is added on a flat rate basis to each sample received PCRr. The invention relates to a fine compensation of the delay linked to the information transport time and requires a prior measurement of these effects .
Si11T-HIa--1V of the invention
For this purpose, the present invention relates to a device able to receive packets in a packet switching network comprising at least two stations, the said device comprising means for:
- means for receiving packets containing samples PCRr x, said samples PCRr x coming from data sampled every Tech period, where Tech is from a time base synchronised on all the stations of said network, i being an index identifying a received sample PCRr x in a univocal manner, received sample PCRr i+1 chronologically succeeding the received sample PCRr i, - means for regenerating a counting ramp CSR-PCR1 having a range value PCR_Modulus using a phase- locked loop (PLL1) receiving the samples PCRr x and also delivering local samples PCR-IoC1 x every Tech period and a reconstituted clock CLK-OUt1, - means for initialising, at every zero-crossing of the counting ramp CSR-PCR1, an image counter CPT that is determined by the reconstituted clock CLK-OUt1,
- means for generating image cues at every zero- crossing of said image counter CPT, and - means for reconstituting a synchronisation signal from said image cues, characterized in that it comprises: means for determining a difference value AE1 between two consecutive received samples PCRr i+1 and PCRr x,
- means for storing the difference values AE1, - means for determining a mean value <ΔE>x of the difference values AE1,
- means for adding the mean value <ΔE>x to the received samples PCR11.
Brief description of the drawings
The invention will be better understood from the following description of an embodiment of the invention provided as an example by referring to the annexed figures, wherein:
- figure 1 shows the transmission of genlock information between two cameras linked via an IP/Ethernet network,
- figure 2 shows the interfacing between the analogue domain and the IP/Ethernet network, figure 3 shows the regeneration of the Genlock signal on the reception side according to the prior art,
- figure 4 diagrammatically shows a phase- locked loop architecture of a reception device according to the prior art, - figure 5 diagrammatically shows a phase- locked loop architecture of a reception device according to the invention.
Detailed description of the embodiments of the invention
The current analogue domain is interfaced with the IP/Ethernet network on the transmission side, and the IP/Ethernet network is interfaced with the analogue domain on the reception side, as illustrated in figure 1. In the same figure, the transmission side comprises a "Genlock master" MGE that is connected to an IP/Analogue interface I_AIP. The Genlock master MGE sends a Genlock signal SGO to the interfaces I_AIP. The reception side is constituted by two cameras (CAMl, CAM2) each connected to an IP/Analogue interface I_IPA. The interfaces I_IPA that will eventually be included in the cameras themselves are responsible for reconstructing the Genlock signals SGl, SG2 intended for cameras CAMl, CAM2. The cameras CAMl, CAM2 each produce a video signal SVl, SV2 that is required to be synchronised perfectly.
The transmission and reception sides are linked together by a packet switching network that is the source of a jitter occurring in the Genlock signal SGO.
A sampling pulse, in the Tech, period, is generated from a first synchronisation layer, for example IEEE1588, and is sent to the transmission and reception sides. Indeed, the PTP protocol (Precision Time Protocol) based on IEEE1588 enables synchronisation to be obtained between the equipment connected on the Ethernet network to an order of microseconds. In other words, all the time bases of every item of equipment progress at the same time with a precision close to the order of microseconds. Each of these time bases can be used in this case to generate its own sampling pulse in the Tech, period. Use of the IEEE1588 layer is not a required route. Any system capable of providing sampling pulses to the various items of equipment on the network in the Tech period could be suitable. For example, a 5 ms sampling pulse from a wireless transmission physical layer can be used.
Figure 2 details the processing of the Genlock signal SGO from MGE within the interface I_AIP.
First, a module EXS extracts the synchronisation information from the signal SGO in order to recover a video timing clock (noted as CIk on figure 2) . More specifically, the module EXS is responsible for the generation of an image cue at the beginning of each image. Furthermore, the module EXS comprises an image counter, for example a 40 ms counter, which is not shown on figure 2. The output of this image counter progresses according to the counting ramp, crossing 0 at each image period, that is every 40 ms in the case of the image counter cited in the aforementioned example. The image counter delivers a stair-step signal whose steps are a unitary height. The signal range value, that is to say the height corresponding to the difference in level between the highest step and the lowest step is equal to 40ms. Fout is the frequency of the clock CIk video. The counter CPT successively delivers all of the integer values from 0 to 40 ms.Fout-l.
The timing video clock is used to determine the rhythm of a counter CPT_PCR. The output of the counter CPT_PCR is a counting ramp, whose period is m image periods. Every "m" image, the counter CPT_PCR is reset, that is to say that the counting ramp CSE_PCR is reset to 0.
"Counting ramp" designates a stair-step signal . The steps have a unitary height (or count increment ΔC) . The signal range value, that is to say the height corresponding to the difference in level between the lowest step and the highest step is equal to m.40ms.Fout. The counter CPT-PCR1 delivers successively all of the integer values from 0 to m.40 ms.Fout-l. Next, a module LCH samples the counting ramp
CSE_PCR every Tech period to produce samples PCRe . These samples PCRe are sent across the network and travel to the reception side through a network interface (block INTE) . Figure 3 shows the reception side according to the prior art. The interface I_IPA recovers the PCR samples that have been sent on the network. These samples PCRe are received by a network interface (module INTR) with a delay linked to the transport between the transmission device and the reception device: the module INTR produces samples PCRr. The samples PCRe, which are produced at regular Tech intervals on the transmission side, arrive at irregular intervals on the reception side: this is largely due to the jitter introduced during transport on the network. The samples PCRr are taken into account at regular Tech intervals and hence, the majority of the jitter introduced during packet transport is eliminated.
The imprecision between the transmission and reception sampling times is absorbed by a phase- locked loop PLL1 whose bandwidth is appropriated. The characteristics of the phase-locked loop PLL1 guarantee a reconstituted clock generation CLK-OUt1 with a reduced jitter.
The phase- locked loop PLL1 acts as a system receiving PCRr samples and delivering: - a reconstituted clock CLK-OUt1,
- a counting ramp CSR-PCR1 and,
- local samples PCR-IoC1.
The counting ramp CSR-PCR1 has a range value PCR-Modulus . When the loop PLL1 operates in a steady state, the samples PCRr are noticeably equal to the samples PCR-IoC1.
The reconstituted clock CLK-OUt1 determines the rhythm of a CPT image counter similar to the image counter on the transmission side, for example a 40 ms counter. The image counter CPT is reset each time the counting ramp CSR-PCR1 crosses 0. Between two successive initialisations, the image counter CPT progresses freely and produces an image cue that supplies a local Genlock generator, GEG to produce a reconstructed Genlock signal
SGl, SG2 designed to synchronise the cameras CAMl, CAM2. The reconstructed Genlock signal SGl, SG2 that is generated from the counting ramp CSR-PCR1 and the reconstituted clock CLK-OUt1 is in phase with the Genlock signal SGO on the transmission side, to the nearest clock pulse.
Figure 4 diagrammatically shows a PLL1 phase- locked loop architecture used in an I_IPA interface according to the prior art . As shown in figure 4, the phase locking loop
PLL1 comprises:
- a sample comparator CMP1 that compares the samples PCRr and local samples delivering a comparison result of the samples , or an error signal ERR, - a corrector COR1 receiving the signal ERR and delivering a corrected error signal ERC, a configurable oscillator VCO1 receiving the corrected error signal ERC and delivering a reconstituted clock CLK-OUt1, the clock CLK-OUt1 has a frequency Fout that depends on the signal ERC,
- a counter CPT_PCR1 that produces a counting ramp CSR_PCR1 according to a rate that is printed by the reconstituted clock CLK-OUt1,
- a support system with the value LATCH1 that generates local samples PCR-IoC1 from the values of the counting ramp CSR-PCR1 at the times Tech,
Figure 5 illustrates a sample locking loop PLL1 of a reception device PLL1 according to the invention.
The loop PLL1 comprises, furthermore, the means for: determining the difference value AE1 between two consecutive received samples PCRr I,
- storing the difference values AE1, - determining a mean value <ΔE>x of the values AE1, - adding the mean value <ΔE>x to the received samples PCR11.
For example, the loop PLL1 comprises a device REC1 that receives the different samples received PCRr x .
Advantageously, the means for determining a difference value AE1 between two consecutive received samples deliver a result which is modulo PCR_Modulus . That is to say that for each index i, the device REC1 determines AE1 from the expression PCRr i+1- PCRr x if (PCR11+1- PCR11) is positive and determines AE1 from the expression PCR_Modulus + (PCR11+1- PCRr J if (PCR11+1- PCRr J is negative.
Next, the device REC1 stores the difference value AE1 then delivers a mean value of the difference AE1.
Advantageously, the means for determining a mean value (<ΔE>J deliver a value which is a linear combination of consecutive difference values. Advantageously, the means for determining a mean value <ΔE>x deliver a value equal to 0.1 AE1 1 + 0.9 AE1.
For each index i, the mean value <ΔE>x is added to the received samples PCR11.
The invention is described in the preceding text as an example. It is understood that those skilled in the art are capable of producing variants of the invention without leaving the scope of the patent.

Claims

1. Reception device able to receive packets in a packet switching network comprising at least two stations, said device comprising: - means for receiving packets containing samples (PCRr J , said samples (PCRr J coming from data sampled every Tech period, where Tech is from a time base synchronised on all the stations of said network, i being an index identifying a received sample (PCRr J in a univocal manner, received sample (PCRr i+1) chronologically succeeding the received sample (PCRr J ,
- means for regenerating a counting ramp (CSR-PCR1) having a range value PCR_Modulus using a phase- locked loop (PLL1) receiving the samples (PCRr J and also delivering local samples (PCR-IoC1 J every Tech period and a reconstituted clock (CLK-OUt1) ,
- means for initialising, at every zero-crossing of the counting ramp (CSR-PCR1) , an image counter (CPT) that is determined by the reconstituted clock (CLK-OUt1) , - means for generating image cues at every zero- crossing of said image counter (CPT) , and means for reconstituting a synchronisation signal from said image cues, characterized in that it further comprises: - means for determining a difference value (ΔEJ between two consecutive received samples (PCRr i+1) and (PCRrJ ,
- means for storing the difference values (ΔEJ ,
- means for determining a mean value (<ΔE>J of the difference values (ΔEJ ,
- means for adding the mean value (<ΔE>J to the received samples (PCRr J .
2. Reception device according to claim 1, characterized in that the means for determining a difference value (ΔEJ between two consecutive received samples deliver a result which is modulo PCR_Modulus .
3. Reception device according to claim 1, characterized in that the means for determining a mean value (<ΔE>1) deliver a value which is a linear combination of consecutive difference values.
4. Reception device according to claim 3, characterized in that the means for determining a mean value (<ΔE>J deliver a value equal to 0.1 AE1-1 + 09 AE1.
PCT/EP2008/061766 2007-09-07 2008-09-05 Fine compensation of a packet transport time for a synchronisation of equipment linked by an ip network WO2009030745A1 (en)

Applications Claiming Priority (2)

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FR0757422 2007-09-07
FR0757422A FR2920941A1 (en) 2007-09-07 2007-09-07 FINE COMPENSATION OF A PACKAGE TRANSPORT DURATION FOR A SYNCHRONIZATION OF EQUIPMENT CONNECTED BY AN IP NETWORK

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020063796A1 (en) * 2000-11-27 2002-05-30 Kyung Pa Min Controlling the system time clock of an MPEG decoder
US20030160897A1 (en) * 2002-02-25 2003-08-28 Park Dong Ho Digital broadcasting receiver and method for compensating color reproduction error of the same
EP1471745A1 (en) * 2003-03-31 2004-10-27 Sony United Kingdom Limited Video synchronisation
WO2007104891A2 (en) * 2006-03-13 2007-09-20 Thomson Licensing Transmitting a synchronizing signal in a packet network

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020063796A1 (en) * 2000-11-27 2002-05-30 Kyung Pa Min Controlling the system time clock of an MPEG decoder
US20030160897A1 (en) * 2002-02-25 2003-08-28 Park Dong Ho Digital broadcasting receiver and method for compensating color reproduction error of the same
EP1471745A1 (en) * 2003-03-31 2004-10-27 Sony United Kingdom Limited Video synchronisation
WO2007104891A2 (en) * 2006-03-13 2007-09-20 Thomson Licensing Transmitting a synchronizing signal in a packet network

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