WO2009080177A1 - Method of manufacturing semiconductor substrate - Google Patents

Method of manufacturing semiconductor substrate Download PDF

Info

Publication number
WO2009080177A1
WO2009080177A1 PCT/EP2008/010237 EP2008010237W WO2009080177A1 WO 2009080177 A1 WO2009080177 A1 WO 2009080177A1 EP 2008010237 W EP2008010237 W EP 2008010237W WO 2009080177 A1 WO2009080177 A1 WO 2009080177A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
carbon
manufacturing
buffer layer
single crystal
Prior art date
Application number
PCT/EP2008/010237
Other languages
French (fr)
Inventor
Keisuke Kawamura
Seiji Takayama
Brian Murphy
Original Assignee
Siltronic Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic Ag filed Critical Siltronic Ag
Publication of WO2009080177A1 publication Critical patent/WO2009080177A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers

Definitions

  • the present invention relates to a technology of manufacturing a semiconductor substrate suitable for the manufacture of power devices and optoelectronic devices, and particularly, relates to a method of manufacturing a semiconductor substrate whose surface portion is made of a single crystal silicon carbide layer.
  • Silicon carbide having high Schottky barrier, high electric breakdown field strength and high heat conductivity, is suitable for the material for power devices. Further, silicon carbide has the lattice constant, which is close to the lattice constant of a nitride compound semiconductor as a typical optoelectronic semiconductor material, and enables epitaxial growth of the nitride compound semiconductor with few defects, and accordingly it is suitable for the material for optoelectronic devices. From such circumstances, technologies of manufacturing a semiconductor substrate having a single crystal silicon carbide layer on the surface portion of a silicon substrate (hereinafter, referred to as "SiC wafer”) are developed (Patent Documents 1 to 8, Non Patent Document 1) .
  • FIG. 5 shows an example of a method of manufacturing a SiC wafer according to the prior art.
  • This manufacturing method includes a step of implanting carbon ions into a silicon substrate and thereby forming a carbon containing layer where silicon and carbon are mixed (SIl) , a step of annealing the silicon substrate and single crystallizing the carbon containing layer and thereby forming a single crystal silicon carbide layer (S12), a step of heating the silicon substrate 11 in dry oxygen atmosphere and forming a sacrifice layer on the single crystal silicon carbide layer (S13), a step of selectively removing the sacrifice layer from the silicon substrate by etching and thereby exposing the carbon containing layer (S14) , and a step of smoothing the surface of the exposed single crystal silicon carbide layer by CMP (Chemical Mechanical Polishing) (S15) .
  • CMP Chemical Mechanical Polishing
  • Patent Document 1 US2007/176210A1
  • Patent Document 2 Japanese Patent Application Laid-Open
  • Patent Document 4 Japanese Patent Application National
  • Patent Document 6 WO03/034485
  • Patent Document 7 WO03/071588
  • Patent Document 9 Japanese Patent Application Laid-Open No.2006-528423
  • Non Patent Document 1 Organic vapor phase epitaxial growth of GaN on a 3c-SiC/Si (111) template formed by C + -ion implantation into Si (111) subs
  • A. Yamamoto et al . Journal of Crystal Growth 261 (2004) 266-270
  • a transition layer made of poly silicon carbide particles and Si crystals of thickness approximately 40nm is formed on the upper part of the single crystal silicon carbide layer. Since this transition layer is not uniform in the plane direction, the surface roughness after the step of exposing the carbon containing layer by etching (S14) in FIG. 5 is as large as 2nm or more (RMS in a lO ⁇ m x lO ⁇ m area, hereinafter, referred to as RMS) .
  • this CMP process has the following problems. Since the chemical reaction of polished surface of SiC is slower than that of silicon crystal, the removal speed of SiC by the CMP process is in the order of lOnm per hour, which is extremely slower than that of silicon at 50nm per minute, and accordingly, it takes many hours to polish SiC. Further, the mechanical hardness of SiC is extremely high, and use of diamond abrasive or abrasive for silicon may only cause polishing flaws. Therefore, in polishing of SiC, it is necessary to use a very special abrasive such as for example colloidal silica particles (Patent Documents 9 to 10) . Thus, the CMP process of SiC has many difficulties, and if this CMP process (S15) can be omitted or reduced, it is possible to greatly reduce the costs and hours required for the manufacture of SiC wafers.
  • one object of the present invention is to provide a method of manufacturing a SiC wafer having a single crystal silicon carbide layer of surface roughness 0.5nm (RMS) or below without carrying out a CMP process.
  • Another object of the present invention is to provide a method of manufacturing a SiC wafer having an extremely small surface roughness at roughly the same level of a Si wafer (approximately 0.2nm by RMS) by only carrying out an extremely minor CMP process.
  • the invention according to the present application includes the following aspects (1) to (13) .
  • a method of manufacturing a SiC wafer including the following steps to be carried out sequentially: a step of forming a buffer layer on the surface of a silicon substrate; a step of implanting carbon ions into the silicon substrate via the buffer layer and thereby forming a carbon containing layer where silicon and carbon are mixed; a step of selectively removing the buffer layer from the silicon substrate and thereby exposing the carbon containing layer; and a step of heat treating the silicon substrate and single crystallizing the carbon containing layer and thereby forming a single crystal silicon carbide layer.
  • a method of manufacturing a SiC wafer including the following steps to be carried out sequentially: a step of forming a buffer layer on the surface of a silicon substrate; a step of implanting carbon ions into the silicon substrate via the buffer layer and thereby forming a carbon containing layer where silicon and carbon are mixed; a step of heat treating the silicon substrate and single crystallizing the carbon containing layer and thereby forming a single crystal silicon carbide layer; and a step of selectively removing the buffer layer from the silicon substrate and thereby exposing the single crystal silicon carbide layer.
  • the buffer layer is made of silicon oxide, silicon nitride or a combination thereof.
  • a method of manufacturing a SiC wafer according to (7) wherein the adjustment of the ion implantation conditions considers any of the thickness of the buffer layer, the implantation energy of carbon ions, and the implantation amount of carbon ions .
  • the present invention it is possible to manufacture a SiC wafer having a single crystal silicon carbide layer of surface roughness 0.5nm (RMS) or below without carrying out a CMP process, and consequently it is possible to greatly reduce the costs and hours required for the manufacture of SiC wafers. Or, it is possible to manufacture a SiC wafer having an extremely small surface roughness at roughly the same level of a Si wafer (approximately 0.2nm by RMS) by only carrying out an extremely minor CMP process.
  • RMS surface roughness 0.5nm
  • FIG. 1 is a process chart showing a series of processes in a manufacturing method according to the present invention.
  • FIG. 2 is a flow chart corresponding to FIG. 1.
  • This manufacturing method is a method of manufacturing a SiC wafer 10, including the following steps to be carried out sequentially, a step Sl of forming a buffer layer 2 on the surface of a silicon substrate 1, a step S2 of implanting carbon ions into the silicon substrate 1 via the buffer layer 2 and thereby forming a carbon containing layer 3 where silicon and carbon are mixed, a step S3 of selectively removing the buffer layer 2 from the silicon substrate 1 and thereby exposing the carbon containing layer 3 , a step S4 of heat treating the silicon substrate 1 and single crystallizing the carbon containing layer 3 and thereby forming a single crystal silicon carbide layer 4, and a step S5 of removing an oxide layer 5 that is formed on the surface of the single crystal silicon carbide layer 4 in the course of the heat treatment and thereby exposing the single crystal silicon carbide layer 4.
  • the buffer layer 2 made of silicon oxide
  • the buffer layer 2 is formed, for example, by dry oxidizing or wet oxidizing the silicon substrate 1 at approximately 1000°C. Alternatively, it is formed on the silicon substrate 1 by use of Chemical Vapor Deposition (CVD) . Or, it is formed by a combination of dry oxidation, wet oxidation and CVD. Further, it is possible to form the buffer layer 2 by use of other solid material that can be selectively removed from the silicon substrate 1, and has the same heat resistance as that of silicon oxide or silicon nitride.
  • the thickness of the buffer layer 2 is selected from values in the range approximately 200nm to 600nm, in the case where 100 to 200keV is used as the implantation energy of carbon ions, for example:
  • ion implantation conditions are adjusted so that the carbon atom concentration in the interface between the carbon containing layer 3 (area where silicon and carbon are mixed) and the buffer layer 2 (hereinafter, referred to as "buffer layer 2 and carbon containing layer 3 interface") (at the side of the carbon containing layer 3), that is, the carbon atom concentration at the upper end of the carbon containing layer 3 at the step S2 in FIG. 1 should be 15 atom% or above, and the maximum value of the carbon atom concentration in the carbon containing layer 3 should be 55 atom% or below, and the implantation of carbon ions is carried out.
  • the carbon atom concentration in the buffer layer 2 and carbon containing layer 3 interface (at the side of the carbon containing layer 3) 25 atom% or above .
  • Making the maximum value of the carbon atom concentration in the carbon containing layer 3 55 atom% or below is extremely important to maintain the crystalline property of the single crystal silicon carbide layer 4. If the maximum value of the carbon atom concentration in the carbon containing layer 3 exceeds 55 atom%, after annealing, defects made of ultrafine carbon particles appear in the single crystal silicon carbide layer 4, and the crystalline property of the single crystal silicon carbide layer 4 is deteriorated. On the other hand, if the maximum value of the carbon atom concentration in the carbon containing layer 3 is made 55 atom% or below, it is possible to prevent appearing of the carbon particles.
  • the implantation of carbon ions is carried out in a state where the silicon substrate is heated up to a temperature of 400°C or above. If the substrate heating temperature goes down below 400°C, after implantation, the orientation of single crystal silicon carbide particles structuring the carbon containing layer 3 is distorted, and after annealing, the crystalline property of the single crystal silicon carbide layer 4 is deteriorated, and in the worst case, the layer may becomes a poly layer or an amorphous layer.
  • the implantation of carbon ions is carried out in a state where the silicon substrate is heated up to a temperature of 1000°C or below. If the substrate heating temperature goes up above 1000°C, after implantation, single crystal silicon carbide particles structuring the carbon containing layer 3 is dendritically fused, and after annealing, the extreme precision and uniformity of the single crystal silicon carbide layer 4 are lost.
  • the adjustment of the ion implantation conditions is made by adjusting the implantation energy of carbon ions, and the implantation amount of carbon ions, according to the thickness of the buffer layer 2.
  • the thickness of the buffer layer 2 is 400nm to 550nm, it is appropriate to set the implantation energy of carbon ions approximately 180keV, and the implantation amount of carbon ions 7 x 10 17 to 8 x 10 17 cm “2 .
  • the buffer layer 2 is liquid phase etched, and thereby only the buffer layer 2 is selectively removed.
  • the buffer layer 2 is an oxide
  • dilute hydrofluoric acid, or ammonium fluoride and the like may be used as a liquid phase etchant .
  • heat phosphoric acid and the like may be used as a liquid phase etchant.
  • the silicon substrate 1 is heat treated in an argon gas atmosphere including approximately 0.5 volume % of oxygen at a temperature of 1100°C or above, and below the silicon melting point.
  • the time required for this heat treatment is around 10 hours.
  • the oxide layer 5 is etched by dilute hydrofluoric acid and removed, and thereby the single crystal silicon carbide layer 4 is exposed.
  • the oxide layer 5 is removed, the oxide that is moved out from the carbon containing layer 3 to the surface and taken into the oxide layer 5 is removed completely.
  • the single crystal silicon carbide layer 4 of its surface roughness of 0.5nm (RMS) or below is exposed. The value of this surface roughness is at the level of surface roughness necessary for epitaxial growth.
  • gas phase etching may be carried out in place of liquid phase etching.
  • the heat treatment at the step S4 may be carried out in a non-oxidizing atmosphere.
  • the step S5 may be omitted, and just after annealing, the single crystal silicon carbide layer 4 is exposed on the surface.
  • FIG. 3 is a process chart showing a series of processes in a manufacturing method according to the present invention.
  • FIG. 4 is a flow chart corresponding to FIG. 3.
  • This manufacturing method is a method of manufacturing a SiC wafer 10, including the following steps to be carried out sequentially, a step Sl-2 of forming a buffer layer 2 on the surface of a silicon substrate 1, a step S2-2 of implanting carbon ions into the silicon substrate 1 via the buffer layer 2 and thereby forming a carbon containing layer 3 where silicon and carbon are mixed, a step S3-2 of heat treating the silicon substrate 1 and single crystallizing the carbon containing layer 3 and thereby forming a single crystal silicon carbide layer 4; and a step S4-2 of selectively removing the buffer layer 2 from the silicon substrate 1 and thereby exposing the single crystal silicon carbide layer 4.
  • the silicon substrate 1 is heat treated in an argon gas atmosphere including approximately 0.5 volume % of oxygen at a temperature of 1100°C or above, and below the silicon melting point.
  • the time required for this heat treatment is around 10 hours.
  • the buffer layer 2 is etched by dilute hydrofluoric acid and removed, and thereby the single crystal silicon carbide layer 4 is exposed.
  • the buffer layer 2 is removed, the oxygen that is moved out from the carbon containing layer 3 and taken into the buffer layer 2 is removed completely.
  • the single crystal silicon carbide layer 4 of its surface roughness 0.5nm (RMS) or below is exposed. The value of this surface roughness is at the level of surface roughness necessary for epitaxial growth.
  • gas phase etching may be carried out in place of liquid phase etching.
  • Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and heat treated in a dry oxygen atmosphere at HOO 0 C, and buffer layers made of 300nm-, 350nm-, 400nm- and 450nm- thick surface oxide films were formed on the wafers.
  • Plural samples of respective buffer layer thicknesses were prepared.
  • carbon ions (C + ) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 10 17 /cm 2 , and thereby a carbon containing layer was formed in the silicon substrates.
  • the respective samples were annealed by a vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O 2 atmosphere, for 10 hours, then, the surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid.
  • cross sectional structures near the respective sample surfaces were evaluated by use of a cross section transmission electron microscope (cross section TEM) .
  • the surface roughness (RMS) of the respective samples was evaluated by an atomic force microscope (AFM) .
  • AFM atomic force microscope
  • the surface roughness (RMS) in the respective samples of the oxide film buffer layer thickness 350nm, 400nm, 450nm was 0.8nm, 0.4nm, 0.3nm respectively, thus, the surface roughness was greatly improved along the increase of the oxide film buffer layer thickness, that is, along the increase of the carbon atom concentration in the interface of the buffer layer and the carbon containing layer.
  • the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
  • Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and without forming a buffer layer to these wafers, carbon ions (C + ) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 10 17 /cm 2 , and thereby a carbon containing layer was formed in the silicon substrates.
  • concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the maximum carbon atom concentration of the carbon containing layer was in the range of 48 to 52 atom% .
  • the surface oxide film, the silicon layer and the transition layer were oxidized in a dry oxygen atmosphere at 1100°C, and the surface oxide film formed on the sample surfaces by the oxidization was removed by dilute hydrofluoric acid. Thereafter, the surface roughness (RMS) of the samples was evaluated by AFM. As a result, it was found that the surface roughness (RMS) of the samples was as large as 2.6 to 3.8nm, and was not suitable for epitaxial growth without a CMP process .
  • Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 450nm-thick surface oxide films were formed on the wafers.
  • carbon ions (C + ) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amounts 7.5 x 10 17 /cm 2 , 8.5 x 10 17 /cm 2 , 9.O x 10 17 /cm 2 , and thereby a carbon containing layer was formed in the silicon substrates.
  • the maximum carbon atom concentrations of the carbon containing layer were 51 atom%, 56 atom% and 59 atom% respectively.
  • the oxide film buffer layer formed on the respective samples was removed by dilute hydrofluoric acid.
  • the respective samples were annealed by the vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O 2 atmosphere, for 10 hours, then, the surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid.
  • n-type float zone silicon wafers of diameter 150mm were heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 300nm-thick surface oxide films were formed on the wafers. Further, by Low Pressure Chemical Vapor Deposition (LPCVD) , a buffer layer made of a silicon nitride (Si 3 N 4 ) of thickness 150nm was formed on the oxide film buffer layer. To these wafers, carbon ions (C + ) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 10 17 /cm 2 , and thereby a carbon containing layer was formed in the silicon substrates.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • cross sectional structures near the sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness approximately 50nm was formed on the wafer surface portion.
  • the surface roughness (RMS) of the samples was 0.4nm, and the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process .
  • n-type float zone silicon wafers of diameter 150mm were heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 450nm-thick surface oxide films were formed on the wafers.
  • carbon ions (C + ) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 10 17 /cm 2 , and thereby a carbon containing layer was formed in the silicon substrates.
  • RBS Rutherford back scattering
  • the carbon atom concentration in the interface of the oxide film buffer layer and the carbon containing layer was 47 atom%, and the maximum carbon atom concentrations of the carbon containing layer were 51 atom% .
  • surface oxide film formed on the respective samples was removed by dilute hydrofluoric acid. Thereafter, the respective samples were annealed by the vertical high temperature heat treating furnace at 1200°C, and in a pure atmosphere, for 10 hours. Thereafter, cross sectional structures near the sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness approximately 90nm was formed on the wafer surface portion. The surface roughness (RMS) of the samples was 0.5nm, and the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
  • Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and heat treated in a dry oxygen atmosphere at HOO 0 C, and buffer layers made of 450nm-thick surface oxide films were formed on the wafers.
  • carbon ions (C + ) were implanted at acceleration energy 180keV, dose amount 7.5 x 10 17 /cm 2 , and thereby a carbon containing layer was formed in the silicon substrates.
  • the wafer heating temperatures were set at 350°C, 400°C, 700°C, 1000°C, 1050°C.
  • the respective samples were annealed by a vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O 2 atmosphere, for 10 hours, then, the surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the respective sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the respective samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that in the samples in which the implantation was carried out at the wafer heating temperatures of 350°C, the upper part and the lower part of the single crystal silicon carbide layer were made amorphous, and was not suitable for epitaxial growth.
  • the single crystal silicon carbide layer becomes a mixed layer of a Si area and a silicon carbide area, and was not suitable for epitaxial growth.
  • the wafer heating temperatures of 400 to 1000°C continuous single crystal silicon carbide layers were formed.
  • the surface roughness (RMS) of the respective samples whose wafer heating temperatures were 40O 0 C, 700°C and 1000°C were 0.5nm, 0.3nm and 0.5nm respectively, and the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
  • n-type float zone silicon wafers of diameter 150mm were heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 450nm-thick surface oxide films were formed on the wafers.
  • carbon ions (C + ) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 10 17 /cm 2 , and thereby a carbon containing layer was formed in the silicon substrates.
  • RBS Rutherford back scattering
  • the carbon atom concentration in the interface of the oxide film buffer layer and the carbon containing layer was 47 atom%, and the maximum carbon atom concentrations of the carbon containing layer were 51 atom% .
  • the surface oxide film formed on the respective samples was removed by dilute hydrofluoric acid. Thereafter, the respective samples were annealed by the vertical high temperature heat treating furnace, and in an Ar + 0.5 volume % O 2 atmosphere, for 10 hours. The annealing holding temperatures were set at 1100°C, 1200°C, 1300°C and 1350°C. The surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the respective sample surfaces were evaluated by use of the cross section TEM.
  • the surface roughness (RMS) of the respective samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness approximately 50 to 80nm was formed on the wafer surface portion.
  • the surface roughness (RMS) was 0.7nm, 0.5nm, 0.4nm and 0.3nm respectively, and was improved along the increase of the annealing holding temperatures.
  • the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
  • Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 300nm-, 350nm-, 400nm-, and 450nm-thick surface oxide films were formed on the wafers.
  • Plural samples of respective buffer layer thickness were prepared.
  • carbon ions (C + ) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 10 17 /cm 2 , and thereby a carbon containing layer was formed in the silicon substrates.
  • the respective samples were annealed by a vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O 2 atmosphere, for 10 hours, then, the buffer layer of the respective sample surfaces was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the respective sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the respective samples was evaluated by an atomic force microscope (AFM) . As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness 50 to 160nm was formed on the wafer surface portion. The thickness of the single crystal silicon carbide layer flatly decreased as the oxide film buffer layer thickness increased.
  • the surface roughness (RMS) in the respective samples of the oxide film buffer layer thickness 350nm, 400nm and 450nm was 1.3nm, 0.7nm and 0.5nm respectively, thus, the surface roughness was greatly improved along the increase of the oxide film buffer layer thickness, that is, along the increase of the carbon atom concentration in the interface of the buffer layer and the carbon containing layer.
  • the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
  • FIG. 1 is a process chart showing a series of processes in a manufacturing method according to the present invention
  • FIG. 2 is a flow chart corresponding to FIG. 1;
  • FIG. 3 is a process chart showing a series of processes in a manufacturing method according to the present invention
  • FIG. 4 is a flow chart corresponding to FIG. 3
  • FIG. 5 is a flow chart showing a series of processes according to the prior manufacturing method. Description of Codes

Abstract

Problem to be Solved: To provide a method of manufacturing a SiC wafer having a single crystal silicon carbide layer of surface roughness 0.5nm (RMS) or below without carrying out a CMP process. Solution: A buffer layer 2 is formed on the surface of a silicon substrate 1 (S1). Carbon ions are implanted via the buffer layer 2, and thereby a carbon containing layer 3 in which silicon and carbon are mixed is formed in the silicon substrate 1 (S2). The buffer layer 2 is selectively removed from the silicon substrate 1 and thereby the carbon containing layer 3 is exposed (S3). The silicon substrate 1 is heat treated and the carbon containing layer 3 is single crystallized and thereby a single crystal silicon carbide layer 4 is formed (S4). An oxide layer 5 that is formed on the surface of the single crystal silicon carbide layer 4 in the course of the heat treatment is removed and thereby the single crystal silicon carbide layer 4 is exposed (S5).

Description

Method of Manufacturing Semiconductor Substrate
Field of the Invention
The present invention relates to a technology of manufacturing a semiconductor substrate suitable for the manufacture of power devices and optoelectronic devices, and particularly, relates to a method of manufacturing a semiconductor substrate whose surface portion is made of a single crystal silicon carbide layer.
Background Art
Silicon carbide, having high Schottky barrier, high electric breakdown field strength and high heat conductivity, is suitable for the material for power devices. Further, silicon carbide has the lattice constant, which is close to the lattice constant of a nitride compound semiconductor as a typical optoelectronic semiconductor material, and enables epitaxial growth of the nitride compound semiconductor with few defects, and accordingly it is suitable for the material for optoelectronic devices. From such circumstances, technologies of manufacturing a semiconductor substrate having a single crystal silicon carbide layer on the surface portion of a silicon substrate (hereinafter, referred to as "SiC wafer") are developed (Patent Documents 1 to 8, Non Patent Document 1) .
FIG. 5 shows an example of a method of manufacturing a SiC wafer according to the prior art. This manufacturing method includes a step of implanting carbon ions into a silicon substrate and thereby forming a carbon containing layer where silicon and carbon are mixed (SIl) , a step of annealing the silicon substrate and single crystallizing the carbon containing layer and thereby forming a single crystal silicon carbide layer (S12), a step of heating the silicon substrate 11 in dry oxygen atmosphere and forming a sacrifice layer on the single crystal silicon carbide layer (S13), a step of selectively removing the sacrifice layer from the silicon substrate by etching and thereby exposing the carbon containing layer (S14) , and a step of smoothing the surface of the exposed single crystal silicon carbide layer by CMP (Chemical Mechanical Polishing) (S15) .
[Patent Document 1] US2007/176210A1 [Patent Document 2] Japanese Patent Application Laid-Open
No.2006-327931
[Patent Document 3] US2006/267024A1
[Patent Document 4] Japanese Patent Application National
Publication (Laid-Open) No. 2005-506699 [Patent Document 5] US2004/0248390A1
[Patent Document 6] WO03/034485
[Patent Document 7] WO03/071588
[Patent Document 8] US2005/0020084A1
[Patent Document 9] Japanese Patent Application Laid-Open No.2006-528423
[Patent Document 10] US7060620B2
[Non Patent Document 1] "Organometallic vapor phase epitaxial growth of GaN on a 3c-SiC/Si (111) template formed by C+-ion implantation into Si (111) subs", A. Yamamoto et al . , Journal of Crystal Growth 261 (2004) 266-270
Disclosure of the Invention
Problems to be Solved by the Invention
In the prior-art technologies mentioned above, after the annealing process, on the upper part of the single crystal silicon carbide layer, a transition layer made of poly silicon carbide particles and Si crystals of thickness approximately 40nm is formed. Since this transition layer is not uniform in the plane direction, the surface roughness after the step of exposing the carbon containing layer by etching (S14) in FIG. 5 is as large as 2nm or more (RMS in a lOμm x lOμm area, hereinafter, referred to as RMS) . Accordingly, in order to make the surface roughness of the single crystal silicon carbide layer exposed by etching 0.5nm (RMS) or below as the surface roughness necessary for epitaxial growth, it is indispensable to further carry out the step of smoothing the surface of the exposed single crystal silicon carbide layer by the CMP process (S15) .
However, this CMP process has the following problems. Since the chemical reaction of polished surface of SiC is slower than that of silicon crystal, the removal speed of SiC by the CMP process is in the order of lOnm per hour, which is extremely slower than that of silicon at 50nm per minute, and accordingly, it takes many hours to polish SiC. Further, the mechanical hardness of SiC is extremely high, and use of diamond abrasive or abrasive for silicon may only cause polishing flaws. Therefore, in polishing of SiC, it is necessary to use a very special abrasive such as for example colloidal silica particles (Patent Documents 9 to 10) . Thus, the CMP process of SiC has many difficulties, and if this CMP process (S15) can be omitted or reduced, it is possible to greatly reduce the costs and hours required for the manufacture of SiC wafers.
Accordingly, one object of the present invention is to provide a method of manufacturing a SiC wafer having a single crystal silicon carbide layer of surface roughness 0.5nm (RMS) or below without carrying out a CMP process. Another object of the present invention is to provide a method of manufacturing a SiC wafer having an extremely small surface roughness at roughly the same level of a Si wafer (approximately 0.2nm by RMS) by only carrying out an extremely minor CMP process. Means for Solving the Problems
The invention according to the present application includes the following aspects (1) to (13) .
(1) A method of manufacturing a SiC wafer, including the following steps to be carried out sequentially: a step of forming a buffer layer on the surface of a silicon substrate; a step of implanting carbon ions into the silicon substrate via the buffer layer and thereby forming a carbon containing layer where silicon and carbon are mixed; a step of selectively removing the buffer layer from the silicon substrate and thereby exposing the carbon containing layer; and a step of heat treating the silicon substrate and single crystallizing the carbon containing layer and thereby forming a single crystal silicon carbide layer.
(2) A method of manufacturing a SiC wafer according to (1) , wherein the atmosphere of the heat treatment is a non- oxidizing atmosphere.
(3) A method of manufacturing a SiC wafer according to (1) , wherein oxygen is included in the atmosphere of the heat treatment, and an oxide layer that is formed on the surface of the single crystal silicon carbide layer in the course of the heat treatment is removed after the heat treatment, and thereby the single crystal silicon carbide layer is exposed.
(4) A method of manufacturing a SiC wafer, including the following steps to be carried out sequentially: a step of forming a buffer layer on the surface of a silicon substrate; a step of implanting carbon ions into the silicon substrate via the buffer layer and thereby forming a carbon containing layer where silicon and carbon are mixed; a step of heat treating the silicon substrate and single crystallizing the carbon containing layer and thereby forming a single crystal silicon carbide layer; and a step of selectively removing the buffer layer from the silicon substrate and thereby exposing the single crystal silicon carbide layer.
(5) A method of manufacturing a SiC wafer according to any one of (1) to (4) , wherein the buffer layer is selectively removed by gas phase etching or liquid phase etching.
(6) A method of manufacturing a SiC wafer according to
(5) , wherein the buffer layer is made of silicon oxide, silicon nitride or a combination thereof.
(7) A method of manufacturing a SiC wafer according to any one of (1) to (6) , wherein just after the implantation of carbon ions, ion implantation conditions are adjusted so that the carbon atom concentration at the side of the carbon containing layer in the interface between the carbon containing layer and the buffer layer should be 15 atom% or above, and the maximum value of the carbon atom concentration in the silicon substrate should be 55 atom% or below.
(8) A method of manufacturing a SiC wafer according to (7) , wherein the adjustment of the ion implantation conditions considers any of the thickness of the buffer layer, the implantation energy of carbon ions, and the implantation amount of carbon ions .
(9) A method of manufacturing a SiC wafer according to (7) or (8) , wherein the carbon atom concentration at the side of the carbon containing layer in the interface between the carbon containing layer and the buffer layer is 25 atom% or above.
(10) A method of manufacturing a SiC wafer according to any one of (1) to (9), wherein the implantation of carbon ions is carried out in a state where the silicon substrate is heated up to a temperature of 400°C or above, and 1000°C or below.
(11) A method of manufacturing a SiC wafer according to any one of (1) to (10), wherein the temperature of the heat treatment is 1100°C or above, and below the silicon melting point .
(12) A method of manufacturing a SiC wafer according to (11) , wherein the temperature of the heat treatment is 1200°C or above, and below the silicon melting point.
(13) A method of manufacturing a SiC wafer according to (12), wherein the temperature of the heat treatment is 1300°C or above, and below the silicon melting point.
Effects of the Invention
According to the present invention, it is possible to manufacture a SiC wafer having a single crystal silicon carbide layer of surface roughness 0.5nm (RMS) or below without carrying out a CMP process, and consequently it is possible to greatly reduce the costs and hours required for the manufacture of SiC wafers. Or, it is possible to manufacture a SiC wafer having an extremely small surface roughness at roughly the same level of a Si wafer (approximately 0.2nm by RMS) by only carrying out an extremely minor CMP process.
Best Mode for Carrying out the Invention Next, exemplary embodiments of the present invention are explained.
First Exemplary Embodiment
FIG. 1 is a process chart showing a series of processes in a manufacturing method according to the present invention. FIG. 2 is a flow chart corresponding to FIG. 1.
This manufacturing method is a method of manufacturing a SiC wafer 10, including the following steps to be carried out sequentially, a step Sl of forming a buffer layer 2 on the surface of a silicon substrate 1, a step S2 of implanting carbon ions into the silicon substrate 1 via the buffer layer 2 and thereby forming a carbon containing layer 3 where silicon and carbon are mixed, a step S3 of selectively removing the buffer layer 2 from the silicon substrate 1 and thereby exposing the carbon containing layer 3 , a step S4 of heat treating the silicon substrate 1 and single crystallizing the carbon containing layer 3 and thereby forming a single crystal silicon carbide layer 4, and a step S5 of removing an oxide layer 5 that is formed on the surface of the single crystal silicon carbide layer 4 in the course of the heat treatment and thereby exposing the single crystal silicon carbide layer 4.
At the step Sl, on the surface layer portion of the silicon substrate 1, the buffer layer 2 made of silicon oxide
(SiO2) , silicon nitride (Si3N4, SiN) or a combination thereof is formed. The buffer layer 2 is formed, for example, by dry oxidizing or wet oxidizing the silicon substrate 1 at approximately 1000°C. Alternatively, it is formed on the silicon substrate 1 by use of Chemical Vapor Deposition (CVD) . Or, it is formed by a combination of dry oxidation, wet oxidation and CVD. Further, it is possible to form the buffer layer 2 by use of other solid material that can be selectively removed from the silicon substrate 1, and has the same heat resistance as that of silicon oxide or silicon nitride. The thickness of the buffer layer 2 is selected from values in the range approximately 200nm to 600nm, in the case where 100 to 200keV is used as the implantation energy of carbon ions, for example:
At the step S2 , just after the implantation of carbon ions, ion implantation conditions are adjusted so that the carbon atom concentration in the interface between the carbon containing layer 3 (area where silicon and carbon are mixed) and the buffer layer 2 (hereinafter, referred to as "buffer layer 2 and carbon containing layer 3 interface") (at the side of the carbon containing layer 3), that is, the carbon atom concentration at the upper end of the carbon containing layer 3 at the step S2 in FIG. 1 should be 15 atom% or above, and the maximum value of the carbon atom concentration in the carbon containing layer 3 should be 55 atom% or below, and the implantation of carbon ions is carried out.
Making the carbon atom concentration in the buffer layer 2 and carbon containing layer 3 interface (at the side of the carbon containing layer 3) 15 atom% or above is extremely important to realize preferable surface roughness. If the carbon atom concentration in the buffer layer 2 and carbon containing layer 3 interface (at the side of the carbon containing layer 3) goes down below 15 atom%, after annealing, on the upper part of the single crystal silicon carbide layer 4, a transition layer made of poly silicon carbide particles and Si crystals starts to appear, and the surface roughness after completion of all the processes is deteriorated. On the other hand, if the carbon atom concentration in the buffer layer 2 and carbon containing layer 3 interface (at the side of the carbon containing layer 3) is made 15 atom% or above, the transition layer disappears, and preferable surface roughness can be realized.
More preferably, in order to stably realize preferable surface roughness, it is desirable to make the carbon atom concentration in the buffer layer 2 and carbon containing layer 3 interface (at the side of the carbon containing layer 3) 25 atom% or above .
Making the maximum value of the carbon atom concentration in the carbon containing layer 3 55 atom% or below is extremely important to maintain the crystalline property of the single crystal silicon carbide layer 4. If the maximum value of the carbon atom concentration in the carbon containing layer 3 exceeds 55 atom%, after annealing, defects made of ultrafine carbon particles appear in the single crystal silicon carbide layer 4, and the crystalline property of the single crystal silicon carbide layer 4 is deteriorated. On the other hand, if the maximum value of the carbon atom concentration in the carbon containing layer 3 is made 55 atom% or below, it is possible to prevent appearing of the carbon particles.
More preferably, in order to stably realize the prevention of carbon particles, it is desirable to make the maximum value of the carbon atom concentration in the carbon containing layer 3 50 atom% or below.
It is desirable that the implantation of carbon ions is carried out in a state where the silicon substrate is heated up to a temperature of 400°C or above. If the substrate heating temperature goes down below 400°C, after implantation, the orientation of single crystal silicon carbide particles structuring the carbon containing layer 3 is distorted, and after annealing, the crystalline property of the single crystal silicon carbide layer 4 is deteriorated, and in the worst case, the layer may becomes a poly layer or an amorphous layer.
More preferably, in order to further increase the crystalline property of the single crystal silicon carbide layer 4, it is desirable to carry out the implantation of carbon ions in a state where the silicon substrate is heated up to a temperature of 500°C or above.
It is desirable that the implantation of carbon ions is carried out in a state where the silicon substrate is heated up to a temperature of 1000°C or below. If the substrate heating temperature goes up above 1000°C, after implantation, single crystal silicon carbide particles structuring the carbon containing layer 3 is dendritically fused, and after annealing, the extreme precision and uniformity of the single crystal silicon carbide layer 4 are lost.
More preferably, in order to further increase the extreme precision and uniformity of the single crystal silicon carbide layer 4, it is desirable to carry out the implantation of carbon ions in a state where the silicon substrate is heated up to a temperature of 800°C or below.
Meanwhile, the adjustment of the ion implantation conditions is made by adjusting the implantation energy of carbon ions, and the implantation amount of carbon ions, according to the thickness of the buffer layer 2.
For example, in the case where the thickness of the buffer layer 2 is 400nm to 550nm, it is appropriate to set the implantation energy of carbon ions approximately 180keV, and the implantation amount of carbon ions 7 x 1017 to 8 x 1017 cm"2.
At the step S3, the buffer layer 2 is liquid phase etched, and thereby only the buffer layer 2 is selectively removed. In the case where the buffer layer 2 is an oxide, dilute hydrofluoric acid, or ammonium fluoride and the like may be used as a liquid phase etchant . In the case where the buffer layer 2 is a nitride, heat phosphoric acid and the like may be used as a liquid phase etchant.
At the step S4, the silicon substrate 1 is heat treated in an argon gas atmosphere including approximately 0.5 volume % of oxygen at a temperature of 1100°C or above, and below the silicon melting point. The time required for this heat treatment is around 10 hours. In order to further improve the surface roughness, it is desirable to carry out the heat treatment at a temperature of 1200°C or above, and furthermore 1300°C or above in the temperature range below the silicon melting point. Since in the course where the carbon containing layer 3 is single crystallized, the oxide in the carbon containing layer 3 moves to the surface, the finally formed oxygen content in the single crystal silicon carbide layer 4 is extremely small.
At the step S5, the oxide layer 5 is etched by dilute hydrofluoric acid and removed, and thereby the single crystal silicon carbide layer 4 is exposed. When the oxide layer 5 is removed, the oxide that is moved out from the carbon containing layer 3 to the surface and taken into the oxide layer 5 is removed completely. As a result, the single crystal silicon carbide layer 4 of its surface roughness of 0.5nm (RMS) or below is exposed. The value of this surface roughness is at the level of surface roughness necessary for epitaxial growth.
At the steps S3 and S5, gas phase etching may be carried out in place of liquid phase etching.
As mentioned above, according to the manufacturing method of the First Exemplary Embodiment, it is possible to manufacture a SiC wafer 10 having the single crystal silicon carbide layer 4 of surface roughness 0.5nm (RMS) or below without carrying out a CMP process.
Meanwhile, the heat treatment at the step S4 may be carried out in a non-oxidizing atmosphere. In this case, the step S5 may be omitted, and just after annealing, the single crystal silicon carbide layer 4 is exposed on the surface.
Second Exemplary Embodiment
FIG. 3 is a process chart showing a series of processes in a manufacturing method according to the present invention. FIG. 4 is a flow chart corresponding to FIG. 3.
This manufacturing method is a method of manufacturing a SiC wafer 10, including the following steps to be carried out sequentially, a step Sl-2 of forming a buffer layer 2 on the surface of a silicon substrate 1, a step S2-2 of implanting carbon ions into the silicon substrate 1 via the buffer layer 2 and thereby forming a carbon containing layer 3 where silicon and carbon are mixed, a step S3-2 of heat treating the silicon substrate 1 and single crystallizing the carbon containing layer 3 and thereby forming a single crystal silicon carbide layer 4; and a step S4-2 of selectively removing the buffer layer 2 from the silicon substrate 1 and thereby exposing the single crystal silicon carbide layer 4.
Among the above steps Sl-2 to S4-2, Sl-2 and S2-2 are same as the steps Sl and S2 in the First Exemplary Embodiment.
At the step S3-2, the silicon substrate 1 is heat treated in an argon gas atmosphere including approximately 0.5 volume % of oxygen at a temperature of 1100°C or above, and below the silicon melting point. The time required for this heat treatment is around 10 hours. In order to further improve the surface roughness, it is desirable to carry out the heat treatment at a temperature of 1200°C or above, and furthermore 1300°C or above, in the temperature range below the silicon melting point. Since in the course where the carbon containing layer 3 is single crystallized, the oxygen in the carbon containing layer 3 moves to the buffer layer 2, the finally formed oxygen content in the single crystal silicon carbide layer 4 is extremely small.
At the step S4-2, the buffer layer 2 is etched by dilute hydrofluoric acid and removed, and thereby the single crystal silicon carbide layer 4 is exposed. When the buffer layer 2 is removed, the oxygen that is moved out from the carbon containing layer 3 and taken into the buffer layer 2 is removed completely. As a result, the single crystal silicon carbide layer 4 of its surface roughness 0.5nm (RMS) or below is exposed. The value of this surface roughness is at the level of surface roughness necessary for epitaxial growth.
At the step S4-2, gas phase etching may be carried out in place of liquid phase etching.
As mentioned above, according to the manufacturing method according to the Second Exemplary Embodiment, it is possible to manufacture a SiC wafer 10 having the single crystal silicon carbide layer 4 of surface roughness 0.5nm (RMS) or below, without carrying out a CMP process.
Embodiments
Hereinafter, the present invention is explained more concretely with reference to embodiments, but it should be noted that the present invention is not limited to these. First Embodiment
Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and heat treated in a dry oxygen atmosphere at HOO0C, and buffer layers made of 300nm-, 350nm-, 400nm- and 450nm- thick surface oxide films were formed on the wafers. Plural samples of respective buffer layer thicknesses were prepared. To these wafers, carbon ions (C+) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 1017/cm2, and thereby a carbon containing layer was formed in the silicon substrates. After the implantation, with regard to part of samples, by Rutherford back scattering (RBS) measurement, concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the carbon atom concentrations in the interface of the buffer layer and the carbon containing layer (at the side of the carbon containing layer) in the respective samples of surface oxide thicknesses 300nm, 350nm, 400nm, and 450nm were 9 atom%, 19 atom%, 32 atom%, and 47atom% respectively. And in each sample, the maximum carbon atom concentration of the carbon containing layer was in the range 48 to 52 atom% . With regard to the remaining samples, after the implantation, the oxide film buffer layer formed on the respective samples was removed by dilute hydrofluoric acid.
Thereafter, the respective samples were annealed by a vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O2 atmosphere, for 10 hours, then, the surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the respective sample surfaces were evaluated by use of a cross section transmission electron microscope (cross section TEM) . Further, the surface roughness (RMS) of the respective samples was evaluated by an atomic force microscope (AFM) . As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness 50 to 120nm was formed on the surface part of the samples. The thickness of the single crystal silicon carbide layer flatly decreased as the oxide film buffer layer thickness increased. In the samples of the oxide film buffer layer thickness of 300nm, a transition layer made of poly SiC particles and Si crystals was seen on the wafer uppermost surface, and it was found that the surface roughness (RMS) was as large as approximately 4nm. In the samples of the oxide film buffer layer thickness 350nm or above, the transition layer disappeared. The surface roughness (RMS) in the respective samples of the oxide film buffer layer thickness 350nm, 400nm, 450nm was 0.8nm, 0.4nm, 0.3nm respectively, thus, the surface roughness was greatly improved along the increase of the oxide film buffer layer thickness, that is, along the increase of the carbon atom concentration in the interface of the buffer layer and the carbon containing layer. In the respective samples of the oxide film buffer layer thickness 400nm, 450nm, the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
First Comparative Example
Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and without forming a buffer layer to these wafers, carbon ions (C+) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 1017/cm2, and thereby a carbon containing layer was formed in the silicon substrates. After the implantation, by the RBS measurement, concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the maximum carbon atom concentration of the carbon containing layer was in the range of 48 to 52 atom% . Thereafter, the respective samples were annealed by the vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O2 atmosphere, for 10 hours. Then, with regard to part of samples, cross sectional structures near the surfaces were evaluated by use of the cross section TEM. As a result, it was found that a laminated structure consisting of a surface oxide film of thickness approximately 130nm, a silicon layer of thickness approximately 260nm, a transition layer of thickness approximately 40nm, and a single crystal silicon carbide layer of thickness approximately 120nm was formed. Further, with regard to part of samples, after high temperature annealing, the surface oxide film, the silicon layer and the transition layer were oxidized in a dry oxygen atmosphere at 1100°C, and the surface oxide film formed on the sample surfaces by the oxidization was removed by dilute hydrofluoric acid. Thereafter, the surface roughness (RMS) of the samples was evaluated by AFM. As a result, it was found that the surface roughness (RMS) of the samples was as large as 2.6 to 3.8nm, and was not suitable for epitaxial growth without a CMP process .
Second Embodiment
Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 450nm-thick surface oxide films were formed on the wafers. To these wafers, carbon ions (C+) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amounts 7.5 x 1017/cm2, 8.5 x 1017/cm2, 9.O x 1017/cm2, and thereby a carbon containing layer was formed in the silicon substrates. After the implantation, with regard to part of samples, by Rutherford back scattering (RBS) measurement, concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the carbon atom concentrations in the interface of the buffer layer and the carbon containing layer (at the side of the carbon containing layer) in the respective samples of dose amounts 7.5 x 1017/cm2, 8.5 x 1017/cm2 and 9.O x 1017/cm2 were 47 atom%, 53 atom% and 56 atom% respectively. And in the respective samples of dose amounts 7.5 x 1017/cm2, 8.5 x 1017/cm2 and 9.0 x 1017/cm2, the maximum carbon atom concentrations of the carbon containing layer were 51 atom%, 56 atom% and 59 atom% respectively. With regard to the remaining samples, after the implantation, the oxide film buffer layer formed on the respective samples was removed by dilute hydrofluoric acid. Thereafter, the respective samples were annealed by the vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O2 atmosphere, for 10 hours, then, the surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the respective sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the respective samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that in the samples whose dose amount was 9.0 x 1017/cm2, defects made of carbon particles occurred in the single crystal silicon carbide layer arising from the excessive dose amount, and were not suitable for epitaxial growth. In the samples whose dose amounts were 7.5 x 1017/cm2, 8.5 x 1017/cm2, defects made of carbon particles were not seen. The surface roughness (RMS) in the respective samples whose dose amounts were 7.5 x 1017/cm2, 8.5 x 1017/cm2 was 0.3nm, 0.4nm respectively, and the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
Third Embodiment
(111) n-type float zone silicon wafers of diameter 150mm were heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 300nm-thick surface oxide films were formed on the wafers. Further, by Low Pressure Chemical Vapor Deposition (LPCVD) , a buffer layer made of a silicon nitride (Si3N4) of thickness 150nm was formed on the oxide film buffer layer. To these wafers, carbon ions (C+) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 1017/cm2, and thereby a carbon containing layer was formed in the silicon substrates. After the implantation, by Rutherford back scattering (RBS) measurement, concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the carbon atom concentration in the interface of the oxide film buffer layer and the carbon containing layer was 45 atom%, and the maximum carbon atom concentrations of the carbon containing layer were 51 atom% . After the implantation, the surface oxide film formed on the respective samples was removed by dilute hydrofluoric acid. Thereafter, the respective samples were annealed by the vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O2 atmosphere, for 10 hours, then, the surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness approximately 50nm was formed on the wafer surface portion.
The surface roughness (RMS) of the samples was 0.4nm, and the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process .
Fourth Embodiment
(111) n-type float zone silicon wafers of diameter 150mm were heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 450nm-thick surface oxide films were formed on the wafers. To these wafers, carbon ions (C+) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 1017/cm2, and thereby a carbon containing layer was formed in the silicon substrates. After the implantation, by Rutherford back scattering (RBS) measurement, concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the carbon atom concentration in the interface of the oxide film buffer layer and the carbon containing layer was 47 atom%, and the maximum carbon atom concentrations of the carbon containing layer were 51 atom% . After the implantation, surface oxide film formed on the respective samples was removed by dilute hydrofluoric acid. Thereafter, the respective samples were annealed by the vertical high temperature heat treating furnace at 1200°C, and in a pure atmosphere, for 10 hours. Thereafter, cross sectional structures near the sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness approximately 90nm was formed on the wafer surface portion. The surface roughness (RMS) of the samples was 0.5nm, and the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
Fifth Embodiment
Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and heat treated in a dry oxygen atmosphere at HOO0C, and buffer layers made of 450nm-thick surface oxide films were formed on the wafers. To these wafers, carbon ions (C+) were implanted at acceleration energy 180keV, dose amount 7.5 x 1017/cm2, and thereby a carbon containing layer was formed in the silicon substrates. At this moment, the wafer heating temperatures were set at 350°C, 400°C, 700°C, 1000°C, 1050°C. After the implantation, with regard to part of samples, by Rutherford back scattering (RBS) measurement, concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the carbon atom concentrations in the interface of the buffer layer and the carbon containing layer (at the side of the carbon containing layer) were in the range of 45 to 48 atom% . And in each sample, the maximum carbon atom concentration of the carbon containing layer was in the range of 47 to 52 atom% . With regard to the remaining samples, after the implantation, the oxide film buffer layer formed on the respective samples was removed by dilute hydrofluoric acid. Thereafter, the respective samples were annealed by a vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O2 atmosphere, for 10 hours, then, the surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the respective sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the respective samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that in the samples in which the implantation was carried out at the wafer heating temperatures of 350°C, the upper part and the lower part of the single crystal silicon carbide layer were made amorphous, and was not suitable for epitaxial growth. Further, it was found that in the samples in which the implantation was carried out at the wafer heating temperatures of 1050°C, the single crystal silicon carbide layer becomes a mixed layer of a Si area and a silicon carbide area, and was not suitable for epitaxial growth. In the samples in which the implantation was carried out at the wafer heating temperatures of 400 to 1000°C, continuous single crystal silicon carbide layers were formed. The surface roughness (RMS) of the respective samples whose wafer heating temperatures were 40O0C, 700°C and 1000°C were 0.5nm, 0.3nm and 0.5nm respectively, and the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
Sixth Embodiment
(111) n-type float zone silicon wafers of diameter 150mm were heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 450nm-thick surface oxide films were formed on the wafers. To these wafers, carbon ions (C+) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 1017/cm2, and thereby a carbon containing layer was formed in the silicon substrates. After the implantation, by Rutherford back scattering (RBS) measurement, concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the carbon atom concentration in the interface of the oxide film buffer layer and the carbon containing layer was 47 atom%, and the maximum carbon atom concentrations of the carbon containing layer were 51 atom% . After the implantation, the surface oxide film formed on the respective samples was removed by dilute hydrofluoric acid. Thereafter, the respective samples were annealed by the vertical high temperature heat treating furnace, and in an Ar + 0.5 volume % O2 atmosphere, for 10 hours. The annealing holding temperatures were set at 1100°C, 1200°C, 1300°C and 1350°C. The surface oxide film formed on the sample surface was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the respective sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the respective samples was evaluated by AFM. As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness approximately 50 to 80nm was formed on the wafer surface portion. In the respective samples whose annealing holding temperatures were 1100°C, 1200°C, 1300°C and 1350°C, the surface roughness (RMS) was 0.7nm, 0.5nm, 0.4nm and 0.3nm respectively, and was improved along the increase of the annealing holding temperatures. In the respective sample whose annealing holding temperatures were 1200°C or above, the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
Seventh Embodiment
Plural (111) n-type float zone silicon wafers of diameter 150mm were prepared, and heat treated in a dry oxygen atmosphere at 1100°C, and buffer layers made of 300nm-, 350nm-, 400nm-, and 450nm-thick surface oxide films were formed on the wafers. Plural samples of respective buffer layer thickness were prepared. To these wafers, carbon ions (C+) were implanted at wafer heating temperature 550°C, acceleration energy 180keV, dose amount 7.5 x 1017/cm2, and thereby a carbon containing layer was formed in the silicon substrates. After the implantation, with regard to part of samples, by Rutherford back scattering (RBS) measurement, concentration profiles of implanted carbon ions in the substrate depth direction were acquired. As a result, the carbon atom concentrations in the interface of the buffer layer and the carbon containing layer (at the side of the carbon containing layer) in the respective samples of surface oxide film thicknesses 300nm, 350nm, 400nm, and 450nm were 9 atom%, 19 atom%, 32 atom%, and 47atom% respectively. And in each sample, the maximum carbon atom concentration of the carbon containing layer was in the range of 48 to 52 atom% . With regard to the remaining samples, after the implantation, the respective samples were annealed by a vertical high temperature heat treating furnace at 1350°C, and in an Ar + 0.5 volume % O2 atmosphere, for 10 hours, then, the buffer layer of the respective sample surfaces was removed by dilute hydrofluoric acid. Thereafter, cross sectional structures near the respective sample surfaces were evaluated by use of the cross section TEM. Further, the surface roughness (RMS) of the respective samples was evaluated by an atomic force microscope (AFM) . As a result of the cross section TEM evaluation, it was found that a single crystal silicon carbide layer of thickness 50 to 160nm was formed on the wafer surface portion. The thickness of the single crystal silicon carbide layer flatly decreased as the oxide film buffer layer thickness increased. In the samples of the oxide film buffer layer thickness 300nm, a transition layer was found partially left on the wafer uppermost surface, and it was found that the surface roughness (RMS) was as large as approximately 7nm. In the samples of the oxide film buffer layer thickness 350nm or above, the transition layer disappeared. The surface roughness (RMS) in the respective samples of the oxide film buffer layer thickness 350nm, 400nm and 450nm was 1.3nm, 0.7nm and 0.5nm respectively, thus, the surface roughness was greatly improved along the increase of the oxide film buffer layer thickness, that is, along the increase of the carbon atom concentration in the interface of the buffer layer and the carbon containing layer. In particular, in the samples of the oxide film buffer layer thickness 450nm, the surface roughness of 0.5nm (RMS) or below suitable for epitaxial growth was achieved without carrying out a CMP process.
Brief Description of Drawings
FIG. 1 is a process chart showing a series of processes in a manufacturing method according to the present invention; FIG. 2 is a flow chart corresponding to FIG. 1;
FIG. 3 is a process chart showing a series of processes in a manufacturing method according to the present invention; FIG. 4 is a flow chart corresponding to FIG. 3; and FIG. 5 is a flow chart showing a series of processes according to the prior manufacturing method. Description of Codes
1 Silicon substrate 2 Buffer layer
3 Carbon containing layer
4 Single crystal silicon carbide layer
5 Oxide layer 10 SiC wafer

Claims

Claims :
1. A method of manufacturing a semiconductor substrate whose surface portion is made of a single crystal silicon carbide layer, comprising the following steps to be carried out sequentially : a step of forming a buffer layer on the surface of a silicon substrate; a step of implanting carbon ions into the silicon substrate via the buffer layer and thereby forming a carbon containing layer where silicon and carbon are mixed; a step of selectively removing the buffer layer from the silicon substrate and thereby exposing the carbon containing layer; and a step of heat treating the silicon substrate and single crystallizing the carbon containing layer and thereby forming a single crystal silicon carbide layer.
2. A method of manufacturing a semiconductor substrate according to claim 1, wherein the atmosphere of the heat treatment is a non-oxygenated atmosphere.
3. A method of manufacturing a semiconductor substrate according to claim 1, wherein oxygen is included in the atmosphere of the heat treatment, and an oxide layer that is formed on the surface of the single crystal silicon carbide layer in the course of the heat treatment is removed after the heat treatment, and thereby the single crystal silicon carbide layer is exposed.
4. A method of manufacturing a semiconductor substrate whose surface portion is made of a single crystal silicon carbide layer, comprising the following steps to be carried out sequentially : a step of forming a buffer layer on the surface of a silicon substrate; a step of implanting carbon ions into the silicon substrate via the buffer layer and thereby forming a carbon containing layer where silicon and carbon are mixed; a step of heat treating the silicon substrate and single crystallizing the carbon containing layer and thereby forming a single crystal silicon carbide layer; and a step of selectively removing the buffer layer from the silicon substrate and thereby exposing the single crystal silicon carbide layer.
5. A method of manufacturing a semiconductor substrate according to one of claims 1 to 4 , wherein the buffer layer is selectively removed by gas phase etching or liquid phase etching.
6. A method of manufacturing a semiconductor substrate according to claim 5, wherein the buffer layer is made of silicon oxide, silicon nitride or a combination thereof.
7. A method of manufacturing a semiconductor substrate according to one of claims 1 to 6, wherein just after the implantation of carbon ions, ion implantation conditions are adjusted so that the carbon atom concentration at the side of the carbon containing layer in the interface between the carbon containing layer and the buffer layer should be 15 atom% or above, and the maximum value of the carbon atom concentration in the carbon containing layer should be 55 atom% or below.
8. A method of manufacturing a semiconductor substrate according to claim 7, wherein the ion implantation conditions include any of the thickness of the buffer layer, the implantation energy of carbon ions, and the implantation amount of carbon ions .
9. A method of manufacturing a semiconductor substrate according to claim 7 or 8, wherein the carbon atom concentration at the side of the carbon containing layer in the interface between the carbon containing layer and the buffer layer is 25 atom% or above.
10. A method of manufacturing a semiconductor substrate according to one of claims 1 to 9 , wherein the implantation of carbon ions is carried out in a state where the silicon substrate is heated up to a temperature of 400°C or above, and 10000C or below.
11. A method of manufacturing a semiconductor substrate according to one of claims 1 to 10, wherein the temperature of the heat treatment is 1100°C or above, and below the silicon melting point.
12. A method of manufacturing a semiconductor substrate according to claim 11, wherein the temperature of the heat treatment is 1200°C or above, and below the silicon melting point .
13. A method of manufacturing a semiconductor substrate according to claim 12, wherein the temperature of the heat treatment is 1300°C or above, and below the silicon melting point.
PCT/EP2008/010237 2007-12-21 2008-12-03 Method of manufacturing semiconductor substrate WO2009080177A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-330563 2007-12-21
JP2007330563A JP2009149481A (en) 2007-12-21 2007-12-21 Method for manufacturing semiconductor substrate

Publications (1)

Publication Number Publication Date
WO2009080177A1 true WO2009080177A1 (en) 2009-07-02

Family

ID=40404338

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/010237 WO2009080177A1 (en) 2007-12-21 2008-12-03 Method of manufacturing semiconductor substrate

Country Status (3)

Country Link
JP (1) JP2009149481A (en)
TW (1) TW200929365A (en)
WO (1) WO2009080177A1 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2172967A1 (en) * 2008-08-04 2010-04-07 Siltronic AG Method for manufacturing silicon carbide
US8860040B2 (en) 2012-09-11 2014-10-14 Dow Corning Corporation High voltage power semiconductor devices on SiC
US8940614B2 (en) 2013-03-15 2015-01-27 Dow Corning Corporation SiC substrate with SiC epitaxial film
US9018639B2 (en) 2012-10-26 2015-04-28 Dow Corning Corporation Flat SiC semiconductor substrate
US9017804B2 (en) 2013-02-05 2015-04-28 Dow Corning Corporation Method to reduce dislocations in SiC crystal growth
US9279192B2 (en) 2014-07-29 2016-03-08 Dow Corning Corporation Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
CN106489187A (en) * 2014-07-10 2017-03-08 株式会社丰田自动织机 Semiconductor substrate and the manufacture method of semiconductor substrate
US9738991B2 (en) 2013-02-05 2017-08-22 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a supporting shelf which permits thermal expansion
US9797064B2 (en) 2013-02-05 2017-10-24 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a support shelf which permits thermal expansion
US20190189450A1 (en) * 2017-12-15 2019-06-20 Nuflare Technology, Inc. Method of manufacturing semiconductor device
EP3666935A4 (en) * 2018-10-16 2020-10-14 Sicc Co., Ltd. High-purity silicon carbide single crystal substrate and preparation method therefor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4440072C1 (en) * 1994-11-10 1996-02-22 Inst Halbleiterphysik Gmbh Forming trenched monocrystalline silicon carbide layer in substrate
US5874348A (en) * 1993-03-30 1999-02-23 Sony Corporation Semiconductor wafer and method of manufacturing same
WO2001072104A1 (en) * 2000-03-31 2001-10-04 Consejo Superior De Investigaciones Científicas Method for the production of silicon carbide (sic) layers by means of ionic implantation of carbon and anneals
DE10024857A1 (en) * 2000-05-19 2001-11-29 Infineon Technologies Ag Production of a partially single crystalline silicon carbide layer in a silicon wafer comprises preparing a silicon wafer, implanting carbon ions into the wafer by ion implantation, and subjecting the wafer to a thermal radiation source
US20040248390A1 (en) * 2001-10-12 2004-12-09 Wilfried Attenberger Method for forming a layered semiconductor technology structure and corresponding layered semiconductor technology structure
JP2005303010A (en) * 2004-04-12 2005-10-27 Matsushita Electric Ind Co Ltd Silicon carbide element and its manufacturing method
JP2006313922A (en) * 1993-03-30 2006-11-16 Sony Corp Solid-state imaging device, manufacturing method thereof, si substrate, and manufacturing method of semiconductor substrate

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5874348A (en) * 1993-03-30 1999-02-23 Sony Corporation Semiconductor wafer and method of manufacturing same
JP2006313922A (en) * 1993-03-30 2006-11-16 Sony Corp Solid-state imaging device, manufacturing method thereof, si substrate, and manufacturing method of semiconductor substrate
DE4440072C1 (en) * 1994-11-10 1996-02-22 Inst Halbleiterphysik Gmbh Forming trenched monocrystalline silicon carbide layer in substrate
WO2001072104A1 (en) * 2000-03-31 2001-10-04 Consejo Superior De Investigaciones Científicas Method for the production of silicon carbide (sic) layers by means of ionic implantation of carbon and anneals
DE10024857A1 (en) * 2000-05-19 2001-11-29 Infineon Technologies Ag Production of a partially single crystalline silicon carbide layer in a silicon wafer comprises preparing a silicon wafer, implanting carbon ions into the wafer by ion implantation, and subjecting the wafer to a thermal radiation source
US20040248390A1 (en) * 2001-10-12 2004-12-09 Wilfried Attenberger Method for forming a layered semiconductor technology structure and corresponding layered semiconductor technology structure
JP2005303010A (en) * 2004-04-12 2005-10-27 Matsushita Electric Ind Co Ltd Silicon carbide element and its manufacturing method

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2172967A1 (en) * 2008-08-04 2010-04-07 Siltronic AG Method for manufacturing silicon carbide
US8860040B2 (en) 2012-09-11 2014-10-14 Dow Corning Corporation High voltage power semiconductor devices on SiC
US9337277B2 (en) 2012-09-11 2016-05-10 Dow Corning Corporation High voltage power semiconductor device on SiC
US9018639B2 (en) 2012-10-26 2015-04-28 Dow Corning Corporation Flat SiC semiconductor substrate
US9165779B2 (en) 2012-10-26 2015-10-20 Dow Corning Corporation Flat SiC semiconductor substrate
US9738991B2 (en) 2013-02-05 2017-08-22 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a supporting shelf which permits thermal expansion
US9017804B2 (en) 2013-02-05 2015-04-28 Dow Corning Corporation Method to reduce dislocations in SiC crystal growth
US9797064B2 (en) 2013-02-05 2017-10-24 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a support shelf which permits thermal expansion
US8940614B2 (en) 2013-03-15 2015-01-27 Dow Corning Corporation SiC substrate with SiC epitaxial film
CN106489187A (en) * 2014-07-10 2017-03-08 株式会社丰田自动织机 Semiconductor substrate and the manufacture method of semiconductor substrate
EP3168862A4 (en) * 2014-07-10 2018-06-20 Sicoxs Corporation Semiconductor substrate and semiconductor substrate production method
CN106489187B (en) * 2014-07-10 2019-10-25 株式会社希克斯 The manufacturing method of semiconductor substrate and semiconductor substrate
US9279192B2 (en) 2014-07-29 2016-03-08 Dow Corning Corporation Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
US10002760B2 (en) 2014-07-29 2018-06-19 Dow Silicones Corporation Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
US20190189450A1 (en) * 2017-12-15 2019-06-20 Nuflare Technology, Inc. Method of manufacturing semiconductor device
EP3666935A4 (en) * 2018-10-16 2020-10-14 Sicc Co., Ltd. High-purity silicon carbide single crystal substrate and preparation method therefor

Also Published As

Publication number Publication date
JP2009149481A (en) 2009-07-09
TW200929365A (en) 2009-07-01

Similar Documents

Publication Publication Date Title
WO2009080177A1 (en) Method of manufacturing semiconductor substrate
TW201707051A (en) Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
KR101030455B1 (en) Silicon semiconductor substrate and its manufacturing method
TW201630113A (en) A method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers
KR100721986B1 (en) Soi wafer and process for producing it
JP4442560B2 (en) Manufacturing method of SOI wafer
JP2020513693A (en) High resistance silicon-on-insulator structure and manufacturing method thereof
KR102551310B1 (en) Radio Frequency Silicon-on-Insulator Wafer Platform with Superior Performance, Stability and Manufacturability
KR101066315B1 (en) Method of producing bonded wafer
JP2010141272A (en) Epitaxial wafer and its production method
EP2187429B1 (en) Bonding wafer manufacturing method
CN114556526A (en) Method of forming a high resistivity process support for a composite substrate
JP3963154B2 (en) Method for manufacturing silicon carbide Schottky barrier diode
US11881404B2 (en) Method and system for diffusing magnesium in gallium nitride materials using sputtered magnesium sources
JP4367599B2 (en) Deposition method of high dielectric constant thin film
JP2008159811A (en) Method for manufacturing soi wafer, and soi wafer
KR20220038695A (en) Method for manufacturing a composite structure including a thin layer of single crystal SIC on a carrier substrate made of polycrystalline SIC
US9153658B2 (en) Semiconductor device and method of manufacturing the same
US8013417B2 (en) Low cost substrates and method of forming such substrates
EP4026644A1 (en) Chemical bonding method and joined structure
EP2172967A1 (en) Method for manufacturing silicon carbide
JP2010062219A (en) Production process of silicon carbide
WO1990013912A1 (en) Silicon oxide film and semiconductor device having the same
US8338277B2 (en) Method for manufacturing SOI substrate
JP4529065B2 (en) Manufacturing method of silicon single crystal wafer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08865779

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08865779

Country of ref document: EP

Kind code of ref document: A1