JP2005303010A - Silicon carbide element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce surface irregularities of a silicon carbide layer generated by activated anneal and to raise dopant concentration in a surface region of the silicon carbide layer without complicating a manufacturing process in the manufacturing method of the silicon carbide element. <P>SOLUTION: The manufacturing method of the silicon carbide element has (A) a process for preparing a substrate 1 with the silicon carbide layer 2 whose surface is covered with a cap layer 5, (B) a process for forming an impurity dope layer 6 by implanting impurity ion 3 to at least a part of the silicon carbide layer 2 via the cap layer 5, (C) a process for executing activated anneal to the silicon carbide layer 5 covered with the cap layer 5 and (D) a process for removing the cap layer 5 from the substrate 1. In the process (B), the impurity ion 3 is implanted so that the concentration of impurities in a surface region of the silicon carbide layer 2 is at least 80% of a maximum concentration of impurities in the inside of the silicon carbide layer 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using silicon carbide and a method for manufacturing the same.

  Silicon carbide (silicon carbide: SiC) is a semiconductor that is expected to be applied to the next generation of low-loss power devices because it has a larger band gap and higher dielectric breakdown field strength than silicon (Si). Material. Silicon carbide has many polytypes such as cubic 3C—SiC and hexagonal 6H—SiC and 4H—SiC. Among these, polytypes commonly used for producing practical silicon carbide semiconductor elements are 6H—SiC and 4H—SiC.

Silicon carbide semiconductor elements such as MOSFETs, MESFETs, and Schottky diodes usually have a 6H-SiC substrate or 4H-SiC substrate whose principal surface is a plane substantially coincident with the (0001) plane perpendicular to the c-axis crystal axis. It is made using. On the 6H—SiC or 4H—SiC substrate (SiC substrate), an epitaxial growth layer serving as an active region of the silicon carbide semiconductor element is formed. An impurity doped layer with a controlled conductivity type and carrier concentration is formed in a selected region of the epitaxial growth layer. The impurity doped layer functions as a p-type well region or an n ⁺ source region in a MOSFET, for example.

  In order to form an impurity doped layer in the epitaxially grown silicon carbide layer, it is indispensable to implant impurity ions into the silicon carbide layer. Furthermore, it is necessary to activate the impurity ions by performing an annealing process after the ion implantation.

  Hereinafter, a conventional method for forming an impurity doped layer will be described with reference to FIGS. 8A to 8D, taking a method for forming a p-type well region in a MOSFET as an example.

  First, as shown in FIG. 8A, a silicon carbide layer 41 functioning as an n-type drift layer is formed on SiC substrate 40. As the SiC substrate 40, an off-angle substrate having a surface (step structure surface) in which the step density is increased by inclining several degrees (off-angle) from the (0001) plane is often used. In this case, the silicon carbide layer 41 is epitaxially grown on the surface of the step structure of the SiC substrate 40 using a step flow by lateral growth of steps. The off-angle of a standard off-angle substrate is 8 ° in the [11-20] direction with the (0001) plane as the reference plane for the 4H-SiC substrate, and the (0001) plane as the reference plane for the 6H-SiC substrate [ 11-20] direction is 3.5 °.

  Subsequently, as shown in FIG. 8B, an ion implantation mask 42 is formed on the surface of the silicon carbide layer 41. Implant mask 42 is provided on a region of silicon carbide layer 41 other than the region where p-type well region 43 is formed.

Next, as shown in FIG. 8C, impurity ions (Al ions) 44 are implanted into the silicon carbide layer 41 from above the implantation mask 42. For the purpose of protecting the surface of silicon carbide layer 41 during ion implantation, a SiO ₂ film may be provided on the surface of silicon carbide layer 41 (for example, Non-Patent Document 1).

  Thereafter, as shown in FIG. 8D, after removing the implantation mask 42, an activation annealing process is performed to recover damage caused by ion implantation and activate impurity ions. The activation annealing treatment is performed by heating the silicon carbide substrate 40 to a temperature of 1700 ° C. or higher in a rare gas (eg, argon gas) atmosphere. By activation annealing, p-type well region 43 is formed as an impurity doped layer in part of silicon carbide layer 41. A region of silicon carbide layer 41 where p-type well region 43 is not formed becomes n-type drift region 47.

  The conventional method described above has two major problems.

  The first problem is that the dopant concentration of the impurity doped layer (p-type well region) 43 is low near the substrate surface. The concentration profile of impurity ions implanted into the silicon carbide layer 41 has a Gaussian distribution, but this profile is maintained even after activation annealing. This is because the impurity diffusion coefficient of the silicon carbide layer 41 is extremely small, so that even if activation annealing is performed in a high temperature region of 1700 ° C. or higher after ion implantation, the ion-implanted dopant hardly diffuses. Therefore, the dopant concentration in the obtained impurity doped layer has a peak inside the substrate and decreases toward the surface of the substrate. The dopant concentration near the substrate surface is significantly lower than the dopant concentration inside the substrate.

  Such a dopant concentration profile causes a decrease in reliability and performance of the silicon carbide element. Hereinafter, this reason will be described by taking MOSFET as an example.

FIG. 9 is a cross-sectional view showing a general configuration of a MOSFET. In this MOSFET, silicon carbide layer 41 formed on SiC substrate 40 has drift region 47, p-type well region 43, and contact region (n ⁺ region) 48. Contact region 48 is connected to source electrode 49. A gate electrode 51 is provided on the p-type well region 43 through a gate oxide film 50. A drain electrode 52 is formed on the back surface of the SiC substrate 40. In the MOSFET having such a configuration, when a voltage is applied to the gate electrode 51, a channel layer is formed on the surface layer of the p-type well region 43 below the gate electrode 51. Therefore, the drain electrode 52 passes through the channel layer. A current flows to the source electrode 49.

  When the p-type well region 23 is formed by the method described with reference to FIG. 8, the dopant concentration in the p-type well region 43 of the obtained MOSFET is not constant with respect to the depth of the p-type well region 43. The peak is in the vicinity of the center in the depth direction of the p-type well region 43 and is low in the vicinity of the surface of the silicon carbide layer 41. In such a MOSFET, when a voltage is applied to the gate electrode 51, a channel layer having a certain thickness is not formed at the interface between the p well region 43 and the oxide film 50. For this reason, variations occur in the electrical characteristics of the MOSFET, particularly the threshold voltage, and there is a possibility that stable element characteristics cannot be obtained.

  When the contact region 48 is formed by the same method as that for the p-type well region 23, the dopant concentration near the surface of the contact region 48 is lower than the dopant concentration inside the contact region 48. Therefore, good ohmic characteristics cannot be obtained at the junction between the contact region 48 and the source electrode 49, and resistance loss due to contact resistance at the junction increases. This increases the power loss of the MOSFET.

  In addition to the MOSFET shown in FIG. 9, in other silicon carbide elements such as MESFETs and Schottky diodes as well, when the impurity doped layer is formed by the conventional method shown in FIG. 8, the impurity doped layer is formed. Since the dopant concentration is low on the surface of the silicon carbide layer, it is difficult to ensure sufficient device performance and reliability.

  On the other hand, the second problem in the conventional method for forming an impurity doped layer is that the surface of the silicon carbide layer is roughened by activation annealing after ion implantation.

  Reference is again made to FIG. As shown in the figure, a macro step 45 is formed on the surface of the p-type well region 43 formed by ion implantation after the activation annealing. Although smaller than macro step 45, macro step 46 is also formed on the surface of silicon carbide layer 41 in the region where ions are not implanted. This is presumably because the step at the atomic layer level on the surface is combined into several bundles by activation annealing. Further, the reason why the macro step 45 on the region formed by ion implantation is larger than the macro step 46 on the region not ion-implanted is that, in the region formed by ion implantation, silicon and carbon atoms are caused by damage due to ion implantation. This is thought to be because it is easily detached from the surface.

  As shown in FIG. 10, the cross-sectional shapes of these macrosteps 45 and 46 are substantially triangular shapes including a vertex 45a and bottom points 45b and 45c. The size of the macro steps 45 and 46 can be represented by the height of the step side wall 45s and the width of the terrace 45w in the cross-sectional shape. Here, the height of the step side wall 45s (hereinafter, simply referred to as “step height”) is a bottom point 45b having a smaller base angle in a cross-sectional view perpendicular to the substrate 40 and perpendicular to the ridge line direction of the macrostep. And the distance H between the vertex 45a. The width of the terrace 45w (hereinafter simply referred to as “terrace width”) refers to the distance W between the base 45c having the larger base angle and the apex 45a in the cross-sectional view. The size of the macro steps 45 and 46 increases as the activation annealing temperature increases, and the step height H may reach several tens of nm and the terrace width W may reach several hundred nm.

  Such macro steps 45 and 46 are factors that degrade device characteristics in various silicon carbide devices, as will be described below.

  In the process of manufacturing the MOSFET as shown in FIG. 9, the impurity doped layers 43 and 48 are usually formed by activation annealing, and then the oxide film 50 is formed on the surface of the silicon carbide layer 41 by thermal oxidation. At this time, if the macro steps 45 and 46 are present on the surface of the silicon carbide layer 41, the thickness of the portion formed on the step side wall 45s and the thickness of the portion formed on the terrace 45w in the oxide film 50 are determined. Different. Therefore, when a gate voltage is applied to the fabricated MOSFET, there is a problem that the thickness of the channel layer (inversion layer) formed on the surface layer of the silicon carbide layer 41 becomes non-uniform and the channel mobility decreases.

  In the Schottky diode, a Schottky electrode is connected to the surface of the silicon carbide layer subjected to activation annealing. Therefore, if a macro step exists on the surface of the silicon carbide layer, there is a problem that an electric field concentrates on the tip portion of the macro step at the interface between the surface of the silicon carbide layer and the Schottky electrode, and the withstand voltage decreases. Further, in the MESFET having a configuration in which a current flows near the surface of the silicon carbide layer, carriers are disturbed by macro steps on the surface of the silicon carbide layer. As a result, there is a problem that the mobility is reduced and the mutual conductance is lowered.

  As described above, when the macro steps 45 and 46 are formed on the surface of the silicon carbide layer 41, even if a semiconductor element is manufactured using the silicon carbide layer 41, it is expected from the excellent physical properties of silicon carbide. It is difficult to obtain such electrical characteristics.

  Methods for solving the first and second problems have been studied.

  In order to solve the first problem, for example, a method of removing a region having a low dopant concentration on the surface of the impurity doped layer by reactive ion etching (RIE) or the like is performed.

  However, according to this method, there is a problem that the number of etching processes by RIE or the like increases. In addition, there is a problem in that the impurity doped layer is damaged by ions in the plasma during the etching process, and crystal defects are generated. Here again, taking MOSFET as an example, when a crystal defect is generated in the p-type well region by RIE, a trap level is formed at the interface between the channel layer and the oxide film formed in the p-type well region. . For this reason, the mobility of electrons in the channel layer decreases, and the current density of the channel layer decreases.

  On the other hand, for example, Patent Document 1 proposes a method for solving the second problem. In the method of Patent Document 1, a diamond-like carbon (DLC) film or a photoresist is used as a protective film after ion implantation and before activation annealing in order to prevent macrosteps from being formed on the surface by activation annealing. It is formed on the surface of the silicon carbide layer.

  However, according to the method of Patent Document 1, the number of steps for forming a protective film such as a diamond-like carbon film or a photoresist on the surface before activation annealing is increased. Depending on the structure of the semiconductor element, it is necessary to perform activation annealing a plurality of times. In this method, it is necessary to form a protective film every time activation annealing is performed.

  Moreover, since the method of Patent Document 1 cannot solve the above-described problem of the dopant concentration on the surface of the doped layer (first problem), it is difficult to realize stable element characteristics.

Therefore, even if the formation of macrosteps can be suppressed by performing activation annealing using a protective film, it is difficult to easily produce a silicon carbide semiconductor element having excellent characteristics.
JP 2001-68428 A Advanced Power Devices Lab., Material Science Division, Hard Electronics Lab., ETL NEWS 2001.2, p.2-p.7 (2001).

  Thus, according to the conventional method for manufacturing a silicon carbide element, the two problems of low dopant concentration on the surface of the silicon carbide layer (impurity doped layer) and unevenness on the surface of the silicon carbide layer due to activation annealing are simultaneously solved. Thus, it is difficult to realize a highly reliable silicon carbide element having excellent performance.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to reduce the surface roughness of the silicon carbide layer by activation annealing without complicating the manufacturing process in the method for manufacturing a silicon carbide element. It is to reduce and increase the dopant concentration in the surface region of the silicon carbide layer.

  A method for manufacturing a silicon carbide element according to the present invention includes (A) preparing a substrate having a silicon carbide layer whose surface is covered with a cap layer, and (B) at least one of the silicon carbide layers via the cap layer. A step of implanting impurity ions into the portion to form an impurity doped layer, (C) a step of performing activation annealing on the silicon carbide layer covered with the cap layer, and (D) the cap from the substrate And in the step (B), the concentration of the impurity in the surface region of the silicon carbide layer is 80% or more of the maximum value of the concentration of the impurity in the silicon carbide layer. The impurity ions are implanted so that

  The cap layer preferably has a thickness of 10 nm to 1 μm.

  In a preferred embodiment, the step (A) includes a step (A1) of forming the cap layer by graphitizing the surface of the silicon carbide layer.

The step (A1) is preferably performed at a pressure of 10 ⁻⁵ Pa to 10 Pa.

  The step (A1) preferably includes a step of heating the substrate to a temperature of 1100 ° C. or higher and 1400 ° C. or lower.

  The step (A) includes a step of forming the silicon carbide layer on the substrate by epitaxial growth, and the step of forming the silicon carbide layer on the substrate by epitaxial growth is the same as the step (A1). It may be performed in a chamber.

  Preferably, the step (D) includes a step of thermally oxidizing the substrate.

  In the step (B), the impurity ions may be implanted a plurality of times with different acceleration energies.

  The step (B) may include a step of forming an implantation mask that covers a selected region of the cap layer.

  The step (B) may include a step of implanting different impurity ions using different implantation masks.

  Another method of manufacturing a silicon carbide element according to the present invention includes a step of preparing a substrate having a silicon carbide layer having an impurity doped layer formed by ion implantation, and a cap layer formed by graphitization on the surface of the silicon carbide layer. Including a step of forming, a step of performing activation annealing on the silicon carbide layer, and a step of removing the cap layer from the substrate, wherein the thickness of the cap layer is a surface region of the silicon carbide layer. The concentration of the impurity in is set to be 80% or more of the maximum value of the concentration of ions in the silicon carbide layer.

  The thickness of the cap layer is preferably 10 nm or more and 1 μm or less.

  The silicon carbide element of the present invention is a silicon carbide element including a substrate and a silicon carbide layer formed on the substrate, and the silicon carbide layer has an impurity doped layer formed by ion implantation. The impurity concentration in the surface region of the silicon carbide layer is 80% or more of the maximum value of the impurity concentration in the silicon carbide layer, and the step height of the surface of the silicon carbide layer is 0 1 nm or more and 1 nm or less, and the doped layer contains knocked-on carbon atoms.

  An electrode covering at least a part of the silicon carbide layer may be further provided.

  An insulating layer may be further provided between the silicon carbide layer and the electrode.

  The silicon carbide layer and the electrode may be in contact, and at least a part of the interface between the silicon carbide layer and the electrode may form a Schottky barrier.

  A concentration of the knocked-on carbon atom in the doped layer may be 0.01% or more and 10% or less of the impurity concentration.

  According to the method for manufacturing a silicon carbide element of the present invention, the surface unevenness of the silicon carbide layer due to activation annealing can be reduced and the dopant concentration in the surface region of the silicon carbide layer can be increased without complicating the manufacturing process. it can. Therefore, a highly reliable silicon carbide element having excellent performance can be provided.

  In the method for manufacturing a silicon carbide element according to the present invention, impurity ions are implanted into the silicon carbide layer through the cap layer formed on the surface of the silicon carbide layer, and then the cap layer is used as it is as a protective film for activation. Annealing is performed. Thereby, an impurity doped layer is formed in the silicon carbide layer. The cap layer is removed after the activation annealing. As will be described in detail later, according to the present invention, the above two problems can be solved simultaneously.

  Hereinafter, a method for forming an impurity doped layer in a preferred embodiment of the present invention will be described with reference to FIG.

  First, as shown in FIG. 1A, a silicon carbide layer 2 is formed on a silicon carbide substrate (off-angle substrate) 1 by, for example, epitaxial growth.

  Next, as shown in FIG. 1B, a cap layer 5 is formed on the surface of the silicon carbide layer 2. Cap layer 5 is preferably formed by heating silicon carbide substrate 1 in a vacuum atmosphere. When silicon carbide substrate 1 is heated in a vacuum atmosphere, silicon is selectively sublimated on the surface of silicon carbide layer 2, so that the surface of silicon carbide layer 2 is graphitized and, as a result, carbon that functions as cap layer 5. A layer can be obtained. Instead of performing such graphitization, a carbon layer such as a DLC film may be formed by a known deposition method.

Next, as shown in FIG. 1C, impurity ions 3 are implanted into the silicon carbide layer 2 through the cap layer 5 to form an impurity ion implanted layer 4. A concentration profile of the implanted impurity ions 3 is schematically shown by a curve of reference symbol “P1”. In the concentration profile P1, the horizontal horizontal direction in the figure indicates the concentration of the impurity ions 3, and changes according to the depth measured from the surface of the cap layer 5. The concentration of the impurity ions 3 shows a peak value N ₁ inside the impurity ion implanted layer 4 (depth: d ₁ ), and decreases as the surface of the cap layer 5 and the substrate 1 are approached (FIG. 1 (f)).

In the present invention, the impurity concentration in the surface region of silicon carbide layer 2, that is, the impurity concentration N ₀ at the interface (depth: d ₀ ) between silicon carbide layer 2 and cap layer 5 is the impurity concentration in silicon carbide layer 2. The impurity ion 3 implantation conditions (acceleration voltage, dose, etc.) and the thickness of the cap layer 5 are adjusted as appropriate so that the maximum value N ₁ is 80% or more. Here, the “impurity concentration in the surface region” of the silicon carbide layer 2 refers to an average value of the impurity concentration in a region having a depth of 10 nm or less from the interface between the cap layer 5 and the silicon carbide layer 2.

  Thereafter, as shown in FIG. 1D, an activation annealing process is performed to activate the implanted impurity ions 3, and an impurity doped layer 6 is formed. At this time, since the cap layer 5 serves as a protective film, the formation of the macro steps 45 and 46 as shown in FIG. 8D on the surface of the silicon carbide layer 2 can be suppressed. The impurity concentration profile P1 'in the silicon carbide layer 2 is substantially the same as the concentration profile P1 of the impurity ions 3 by ion implantation. This is because the impurity diffusion coefficient of the silicon carbide layer 2 is small, so that the impurity hardly diffuses even after activation annealing.

Subsequently, the cap layer 5 is removed from the surface of the silicon carbide layer 2 as shown in FIG. By removing cap layer 5, a region having an impurity concentration lower than concentration N ₀ is removed from silicon carbide layer 2, so that silicon carbide layer 2 having a high impurity concentration (N ₀ ) on the surface is obtained. The method for removing the cap layer 5 is not particularly limited, but when the cap layer 5 is a carbon layer formed by the above graphitization or by another method, it is preferable to remove the carbon layer 5 by thermal oxidation. . This is because the carbon layer 5 can be removed almost completely without damaging the surface of the silicon carbide layer 2. It is also advantageous to perform the oxidation annealing shown in FIG. 1D in a heating furnace and then thermally oxidize the carbon layer 5 in the heating furnace because the manufacturing process can be simplified.

  When the above method is used, the impurity concentration in the surface region of the silicon carbide layer 2 (impurity doped layer 6) can be sufficiently increased without making the process more complicated than in the past, and silicon carbide in the activation annealing step can be achieved. Generation of macro steps on the surface of the layer 2 can be suppressed.

  The thickness of the cap layer 5 varies depending on the dopant and ion implantation conditions, but is preferably 10 nm or more and 1 μm or less. The concentration profile of the impurities ion-implanted into the substrate typically has a peak in the range of 100 nm to 1 μm in depth from the substrate surface. Therefore, if the thickness of the cap layer 5 is 10 nm or more and 1 μm or less, more preferably 20 nm or more and 0.5 μm or less, the region having a low impurity concentration on the substrate surface can be more reliably removed and the surface region of the silicon carbide layer 2 can be removed. The impurity concentration in can be sufficiently increased.

  The cap layer 5 is required to have sufficient heat resistance so as not to be deformed at the activation annealing temperature. This is because if the cap layer 5 is deformed or evaporated during the activation annealing step, the unevenness of the surface of the silicon carbide layer 2 cannot be reduced effectively.

In Non-Patent Document 1 described above, a silicon oxide (SiO ₂ ) film is formed on the surface of the silicon carbide layer for the purpose of protecting the surface of the silicon carbide layer during ion implantation. However, since the silicon oxide film has low heat resistance and evaporates at the annealing temperature, the surface unevenness of the silicon carbide layer 2 cannot be sufficiently reduced. In addition, only a silicon oxide film having a thickness of about 10 nm can be formed on the surface of the silicon carbide layer even if time is taken. Therefore, the silicon oxide film is not suitable for the purpose of sufficiently increasing the impurity concentration on the surface of the silicon carbide layer. Thus, even if the silicon oxide film of Non-Patent Document 1 is used, none of the above-described problems can be solved.

  The cap layer 5 is preferably formed using graphitization by heat treatment. It has been known that when a silicon carbide film is processed at a high temperature, the surface of the silicon carbide film is graphitized. However, conventionally, such graphitization has been considered to be a cause of deteriorating element characteristics. Therefore, for example, an activation annealing method for preventing silicon from evaporating from the surface of the silicon carbide film has been studied. On the other hand, the formation of the cap layer (carbon layer) 5 by the heat treatment actively uses this graphitization in the manufacturing process of the silicon carbide element.

  When the cap layer 5 is formed using graphitization, there are the following advantages.

  By controlling the heat treatment conditions, the interface between the silicon carbide layer 2 and the cap layer (carbon layer) 5 can be made extremely flat. The surface of the obtained cap layer (carbon layer) 5 is substantially flat. In addition, the structure of such a carbon layer is described in a literature (M. Kusunoki, T. Suzuki, T. Hirayama, N. Shibata, APPLIED PHYSICS LETTERS, 77) which proposes a method for forming a carbon nanotube film by graphitization of silicon carbide. , p.531-p533 (2000)).

  In addition, since the cap layer 5 can be formed and removed using a heating furnace used for epitaxial growth of silicon carbide or activation annealing, a new apparatus for forming or removing the cap layer 5 is introduced. There is no need to do. Furthermore, when the silicon carbide layer 2 is epitaxially grown in a heating furnace and subsequently the cap layer 5 is formed in the same heating furnace, the manufacturing process can be greatly simplified. Similarly, the activation annealing and the removal of the cap layer 5 can be continuously performed in the same heating furnace.

  If the cap layer 5 is formed without using graphitization, the cap layer 5 may contain impurities even if the cap layer 5 is a carbon layer. This impurity causes various problems. For example, when activation annealing is performed at a high temperature of 1600 ° C. or higher after the cap layer 5 is formed, impurities contained in the cap layer 5 enter the silicon carbide layer 2 by diffusion, and the characteristics of the silicon carbide semiconductor element are significantly deteriorated. There is a risk of causing. Further, impurities in the cap layer 5 may sublimate and contaminate the annealing furnace. On the other hand, when the cap layer 5 is formed by graphitization, the cap layer 5 is formed only from the material (carbon) contained in the silicon carbide layer 2 and contains almost no impurities. Therefore, the above problem caused by impurities contained in the cap layer 5 can be prevented.

When the cap layer 5 is formed by graphitization, it is preferable to set the pressure of a heating furnace (chamber) in which the substrate 1 is installed to 10 ⁻⁵ Pa or more and 10 Pa or less. When the pressure is higher than 10 Pa, a step is formed on the surface of the silicon carbide substrate 1 by this heat treatment. When the pressure is lower than 10 ⁻⁵ Pa, not only silicon but also carbon is sublimated by this heat treatment. Because there is a fear. Moreover, it is preferable that the temperature of the board | substrate 1 in heat processing is 1100 degreeC or more and 1400 degrees C or less. This is because when the substrate temperature is lower than 1100 ° C., silicon does not sublime from the substrate surface, and when it is higher than 1400 ° C., carbon may be sublimated.

  The cap layer 5 is desirably a carbon layer regardless of the formation method. When the carbon layer is used as the cap layer 5 and the ion implantation shown in FIG. 1C is performed, the carbon atoms 5a are implanted (knocked on) into the silicon carbide layer 2 together with the impurity ions 3 as shown in FIG. Therefore, silicon carbide layer 2 obtained through the subsequent steps contains carbon atoms knocked on (at a low concentration). The concentration of knocked-on carbon atom 5a in silicon carbide layer 2 is, for example, 0.01% to 10% of the impurity concentration.

  When activation annealing is performed after implanting only impurity ions (for example, boron) 3 into the silicon carbide layer 2, the impurity ions 3 diffuse into a region having many defects in the silicon carbide layer 2 during the activation annealing, and the impurity concentration distribution cannot be controlled. May cause fluctuations. On the other hand, when ion implantation is performed through the carbon layer that is the cap layer 5, the carbon atoms 5 a implanted into the silicon carbide layer 2 together with the impurity ions 3 prevent fluctuations in the concentration of the impurity ions 3 that are difficult to control. Has an effect. The mechanism by which the carbon atom 5a prevents the impurity ions 3 from diffusing is described in Michael Laube, Gerhard Pensl, Hisayashi Itoh, APPLIED PHYSICS LETTERS, 74, p.2292-p.2294 (1999).

  In the method described with reference to FIG. 1, the cap layer 5 is formed before the ion implantation step, and the cap layer 5 is used as it is as a protective film in the activation annealing step, but instead after the ion implantation step. The cap layer 5 can also be formed.

  Hereinafter, an example of a method for forming the impurity doped layer when the cap layer 5 is formed after the ion implantation step will be described with reference to FIG.

  First, as shown in FIG. 3A, impurity ions 3 are implanted into the silicon carbide layer 2 formed on the substrate 1. Thereby, impurity ion implanted layer 4 is formed in silicon carbide layer 2 as shown in FIG. A concentration profile of the implanted impurity ions 3 is schematically shown by a curve of reference symbol “P2”. The density profile P2 shows the same tendency as the density profile P1 in FIG.

  Next, as shown in FIG. 3C, the surface of the impurity ion implanted layer 4 is graphitized to form a cap layer (carbon layer) 5. As a result, a region having a relatively low impurity concentration in the vicinity of the surface of the impurity ion implanted layer 4 becomes a carbon layer (thickness: 10 nm to 1 μm, for example). The method of forming the carbon layer 5 by graphitization is the same as the method described with reference to FIG.

  Thereafter, as shown in FIG. 3D, activation annealing is performed to form an impurity doped layer 6. At this time, since the carbon layer 5 functions as a protective film, the occurrence of macro steps on the surface of the silicon carbide layer 2 can be suppressed.

  Subsequently, as shown in FIG. 3E, the carbon layer 5 is removed by, for example, thermal oxidation. Thereby, as shown in concentration profile P2 ', the impurity concentration in the surface region of silicon carbide layer 2 can be increased to a value close to the peak concentration. Thus, impurity doped layer 6 having a high impurity concentration on the surface can be formed while keeping the surface of silicon carbide layer 2 flat.

  Also in the method shown in FIG. 3, the thickness of cap layer 5 and the ion implantation conditions are such that the impurity concentration in the surface region of silicon carbide layer 2 is 80% or more of the maximum value of the impurity concentration in silicon carbide layer 2. Is set as follows.

  The silicon carbide element of the present invention is manufactured using the method described with reference to FIG. 1 or FIG. 3, for example. The impurity concentration of the surface region of silicon carbide layer 2 in the obtained silicon carbide element is 80% or more, more preferably 90% or more of the maximum value of the impurity concentration inside silicon carbide layer 2, and is extremely higher than before. . Further, the step height H of the surface of silicon carbide layer 2 is suppressed to 0.1 nm to 1 nm, more preferably 0.1 nm to 0.5 nm. Therefore, it is possible to realize a silicon carbide semiconductor element that can flow a current having a high withstand voltage, a high current density, and little variation in electrical characteristics.

  An oxide film and an electrode may be formed in this order on silicon carbide layer 2. As a result, a good oxide film-semiconductor interface having a high gate breakdown voltage can be formed, and thus a good current-voltage characteristic can be realized.

  Furthermore, you may have the electrode which contacts the surface of the silicon carbide layer 2 (or impurity doped layer 6). In this case, it is preferable to form a Schottky barrier at at least a part of the interface where silicon carbide layer 2 and the electrode are in contact. Thereby, a good Schottky barrier can be realized on the surface of the silicon carbide element, so that a good current-voltage characteristic can be obtained.

(Embodiment 1)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present embodiment, a method of forming an impurity doped layer by implanting impurity ions into a silicon carbide layer having a cap layer formed on the surface and then performing activation annealing will be described.

  First, the structure of the heating furnace used in this embodiment will be described with reference to FIG.

  The heating furnace shown in FIG. 4 includes a reaction furnace 150 and a coil 154 for heating the reaction furnace 150. The coil 154 is provided around the reaction furnace 150 and heats the reaction furnace 150 by high frequency induction heating. A chamber 163 supported by a support shaft 153 is provided inside the reaction furnace 150. The chamber 163 is covered with a heat insulating material 62 around. A susceptor 152 made of carbon is disposed inside the chamber 163. A sample 151 such as a silicon carbide substrate is fixed to the chamber 163 by the susceptor 152. The chamber 163 is connected to a gas exhaust system 159 and a gas supply system 158, respectively. The gas exhaust system 159 includes an exhaust gas pipe 60 and a pressure adjustment valve 61, and exhausts the gas in the chamber 163 as necessary. The gas supply system 158 supplies an argon gas 155, a source gas 156 used for epitaxial growth of silicon carbide, an oxygen gas 157, and the like to the chamber 163 as necessary.

  In the present embodiment, epitaxial growth of the silicon carbide layer, formation of the cap layer, activation annealing, and removal of the cap layer are all performed using the heating furnace shown in FIG. Therefore, the manufacturing process and cost can be greatly reduced.

  Next, a process for forming an impurity doped layer will be described with reference to FIGS.

  First, as shown in FIG. 5A, the cap layer 5 is formed on the surface of the silicon carbide layer 2 grown on the substrate 1. As the substrate 1, for example, a silicon carbide substrate (4H—SiC substrate) having a diameter of 50 mm and having an off angle of 8 degrees in the [11-20] (112 bar 0) direction is used.

  Silicon carbide layer 2 is formed, for example, as follows. First, the substrate 1 is placed in the chamber 163 of the heating furnace shown in FIG. Thereafter, a high frequency power of 20.0 kHz and 20 kW is applied to the induction heating coil 154 to heat the substrate 1 to, for example, 1600 ° C. by induction heating. A silicon carbide source gas 156 is supplied from a gas supply system 158 to a chamber 163 together with a carrier gas, and a silicon carbide layer (thickness: 10 μm, for example) 2 is epitaxially grown on the substrate 1 by a CVD method. As the source gas 156, for example, monosilane (SiH4) and propane (C3H8) are used. The carrier gas is, for example, hydrogen.

In the present embodiment, the cap layer 5 is formed by heating the silicon carbide layer 2 in a vacuum. After the silicon carbide layer 2 is epitaxially grown, the chamber 163 is evacuated by the gas exhaust system 59 while the substrate 1 is placed in the chamber 163, and the degree of vacuum of the chamber 163 is about 10 ⁻⁴ Pa. Next, in a state where the chamber 163 is kept in vacuum, high-frequency power is applied to the coil 154 to set the temperature of the substrate 1 to 1400 ° C., and the substrate 1 is annealed for 60 minutes. Thereby, cap layer (carbon layer) 5 is formed on the surface of silicon carbide layer 2.

  In addition, by performing composition analysis of the surface by secondary ion mass spectrometry (SIMS) on the substrate 1 after the silicon carbide layer 2 is heated in vacuum, the carbon layer 5 having a thickness of about 200 nm becomes the silicon carbide layer 2. It was confirmed that it was formed in the surface region of

After forming the carbon layer 5, as shown in FIG. 5 (b), impurity ions 3 are implanted into the silicon carbide layer 2 by using an ion implantation apparatus, whereby an impurity ion implanted layer (thickness: 4 μm, for example) 4 Form. In the present embodiment, aluminum ions are selected as the impurity ions 3 in order to form a p-type impurity doped layer. Here, aluminum ions are implanted in multiple stages at seven acceleration voltages. The ion dose of the acceleration voltage of 1.0 MeV, 1.6 MeV, 2.4 MeV is 3 × 10 ¹⁴ cm ⁻³ , the dose of the acceleration voltage of 3.3 MeV, 4.4 MeV is 7 × 10 ¹⁴ cm ⁻³ , 5 The dose of the acceleration voltage of 0.6 MeV and 7.0 MeV is set to 3 × 10 ¹⁴ cm ⁻³ . The substrate temperature during ion implantation is room temperature.

  Next, as shown in FIG. 5C, the impurity doped layer 6 is formed by performing activation annealing on the impurity ion implanted layer 4. The activation annealing can be performed as follows, for example. The substrate 1 into which the impurity ions 3 are implanted is placed again in the chamber 163 of the heating furnace, and an annealing atmosphere gas (annealing gas) is supplied from the gas supply system 58. For example, argon gas 55 is used as the annealing gas. The flow rate of the argon gas 55 is 0.5 liter / min. The pressure in the chamber 163 at the time of activation annealing is adjusted to be constant at 91 kPa using the pressure adjusting valve 161. Further, by applying high frequency power to the coil 154, the substrate 1 is heated so that the temperature of the substrate 1 becomes 1750 ° C. The heating time is 30 minutes. When the activation annealing is completed, the application of the high frequency power to the coil 54 is stopped while the argon gas 55 is supplied, and the substrate 1 is cooled to about 800 ° C.

  Subsequently, as shown in FIG. 5D, the carbon layer 5 is removed from the substrate 1 by thermally oxidizing the carbon layer 5 while the substrate 1 is placed in the chamber 163. Thermal oxidation is performed by heating the carbon layer 5 while supplying oxygen (flow rate: 5 liter / min) to the chamber 163. The heating temperature is constant at 800 ° C., and the heating time is 30 minutes. In this way, a silicon carbide substrate (hereinafter referred to as “implanted epi substrate”) 10 having an impurity doped layer 6 formed on the surface is obtained.

  Next, since the surface morphology of the implantation epitaxial substrate 10 manufactured by the above method and the doping profile of the impurity doped layer 6 were examined, the method and result will be described.

  Analysis of the surface morphology of the implanted epitaxial substrate 10 was performed using an atomic force microscope (AFM), and analysis of the doping profile of the impurity doped layer 6 was performed using a secondary ion mass spectrometer (SIMS).

  For comparison, an implanted epitaxial substrate of Comparative Example 1 was fabricated by implanting impurity ions into the silicon carbide layer without forming a cap layer and performing activation annealing. Impurity ion implantation in Comparative Example 1 was performed by the same method and conditions as in Embodiment 1 except that the cap layer was not used. The activation annealing in Comparative Example 1 was performed for 30 minutes in an argon gas atmosphere at a substrate temperature of 1750 ° C. and an argon gas flow rate of 0.5 liters / minute. The chamber pressure during annealing is kept constant at 91 kPa. The surface morphology and doping profile of the implanted epitaxial substrate of Comparative Example 1 were also measured in the same manner as the implanted epitaxial substrate 10.

  According to the measurement result of the surface morphology, the surface roughness (step height H) of the implanted epitaxial substrate 10 obtained in the present embodiment is about 0.5 nm, which is larger than the surface roughness of the implanted epitaxial substrate of Comparative Example 1. It was confirmed that it was reduced by 2 digits or more.

  Further, when the profile of aluminum in the implanted epitaxial substrate 10 was measured, it was found that the dopant concentration in the surface region of the silicon carbide layer 2 was about 90% of the maximum value. On the other hand, in the implantation epitaxial substrate of Comparative Example 1, the dopant concentration in the surface region of the silicon carbide layer was 10% or less of the maximum value. Further, when the activation rate of aluminum ions in the implanted epitaxial substrate 10 was examined, it was confirmed that a very high activation of about 90% was realized.

  As described above, according to the present embodiment, by forming the cap layer 5 before ion implantation, it is possible to prevent the surface from being roughened during the activation annealing, and at the same time, the region having a low dopant concentration present in the cap layer 5 is the cap layer. Therefore, the dopant concentration in the surface region of the silicon carbide layer 2 can be increased to almost the same as the dopant concentration in the impurity doped layer 6.

  In the present embodiment, the cap layer 5 is formed by heating the silicon carbide layer 2 in a vacuum. Alternatively, the cap layer 5 can be formed by sputtering, vapor deposition, CVD, or the like. Similarly, instead of removing the cap layer 5 by thermal oxidation, the carbon layer 5 may be removed by plasma treatment using oxygen or ozone treatment.

  In the present embodiment, the activation annealing of the impurity ion implantation layer 23 and the removal of the carbon layer 5 are continuously performed in the same heating furnace, but each process may be performed in separate furnaces.

  In this embodiment, 4H—SiC is used as the silicon carbide substrate 1, but a substrate made of a polytype other than 4H—SiC may be used.

(Embodiment 2)
Hereinafter, a method for manufacturing a silicon carbide MOSFET according to an embodiment of the present invention will be described with reference to the drawings.

First, as shown in FIG. 6A, a cap layer 25 is formed on the surface of the silicon carbide layer 22 formed on the silicon carbide substrate 21. As the silicon carbide substrate 21, for example, a 4H—SiC substrate having a diameter of 50 mm and having an off angle of 8 degrees in the direction from (0001) to [11-20] (112 bar 0) is used. The conductivity type of the substrate 21 is n-type, and the carrier concentration is 1 × 10 ¹⁸ cm ⁻³ . Formation of silicon carbide layer 22 can be performed by a CVD method using a heating furnace shown in FIG. Here, a silicon carbide layer (thickness: 10 μm) 22 doped with n-type impurities is epitaxially grown on the main surface of the substrate 1. The source gas and carrier gas used for forming the silicon carbide layer 22 are the same as those used in the first embodiment. However, in the present embodiment, a doping gas (N ₂ ) having a constant flow rate is mixed into the source gas. The carrier concentration of silicon carbide layer 2 is controlled by the flow rate of the doping gas, and here is about 5 × 10 ¹⁵ cm ⁻³ .

The cap layer 25 is formed while the substrate 21 is placed in the chamber 163 of the heating furnace after the silicon carbide layer 22 is formed. First, the chamber 163 is evacuated using the gas exhaust system 159, and the degree of vacuum of the chamber 163 is set to about 10 ⁻⁴ Pa. In this state, the substrate 1 is heated so that the substrate temperature becomes 1400 ° C. The heating time is 60 minutes. Thereby, Si is sublimated from the surface of silicon carbide layer 2 (graphitization), and carbon layer 25 having a thickness of about 200 nm is obtained.

Next, as shown in FIG. 6B, a first impurity ion implantation layer (thickness: for example, 1.5 μm to 2 μm) 23 is formed in a selected region of the silicon carbide layer 22. Specifically, first, a first implantation mask 33 made of, for example, a silicon oxide film (SiO ₂ ) is formed on the surface of the silicon carbide layer 22. The first implantation mask 33 has an opening that defines a region to be the first impurity ion implantation layer 23 in the silicon carbide layer 22. The shape of the first implantation mask 33 can be arbitrarily formed by photolithography and etching. The thickness of the first implantation mask 33 is determined by its material and implantation conditions, but is preferably set sufficiently larger than the implantation range. Next, p-type impurity ions (Al ions) are implanted into silicon carbide layer 22 through cap layer 25 from above first implantation mask 33. Impurity ion implantation is performed in multiple stages as in the method described in the first embodiment. After the ion implantation, the first implantation mask 33 is removed. Thereby, first impurity ion implanted layer 23 is formed in a region of silicon carbide layer 22 where impurity ions are implanted. In addition, the region of silicon carbide layer 22 that remains without being implanted with impurity ions becomes n-type drift region 32.

  Subsequently, as shown in FIG. 6C, a second impurity ion implantation layer (thickness: for example, 0.5 μm to 1 μm) 24 is formed in the silicon carbide layer 22. Specifically, first, second implantation mask 34 having an opening exposing a part of the surface of first impurity ion implantation layer 24 is formed on silicon carbide layer 22. The second implantation mask 34 is formed in the same manner as the first implantation mask 33, but its planar pattern is different from the planar pattern of the first implantation mask 33. Next, n-type impurity ions (nitrogen ions) are implanted into silicon carbide layer 22 through cap layer 25 from above second implantation mask 34. After the ion implantation, the second implantation mask 34 is removed.

Thereafter, as shown in FIG. 7A, activation annealing is performed on the first and second impurity ion implantation layers 23 and 24 to form a p-type well region 26 and a contact region 27, respectively. The activation annealing is performed using the heating furnace shown in FIG. 4 under the same method and conditions as the activation annealing described in the first embodiment. The resulting p-type well region 26 has a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ , and the n-type contact region 27 has a carrier concentration of 1 × 10 ¹⁸ cm ⁻³ .

  Subsequently, as shown in FIG. 7B, the carbon layer 25 is removed from the substrate 21 while the substrate 21 is installed in the chamber 163 of the heating furnace. The removal of the carbon layer 25 is performed by the same method and conditions as the method described in the first embodiment. Thereby, the implantation epitaxial substrate 90 is obtained.

  Finally, as shown in FIG. 7C, the gate insulating film 28, the source electrode 29, the drain electrode 30, and the gate electrode 31 are formed on the implantation epitaxial substrate 90. Gate insulating film 28 is formed on the surface of silicon carbide layer 22 by thermally oxidizing substrate 21 after cap layer 25 is removed at a temperature of 1100 ° C. The thickness of the gate insulating film 28 is, for example, 30 nm. Thereafter, the source electrode 29 and the drain electrode 30 are formed as follows. First, a Ni film is deposited so as to be in contact with the contact region 27 using an electron beam (EB) vapor deposition apparatus. A Ni film is also deposited on the back surface of the silicon carbide substrate 21. Subsequently, these Ni films are heated at a temperature of 1000 ° C. using a heating furnace. As a result, a source electrode (first ohmic electrode) 29 ohmically joined to the contact region 27 and a drain electrode (second ohmic electrode) 30 ohmically joined to the back surface of the substrate 21 are formed. The gate electrode 31 is formed by evaporating aluminum on the gate insulating film 28. In this way, silicon carbide element (MOSFET) 100 is obtained.

  The surface roughness of silicon carbide layer 22 and the dopant concentration of the surface region in silicon carbide element 100 can be examined by measuring the surface morphology and impurity concentration profile of implanted epitaxial substrate 90 shown in FIG. These measurements may be performed by a method similar to the method described in the first embodiment.

As a result of measuring the surface morphology of the silicon carbide layer 22 on the implanted epitaxial substrate 90, the step height on the surface of the silicon carbide layer 22 is 1 nm or less despite the fact that two ion implantation steps were performed using different impurity ions. It was confirmed that. As a result of measuring the impurity concentration profile of the p-type well region 26, it was found that the impurity (Al) concentration in the surface region of the silicon carbide layer 22 was 80% or more of the Al peak concentration. Similarly, when the impurity concentration profile of the contact region 27 was measured, it was found that the impurity (N ₂ ) concentration in the surface region of the silicon carbide layer 22 was 80% or more of the N ₂ peak concentration.

  For comparison, a MOSFET (silicon carbide element of Comparative Example 2) having the same structure as that of the silicon carbide element 100 was fabricated by a conventional method that does not use a cap layer. Impurity ion implantation in Comparative Example 2 was performed by the same method and conditions as in Embodiment 2 except that the cap layer was not used. The activation annealing in Comparative Example 2 was performed in an argon gas atmosphere for 30 minutes at a substrate temperature of 1750 ° C. and an argon gas flow rate of 0.5 liter / min. The pressure in the chamber during activation annealing was constant at 91 kPa.

When the surface roughness and impurity concentration profile of the silicon carbide element of Comparative Example 2 were examined by the same method as that of silicon carbide element 100, the step height H of the silicon carbide layer was about 10 nm, and the surface area of the silicon carbide layer was The concentrations of Al and N ₂ were 10% or less of the peak concentration of the p-type well region and the peak concentration of the contact region, respectively.

  Hereinafter, current-voltage characteristics of the silicon carbide element 100 obtained in the present embodiment and the silicon carbide element of Comparative Example 2 will be described.

  When the drain current values of silicon carbide element 100 and the silicon carbide element of Comparative Example 2 were measured, the drain current of silicon carbide element 100 was 5 times or more larger than the drain current of the silicon carbide element of Comparative Example 2. all right. This is considered to be due to the following reasons.

  In the silicon carbide element of Comparative Example 2, since the surface roughness of the silicon carbide layer is large, the carrier mobility in the vicinity of the surface is low and the drain current hardly flows. On the other hand, in silicon carbide element 100, since silicon carbide layer 22 has a surface roughness as small as 1 nm or less, a region in which channel layer is formed in silicon carbide layer 22 (p-type well region 23 under gate electrode 31). The lowering of the carrier mobility of the surface layer) can be suppressed. Therefore, a drain current having a higher current density can be passed through the channel layer. Further, in the silicon carbide element of Comparative Example 2, the contact concentration is high because the dopant concentration in the vicinity of the surface of the contact region is low, but in the silicon carbide element 100, the dopant concentration in the surface of the contact region 27 is high. The contact resistance with the source electrode 29 can be reduced. Thus, in silicon carbide element 100, since the carrier mobility of the channel layer is high and the contact resistance is low, a larger drain current can flow.

  Subsequently, when the threshold voltage of silicon carbide element 100 and silicon carbide element of comparative example 2 was measured, the threshold value of silicon carbide element of comparative example 2 varied in the range of 2 to 10 V. It was confirmed that the threshold value of the element 100 was stable at 3 to 3.5V. This is considered to be due to the following reasons.

  In the silicon carbide element of Comparative Example 2, since the dopant concentration in the vicinity of the surface of the p-type well region decreases toward the surface of the substrate, a constant thickness is applied to the interface between the p-type well region and the oxide film. The channel layer is not formed, and the threshold voltage varies. On the other hand, in silicon carbide element 100, since the dopant concentration in the vicinity of the surface of p-type well region 26 is substantially equal to the dopant concentration in p-type well region 26, a channel layer having a uniform thickness is formed and stable. The threshold value obtained is obtained.

  As apparent from the above measurement results, when the carbon layer 25 is formed on the surface of the silicon carbide layer 22 by annealing in a reduced pressure atmosphere after the silicon carbide layer 22 is formed and before ion implantation and activation annealing are performed. By the subsequent activation annealing treatment, a high activation rate can be achieved while maintaining a flat surface (step height: 1 nm or less). Furthermore, by removing the carbon layer 25, the dopant concentration in the surface region of the silicon carbide layer 22 can be significantly increased as compared with the conventional case. Thus, by improving the surface characteristics of silicon carbide layer 22, the electrical characteristics and reliability of silicon carbide MOSFET can be improved.

  Although the inversion type MOSFET has been described in the present embodiment, the same effect can be obtained even if the present invention is applied to a storage type MOSFET. Further, the present invention can be applied not only to MOSFETs but also to silicon carbide elements such as MESFETs and Schottky diodes having a Schottky barrier on the substrate surface, and the same effects as those described in this embodiment can be obtained.

  In each of the embodiments described above, the step of further etching the surface of the silicon carbide layer 5 is not performed after the cap layer 5 is removed, but the purpose of adjusting the impurity concentration in the surface region of the silicon carbide layer 5, For other reasons, the surface of silicon carbide layer 5 may be etched.

  According to the present invention, a highly reliable silicon carbide device having excellent electrical characteristics can be provided without complicating the manufacturing process.

  The present invention can be widely applied to various silicon carbide elements including MOSFET, MESFET, Schottky diode and the like. The silicon carbide element of the present invention can be used for a low-loss power device that can be used for various electric power / electric equipment such as home appliances, automobiles, electric power transportation / conversion devices, and industrial equipment.

(A)-(f) is process sectional drawing for demonstrating the formation method of the impurity dope layer by this invention. It is a cross-sectional schematic diagram for demonstrating the state of the impurity ion implantation layer in the case of performing ion implantation using a carbon layer as a cap layer. (A)-(e) is process sectional drawing for demonstrating the formation method of the impurity doped layer by this invention. It is the schematic which shows the structure of the annealing furnace used by embodiment by this invention. (A)-(d) is process sectional drawing for demonstrating the manufacturing method of the implantation epitaxial substrate of Embodiment 1 by this invention. (A)-(c) is process sectional drawing for demonstrating the manufacturing method of the silicon carbide element of Embodiment 2 by this invention. (A)-(c) is process sectional drawing for demonstrating the manufacturing method of the silicon carbide element of Embodiment 2 by this invention. (A)-(d) is process sectional drawing for demonstrating the formation method of the conventional impurity dope layer. It is a cross-sectional schematic diagram which shows the general structure of MOSFET. It is a figure for demonstrating the step height and terrace width of a macro step.

Explanation of symbols

1, 21, 40 Silicon carbide substrate 2, 22, 41 Silicon carbide layer 3, 44 Impurity ion 4 Impurity ion implantation layer 5, 25 Cap layer (carbon layer)
6 Impurity doped layer 23 First impurity ion implantation layer 24 Second impurity ion implantation layer 26, 43 p-type well region 27, 48 n-type source contact region 28, 50 Gate insulating film 29, 49 Source electrode 30, 52 Drain electrode 31, 51 Gate electrode 32, 47 N-type drift region 33, 34, 42 Ion implantation mask 45, 46 Macro step 10, 90 Implanted epitaxial substrate 100 Silicon carbide element 150 Reactor (chamber)
151 Sample 152 Susceptor 153 Susceptor support shaft 154 Coil 155 Argon gas 156 Silicon carbide source gas 157 Oxygen gas 158 Gas supply system 159 Gas exhaust system 160 Exhaust gas piping 161 Pressure adjustment valve 162 Heat insulating material

Claims (17)

(A) preparing a substrate having a silicon carbide layer whose surface is covered with a cap layer;
(B) forming an impurity doped layer by implanting impurity ions into at least part of the silicon carbide layer through the cap layer;
(C) performing activation annealing on the silicon carbide layer covered with the cap layer;
(D) removing the cap layer from the substrate,
In the step (B), the impurity ions are implanted so that the concentration of the impurity in the surface region of the silicon carbide layer is 80% or more of the maximum value of the concentration of the impurity in the silicon carbide layer. A method for manufacturing a silicon element.   The method for manufacturing a silicon carbide element according to claim 1, wherein the cap layer has a thickness of 10 nm to 1 μm.   The method for manufacturing a silicon carbide element according to claim 1, wherein the step (A) includes a step (A1) of forming the cap layer by graphitizing a surface of the silicon carbide layer. The said process (A1) is a manufacturing method of the silicon carbide semiconductor element of Claim 3 performed by the pressure of 10 < ^-5 > Pa or more and 10 Pa or less.   The said process (A1) is a manufacturing method of the silicon carbide element of Claim 3 or 4 including the process of heating the said board | substrate to the temperature of 1100 degreeC or more and 1400 degrees C or less. The step (A) includes a step of forming the silicon carbide layer on the substrate by epitaxial growth,
The method for manufacturing a silicon carbide element according to claim 3, wherein the step of forming the silicon carbide layer on the substrate by epitaxial growth and the step (A1) are performed in the same chamber.   The method for manufacturing a silicon carbide element according to claim 1, wherein the step (D) includes a step of thermally oxidizing the substrate.   The method for manufacturing a silicon carbide element according to claim 1, wherein in the step (B), the impurity ions are implanted a plurality of times with different acceleration energies.   The method for manufacturing a silicon carbide element according to claim 1, wherein the step (B) includes a step of forming an implantation mask that covers a selected region of the cap layer.   The method for manufacturing a silicon carbide element according to claim 9, wherein the step (B) includes a step of implanting different impurity ions using different implantation masks. Preparing a substrate including a silicon carbide layer having an impurity doped layer formed by ion implantation;
Forming a cap layer by graphitization on the surface of the silicon carbide layer;
Performing activation annealing on the silicon carbide layer;
Removing the cap layer from the substrate,
The thickness of the cap layer is set so that the impurity concentration in the surface region of the silicon carbide layer is set to 80% or more of the maximum value of the ion concentration in the silicon carbide layer. Method.   The method for manufacturing a silicon carbide element according to claim 11, wherein the thickness of the cap layer is not less than 10 nm and not more than 1 μm. A silicon carbide element comprising a substrate and a silicon carbide layer formed on the substrate,
The silicon carbide layer has an impurity doped layer formed by ion implantation,
The impurity concentration in the surface region of the silicon carbide layer is 80% or more of the maximum value of the impurity concentration in the silicon carbide layer, and the step height of the surface of the silicon carbide layer is 0.1 nm or more and 1 nm. And
The silicon carbide device, wherein the doped layer contains knock-on carbon atoms.   The silicon carbide element according to claim 13, further comprising an electrode covering at least a part of the silicon carbide layer.   The silicon carbide element according to claim 14, further comprising an insulating layer between the silicon carbide layer and the electrode.   The silicon carbide element according to claim 14, wherein the silicon carbide layer and the electrode are in contact with each other, and at least a part of an interface between the silicon carbide layer and the electrode forms a Schottky barrier.   17. The silicon carbide element according to claim 13, wherein a concentration of the knocked-on carbon atom in the doped layer is 0.01% or more and 10% or less of the concentration of the impurity.