WO2009034496A3 - Wafer, method of manufacturing integrated circuits on a wafer, and method of storing data about said circuits - Google Patents

Wafer, method of manufacturing integrated circuits on a wafer, and method of storing data about said circuits Download PDF

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Publication number
WO2009034496A3
WO2009034496A3 PCT/IB2008/053499 IB2008053499W WO2009034496A3 WO 2009034496 A3 WO2009034496 A3 WO 2009034496A3 IB 2008053499 W IB2008053499 W IB 2008053499W WO 2009034496 A3 WO2009034496 A3 WO 2009034496A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
circuits
integrated circuits
storing data
manufacturing integrated
Prior art date
Application number
PCT/IB2008/053499
Other languages
French (fr)
Other versions
WO2009034496A2 (en
Inventor
Heimo Scheucher
Original Assignee
Nxp Bv
Heimo Scheucher
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv, Heimo Scheucher filed Critical Nxp Bv
Publication of WO2009034496A2 publication Critical patent/WO2009034496A2/en
Publication of WO2009034496A3 publication Critical patent/WO2009034496A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67294—Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a wafer (2), comprising a plurality of integrated circuits (1) formed on the wafer (2); and at least one auxiliary integrated circuit (Ia) formed on the wafer (2); wherein data carrying information about said integrated circuits (1) are stored in said at least one auxiliary integrated circuit (Ia). Examples for said data are test results of a test performed on said individual integrated circuits (1) and/or a wafer identification or a product identification. The invention furthermore discloses a method of manufacturing said integrated circuits (1) and a method of storing said data about said circuits (1a).
PCT/IB2008/053499 2007-09-12 2008-08-29 Wafer, method of manufacturing integrated circuits on a wafer, and method of storing data about said circuits WO2009034496A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07116200.2 2007-09-12
EP07116200 2007-09-12

Publications (2)

Publication Number Publication Date
WO2009034496A2 WO2009034496A2 (en) 2009-03-19
WO2009034496A3 true WO2009034496A3 (en) 2009-05-22

Family

ID=40090471

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/053499 WO2009034496A2 (en) 2007-09-12 2008-08-29 Wafer, method of manufacturing integrated circuits on a wafer, and method of storing data about said circuits

Country Status (1)

Country Link
WO (1) WO2009034496A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1399914B1 (en) * 2010-04-29 2013-05-09 St Microelectronics Srl TEST CIRCUIT OF A CIRCUIT INTEGRATED ON THE WAFER OF THE TYPE INCLUDING AT LEAST AN EMBEDDED TYPE ANTENNA AND ITS INTEGRATED CIRCUIT OBTAINED THROUGH A SINGULATION STARTING FROM A WAFER PORTION EQUIPPED WITH SUCH A TEST CIRCUIT.
FR2973562A1 (en) * 2011-04-01 2012-10-05 St Microelectronics Rousset Wafer i.e. silicon wafer, for manufacturing integrated circuits, has set of chips separated from each other by cut lines, and contactless communication device partially placed on cut lines and completely integrated in cut lines
FR2973560A1 (en) * 2011-04-01 2012-10-05 St Microelectronics Rousset Method for manufacturing silicon wafer for manufacturing integrated circuits, involves testing chips of wafer, and classifying chips into categories, where chips classified into one category are determined to be non-failure chips
FR2973563A1 (en) * 2011-04-01 2012-10-05 St Microelectronics Rousset Method for manufacturing silicon wafer for use during manufacture of integrated circuits, involves writing data related to chips of wafer in memories of chips by performing contactless communication, where memories are distinct from wafer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0760580A (en) * 1993-08-31 1995-03-07 Disco Abrasive Syst Ltd Fa system
US5787174A (en) * 1992-06-17 1998-07-28 Micron Technology, Inc. Remote identification of integrated circuit
US20060223340A1 (en) * 2005-03-31 2006-10-05 Fujitsu Limited Manufacturing managing method of semiconductor devices and a semiconductor substrate
WO2007028150A2 (en) * 2005-09-02 2007-03-08 Hynix Semiconductor Inc. Integrated circuit with embedded feram-based rfid

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787174A (en) * 1992-06-17 1998-07-28 Micron Technology, Inc. Remote identification of integrated circuit
JPH0760580A (en) * 1993-08-31 1995-03-07 Disco Abrasive Syst Ltd Fa system
US20060223340A1 (en) * 2005-03-31 2006-10-05 Fujitsu Limited Manufacturing managing method of semiconductor devices and a semiconductor substrate
WO2007028150A2 (en) * 2005-09-02 2007-03-08 Hynix Semiconductor Inc. Integrated circuit with embedded feram-based rfid

Also Published As

Publication number Publication date
WO2009034496A2 (en) 2009-03-19

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