WO2009034496A2

WO2009034496A2 - Wafer, method of manufacturing integrated circuits on a wafer, and method of storing data about said circuits

Info

Publication number: WO2009034496A2
Application number: PCT/IB2008/053499
Authority: WO
Inventors: Heimo Scheucher
Original assignee: Nxp B.V.
Priority date: 2007-09-12
Filing date: 2008-08-29
Publication date: 2009-03-19
Also published as: WO2009034496A3

Abstract

The invention discloses a wafer (2), comprising a plurality of integrated circuits (1) formed on the wafer (2); and at least one auxiliary integrated circuit (Ia) formed on the wafer (2); wherein data carrying information about said integrated circuits (1) are stored in said at least one auxiliary integrated circuit (Ia). Examples for said data are test results of a test performed on said individual integrated circuits (1) and/or a wafer identification or a product identification. The invention furthermore discloses a method of manufacturing said integrated circuits (1) and a method of storing said data about said circuits (1a).

Description

Wafer, method of manufacturing integrated circuits on a wafer, and method of storing data about said circuits

FIELD OF THE INVENTION

The invention relates to a wafer, comprising a plurality of integrated circuits formed on the wafer; a method of manufacturing integrated circuits on a wafer, comprising the step of forming a plurality of integrated circuits on the wafer; and a method of storing data carrying information about integrated circuits formed on a wafer.

BACKGROUND OF THE INVENTION

Integrated circuits are usually produced by forming a plurality of integrated circuits on a semiconductor wafer by repeatedly exposing the wafer to a reticle mask utilizing a stepper, thereby forming a plurality of exposed areas arranged on the wafer surface. The image of the mask pattern is printed on a resist layer applied on the wafer surface and developed to form a resist pattern used as a mask for, for instance, etching a layer formed on the wafer surface. The integrated circuits are formed by repeating these processes. The individual integrated circuits are separated by saw lines used for a successive separation step.

In addition to the integrated circuits, test devices for measuring electric characteristics are also formed on the wafer. The test devices are usually known as process control modules (PCM), may include active or passive electric devices, such as transistors or resistive tracks, and are usually located within the saw lines. Published U.S. application for patent No. 2003/0017631 Al discloses a reticle including a device pattern region, in which a plurality of mask patterns of semiconductor device chips is formed, and including a test element group (TEG) pattern region formed on one side of the device pattern region. The TEG pattern region is provided for arranging patterns of TEGs and alignment marks for the exposing apparatus. The lateral dimension of the TEG pattern region is the same as that of the device pattern region. The width, i.e. the vertical dimension, of the TEG pattern region corresponds to two rows of the semiconductor device chip patterns.

However, despite all measures to simplify the production process, there is still room of improvement, in particular how to track wafers as a whole and integrated circuits, either fulfilling a product specification or not. OBJECT AND SUMMARY OF THE INVENTION

It is an object of the present invention to provide integrated circuits on a wafer whose production can be simplified and a simplified method for producing such integrated circuits on the wafer.

The object of the invention is achieved by a wafer as presented in the introduction, additionally comprising: at least one auxiliary integrated circuit formed on the wafer; wherein data carrying information about said integrated circuits are stored in said at least one auxiliary integrated circuit.

Furthermore, the object of the invention is achieved by a method of manufacturing integrated circuits on a wafer as presented in the introduction, additionally comprising the step of: forming at least one auxiliary integrated circuit on the wafer connected to data input means on the wafer such that data carrying information about said integrated circuits can be stored in said at least one auxiliary integrated circuit.

Finally, the object of the invention is achieved by a method of storing data carrying information about integrated circuits formed on a wafer as presented in the introduction, wherein said data are written in at least one auxiliary integrated circuit formed on the wafer.

A wafer in accordance with the invention comprises a plurality of integrated circuits formed on the wafer and at least one auxiliary integrated circuit formed on the wafer. Data carrying information about said integrated circuits are stored in said at least one auxiliary integrated circuit. Thus, the information are located on the wafer itself, and no external storage medium is required.

In a preferred embodiment, said auxiliary integrated circuit is an RFID circuit which is coupled to an antenna formed on said wafer. Thus, writing to and reading from said auxiliary integrated circuit may be performed in a wireless manner. In a further preferred embodiment, in addition to the said auxiliary integrated circuit being an RFID circuit also said integrated circuits are designed as RFID circuits. In this case, basically any of the circuits on the wafer can be used as an auxiliary integrated circuit by just adding a data interface to it, e.g. an antenna.

In another preferred embodiment, said auxiliary integrated circuit is an RFID circuit comprising at least one data input pad. In this way a more fail safe data transfer to or from the auxiliary integrated circuit can be achieved. One should also note that the auxiliary integrated circuit designed as an RFID circuit can be connected to both an antenna and a data input pad. In this way, data can be transferred by wire or wireless.

Advantageously, said auxiliary integrated circuit is formed adjacent to or in a process control module. Usually, there is some unused space nearby the process control module which advantageously is used for the auxiliary integrated circuit in this embodiment.

In yet another preferred embodiment, said data carry information about test results of a test performed on said individual integrated circuits. This helps to quickly proceed with a wafer test after a shutdown or current failure of the test equipment.

Furthermore, it is preferred if said data carry information about a wafer identification or product identification of said wafer. So, data in the auxiliary integrated circuit may not just be used for testing data but also for supply chain management, i.e. to track wafers.

It is preferred that said data are transferred to a separate storage medium before said wafer is cut into individual chips. Otherwise, if no separate storage medium is used, the link between the integrated circuits and the data in the auxiliary integrated circuit gets lost. This is undesired if the data is used for supply chain management. Preferably, said separate storage medium is a RFID circuit attached to a cutting frame used for cutting said wafer into individual chips. Here, data is transferred to a device (i.e. the cutting frame) which intuitively is associated with the integrated circuits on the wafer held by it. It is preferred that said data carry information about test results of a test performed on said individual integrated circuits and said data are retrieved in order to qualify each individual integrated circuits as good or bad. This helps to separate the good ones from the bad ones after cutting the wafer into individual integrated circuits and to keep the product quality high. However, said data may carry information about a wafer identification or product identification of said wafer or any other useful information. As mentioned hereinbefore, the wafer identification or product identification may be used for supply chain management. It should be noted that both test results and wafer identification or product identification may be stored in a single auxiliary circuit, why the auxiliary circuit can be used in a synergetic way.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in greater detail hereinafter, by way of non- limiting examples, with reference to the embodiments shown in the drawings.

In the Figures: - A -

Fig. 1 is a top-view of a plurality of integrated circuits on a wafer;

Fig. 2 is a part of the top-view of Fig. 1 showing a reticle field;

Fig. 3a,b are enlarged views of an auxiliary integrated circuit of Fig. 2, namely Fig. 3a a plain view and Fig. 3b a cross-section along line A-A' in Fig. 3a; Fig. 4 is a diagram for explaining a first programming example of an auxiliary integrated circuit of Fig. 3a,b;

Fig. 5 is a diagram for explaining a second programming example of an auxiliary integrated circuit of Fig. 3a,b; and

Fig. 6 is a diagram for explaining a third programming example of an auxiliary integrated circuit of Fig. 3a,b.

DESCRIPTION OF EMBODIMENTS

Fig. 1 shows a top-view of a plurality of integrated circuits 1 and auxiliary integrated circuits Ia on a semiconductor wafer 2 and Fig. 2 shows as detail of this top-view a reticle field. The integrated circuits 1 may have been formed on the wafer 2 as it will be explained below.

The integrated circuits 1 and auxiliary integrated circuits Ia on the wafer 2 are separated by first saw lines 4 running parallel in a first direction x and by second saw lines 5 running parallel in a second direction y. The first and second saw lines 4, 5 are each spaced such that two consecutive first saw lines 4 are equidistant and two consecutive second saw lines 5 are equidistant as well. Therefore, the integrated circuits 1 and auxiliary integrated circuits Ia are formed on the wafer 2 in rows running in the first direction x and columns running in the second direction y.

In addition to the integrated circuits 1 and auxiliary integrated circuits Ia, process control modules 6 and optical control modules 7 are formed on the wafer 2. The process control modules 6 are test devices for measuring electric characteristics of the wafer 2 and may include active or passive electric devices, such as transistors or resistive tracks. The optical control modules 7 are alignment marks formed on the wafer 2 and used for automatically aligning a reticle during the process of manufacturing the integrated circuits 1 and auxiliary integrated circuits Ia on the wafer 2 in this embodiment.

The optical control modules 7 may be comprised of square, rectangular or cross-shaped interference fields particularly automatically detectable by a stepper used for the reticle. Automatic alignment utilizing the optical control modules 7 may be accomplished by passing low-energy laser beams through alignment marks on the reticle and reflecting them off corresponding alignment marks, i.e. the optical control modules 7, on the wafer surface. The optical control modules 7 may particularly have a three dimensional structure such that they can be used for each exposure step during the manufacture of the integrated circuits 1 and auxiliary integrated circuits Ia on the wafer 2.

In the exemplary embodiment, each process control module 6 fits within a single column, but extends in the second direction y corresponding to several integrated circuits 1. Thus, each process control module 6 is delimitated by two consecutive second saw lines 5. Alternatively, the process control modules 6 can be located within a single row, and thus be delimitated by two consecutive first saw lines 4. It is also possible that each process control module 6 is delimitated by both, two consecutive first and two consecutive second saw lines 4, 5.

Above each process control module 6, there is a single, auxiliary integrated circuit Ia. Since for the exemplary embodiment the integrated circuits 1 have been formed on the wafer 2 utilizing a reticle and a stepper, the wafer surface, on which the integrated circuits 1 and auxiliary integrated circuits Ia are formed, is comprised of several exposure fields 9. Fig. 1 shows only four exposure fields 9 having sections 9a, 9b reserved for the saw lines 4 and 5. During manufacturing of the integrated circuits 1 on the wafer 2, an area of the wafer 2 corresponding to the reticle is exposed and then the reticle is moved to a further area of the wafer 2 utilizing the stepper. The wafer area between the four exposure fields 9 can either be exposed with the same exposure field 9 or with a different exposure field, e.g. an exposure field without process control module 6 or without auxiliary integrated circuit.

Fig. 3a,b are enlarged views of an auxiliary integrated circuit of Fig. 2, namely Fig. 3a a plain view and Fig. 3b a cross-section along line A-A' in Fig. 3a.

As may be obtained from Fig. 3a, the auxiliary integrated circuit Ia is an RFID circuit which is connected to an antenna 10a made of a metal layer such as a gold layer, formed on an upper surface of the wafer 2. Although antenna 10a has a simple shape in the Fig. 3a, any applicable shape like a loop, a monopole, a dipole, or meander structures is imaginable. The antenna 10a moreover may also exceed the size of the auxiliary integrated circuit Ia. For example, the antenna 10a may be a loop antenna having the size of one reticle or even the size of the wafer. As such an antenna is destroyed when the wafer is cut, it is important to transfer data from the auxiliary integrated circuit Ia to a separate storage medium before the wafer is cut.

The internal RFID circuit 5 a is connected to said antenna 10a via two wiring lines 6a, 6b. The RFID auxiliary integrated circuit also comprises an input pad 15a connected to said internal RFID circuit 5 a via wiring line 6c. Particularly, the internal RFID circuit 5 a includes a memory section 50a where data can be stored and wherefrom data can be retrieved either via said antenna 10a or via said pad 15 a.

If the integrated circuits 1 are RFID circuits as well, the mere difference between the integrated circuits 1 formed on said wafer 2 and the auxiliary integrated circuit Ia formed above the respective process control modules 6 is that the auxiliary integrated circuit Ia is connected to an antenna 10a and comprises the additional pad 15a for input/output and wiring 6c. It should be mentioned that it would be sufficient to have either the additional antenna 10a or the additional pin 15a for accessing the memory section 50a of the internal RFID circuit 5 a.

Fig. 4 is a diagram for explaining a first programming example of an auxiliary integrated circuit of Fig. 3a,b.

After all integrated circuits 1, auxiliary integrated circuits Ia, and process control modules 6 have been fabricated on the wafer 2, all integrated circuits 1 have to be tested before they are cut into individual chips. Usually, a test head 50 contacts each individual integrated circuit 1 using test needles 51, 52 and a test system 60 initiates a predetermined electrical test sequence.

These needles 51, 52 are relatively thin and sharp and are pressed with high pressure against the (not shown) contact pad of the integrated RFID circuit 1. Because the contact pads of the integrated RFID circuit 1 are made of soft metal such as aluminum or gold, they are deformed or get damaged. The deformations arising from the needles 51, 52 are undesired, because they make it more difficult to contact the integrated circuits 1 when mounting the particular RFID device. Thus, usually only two needle deformations per pad are allowed according to common technical standards.

According to prior art, after a shut down of the testing system 60 due to current failures or similar, the testing of the wafer 2 has to be restarted from the beginning, and already tested integrated circuits 1 receive further needle deformations. According to the first embodiment, the tester system 60, which controls the test head 50 and the test sequence to be applied to the integrated circuit 1 , sends each individual test result or test status TR to the RFID auxiliary integrated circuit Ia. The data carrying the information about the test result TR are stored in the memory section 50a of the internal circuit 5 a of the auxiliary integrated circuit Ia. Thus, even in case of a shutdown of the testing system 60, it is not necessary to test any integrated circuit Ia a second time, because the corresponding data are permanently kept in the auxiliary integrated circuit Ia and can be retrieved later.

Data retrieval and storage in a separate storage medium may be performed before the wafer 2 is cut into chips, either via the antenna 10a or via the pad 15 a. For example, said separate storage medium is a RFID circuit attached to a cutting frame used for cutting said wafer into individual chips.

Although in this embodiment the auxiliary integrated circuit Ia is positioned adjacent to or in the process control module 6 because of the space requirements, this is no mandatory measure. By contrast, the auxiliary integrated circuit Ia may be arranged at any position on the wafer 2.

Furthermore, it should be mentioned that not only test results TR can be stored in the memory section 50a, but also a serial number of the wafer 2, a lot number, a product identification, etc. Fig. 5 is a diagram for explaining a second programming example of an auxiliary integrated circuit of Fig. 3a,b.

The difference between the first and second embodiment consists in the way how the test result TR is stored in the auxiliary integrated circuit Ia. As can be seen in Fig. 5, here another needle 61 is connected to the testing system 60' and contacts the pad 15a of the auxiliary integrated circuit Ia during testing in order to write the test results TR into the memory section 50a of the circuit Ia. However, one can imagine that also two or more needles are used to connect to the auxiliary circuit Ia.

Fig. 6 is a diagram for explaining a third programming example of an auxiliary integrated circuit of Fig. 3a,b. Fig. 6 shows that additional data ID carrying any kind of information can be inputted in a transceiver 70 via an input means 71, such as a keyboard, and send to the memory section 50a of the auxiliary integrated circuit 1. Data ID retrieval can also be performed via the transceiver 70, and data can be displayed on an output means, such as a display 72. Thus, in principle it is possible to test the functionality of the auxiliary integrated circuit Ia by means of the transceiver 70 and to conclude that all integrated circuits 1 are properly functioning if auxiliary integrated circuit Ia is properly functioning.

Thus, it is possible to receive a (wireless) fast good/bad qualification about the wafer 2 using said auxiliary integrated circuit Ia. Of course, the auxiliary integrated circuit Ia can also be used for the supply chain management. The wafer receives a particular ID number or other data, if desired, and can be monitored during all process stages. Before the wafer 2 is cut into chips, the data stored in the memory section 50a of the auxiliary integrated circuit Ia can be retrieved and can be stored in a separate storage medium, such as a separate RFID chip attached to a cutting frame on which the wafer 2 is cut into pieces. Finally, it should be noted that the aforementioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprise" and its conjugations do not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice- versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A wafer (2), comprising: a plurality of integrated circuits (1) formed on the wafer (2); and at least one auxiliary integrated circuit (Ia) formed on the wafer (2); wherein data carrying information about said integrated circuits (1) are stored in said at least one auxiliary integrated circuit (Ia).

2. The wafer (2) of claim 1, wherein said auxiliary integrated circuit (Ia) is an RFID circuit which is coupled to an antenna (10a) formed on said wafer (2).

3. The wafer (2) of claim 1, wherein said auxiliary integrated circuit (Ia) is an RFID circuit comprising at least one data input pad (15a).

4. The wafer (2) of claim 1, wherein said auxiliary integrated circuit (Ia) is formed adjacent to or in a process control module (6).

5. The wafer (2) of claim 1, wherein said data carry information about test results of a test performed on said individual integrated circuits (1).

6. The wafer (2) of claim 1, wherein said data carry information about a wafer identification or product identification of said wafer (2).

7. A method of manufacturing integrated circuits (1) on a wafer (2), comprising the steps of: forming a plurality of integrated circuits (1) on the wafer (2); and forming at least one auxiliary integrated circuit (Ia) on the wafer (2) connected to data input means (10a; 15 a) on the wafer (2) such that data carrying information about said integrated circuits (1) can be stored in said at least one auxiliary integrated circuit (Ia).

8. The method of claim 7, wherein said auxiliary integrated circuit (Ia) is an

RFID circuit to which an antenna (10a) formed on said wafer (2) is added as said data input means (10a; 15a).

9. The method of claim 7, wherein said auxiliary integrated circuit (Ia) is an

RFID circuit to which at least one data input pad(15a) is added as said data input means (10a; 15a).

A method of storing data carrying information about integrated circuits (1) formed on a wafer (2), wherein said data are written in at least one auxiliary integrated circuit (Ia) formed on the wafer (2).

11. The method of claim 10, wherein said data are written via a wireless interface in said at least one auxiliary integrated circuit (Ia).

12. The method of claim 10, wherein said data are written via a wired interface in said at least one auxiliary integrated circuit (Ia).

13. The method of claim 10, wherein said data are transferred to a separate storage medium before said wafer (2) is cut into individual chips.

14. The method of claim 13, wherein said separate storage medium is a RFID circuit attached to a cutting frame used for cutting said wafer (2) into individual chips.

15. The method of claim 10, wherein said data carry information about test results of a test performed on said individual integrated circuits (1); and said data are retrieved in order to qualify each individual integrated circuit (1) as good or bad.

16. The method of claim 10, wherein said data carry information about a wafer identification or product identification of said wafer (2).