WO2009032678A1 - Semiconductor device and method for manufacturing thereof - Google Patents

Semiconductor device and method for manufacturing thereof Download PDF

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Publication number
WO2009032678A1
WO2009032678A1 PCT/US2008/074417 US2008074417W WO2009032678A1 WO 2009032678 A1 WO2009032678 A1 WO 2009032678A1 US 2008074417 W US2008074417 W US 2008074417W WO 2009032678 A1 WO2009032678 A1 WO 2009032678A1
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WO
WIPO (PCT)
Prior art keywords
insulating film
gate
semiconductor device
charge storage
gate electrode
Prior art date
Application number
PCT/US2008/074417
Other languages
French (fr)
Inventor
Takayuki Muruyama
Fumihiko Inoue
Katsuhide Sone
Original Assignee
Spansion Llc
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Publication date
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Publication of WO2009032678A1 publication Critical patent/WO2009032678A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing thereof, and more particularly, to a semiconductor device provided with a non-volatile memory and a method for manufacturing thereof.
  • a non-volatile memory as a semiconductor device capable of retaining data after turning the power off has been widely employed.
  • a flash memory as a representative non-volatile memory
  • a transistor which forms a memory cell has a floating gate or an insulating film so called a charge storage layer for storing charges to record data.
  • the flash memory having the insulating film as the charge storage layer includes a SONOS (Silicon Oxide Nitride Oxide Silicon) structure for storing charge in a trap layer inside an ONO (Oxide film/Nitride film/Oxide film) film.
  • ONO Oxide film/Nitride film/Oxide film
  • Japanese Patent Application Publication Nos. 2000-004014 and 2004-343014 disclose the technology having the charge storage layer partially formed on an area below a gate electrode.
  • the present invention provides a semiconductor device having a charge storage layer separated below a gate electrode, and a method for easily manufacturing thereof.
  • a semiconductor device which includes a gate electrode provided above a semiconductor substrate, a gate insulating film provided on the semiconductor substrate below a center of the gate electrode, a first insulating film provided from an area above the gate insulating film to areas below both ends of the gate electrode, which is formed of a material different from that of the gate insulating film, a tunnel insulating film formed on the semiconductor substrate at both sides of the gate insulating film, and a charge storage layer interposed between the tunnel insulating film and the first insulating film.
  • the semiconductor device having the charge storage layer separated below the gate electrode can be easily manufactured, and each thickness of the first insulating film and the tunnel insulating film can be individually set.
  • a method for manufacturing a semiconductor device which includes the steps of forming a gate insulating film on a semiconductor substrate, forming a first insulating film on the gate insulating film, forming a gate electrode on the first insulating film, selectively eliminating the gate electrode, the first insulating film and the gate insulating film which are laminated to allow the gate electrode and the first insulating film to be anisotropically etched, and the gate insulating film to be side-etched, forming a tunnel insulating film on a region where the gate insulating film on the semiconductor substrate is side-etched, and forming a charge storage layer on the tunnel insulating film.
  • the semiconductor device having the charge storage layer separated below the gate electrode can be easily manufactured, and each thickness of the first insulating film and the tunnel insulating film can be individually set.
  • FIG. 1 is a plan view of a flash memory according to a comparative example, and first to third embodiments of the present invention
  • FIGS. 2A to 2C show steps of manufacturing the flash memory according to the comparative example corresponding to a cross section taken along line A-A shown in FIG. 1 (part 1);
  • FIGS. 3 A to 3C show steps of manufacturing the flash memory according to the comparative example corresponding to the cross section taken along line A-A shown in FIG. 1 (part 2);
  • FIGS. 4A to 4C show steps of manufacturing the flash memory according to the first embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 1);
  • FIGS. 5A to 5C show steps of manufacturing the flash memory according to the first embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 2);
  • FIG. 6 is a sectional view showing the step of manufacturing the flash memory according to the first embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 3);
  • FIGS. 7A and 7B show steps of manufacturing the flash memory according to the first embodiment, wherein FIG. 7A is a sectional view corresponding to the cross section taken along line A-A shown in FIG. 1, and FIG. 7B is a sectional view corresponding to the cross section taken along line B-B shown in FIG. 1;
  • FIGS. 8 A to 8C show steps of manufacturing the flash memory according to the second embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 1);
  • FIG. 9 is a sectional view showing the step of manufacturing the flash memory according to the second embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 2);
  • FIGS. 1OA to 1OC show steps of manufacturing the flash memory according to the third embodiment corresponding to the cross section taken along line A-A shown in FIG. 1. Detailed Description
  • FIG. 1 is a plan view of a flash memory according to a comparative example, and first to third embodiments.
  • a bit line as a diffusion region 30 extends inside a silicon substrate 10.
  • a word line 34 extends to intersect the diffusion region 30 on the semiconductor substrate 10.
  • the semiconductor substrate 10 between the diffusion regions 30 serves as a channel region 44 on which a charge storage layer 26 is formed.
  • the charge storage layers 26 are shown, through the word line 34, as hatched areas.
  • the charge storage layers 26 are formed at ends El and E2 on the channel region 44 in an extending direction of the word line 34. As the charge storage layers 26 are separated from each other, the interference between two bits stored in a single memory cell is suppressed.
  • the charge storage layers 26 may be continuously formed in the extending direction of the diffusion region 30.
  • FIGS. 2A to 3C corresponds to the cross section taken along line A-A shown in FIG. 1.
  • a gate insulating film 12 is formed on the semiconductor substrate 10, and a dummy layer 36 is further formed on the gate insulating film 12. Predetermined areas of the dummy layer 36 and the gate insulating film 12 are etched.
  • the gate insulating film 12 is subjected to the side etching from both ends of the dummy layer 36 to form undercut portions 18. Referring to FIG.
  • an insulating film 20 is formed on the side surfaces of the gate insulating film 12, the upper surface of the semiconductor substrate 10, and the lower surface of the dummy layer 36, respectively.
  • the insulating film 20 on the semiconductor substrate 10 becomes a tunnel insulating film 21, and the insulating film 20 below the dummy layer 36 becomes a second insulating film 23.
  • the charge storage layer 26 is formed between the second insulating film 23 and the tunnel insulating film 21.
  • a diffusion region 30 is formed inside the semiconductor substrate 10 using the dummy layer 36 as a mask.
  • An insulating layer 32 is formed to cover the dummy layer 36, and polished until the upper surface of the dummy layer 36 is exposed.
  • the dummy layer 36 is eliminated.
  • a first insulating film 38 is formed on the gate insulating film 12, the second insulating film 23, and the insulating layer 32.
  • a top insulating film 40 is formed of the first insulating film 38 and the second insulating film 23.
  • the word line 34 also serving as the gate electrode is formed on the first insulating film 38. In this way, the semiconductor device according to the comparative example is produced.
  • the use of the dummy layer 36 makes the manufacturing step complicated.
  • the dummy layer 36 is used for forming the top insulating film 40 to be thicker than the tunnel insulating film 21.
  • the tunnel insulating film 21 and the second insulating film 23 are formed using the undercut portion 18 as shown in FIG. 2C, the tunnel insulating film 21 has substantially the same thickness as that of the second insulating film 23. Therefore, as shown in FIG. 3B, after eliminating the dummy layer 36, the first insulating film 38 is formed on the second insulating film 23, and the top insulating film 40 is formed of the first insulating film 38 and the second insulating film 23. As a result, the top insulating film 40 can be made thicker than the tunnel insulating film 21.
  • the top insulating film 40 is made thicker than the tunnel insulating film 21 for the following reason.
  • the tunnel insulating film 21 is required to be thin for the purpose of storing or eliminating the charge (electron) of the electric current applied between the charge storage layer 26 and the channel region 44.
  • the thickness of the top insulating film 40 is required to be thick for the purpose of maintaining the charge retention property of the charge storage layer 26. That is, the top insulating film 40 is required to be thick for suppressing migration of the charge from the gate electrode 16 to the charge storage layer 26 when eliminating the charge. That is why the top insulating film 40 is made thicker than the tunnel insulating film 21.
  • FIG. 1 shows the semiconductor device having the charge storage layer 26 separated under the gate electrode, which has been produced through a simple manufacturing process that allows each of the tunnel insulating film 21 and the top insulating film 40 to have an optimal thickness without using the dummy layer 36.
  • FIGS. 4A to 7B a method for manufacturing a semiconductor device according to a first embodiment will be described.
  • FIGS. 4A to 6 are sectional views corresponding to the cross sections taken along lines A-A and B-B shown in
  • FIG. 7A is a view corresponding to the cross section taken along line A-A shown in FIG. 1.
  • FIG. 7B is a view corresponding to the cross section taken along line B-B shown in FIG. 1.
  • the gate insulating film 12 formed of a silicon oxide film is formed on a P-type silicon semiconductor substrate (or a P type region in the silicon semiconductor substrate) 10 through a thermal oxidation process.
  • a first insulating film 14 formed of aluminum oxide is formed on the gate insulating film 12 through an ALD (Atomic Layer Deposition) process.
  • a gate electrode 16 formed of polysilicon is formed on the first insulating film 14 through a CVD (Chemical Vapor Deposition) process.
  • the thicknesses of the gate insulating film 12, the first insulating film 14, and the gate electrode 16 may be set to 20 nm, 10 nm, and 150 nm, respectively. Referring to FIG.
  • the gate electrode 16, the first insulating film 14, and the gate insulating film 12 are subjected to anisotropic etching to be eliminated so as to form a stripe pattern extending in the extending direction of the bit line.
  • the gate insulating film 12 is subjected to side etching using, for example, a fluorinated acid aqueous solution.
  • the undercut portions 18, which are side-etched regions, are formed below both ends of the gate electrode 16.
  • the insulating film 20 formed of aluminum oxide is formed through the ALD process to cover the inner surfaces of the undercut portions 18 (that is, areas of the undercut portion 18 on the semiconductor substrate 10 and below the first insulating film 14, and the side surfaces of the gate insulating film 12), and the gate electrode 16.
  • the thickness of the insulating film 20 may be set to 5 nm.
  • the insulating film 20 on the area of the undercut portion 18 on the semiconductor substrate 10 becomes the tunnel insulating film 21.
  • the insulating film 20 on the area of the undercut portion 18 below the first insulating film 14 becomes the second insulating film 22.
  • the first insulating film 14 and the second insulating film 22 form a top insulating film 24. Referring to FIG.
  • the charge storage layer 26 formed of hafnium oxide is formed through the ALD process so as to be filled in the undercut portion 18 and to cover the insulating film 20.
  • a laminated layer 28 which includes the tunnel insulating film 21, the charge storage layer 26 and the top insulating film 24 is formed inside the undercut portion 18.
  • the charge storage layer 26 and the insulating film 20 are etched using the gate electrode 16 as a mask.
  • arsenic ion is implanted into the semiconductor substrate 10 using the gate electrode 16 as the mask to form a bit line as an N-type diffusion region 30.
  • An insulating layer 32 formed of silicon oxide is formed to cover the upper surface of the diffusion region 30 and the gate electrode 16.
  • the insulating layer 32 is polished to expose the gate electrode 16 through a CMP (Chemical Mechanical Polish) process. This makes it possible to flatten the upper surfaces of the gate electrode 16 and the insulating layer 32.
  • a polysilicon layer is formed on the gate electrode 16 and the insulating layer 32.
  • the polysilicon layer and the gate electrode 16 corresponding to the area (line B-B shown in FIG. 1) expected to be formed between the word lines are eliminated.
  • the polysilicon layer resides in the area expected to be formed as the word line, and is electrically coupled with the gate electrode 16.
  • the word line 34 which intersects the diffusion region 30 is formed.
  • an inter-layer insulating film, a plug metal, a wiring layer and the like are formed to produce the semiconductor device according to the first embodiment.
  • the gate insulating film 12 and the first insulating film 14 are formed of different materials.
  • the chemical which etches the gate insulating film 12 but hardly etches the first insulating film 14 is used.
  • the fluorinated acid aqueous solution is used to side etch the gate insulating film 12.
  • the etching is performed as shown in FIG. 4B such that the gate electrode 16 and the first insulating film 14 are anisotropically etched.
  • the etching as shown in FIG. 4C allows the gate insulating film 12 to be selectively side-etched using the gate electrode 16 as the mask. In this way, the laminated gate electrode 16, the first insulating film 14 and the gate insulating film 12 are selectively eliminated.
  • the first and the second insulating films 14 and 22 form the top insulating film 24 as shown in FIG. 5A.
  • the insulating film 20 is formed through the ALD process to allow the tunnel insulating film 21 and the second insulating film 22 to have substantially the same thickness.
  • the thickness of the top insulating film 24 (the film thickness obtained by adding those of the first and the second insulating films) can be made larger than that of the tunnel insulating film 21. Accordingly, each thickness of the top insulating film 24 and the tunnel insulating film 21 can be set to an optimal value.
  • the first embodiment does not use a dummy layer, thus simplifying the manufacturing step compared with the comparative example.
  • the gate electrode 16 is formed above the semiconductor substrate 10 as shown in FIG. 7A.
  • the gate insulating film 12 is formed below the center (center of the gate electrode 16 in the extending direction of the word line 34) of the gate electrode 16, and on the semiconductor substrate 10.
  • the first insulating film 14 is formed to extend from the area on the gate insulating film 12 to the areas below both ends of the gate electrode 16 (both ends of the gate electrode 16 in the extending direction of the word line 34).
  • the first insulating film 14 is formed of a material different from that of the gate insulating film 12.
  • the charge storage layer 26 is interposed between the tunnel insulating film 21 and the first insulating film 14.
  • the second insulating film 22 is formed below the first insulating film 14 and on the charge storage layer 26. The second insulating film
  • the tunnel insulating film 21 are formed of the same material.
  • the tunnel insulating film 21 serves as a tunnel barrier of the charge storage layer 26.
  • the energy gap of the tunnel insulating film 21 with respect to the charge storage layer 26 is large.
  • the charge storage layer 26 may be formed of hafnium oxide.
  • the thin silicon oxide film with the thickness of about 1 nm may be formed on the semiconductor substrate 10. This makes it possible to improve the film quality of the tunnel oxide film 21 formed from the insulating film 20.
  • the top insulating film is formed of the first insulating film.
  • the manufacturing steps shown in FIGS. 4A to 4C according to the first embodiment are performed.
  • the thermal oxidation process is used to form an insulating film 20a formed of silicon oxide film to cover the upper surface of the semiconductor substrate 10 and the gate electrode 16.
  • the use of the thermal oxidation process does not allow the insulating film 20a to be formed below the first insulating film 14 and on the side surfaces of the gate insulating film 12.
  • the thickness of the insulating film 20a may be set to 5 nm, for example.
  • a tunnel insulating film 21a is formed from the insulating film 20a on the semiconductor substrate 10 in the undercut portion 18.
  • a charge storage layer 26a formed of silicon nitride film is formed through the CVD process so as to be filled in the undercut portion 18, and to cover the insulating film 20a.
  • the first insulating film 14 is directly formed on the charge storage layer 26a.
  • a laminated layer 28a is formed of the tunnel insulating film 21a, the charge storage layer 26a, and a top insulating layer 24a.
  • the manufacturing steps shown in FIGS. 5C to 7B according to the first embodiment are performed to produce the semiconductor device according to the second embodiment.
  • the second embodiment does not require the second insulating film to be formed upon formation of the tunnel insulating film 21a.
  • the tunnel insulating film 21 may be formed simultaneously with the formation of the second insulating film 22 as shown in FIG. 5A according to the first embodiment.
  • the first insulating film 14 when the gate insulating film 12 is formed of a silicon oxide film, the first insulating film 14 is formed of an aluminum oxide film for obtaining selectivity of the side etching shown in FIG. 4C.
  • the insulating film 20 that is, the tunnel insulating film 21
  • an arbitrary material may be selected for forming the tunnel insulating film 21a. This allows the use of the silicon oxide film capable of forming the tunnel insulating film with further excellent quality as the tunnel insulating film 21a.
  • the hafnium oxide with the energy gap smaller than that of aluminum oxide is used for forming the charge storage layer 26.
  • the silicon oxide film is used for forming the tunnel insulating film 21
  • the silicon nitride film which allows easy manufacturing can be used for forming the charge storage layer 26a.
  • each thickness of the top insulating film 24a and the tunnel insulating film 21a may be individually set.
  • the thickness of the first insulating film 14 that is, the top insulating film 24a
  • the tunnel insulating film 21a allows the tunnel current to flow, and the top insulating film 24a to have the thickness enough to keep the charge retention property of the charge storage layer 26a.
  • the first and the second insulating films are formed of different materials.
  • FIG. 1OA the manufacturing steps according to the first embodiment shown in FIGS. 4A to 4C are performed.
  • an insulating film 20b formed of silicon oxide is formed through the ALD process so as to cover the inner surface of the undercut portion 18 and the gate electrode 16.
  • the thickness of the insulating film 20b may be set to 5 nm.
  • a tunnel insulating film 21b is formed from the insulating film 20b on the semiconductor substrate 10 in the undercut portion 18.
  • the insulating film 20b below the first insulating film 14 in the undercut portion 18 becomes a second insulating film 22b.
  • a top insulating film 24b is formed of the first and the second insulating films 14 and 22b.
  • a charge storage layer 26b formed of silicon nitride film is formed through the CVD process so as to be filled in the undercut portions 18 and to cover the insulating film 20b.
  • a laminated layer 28b formed of the tunnel insulating film 21b, the charge storage layer 26b, and the top insulating film 24b is formed inside the undercut portion 18.
  • the aluminum oxide film is used for forming the first insulating film 14, and the silicon oxide film is used for forming the gate insulating film 12, the second insulating film 22b, and the tunnel insulating film 21b.
  • the first insulating film 14 is hardly etched upon the side etching of the gate insulating film 12.
  • Each of the gate insulating film 12 and the tunnel insulating film 21b may be formed of a silicon oxide film with excellent film quality.
  • the charge storage layer 26 may be a conductor such as polysilicon.
  • the charge storage layer 26 is formed by a conductor and disposed between the word lines 34 as shown in FIG. 7B, the charge storage layers 26 of the adjacent memory cells in the extending direction of the diffusion region 30 are electrically coupled.
  • the conductor is used as the charge storage layer, the step of eliminating the charge storage layer 26 between the word lines is performed.
  • any one of the hafnium oxide, the silicon nitride film, and the silicon film (for example, polysilicon film) may be used for forming the charge storage layer 26.
  • the use of the conductor silicon film as the charge storage layer allows a large quantity of charges to be stored.
  • the insulating film such as the hafnium oxide, the silicon nitride film can be used as the charge storage layer to omit the step of eliminating the charge storage layer between the word lines.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
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Abstract

A semiconductor device that includes a gate electrode (16) formed above a semiconductor substrate (10), a gate insulating film (12) formed on the semiconductor substrate (10) below the center of the gate electrode (16), a first insulating film (14) which is applied from an area on the gate insulating film (12) to areas below both ends of the gate electrode (16) and which is formed of a material different from that of the gate insulating film (12), a tunnel insulating film (21) formed on the semiconductor substrate (10) at both sides of the gate insulating film (12), and a charge storage layer (26) interposed between the tunnel insulating film (21) and the first insulating film (14), and a method for manufacturing the semiconductor device are provided.

Description

SEMICONDUCTOR DEVICE AlVD METHOD FOR MANUFACTURING
THEREOF
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing thereof, and more particularly, to a semiconductor device provided with a non-volatile memory and a method for manufacturing thereof.
Background
Recently, a non-volatile memory as a semiconductor device capable of retaining data after turning the power off has been widely employed. In a flash memory as a representative non-volatile memory, a transistor which forms a memory cell has a floating gate or an insulating film so called a charge storage layer for storing charges to record data. The flash memory having the insulating film as the charge storage layer includes a SONOS (Silicon Oxide Nitride Oxide Silicon) structure for storing charge in a trap layer inside an ONO (Oxide film/Nitride film/Oxide film) film. US Patent No. 6,011,725 discloses one type of the SONOS flash memory, that is, the flash memory having a virtual ground type memory cell which symmetrically operates a source and a drain which are switchable.
Japanese Patent Application Publication Nos. 2000-004014 and 2004-343014 disclose the technology having the charge storage layer partially formed on an area below a gate electrode.
In US Patent No. 6,011,725, two-bit data can be stored in a single memory cell. As the memory cell is miniaturized, the interference between two-bit data is more likely to occur. The charge storage layer is separated for storing the two bits respectively so as to suppress the interference. However, it is not easy to manufacture the semiconductor device having the charge storage layer below the gate electrode that is divided into two sections. Summary
The present invention provides a semiconductor device having a charge storage layer separated below a gate electrode, and a method for easily manufacturing thereof. According to an aspect of the present invention, there is provided a semiconductor device which includes a gate electrode provided above a semiconductor substrate, a gate insulating film provided on the semiconductor substrate below a center of the gate electrode, a first insulating film provided from an area above the gate insulating film to areas below both ends of the gate electrode, which is formed of a material different from that of the gate insulating film, a tunnel insulating film formed on the semiconductor substrate at both sides of the gate insulating film, and a charge storage layer interposed between the tunnel insulating film and the first insulating film. According to the present invention, the semiconductor device having the charge storage layer separated below the gate electrode can be easily manufactured, and each thickness of the first insulating film and the tunnel insulating film can be individually set.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device which includes the steps of forming a gate insulating film on a semiconductor substrate, forming a first insulating film on the gate insulating film, forming a gate electrode on the first insulating film, selectively eliminating the gate electrode, the first insulating film and the gate insulating film which are laminated to allow the gate electrode and the first insulating film to be anisotropically etched, and the gate insulating film to be side-etched, forming a tunnel insulating film on a region where the gate insulating film on the semiconductor substrate is side-etched, and forming a charge storage layer on the tunnel insulating film. According to the present invention, the semiconductor device having the charge storage layer separated below the gate electrode can be easily manufactured, and each thickness of the first insulating film and the tunnel insulating film can be individually set. Brief Description of the Drawings
FIG. 1 is a plan view of a flash memory according to a comparative example, and first to third embodiments of the present invention;
FIGS. 2A to 2C show steps of manufacturing the flash memory according to the comparative example corresponding to a cross section taken along line A-A shown in FIG. 1 (part 1);
FIGS. 3 A to 3C show steps of manufacturing the flash memory according to the comparative example corresponding to the cross section taken along line A-A shown in FIG. 1 (part 2); FIGS. 4A to 4C show steps of manufacturing the flash memory according to the first embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 1);
FIGS. 5A to 5C show steps of manufacturing the flash memory according to the first embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 2);
FIG. 6 is a sectional view showing the step of manufacturing the flash memory according to the first embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 3);
FIGS. 7A and 7B show steps of manufacturing the flash memory according to the first embodiment, wherein FIG. 7A is a sectional view corresponding to the cross section taken along line A-A shown in FIG. 1, and FIG. 7B is a sectional view corresponding to the cross section taken along line B-B shown in FIG. 1;
FIGS. 8 A to 8C show steps of manufacturing the flash memory according to the second embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 1);
FIG. 9 is a sectional view showing the step of manufacturing the flash memory according to the second embodiment corresponding to the cross section taken along line A-A shown in FIG. 1 (part 2); and
FIGS. 1OA to 1OC show steps of manufacturing the flash memory according to the third embodiment corresponding to the cross section taken along line A-A shown in FIG. 1. Detailed Description
FIG. 1 is a plan view of a flash memory according to a comparative example, and first to third embodiments. A bit line as a diffusion region 30 extends inside a silicon substrate 10. A word line 34 extends to intersect the diffusion region 30 on the semiconductor substrate 10. The semiconductor substrate 10 between the diffusion regions 30 serves as a channel region 44 on which a charge storage layer 26 is formed. Referring to FIG. 1, the charge storage layers 26 are shown, through the word line 34, as hatched areas. The charge storage layers 26 are formed at ends El and E2 on the channel region 44 in an extending direction of the word line 34. As the charge storage layers 26 are separated from each other, the interference between two bits stored in a single memory cell is suppressed. The charge storage layers 26 may be continuously formed in the extending direction of the diffusion region 30.
Next, a method for manufacturing the semiconductor device according to the comparative example will be described. Each of FIGS. 2A to 3C corresponds to the cross section taken along line A-A shown in FIG. 1. Referring to FIG. 2A, a gate insulating film 12 is formed on the semiconductor substrate 10, and a dummy layer 36 is further formed on the gate insulating film 12. Predetermined areas of the dummy layer 36 and the gate insulating film 12 are etched. Referring to FIG. 2B, the gate insulating film 12 is subjected to the side etching from both ends of the dummy layer 36 to form undercut portions 18. Referring to FIG. 2C, an insulating film 20 is formed on the side surfaces of the gate insulating film 12, the upper surface of the semiconductor substrate 10, and the lower surface of the dummy layer 36, respectively. The insulating film 20 on the semiconductor substrate 10 becomes a tunnel insulating film 21, and the insulating film 20 below the dummy layer 36 becomes a second insulating film 23.
Referring to FIG. 3A, the charge storage layer 26 is formed between the second insulating film 23 and the tunnel insulating film 21. A diffusion region 30 is formed inside the semiconductor substrate 10 using the dummy layer 36 as a mask. An insulating layer 32 is formed to cover the dummy layer 36, and polished until the upper surface of the dummy layer 36 is exposed. Referring to FIG. 3B, the dummy layer 36 is eliminated. A first insulating film 38 is formed on the gate insulating film 12, the second insulating film 23, and the insulating layer 32. A top insulating film 40 is formed of the first insulating film 38 and the second insulating film 23. Referring to FIG. 3C, the word line 34 also serving as the gate electrode is formed on the first insulating film 38. In this way, the semiconductor device according to the comparative example is produced.
In the comparative example, two charge storage layers 26 are formed below the gate electrode. However, the use of the dummy layer 36 makes the manufacturing step complicated. The dummy layer 36 is used for forming the top insulating film 40 to be thicker than the tunnel insulating film 21. When the tunnel insulating film 21 and the second insulating film 23 are formed using the undercut portion 18 as shown in FIG. 2C, the tunnel insulating film 21 has substantially the same thickness as that of the second insulating film 23. Therefore, as shown in FIG. 3B, after eliminating the dummy layer 36, the first insulating film 38 is formed on the second insulating film 23, and the top insulating film 40 is formed of the first insulating film 38 and the second insulating film 23. As a result, the top insulating film 40 can be made thicker than the tunnel insulating film 21.
The top insulating film 40 is made thicker than the tunnel insulating film 21 for the following reason. The tunnel insulating film 21 is required to be thin for the purpose of storing or eliminating the charge (electron) of the electric current applied between the charge storage layer 26 and the channel region 44. Meanwhile, the thickness of the top insulating film 40 is required to be thick for the purpose of maintaining the charge retention property of the charge storage layer 26. That is, the top insulating film 40 is required to be thick for suppressing migration of the charge from the gate electrode 16 to the charge storage layer 26 when eliminating the charge. That is why the top insulating film 40 is made thicker than the tunnel insulating film 21.
FIG. 1 shows the semiconductor device having the charge storage layer 26 separated under the gate electrode, which has been produced through a simple manufacturing process that allows each of the tunnel insulating film 21 and the top insulating film 40 to have an optimal thickness without using the dummy layer 36. First Embodiment
Referring to FIGS. 4A to 7B, a method for manufacturing a semiconductor device according to a first embodiment will be described. FIGS. 4A to 6 are sectional views corresponding to the cross sections taken along lines A-A and B-B shown in
FIG. 1, respectively. FIG. 7A is a view corresponding to the cross section taken along line A-A shown in FIG. 1. FIG. 7B is a view corresponding to the cross section taken along line B-B shown in FIG. 1.
Referring to FIG. 4A, the gate insulating film 12 formed of a silicon oxide film is formed on a P-type silicon semiconductor substrate (or a P type region in the silicon semiconductor substrate) 10 through a thermal oxidation process. A first insulating film 14 formed of aluminum oxide is formed on the gate insulating film 12 through an ALD (Atomic Layer Deposition) process. A gate electrode 16 formed of polysilicon is formed on the first insulating film 14 through a CVD (Chemical Vapor Deposition) process. The thicknesses of the gate insulating film 12, the first insulating film 14, and the gate electrode 16 may be set to 20 nm, 10 nm, and 150 nm, respectively. Referring to FIG. 4B, the gate electrode 16, the first insulating film 14, and the gate insulating film 12 are subjected to anisotropic etching to be eliminated so as to form a stripe pattern extending in the extending direction of the bit line. Referring to FIG. 4C, the gate insulating film 12 is subjected to side etching using, for example, a fluorinated acid aqueous solution. Thus, the undercut portions 18, which are side-etched regions, are formed below both ends of the gate electrode 16.
Referring to FIG. 5A, the insulating film 20 formed of aluminum oxide is formed through the ALD process to cover the inner surfaces of the undercut portions 18 (that is, areas of the undercut portion 18 on the semiconductor substrate 10 and below the first insulating film 14, and the side surfaces of the gate insulating film 12), and the gate electrode 16. The thickness of the insulating film 20 may be set to 5 nm. The insulating film 20 on the area of the undercut portion 18 on the semiconductor substrate 10 becomes the tunnel insulating film 21. The insulating film 20 on the area of the undercut portion 18 below the first insulating film 14 becomes the second insulating film 22. The first insulating film 14 and the second insulating film 22 form a top insulating film 24. Referring to FIG. 5B, the charge storage layer 26 formed of hafnium oxide is formed through the ALD process so as to be filled in the undercut portion 18 and to cover the insulating film 20. As a result, a laminated layer 28 which includes the tunnel insulating film 21, the charge storage layer 26 and the top insulating film 24 is formed inside the undercut portion 18. Referring to FIG. 5C, the charge storage layer 26 and the insulating film 20 are etched using the gate electrode 16 as a mask.
Referring to FIG. 6, arsenic ion is implanted into the semiconductor substrate 10 using the gate electrode 16 as the mask to form a bit line as an N-type diffusion region 30. An insulating layer 32 formed of silicon oxide is formed to cover the upper surface of the diffusion region 30 and the gate electrode 16. The insulating layer 32 is polished to expose the gate electrode 16 through a CMP (Chemical Mechanical Polish) process. This makes it possible to flatten the upper surfaces of the gate electrode 16 and the insulating layer 32.
Referring to FIGS. 7A and 7B, a polysilicon layer is formed on the gate electrode 16 and the insulating layer 32. Referring to FIG. 7B, the polysilicon layer and the gate electrode 16 corresponding to the area (line B-B shown in FIG. 1) expected to be formed between the word lines are eliminated. Referring to FIG. 7A, the polysilicon layer resides in the area expected to be formed as the word line, and is electrically coupled with the gate electrode 16. As a result, the word line 34 which intersects the diffusion region 30 is formed. Thereafter, an inter-layer insulating film, a plug metal, a wiring layer and the like are formed to produce the semiconductor device according to the first embodiment.
Referring to FIG. 4A, the gate insulating film 12 and the first insulating film 14 are formed of different materials. Referring to FIG. 4C, upon the side etching of the gate insulating film 12, the chemical which etches the gate insulating film 12 but hardly etches the first insulating film 14 is used. In the condition where the gate insulating film 12 is formed of a silicon oxide film, and the first insulating film 14 is formed of an aluminum oxide film, the fluorinated acid aqueous solution is used to side etch the gate insulating film 12. In the aforementioned step, the etching is performed as shown in FIG. 4B such that the gate electrode 16 and the first insulating film 14 are anisotropically etched. The etching as shown in FIG. 4C allows the gate insulating film 12 to be selectively side-etched using the gate electrode 16 as the mask. In this way, the laminated gate electrode 16, the first insulating film 14 and the gate insulating film 12 are selectively eliminated.
As shown in FIG. 4C, because the first insulating film 14 resides above the undercut portion 18, the first and the second insulating films 14 and 22 form the top insulating film 24 as shown in FIG. 5A. The insulating film 20 is formed through the ALD process to allow the tunnel insulating film 21 and the second insulating film 22 to have substantially the same thickness. As a result, the thickness of the top insulating film 24 (the film thickness obtained by adding those of the first and the second insulating films) can be made larger than that of the tunnel insulating film 21. Accordingly, each thickness of the top insulating film 24 and the tunnel insulating film 21 can be set to an optimal value. Unlike the comparative example, the first embodiment does not use a dummy layer, thus simplifying the manufacturing step compared with the comparative example.
In the semiconductor device manufactured as described above, the gate electrode 16 is formed above the semiconductor substrate 10 as shown in FIG. 7A. Referring to FIG. 7A and FIG. 1, the gate insulating film 12 is formed below the center (center of the gate electrode 16 in the extending direction of the word line 34) of the gate electrode 16, and on the semiconductor substrate 10. The first insulating film 14 is formed to extend from the area on the gate insulating film 12 to the areas below both ends of the gate electrode 16 (both ends of the gate electrode 16 in the extending direction of the word line 34). The first insulating film 14 is formed of a material different from that of the gate insulating film 12. The tunnel insulating film
21 is formed on the semiconductor substrate 10 at both sides of the gate insulating film 12. The charge storage layer 26 is interposed between the tunnel insulating film 21 and the first insulating film 14. The second insulating film 22 is formed below the first insulating film 14 and on the charge storage layer 26. The second insulating film
22 and the tunnel insulating film 21 are formed of the same material.
The tunnel insulating film 21 serves as a tunnel barrier of the charge storage layer 26. Preferably, the energy gap of the tunnel insulating film 21 with respect to the charge storage layer 26 is large. For example, when the aluminum oxide film is used for forming the tunnel insulating film 21, the charge storage layer 26 may be formed of hafnium oxide. Referring to FIG. 5 A, prior to formation of the insulating film 20 through the ALD process, the thin silicon oxide film with the thickness of about 1 nm may be formed on the semiconductor substrate 10. This makes it possible to improve the film quality of the tunnel oxide film 21 formed from the insulating film 20.
Second Embodiment
In a second embodiment, the top insulating film is formed of the first insulating film. Referring to FIG. 8A, the manufacturing steps shown in FIGS. 4A to 4C according to the first embodiment are performed. Referring to FIG. 8B, the thermal oxidation process is used to form an insulating film 20a formed of silicon oxide film to cover the upper surface of the semiconductor substrate 10 and the gate electrode 16. The use of the thermal oxidation process does not allow the insulating film 20a to be formed below the first insulating film 14 and on the side surfaces of the gate insulating film 12. The thickness of the insulating film 20a may be set to 5 nm, for example. A tunnel insulating film 21a is formed from the insulating film 20a on the semiconductor substrate 10 in the undercut portion 18.
Referring to FIG. 8C, a charge storage layer 26a formed of silicon nitride film is formed through the CVD process so as to be filled in the undercut portion 18, and to cover the insulating film 20a. Thus, the first insulating film 14 is directly formed on the charge storage layer 26a. A laminated layer 28a is formed of the tunnel insulating film 21a, the charge storage layer 26a, and a top insulating layer 24a.
Referring to FIG. 9, the manufacturing steps shown in FIGS. 5C to 7B according to the first embodiment are performed to produce the semiconductor device according to the second embodiment. As shown in FIG. 8B, the second embodiment does not require the second insulating film to be formed upon formation of the tunnel insulating film 21a. The tunnel insulating film 21 may be formed simultaneously with the formation of the second insulating film 22 as shown in FIG. 5A according to the first embodiment.
In the first embodiment, when the gate insulating film 12 is formed of a silicon oxide film, the first insulating film 14 is formed of an aluminum oxide film for obtaining selectivity of the side etching shown in FIG. 4C. When the film formed of the same material as the first insulating film 14 is required to be used for forming the top insulating film 24, the insulating film 20 (that is, the tunnel insulating film 21) is expected to be formed of the aluminum oxide film. Meanwhile, in the second embodiment, an arbitrary material may be selected for forming the tunnel insulating film 21a. This allows the use of the silicon oxide film capable of forming the tunnel insulating film with further excellent quality as the tunnel insulating film 21a.
In the first embodiment, as the aluminum oxide film is used as the tunnel insulating film 21, the hafnium oxide with the energy gap smaller than that of aluminum oxide is used for forming the charge storage layer 26. In the second embodiment, as the silicon oxide film is used for forming the tunnel insulating film 21, the silicon nitride film which allows easy manufacturing can be used for forming the charge storage layer 26a.
In the second embodiment, each thickness of the top insulating film 24a and the tunnel insulating film 21a may be individually set. As the thickness of the first insulating film 14 (that is, the top insulating film 24a) is made larger than that of the tunnel insulating film 21a, the tunnel insulating film 21a allows the tunnel current to flow, and the top insulating film 24a to have the thickness enough to keep the charge retention property of the charge storage layer 26a.
Third Embodiment In a third embodiment, the first and the second insulating films are formed of different materials. Referring to FIG. 1OA, the manufacturing steps according to the first embodiment shown in FIGS. 4A to 4C are performed. Referring to FIG. 1OB, an insulating film 20b formed of silicon oxide is formed through the ALD process so as to cover the inner surface of the undercut portion 18 and the gate electrode 16. The thickness of the insulating film 20b may be set to 5 nm. A tunnel insulating film 21b is formed from the insulating film 20b on the semiconductor substrate 10 in the undercut portion 18. The insulating film 20b below the first insulating film 14 in the undercut portion 18 becomes a second insulating film 22b. A top insulating film 24b is formed of the first and the second insulating films 14 and 22b. A charge storage layer 26b formed of silicon nitride film is formed through the CVD process so as to be filled in the undercut portions 18 and to cover the insulating film 20b. Thus, a laminated layer 28b formed of the tunnel insulating film 21b, the charge storage layer 26b, and the top insulating film 24b is formed inside the undercut portion 18. Referring to FIG. 1OC, the manufacturing steps according to the first embodiment shown in FIGS. 5C to 7B are performed to produce the semiconductor device according to the third embodiment. In the third embodiment, the aluminum oxide film is used for forming the first insulating film 14, and the silicon oxide film is used for forming the gate insulating film 12, the second insulating film 22b, and the tunnel insulating film 21b. Referring to FIG. 1OA, the first insulating film 14 is hardly etched upon the side etching of the gate insulating film 12. Each of the gate insulating film 12 and the tunnel insulating film 21b may be formed of a silicon oxide film with excellent film quality.
In the first to the third embodiments, the charge storage layer 26 may be a conductor such as polysilicon. When the charge storage layer 26 is formed by a conductor and disposed between the word lines 34 as shown in FIG. 7B, the charge storage layers 26 of the adjacent memory cells in the extending direction of the diffusion region 30 are electrically coupled. When the conductor is used as the charge storage layer, the step of eliminating the charge storage layer 26 between the word lines is performed. In this way, any one of the hafnium oxide, the silicon nitride film, and the silicon film (for example, polysilicon film) may be used for forming the charge storage layer 26. The use of the conductor silicon film as the charge storage layer allows a large quantity of charges to be stored. The insulating film such as the hafnium oxide, the silicon nitride film can be used as the charge storage layer to omit the step of eliminating the charge storage layer between the word lines.
While the preferred embodiments of the present invention are described in detail above, the present invention is not limited to those specific embodiments and, within the spirit and scope of the present invention as defined in the appended claims, various modifications and alterations may be made.

Claims

Claims
What is claimed is:
L A semiconductor device comprising: a gate electrode provided above a semiconductor substrate; a gate insulating film provided on the semiconductor substrate below a center of the gate electrode; a first insulating film provided from an area above the gate insulating film to areas below both ends of the gate electrode, which is formed of a material different from that of the gate insulating film; a tunnel insulating film formed on the semiconductor substrate at both sides of the gate insulating film; and a charge storage layer interposed between the tunnel insulating film and the first insulating film .
2. The semiconductor device according to claim 1, wherein the first insulating film has a thickness larger than that of the tunnel insulating film.
3. The semiconductor device according to claim 1 or 2, further comprising a second insulating film which is provided on the charge storage layer and below the first insulating film.
4. The semiconductor device according to claim 3, wherein the second insulating film is formed of the same material as that of the tunnel insulating film.
5. A method for manufacturing the semiconductor device according to claim 3 or 4, wherein a total thicknesses of the first and the second insulating films is larger than a thickness of the tunnel insulating film.
6. The semiconductor device according to claim 1 or 2, wherein the first insulating film is directly formed on the charge storage layer.
7. The semiconductor device according to any one of claims 1 to 6, wherein: the gate insulating film is formed of a silicon oxide film; and the first insulating film is formed of an aluminum oxide film.
8. The semiconductor device according to any one of claims 1 to 6, wherein the charge storage layer is formed of a silicon film.
9. A method for manufacturing a semiconductor device comprising: forming a gate insulating film on a semiconductor substrate; forming a first insulating film on the gate insulating film; forming a gate electrode on the first insulating film; selectively eliminating the gate electrode, the first insulating film and the gate insulating film which are laminated to allow the gate electrode and the first insulating film to be anisotropically etched, and the gate insulating film to be side-etched; forming a tunnel insulating film on a region where the gate insulating film on the semiconductor substrate is side-etched; and forming a charge storage layer on the tunnel insulating film.
10. The method for manufacturing a semiconductor device according to claim
9, further comprising: forming a second insulating film on the side-etched region below the first insulating film, wherein forming the tunnel insulating film is performed simultaneously with forming the second insulating film.
PCT/US2008/074417 2007-09-03 2008-08-27 Semiconductor device and method for manufacturing thereof WO2009032678A1 (en)

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