JP2004071877A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device and its manufacturing method, wherein an electric charge holding part formed by isolating at both ends of a gate is constituted in self-matching for a control gate. <P>SOLUTION: The semiconductor storage device comprises the gate obtained by sequentially laminating at least a tunnel insulating film 3, a pair of electric charge stored films 10 isolated by an isolated oxide film 4, a barrier insulating film 5 and a control gate electrode 6. The pair of electric charge stored films 10 of the device is constituted with the same material as a sidewall 9 covering a sidewall of the gate. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and is particularly characterized by a structure for accurately forming a pair of charge holding portions of a multi-level flash memory in which charge storage layers are spatially separated. The present invention relates to a semiconductor memory device and a method for manufacturing the same.
[0002]
[Prior art]
Flash memories and ferroelectric memories are known as nonvolatile memories that can store information even when the power is turned off. Among them, the flash memory is a gate insulating film of an insulated gate field effect transistor (IGFET). It has a floating gate embedded therein and stores information by storing charges representing stored information in the floating gate. For writing and erasing information, a tunnel current passing through an insulating film flows.
[0003]
In recent years, as one type of such a flash memory, a pair of charge holding portions which are spatially separated on a source side and a drain side are provided in a charge storage layer in a memory cell having a MONOS (Metal / Oxide / Nitride / Oxide / Semiconductor) structure. Multi-level flash memory has been attracting attention with the press announcement.
[0004]
Here, the principle of the conventional multi-level flash memory will be described with reference to FIG.
FIG. 6A is a schematic cross-sectional view of a principal part of one memory cell constituting a conventional multilevel flash memory. A tunnel oxide film 32 and a charge storage layer are formed on a p-type silicon substrate 31. A SiN film 33, a barrier oxide film 34, and a control gate electrode 35 made of polycrystalline silicon are sequentially formed and patterned into a gate structure, and then n-type impurities are ion-implanted to form an n ⁺ -type drain region 36 and An n-type source region 37 is provided.
[0005]
In this multi-valued flash memory, electrons are locally injected into the SiN film 33 serving as a charge storage layer from the n ⁺ -type drain region 36 or the n ⁺ -type source region 37 where the pn junction becomes reverse biased at the time of writing. The electrons are trapped by the traps in the SiN film 33 in the region where the drain-side charge holding portion 38 or the source-side charge holding portion 39 is formed.
Due to the held electrons, the threshold voltage of the cell transistor shifts, so that the current value of the cell transistor at the time of reading changes, and the information becomes "1" or "0".
[0006]
In such an element structure, generally, electrons injected and held on the source side of the cell transistor greatly contribute to the threshold voltage shift of the cell transistor. Therefore, the state of holding electrons at both ends of the gate is read out by exchanging the source and the drain. By performing the operation twice, it is possible to obtain 2-bit information in one memory cell of “00”, “01”, “10”, and “11”.
[0007]
FIG 6 (b) see FIG. 6 (b), if the charge on either of the drain side charge storage part 38 or the source side charge holding portion 39 is not held, i.e., the "00" state _I d -V _g This is a characteristic diagram, and the characteristics are the same even if reading is performed twice by exchanging the source and the drain.
[0008]
FIG 6 (c) refer to FIG. 6 (c), when the drain side charge storage part 38 only in the charge is held, i.e., "01" and _I d -V _g characteristics diagram of state, the source and drain When the reading is performed twice with the replacement, in the case of S → D, the influence of the accumulated charges is hardly affected.
[0009]
On the other hand, when the source and the drain are exchanged and D → S, the charge of the drain-side charge holding unit 38 is operatively the source-side charge, so that the threshold voltage _Vg is as shown by the broken line. , The shift from the threshold voltage V _g1 when no charge is held.
[0010]
Although illustration is omitted, when electric charges are held only in the source-side charge holding section 39, that is, in the case of the “10” state, the characteristics of S → D and D → S are as shown in FIG. The reverse is the case of c).
Also, if the charge on both the drain side charge storage part 38 or the source side charge storage part 39 is held, it will exhibit I _d -V _g characteristics indicated by the broken line in both cases Figure 6 (c) .
[0011]
[Problems to be solved by the invention]
However, in the above-described conventional multi-valued memory cell, the charge is redistributed because the SiN film holding the charge exists in the entire gate.
That is, when the electrons injected into the SiN film at one end of the gate at the time of writing is re-distributed, with a varying amount of shift of the threshold voltage V _g, the possibility of rewriting the opposite side of the information of the gate Therefore, there is a problem that read errors increase.
[0012]
This is because the charge existing at the center of the gate contributes most to the change in the threshold voltage. If the gate length is further reduced in the future, the frequency of read errors due to redistribution will increase.
[0013]
In order to solve such a problem, in principle, a film for retaining electric charges may be formed in a limited gate region. Usually, the film is formed at both ends of the gate region.
[0014]
However, in the manufacturing process, there is a problem that the patterning of the film for retaining electric charges and the patterning of the control gate must be adjusted with high precision, which is technically difficult.
[0015]
Therefore, an object of the present invention is to form a charge holding portion formed separately at both ends of a gate in a self-aligned manner with respect to a control gate in order to prevent redistribution of held charge.
[0016]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the basic configuration of the present invention. Here, means for solving the problem in the present invention will be described with reference to FIG.
Reference numerals 7 and 8 in the figure denote an oxide film and a protective film, respectively.
Referring to FIG. 1, in order to achieve the above object, the present invention provides at least a pair of charge storage films 10 separated by at least a tunnel insulating film 3, an isolation oxide film 4, a barrier insulating film 5, and a In the semiconductor memory device having a gate in which the control gate electrodes 6 are sequentially stacked, the pair of charge storage films 10 are made of the same material as the side wall 9 covering the side wall of the gate.
[0017]
By utilizing the sidewalls 9 in this manner, a pair of symmetric charge storage films 10 can be formed on each side of the source / drain region 2 of the opposite conductivity type.
Note that the channel region in the figure is the surface of the one conductivity type semiconductor substrate 1.
[0018]
In this case, the charge storage film 10 may be formed using any of silicon nitride, aluminum oxide, and tantalum oxide capable of forming a trap level.
[0019]
Further, by utilizing the oxidation of the side wall 9 and the side wall of the side wall 9, even in a semiconductor memory device having a floating gate structure, in particular, in a multi-level flash memory, each side of the opposite conductivity type source / drain region 2 is provided. A pair of symmetric charge storage films 10 can be formed.
[0020]
When the above-described semiconductor memory device is formed, at least a tunnel insulating film 3, a non-single-crystal semiconductor film, a barrier insulating film 5, and a control gate electrode 6 are sequentially stacked at least on a channel region. After forming, the laminated film is patterned to form a gate, and then the non-single-crystal semiconductor film forming the gate is side-etched, and then the side-etched non-single-crystal semiconductor film is completely oxidized. After the charge storage material is deposited on the entire surface, the charge storage film 10 and the side walls 9 separated by the separation oxide film 4 are simultaneously and integrally formed by depositing a charge storage material on the entire surface. It may be formed.
Note that a non-single-crystal semiconductor means a polycrystalline semiconductor, an amorphous semiconductor, or a microcrystalline semiconductor.
[0021]
When the above-mentioned floating gate type semiconductor memory device is formed, at least a tunnel insulating film 3, a non-single-crystal semiconductor film, a barrier insulating film 5, and a control gate electrode 6 are sequentially stacked at least on a channel region. After forming a stacked film, the stacked film is patterned to form a gate, then, the non-single-crystal semiconductor film forming the gate is side-etched, and the side-etched non-single-crystal semiconductor film is completely removed. Then, after a charge storage material is deposited on the entire surface, the charge storage film 10 and the side walls 9 separated by the separation oxide film 4 are subjected to anisotropic etching. Are simultaneously formed integrally, and then oxidized in an oxidizing atmosphere to convert the sidewalls 9 into oxide sidewalls 9. It may be Re.
[0022]
Note that, in the step of forming the isolation oxide film 4 in this case, the non-single-crystal semiconductor film may be a phosphorus-doped non-single-crystal semiconductor film, and the oxidation step of the non-single-crystal semiconductor film may be performed by a dry oxidation step. Controllability can be improved.
[0023]
Alternatively, in the step of forming the isolation oxide film 4, the non-single-crystal semiconductor film may be an undoped non-single-crystal semiconductor film, and the oxidation step of the non-single-crystal semiconductor film may be performed by a wet oxidation step. The entire crystal semiconductor film can be reliably oxidized.
[0024]
In depositing the charge storage material, it is preferable to use a reduced pressure chemical vapor deposition method in which the raw material is easily wrapped around.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Here, the manufacturing process of the multilevel flash memory according to the first embodiment of the present invention will be described with reference to FIGS.
Referring to FIG. 2A, first, a tunnel oxide film 12 having a thickness of, for example, 10 nm is formed on a p-type silicon substrate 11 in the same process as that of a conventional floating gate type flash memory. For example, an undoped polycrystalline silicon film 13 having a thickness of 50 nm, an ONO film 14 having a thickness of, for example, 10 nm in a silicon oxide film / silicon nitride film / silicon oxide film configuration, and a doped polycrystalline silicon film having a thickness of, for example, 100 nm After sequentially depositing a SiN film 16 having a thickness of, for example, 100 nm, the width (gate length) is obtained by performing reactive ion etching (RIE) and etching away the SiN films 16 to the ONO film 14. Form the top of a 0.2 μm gate structure, for example.
[0026]
The doped polycrystalline silicon film may be formed by depositing an amorphous silicon film, then implanting P ions, and forming a doped polycrystalline silicon film in the activation annealing step. The doped polycrystalline silicon film has a gate structure. Is patterned to form the control gate electrode 15.
[0027]
2B, the exposed portion of the polycrystalline silicon film 13 is etched by RIE and overetched to form a side etched portion 17 having a biting width of, for example, 0.05 μm.
Since the reaction product from the previous etching step adheres to the side wall of the control gate electrode 15, the side etching is not so much performed in this etching step.
[0028]
Next, as shown in FIG. 2C, n ⁺ -type drain region 19 and n ⁺ -type source region 20 are formed by implanting As ions 18 using the gate structure as a mask.
[0029]
Referring to FIG. 3 (d), the side-etched polycrystalline silicon film 13 is completely oxidized by performing an oxidizing process in a wet oxidizing atmosphere, and becomes an oxide film serving as a separation oxide film for separating a charge holding portion described later. 21 are formed.
In this oxidation step, an oxide film 22 is also formed on the exposed side surface of the control gate electrode 15.
[0030]
Next, as shown in FIG. 3E, an SiN film 23 having a thickness of, for example, 100 nm is deposited on the entire surface by a low pressure chemical vapor deposition method (LPCVD method) that enables good wraparound deposition.
[0031]
Next, referring to FIG. 3F, the sidewall 24 is formed by etching the SiN film 23 by performing anisotropic etching.
In this etching step, the SiN film 23 separated by the oxide film 21 below the gate structure becomes a pair of charge holding portions 25.
[0032]
Thereafter, the basic configuration of the multi-level flash memory is completed by repeating the steps of forming the interlayer insulating film, forming the via hole, filling the via, and forming the wiring layer as many times as required in the conventional flash memory. I do.
[0033]
As described above, in the first embodiment of the present invention, the isolation oxide film is formed by excessive etching and oxidation, and the pair of charge holding portions 25 are formed in the side wall forming process using anisotropic etching. Accordingly, the pair of charge holding portions 25 can be formed in a self-aligned manner with respect to the control gate 15 without requiring alignment.
[0034]
Therefore, it is possible to accurately form a charge storage layer in which charge redistribution does not occur, thereby suppressing occurrence of a read error in a multi-level flash memory.
The writing operation, reading operation, and erasing operation of the multi-level flash memory according to the first embodiment are the same as those of the conventional multi-level flash memory.
[0035]
Next, with reference to FIGS. 4 and 5, a description will be given of a manufacturing process of the multilevel flash memory according to the second embodiment of the present invention.
Referring to FIG. 4A, first, a tunnel oxide film 12, an undoped polycrystalline silicon film 13, an ONO film 14, and a doped polycrystalline silicon are formed on a p-type silicon substrate 11 in exactly the same manner as in the first embodiment. After the film and the SiN film 16 are sequentially deposited, reactive ion etching (RIE) is performed, and the SiN film 16 to the polycrystalline silicon film 13 are removed by etching to form a gate structure and a side etching portion. 17 is formed.
[0036]
Referring to FIG. 4B, n ⁺ -type drain region 19 and n ⁺ -type source region 20 are formed by implanting As ions 18 using the gate structure as a mask.
[0037]
Referring to FIG. 4 (c), the side-etched polycrystalline silicon film 13 is completely oxidized by performing an oxidizing process in a wet oxidizing atmosphere, thereby forming an oxide film serving as an isolation oxide film for separating a charge holding portion described later. 21 are formed.
In this oxidation step, an oxide film 22 is also formed on the exposed side surface of the control gate electrode 15.
[0038]
Referring to FIG. 5D, an undoped polycrystalline silicon layer 26 having a thickness of, for example, 100 nm is deposited on the entire surface by a low pressure chemical vapor deposition method (LPCVD method) capable of favorably performing wraparound deposition.
[0039]
Referring to FIG. 5E, the polysilicon layer 26 is etched by performing anisotropic etching to form a polysilicon sidewall 27.
[0040]
Referring to FIG. 5F, the polycrystalline silicon sidewall 27 is oxidized into an oxide sidewall 28 by performing an oxidation process in a dry oxidizing atmosphere. In this oxidation step, the pair of polycrystalline silicon layers left unoxidized under the gate structure becomes the charge retaining polycrystalline silicon layer 29.
[0041]
Thereafter, the basic configuration of the multi-level flash memory is completed by repeating the steps of forming the interlayer insulating film, forming the via hole, filling the via, and forming the wiring layer as many times as required in the conventional flash memory. I do.
[0042]
As described above, in the second embodiment of the present invention, the isolation oxide film is formed by over-etching and oxidation, and a pair of charge holding layers is formed in the side wall forming step and the oxidizing step using anisotropic etching. Since the crystalline silicon layer 29 is formed, a pair of charge retaining portions having a floating gate structure can be formed in a self-aligned manner with respect to the control gate 15 without requiring alignment.
[0043]
Therefore, it is possible to accurately form a charge accumulation layer having a floating gate structure in which charge redistribution does not occur, thereby suppressing occurrence of a read error in a multi-level flash memory.
The writing operation, reading operation, and erasing operation of the multi-level flash memory according to the second embodiment are the same as those of the conventional multi-level flash memory.
[0044]
The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible.
For example, in each of the above-described embodiments, the oxide film 21 serving as the isolation oxide film is formed by wet oxidation with a high oxidation rate, but may be performed by dry oxidation. The silicon layer 13 may be composed of a P-doped polycrystalline silicon layer having a high oxidation rate.
[0045]
In the first embodiment, the charge storage layer is formed by the SiN film. However, the charge storage layer is not limited to the SiN film. _{A 2} O ₃ film or a Ta ₂ O ₅ film may be used.
[0046]
Further, in the above-described second embodiment, when the oxide sidewall is formed, dry oxidation having excellent oxidation controllability is used, but the oxidation treatment may be performed by a wet oxidation method.
[0047]
Further, in each of the above embodiments, the ONO film is used as the barrier insulating film for preventing the injected electrons from flowing to the control gate electrode side. However, the ONO film is not limited to the ONO film, and is not limited to the ONO film. An insulating film having another configuration such as a SiO ₂ film may be used.
[0048]
In each of the above embodiments, the control gate electrode is formed of polycrystalline silicon. However, the present invention is not limited to polycrystalline silicon, and may have a silicide structure such as tungsten silicide or a polycide structure. Things.
[0049]
In each of the above embodiments, the channel region is the surface of the p-type silicon substrate, but may be the surface of the p-type well region where the n-type silicon substrate is formed.
[0050]
Further, in each of the above embodiments, the source / drain region has a single structure for simplicity of description. However, it is possible that the source / drain region has a multiplex structure of a shallow extension region and a deep n ⁺ -type region. Needless to say.
[0051]
Here, the detailed features of the present invention will be described again with reference to FIG. 1 again.
Again referring to FIG. 1 (Supplementary Note 1) At least a pair of a charge storage film 10, a barrier insulating film 5, and a control gate electrode 6, which are separated by a tunnel insulating film 3, an isolation oxide film 4, at least on a channel region, are sequentially stacked. A semiconductor memory device provided with a gate according to claim 1, wherein said pair of charge storage films (10) are made of the same material as a side wall (9) covering a side wall of said gate.
(Supplementary Note 2) The semiconductor memory device according to Supplementary Note 1, wherein the charge storage film 10 is made of any one of silicon nitride, aluminum oxide, and tantalum oxide.
(Supplementary Note 3) At least on the channel region, a gate is provided in which at least a tunnel insulating film 3, a pair of charge storage films 10, a barrier insulating film 5, and a control gate electrode 6 separated by a separation oxide film 4 are sequentially stacked. 2. The semiconductor memory device according to claim 1, wherein the side wall covering the side wall of the gate is formed of an oxide obtained by oxidizing the charge storage film.
(Supplementary Note 4) A step of sequentially stacking at least a tunnel insulating film 3, a non-single-crystal semiconductor film, a barrier insulating film 5, and a control gate electrode 6 on at least a channel region to form a stacked film, and patterning the stacked film. Forming a gate, performing a side etching of the non-single-crystal semiconductor film forming the gate, completely oxidizing the side-etched non-single-crystal semiconductor film to form an isolation oxide film 4, and charging the entire surface. Depositing a material for storage and then performing anisotropic etching to simultaneously and integrally form the charge storage film 10 and the side walls 9 separated by the separation oxide film 4. A method for manufacturing a semiconductor memory device.
(Supplementary Note 5) A step of sequentially laminating at least a tunnel insulating film 3, a non-single-crystal semiconductor film, a barrier insulating film 5, and a control gate electrode 6 on at least a channel region to form a laminated film, and patterning the laminated film Forming a gate, performing a side etching of the non-single-crystal semiconductor film forming the gate, completely oxidizing the side-etched non-single-crystal semiconductor film to form an isolation oxide film 4, and charging the entire surface. Depositing a material for storage and then performing anisotropic etching to simultaneously form the charge storage film 10 and the side walls 9 separated by the separation oxide film 4 simultaneously, oxidizing in an oxidizing atmosphere Converting the side wall 9 into the oxide side wall 9 by the following method.
(Supplementary Note 6) The supplementary note 4 or 5, wherein the non-single-crystal semiconductor film is formed of a phosphorus-doped non-single-crystal semiconductor film, and the non-single-crystal semiconductor film is oxidized by a dry oxidation process. A method for manufacturing a semiconductor memory device.
(Supplementary Note 7) The semiconductor according to Supplementary Note 4 or 5, wherein the non-single-crystal semiconductor film is formed of an undoped non-single-crystal semiconductor film, and the oxidation process of the non-single-crystal semiconductor film is performed by a wet oxidation process. A method for manufacturing a storage device.
(Supplementary Note 8) The method for manufacturing a semiconductor memory device according to any one of Supplementary Notes 4 to 7, wherein the charge storage material is deposited by a low pressure chemical vapor deposition method.
[0052]
【The invention's effect】
According to the present invention, by using an over-etching process and a sidewall forming process, a charge holding portion formed separately at both ends of a gate can be formed in a self-aligned manner with respect to a control gate without requiring alignment. This makes it possible to prevent redistribution of the charges held in the charge holding portion, which greatly contributes to the practical use of highly reliable semiconductor memory devices such as multi-valued flash memories.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing process of the multilevel flash memory according to the first embodiment of the present invention up to a certain point;
FIG. 3 is an explanatory diagram of a manufacturing process of the multilevel flash memory according to the first embodiment of the present invention after FIG. 2;
FIG. 4 is an explanatory diagram of a manufacturing process of a multilevel flash memory according to a second embodiment of the present invention up to a certain point;
FIG. 5 is an explanatory diagram of a manufacturing process of the multilevel flash memory according to the second embodiment of the present invention after FIG. 4;
FIG. 6 is a diagram illustrating the principle of a conventional multilevel flash memory.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 One conductivity type semiconductor substrate 2 Reverse conductivity type source / drain region 3 Tunnel insulating film 4 Isolation oxide film 5 Barrier insulating film 6 Control gate electrode 7 Oxide film 8 Protective film 9 Side wall 10 Charge storage film 11 P-type silicon substrate 12 Tunnel Oxide film 13 Polycrystalline silicon layer 14 ONO film 15 Control gate electrode 16 SiN film 17 Side etching portion 18 As ion 19 n ⁺ -type drain region 20 n ⁺ -type source region 21 Oxide film 22 Oxide film 23 SiN film 24 Side wall 25 Charge Retaining part 26 Polycrystalline silicon layer 27 Polycrystalline silicon sidewall 28 Oxide sidewall 29 Charge retaining polycrystalline silicon layer 31 P-type silicon substrate 32 Tunnel oxide film 33 SiN film 34 Barrier oxide film 35 Control gate electrode 36 n ⁺ type drain Region 37 n ⁺ type source region 3 8 Drain side charge holding unit 39 Source side charge holding unit

Claims (5)

In a semiconductor memory device including at least a gate on which at least a channel insulating film, a pair of charge storage films separated by an isolation oxide film, a barrier insulating film, and a control gate electrode are sequentially stacked on at least a channel region, A semiconductor memory device, wherein a storage film is made of the same material as a sidewall covering a sidewall of the gate. 2. The semiconductor memory device according to claim 1, wherein said charge storage film is made of one of silicon nitride, aluminum oxide, and tantalum oxide. In a semiconductor memory device including at least a gate on which at least a tunnel insulating film, a pair of charge storage films separated by an isolation oxide film, a barrier insulating film, and a control gate electrode are sequentially stacked on a channel region, a side wall of the gate is provided. A side wall that covers the semiconductor device is formed of an oxide obtained by oxidizing the charge storage film. Forming a stacked film by sequentially stacking at least a tunnel insulating film, a non-single-crystal semiconductor film, a barrier insulating film, and a control gate electrode on at least a channel region; and forming a gate by patterning the stacked film. A step of side-etching the non-single-crystal semiconductor film forming the gate, a step of completely oxidizing the side-etched non-single-crystal semiconductor film to form an isolation oxide film, and after depositing a charge storage material on the entire surface. Forming a charge storage film and a side wall separated by the separation oxide film simultaneously by performing anisotropic etching. Forming a stacked film by sequentially stacking at least a tunnel insulating film, a non-single-crystal semiconductor film, a barrier insulating film, and a control gate electrode on at least a channel region; and forming a gate by patterning the stacked film. A step of side-etching the non-single-crystal semiconductor film forming the gate, a step of completely oxidizing the side-etched non-single-crystal semiconductor film to form an isolation oxide film, and after depositing a charge storage material on the entire surface. Forming the charge storage film and the sidewall separated by the isolation oxide film simultaneously by performing anisotropic etching, and converting the sidewall into an oxide sidewall by oxidizing in an oxidizing atmosphere. And a method of manufacturing a semiconductor memory device.

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