WO2008155822A1 - キャッシュ制御装置及び制御方法 - Google Patents

キャッシュ制御装置及び制御方法 Download PDF

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Publication number
WO2008155822A1
WO2008155822A1 PCT/JP2007/062325 JP2007062325W WO2008155822A1 WO 2008155822 A1 WO2008155822 A1 WO 2008155822A1 JP 2007062325 W JP2007062325 W JP 2007062325W WO 2008155822 A1 WO2008155822 A1 WO 2008155822A1
Authority
WO
WIPO (PCT)
Prior art keywords
port means
thread
access requests
access
accordance
Prior art date
Application number
PCT/JP2007/062325
Other languages
English (en)
French (fr)
Inventor
Naohiro Kiyota
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07767183A priority Critical patent/EP2159700A4/en
Priority to JP2009520176A priority patent/JP4706030B2/ja
Priority to KR1020097026258A priority patent/KR101077514B1/ko
Priority to PCT/JP2007/062325 priority patent/WO2008155822A1/ja
Priority to CN2007800532016A priority patent/CN101681303B/zh
Publication of WO2008155822A1 publication Critical patent/WO2008155822A1/ja
Priority to US12/654,310 priority patent/US8412886B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1048—Scalability

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

　スレッドに共有される形態で設けられ、複数のエントリを有してそれらのエントリにアクセス要求を保持するポート手段を備えて、そのポート手段を使って、同時に実行される複数のスレッドで共有されるキャッシュに対してのアクセス要求を制御するという構成を採るときに、各スレッドの発行するアクセス要求を、そのスレッドに割り付けられたポート手段のポート部分に登録し、これにより、ポート手段をスレッド構成に合わせて分割して使用するように制御する。そして、アクセス要求を選択する場合には、各スレッド毎に、ポート手段の保持するそのスレッドの発行したアクセス要求の中から、規定の優先制御に従ってアクセス要求を選択して、その選択したアクセス要求の中からスレッド選択信号に従って最終的なアクセス要求を選択する。この構成に従って、ポート手段の資源量を抑えつつ効率的に使用しながらキャッシュアクセス処理を実行できるようになる。
PCT/JP2007/062325 2007-06-19 2007-06-19 キャッシュ制御装置及び制御方法 WO2008155822A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP07767183A EP2159700A4 (en) 2007-06-19 2007-06-19 CACHE CONTROL AND CONTROL PROCEDURES
JP2009520176A JP4706030B2 (ja) 2007-06-19 2007-06-19 キャッシュ制御装置及び制御方法
KR1020097026258A KR101077514B1 (ko) 2007-06-19 2007-06-19 캐시 제어장치 및 제어방법
PCT/JP2007/062325 WO2008155822A1 (ja) 2007-06-19 2007-06-19 キャッシュ制御装置及び制御方法
CN2007800532016A CN101681303B (zh) 2007-06-19 2007-06-19 高速缓存控制装置以及控制方法
US12/654,310 US8412886B2 (en) 2007-06-19 2009-12-16 Cache controller and control method for controlling access requests to a cache shared by plural threads that are simultaneously executed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062325 WO2008155822A1 (ja) 2007-06-19 2007-06-19 キャッシュ制御装置及び制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,310 Continuation US8412886B2 (en) 2007-06-19 2009-12-16 Cache controller and control method for controlling access requests to a cache shared by plural threads that are simultaneously executed

Publications (1)

Publication Number Publication Date
WO2008155822A1 true WO2008155822A1 (ja) 2008-12-24

Family

ID=40155987

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062325 WO2008155822A1 (ja) 2007-06-19 2007-06-19 キャッシュ制御装置及び制御方法

Country Status (6)

Country Link
US (1) US8412886B2 (ja)
EP (1) EP2159700A4 (ja)
JP (1) JP4706030B2 (ja)
KR (1) KR101077514B1 (ja)
CN (1) CN101681303B (ja)
WO (1) WO2008155822A1 (ja)

Cited By (1)

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WO2011045931A1 (ja) * 2009-10-14 2011-04-21 パナソニック株式会社 情報処理装置

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CN101689143B (zh) * 2007-06-20 2012-07-04 富士通株式会社 高速缓存控制装置以及控制方法
US9086909B2 (en) * 2011-05-17 2015-07-21 Oracle International Corporation System and method for supporting work sharing muxing in a cluster
US8671232B1 (en) * 2013-03-07 2014-03-11 Freescale Semiconductor, Inc. System and method for dynamically migrating stash transactions
US9632958B2 (en) 2014-07-06 2017-04-25 Freescale Semiconductor, Inc. System for migrating stash transactions

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WO2004068361A1 (ja) * 2003-01-27 2004-08-12 Fujitsu Limited 記憶制御装置、データキャッシュ制御装置、中央処理装置、記憶装置制御方法、データキャッシュ制御方法およびキャッシュ制御方法
JP2006040141A (ja) * 2004-07-29 2006-02-09 Fujitsu Ltd マルチスレッドプロセッサ
JP2006524380A (ja) * 2003-04-23 2006-10-26 インターナショナル・ビジネス・マシーンズ・コーポレーション 同時マルチスレッド（ｓｍｔ）プロセッサにおいてスレッドごとのプロセッサ・リソース使用率を決定するためのアカウンティング方法および論理

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US7073033B2 (en) * 2000-02-25 2006-07-04 Oracle International Corporation Memory model for a run-time environment
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KR100429543B1 (ko) * 2002-05-25 2004-04-29 삼성전자주식회사 네트워크 프로세서에서 다양한 개수의 포트들을 처리하기위한 방법
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Publication number Priority date Publication date Assignee Title
WO2011045931A1 (ja) * 2009-10-14 2011-04-21 パナソニック株式会社 情報処理装置

Also Published As

Publication number Publication date
US20100100686A1 (en) 2010-04-22
CN101681303B (zh) 2011-12-14
EP2159700A1 (en) 2010-03-03
CN101681303A (zh) 2010-03-24
JP4706030B2 (ja) 2011-06-22
KR20100017837A (ko) 2010-02-16
EP2159700A4 (en) 2011-07-20
KR101077514B1 (ko) 2011-10-28
JPWO2008155822A1 (ja) 2010-08-26
US8412886B2 (en) 2013-04-02

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