WO2012122182A3 - Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers - Google Patents

Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers Download PDF

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Publication number
WO2012122182A3
WO2012122182A3 PCT/US2012/027905 US2012027905W WO2012122182A3 WO 2012122182 A3 WO2012122182 A3 WO 2012122182A3 US 2012027905 W US2012027905 W US 2012027905W WO 2012122182 A3 WO2012122182 A3 WO 2012122182A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
memory
memory cells
systems
distributing
Prior art date
Application number
PCT/US2012/027905
Other languages
French (fr)
Other versions
WO2012122182A2 (en
Inventor
Robert Walker
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to EP12755210.7A priority Critical patent/EP2684133B1/en
Priority to CN201280019658.6A priority patent/CN103493026B/en
Priority to EP18170452.9A priority patent/EP3373150B1/en
Priority to KR1020137025982A priority patent/KR101993651B1/en
Publication of WO2012122182A2 publication Critical patent/WO2012122182A2/en
Publication of WO2012122182A3 publication Critical patent/WO2012122182A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)

Abstract

Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.
PCT/US2012/027905 2011-03-07 2012-03-06 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers WO2012122182A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP12755210.7A EP2684133B1 (en) 2011-03-07 2012-03-06 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
CN201280019658.6A CN103493026B (en) 2011-03-07 2012-03-06 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
EP18170452.9A EP3373150B1 (en) 2011-03-07 2012-03-06 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
KR1020137025982A KR101993651B1 (en) 2011-03-07 2012-03-06 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/042,164 US8892844B2 (en) 2011-03-07 2011-03-07 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
US13/042,164 2011-03-07

Publications (2)

Publication Number Publication Date
WO2012122182A2 WO2012122182A2 (en) 2012-09-13
WO2012122182A3 true WO2012122182A3 (en) 2013-01-31

Family

ID=46797130

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/027905 WO2012122182A2 (en) 2011-03-07 2012-03-06 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers

Country Status (6)

Country Link
US (3) US8892844B2 (en)
EP (2) EP3373150B1 (en)
KR (1) KR101993651B1 (en)
CN (2) CN103493026B (en)
TW (1) TWI539286B (en)
WO (1) WO2012122182A2 (en)

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US8892844B2 (en) 2011-03-07 2014-11-18 Micron Technology, Inc. Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
US10838886B2 (en) 2011-04-19 2020-11-17 Micron Technology, Inc. Channel depth adjustment in memory systems
US9208755B2 (en) 2012-12-03 2015-12-08 Nvidia Corporation Low power application execution on a data processing device having low graphics engine utilization
US9183057B2 (en) 2013-01-21 2015-11-10 Micron Technology, Inc. Systems and methods for accessing memory
US10042750B2 (en) * 2013-03-15 2018-08-07 Micron Technology, Inc. Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor
US9507628B1 (en) 2015-09-28 2016-11-29 International Business Machines Corporation Memory access request for a memory protocol
KR102530889B1 (en) * 2016-04-06 2023-05-11 에스케이하이닉스 주식회사 Data processing system and operating method of data processing system
KR20180061851A (en) 2016-11-30 2018-06-08 삼성전자주식회사 Storage device supporting byte accessible interface and block accessible interface and electronic system including the same
US10977198B2 (en) 2018-09-12 2021-04-13 Micron Technology, Inc. Hybrid memory system interface

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Also Published As

Publication number Publication date
US10162557B2 (en) 2018-12-25
US9933972B2 (en) 2018-04-03
CN103493026A (en) 2014-01-01
EP3373150A1 (en) 2018-09-12
KR20140013010A (en) 2014-02-04
US20180300079A1 (en) 2018-10-18
CN103493026B (en) 2017-02-15
TW201243606A (en) 2012-11-01
US20120233413A1 (en) 2012-09-13
CN107025181B (en) 2020-07-31
US8892844B2 (en) 2014-11-18
US20150074370A1 (en) 2015-03-12
KR101993651B1 (en) 2019-06-27
CN107025181A (en) 2017-08-08
WO2012122182A2 (en) 2012-09-13
EP3373150B1 (en) 2020-05-13
EP2684133A4 (en) 2015-05-06
EP2684133B1 (en) 2018-05-23
TWI539286B (en) 2016-06-21
EP2684133A2 (en) 2014-01-15

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