WO2008143461A2 - Wafer level chip scale package of an image sensor by means of through hole interconnection and method for manufacturing the same - Google Patents

Wafer level chip scale package of an image sensor by means of through hole interconnection and method for manufacturing the same Download PDF

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Publication number
WO2008143461A2
WO2008143461A2 PCT/KR2008/002837 KR2008002837W WO2008143461A2 WO 2008143461 A2 WO2008143461 A2 WO 2008143461A2 KR 2008002837 W KR2008002837 W KR 2008002837W WO 2008143461 A2 WO2008143461 A2 WO 2008143461A2
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WO
WIPO (PCT)
Prior art keywords
image sensor
wafer substrate
hole
electrode pads
conductive material
Prior art date
Application number
PCT/KR2008/002837
Other languages
French (fr)
Other versions
WO2008143461A3 (en
Inventor
Tae-Seok Park
Young Sung Kim
Original Assignee
Tae-Seok Park
Young Sung Kim
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020070049202A external-priority patent/KR100897761B1/en
Priority claimed from KR1020070056453A external-priority patent/KR100903553B1/en
Application filed by Tae-Seok Park, Young Sung Kim filed Critical Tae-Seok Park
Publication of WO2008143461A2 publication Critical patent/WO2008143461A2/en
Publication of WO2008143461A3 publication Critical patent/WO2008143461A3/en

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    • H01L27/14687—Wafer level processing
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Definitions

  • the present invention relates to an image sensor and a method for manufacturing the same and, more particularly, to a wafer level chip scale package of an image sensor for a camera module, which is used for portable appliances such as a cellular phone, a mobile communication terminal, etc., and a method for manufacturing the same.
  • an image sensor is a semiconductor module for converting an optical image to an electric signal and used to store an image signal and transfer it to a display device.
  • Image sensors are roughly classified into two classes, i.e., one is a charge- coupled device (CCD) and the other is a complementary metal oxide semiconductor (CMOS).
  • CCD charge- coupled device
  • CMOS complementary metal oxide semiconductor
  • the CCD image sensor transfers an electric charge by continually controlling a depth of a potential well in the direction of the charge transfer.
  • the CMOS image sensor performs an image sensing by using one or more transistor and a photo diode included in a pixel unit cell, wherein the photo diode acts as a photo sensor.
  • the image sensors such as CCD image sensors and CMOS image sensors have been widely used for cameras of cellular phones or personal digital assistances (PDAs), etc.
  • portable devices such as cellular phones are required to be made smaller and thinner so that they can be carried conveniently.
  • camera modules for use in such cellular phones need to have a height and a length x width size as small as possible, and if possible, in a sensor chip size.
  • An image sensor chip is bonded to the upper part of a printed circuit board (PCB) in the last process for packaging, and the packaged image sensor is assembled in a camera.
  • PCB printed circuit board
  • Modularization of an image sensor can not be easily performed using general methods, since an image-sensing window and electrode pads for input/output signals from the image-sensing window are formed on a same plane. Thus, it is required to modularize a camera on a PCB through the methods such as die bonding, wire bonding, etc.
  • a camera module packaged using the conventional processes has an increased height and size, and thus it is difficult to make a portable device with a built-in camera module, in the recent trend of smaller and thinner portable devices.
  • a wafer level chip scale package (WL-CSP) method has been developed as one modularization method for solving such size problems.
  • FPCB or a rigid printed circuit board (RPCB) using an anisotropic conductive film (ACF).
  • ACF anisotropic conductive film
  • the processes of forming a window on an ACF and pre-bonding of an image sensor and a PCB using the window can not be automated easily and the processes are performed manually, which results in a decrease in a production yield.
  • FIG. 1 is a cross-sectional view of an image sensor processed for packaging using a conventional technology.
  • FIG. 2 is a cross-sectional view of an image sensor processed for packaging using another conventional technology.
  • a silicon wafer (21) is formed to have electrode pads (22) and image sensors (23) on its surface, and a cover glass (24) is attached to the front side of the silicon wafer.
  • the back side of the silicon wafer (21) is ground to a predetermined depth, and then the silicon wafer corresponding to the underneath of the electrode pads on the front side is selectively etched from the back side using a deep reactive ion etching method, until the electrode pads (22) on the front side of the silicon wafer (21) are exposed.
  • via holes (27) are formed.
  • the via holes (27) are filled with metal using electroplating or electroless plating, and on the via holes filled with metal are solder ball bumps (25) formed.
  • the silicon wafer is diced along a dicing line (26) to complete a packaged image sensor.
  • a dicing line (26) it is difficult to form via holes (27) at the specific positions of back side of the silicon wafer (21) so that they are located under the corresponding electrode pads (22).
  • the conventional techniques described above incorporate attachment of a cover glass for protection of a sensor and simple processes.
  • a cover glass reflects or absorbs a part of the light entering a sensor from the outside, which results in a light loss and accordingly, a decrease in a sensor' sensitivity.
  • CMOS image sensors with over 2 megapixels have been mainly developed, such light loss from the cover glass is an even bigger problem to a sensor' sensitivity, and also, a sensor chip packaged using a cover glass is expensive because of a high price of cover glass used therefor.
  • the present invention has been proposed in order to overcome the above-described problems in the related art. It is, therefore, an object of the present invention to provide a wafer level chip scale (size) package of an image sensor by means of through hole interconnection and a method for manufacturing the same, in which through hole- interconnected electrodes, through holes filled with metals, are induced to the back side of a wafer substrate. In this structure, a length of wiring can be minimized to decrease a power loss and speed up signal transfer.
  • a wafer level chip scale package of an image sensor by means of through hole interconnection comprising: an image sensor for converting light from outside to electrical signals, the image sensor being located on the front side of a wafer substrate; electrode pads for outputting the electrical signals made in the image sensor, the electrode pads being located on the wafer substrate and extending near or into a dicing street; through hole- interconnected electrodes for transferring the electrical signals outputted from the electrode pads to the back side of the wafer substrate; and bumps on the through hole- interconnected electrodes.
  • a method for manufacturing a wafer level chip package of an image sensor by means of through hole interconnection comprising the steps of: forming an image sensor and electrode pads on a wafer substrate so that the electrode pads extend near or into a dicing street; forming via holes adjacently to the electrode pads; forming an insulating layer on the internal surfaces of the via holes and filling the via holes with conductive material; grinding and etching the back side of the wafer substrate to expose the conductive material of the via holes; forming an insulating layer on the back side of the wafer substrate; and forming bumps on the conductive material.
  • a method for manufacturing a wafer level chip scale package of an image sensor by means of through hole interconnection comprising the steps of: forming an image sensor and electrode pads on an wafer substrate so that the electrode pads extend near or into a dicing street; forming via holes adjacently to the electrode pads; grinding the back side of the wafer substrate till the via holes are exposed to form through holes; forming an insulating layer on the back side of the wafer substrate and on the internal surfaces of the through holes, and filling the through holes with conductive material; and forming bumps on the conductive material.
  • the present invention has advantageous effects in that it does not use a cover glass for protecting an image sensor, and thus reduce a height and a price of a packaged image sensor. [25] Also, the present invention has advantageous effects in that it can minimize a wiring length in a way that an electrode is filled in a via hole which has been formed through a wafer substrate and then the electrode is induced to the back side of the wafer substrate, and according to the minimization of a wiring length, it can block a power loss and speed up signal transfer.
  • the present invention has remarkable advantageous effects in that it can prevent the light loss, which would be generated in the case of using a cover glass, and thus reduce a decrease in an image sensor' sensitivity and image quality, in spite of miniaturization of a high-definition image sensor.
  • FIGS. 1 and 2 are cross-sectional views of image sensors processed for packaging using conventional technologies;
  • FIGs. 3 to 11 illustrate processes for manufacturing a wafer substrate before formation of bumps, in accordance with the present invention;
  • Figs. 12 to 16 show processes for forming solder ball bumps in accordance with a first embodiment of the present invention;
  • Figs. 17 to 25 show processes for forming solder ball bumps in accordance with a second embodiment of the present invention;
  • Figs. 26 to 30 show processes for forming stud bumps in accordance with another embodiment of the present invention.
  • Figs. 3 to 30 illustrate wafer level chip scale packages of an image sensor by means of through hole interconnection and methods for manufacturing the same, in accordance with embodiments of the present invention.
  • a sensor is formed on an epi-layer (not shown) of the upper part of a substrate (140), and on the individual pixels of the sensor, plural electrode pads (120) and plural CMOS image sensors (110) with micro lenses (not shown) of organic materials are formed.
  • the substrate (140) for example, can be a silicon wafer substrate.
  • the electrode pads are extended in the directions to dicing lines. They can be formed to extend near or into a dicing street, a region which will be removed by dicing a substrate along a dicing line. For such extension, the electrode pads can be increased in their lengths. Also, such extension can be made by forming additional electrode pads, which are electrically connected to the original electrode pads of a CMOS image sensor (110), near or into a dicing street. At this time, the electrode pads additionally formed have areas equal to or bigger than those of the original electrode pads.
  • a film (130) is attached to the front side of the wafer substrate (140).
  • the film in accordance with the present invention can be photoresist (PR) or dry film resist (DFR).
  • each of the electrode pads (120) and the wafer substrate have an oxide film (not shown) on their surfaces.
  • the oxide film is partially removed, which is for forming via holes near a dicing street so that they contact the electrode pads.
  • via holes (150) having a diameter of from several or several tens of ⁇ m and a depth within the range of about 100/M to about 300/M.
  • dry etching for forming the via holes (150) can be performed by deep reactive ion etching (deep RIE).
  • Fig. 5b shows a part of the front side of the wafer substrate (140) from which via holes (150) have been formed. From Fig. 5b, it is noted that the electrode pads (120) and the via holes (150) are located adjacently on the front side of the wafer substrate.
  • Fig. 5c shows a part of the front side of the wafer substrate (140) with through hole- interconnected electrodes (171) which will be formed.
  • the oxide film on the surface of each of the electrode pads (120) is etched partially to expose their Al layers.
  • the via holes are formed from the parts of the wafer substrate from which the oxide film has been etched, and thus the via holes (150) are located adjacently to the electrode pads (120). Accordingly, through hole-interconnected electrodes (171) which will be described below can be connected electrically to lateral sides and the front sides of the electrode pads.
  • an insulating layer (160) is formed on the internal surfaces of the via holes (150) using a plasma-enhanced chemical vapor deposition (PECVD) technique, a dry oxidation technique or a wet oxidation technique.
  • PECVD plasma-enhanced chemical vapor deposition
  • the insulating layer can include any one or both of an oxide film and a nitride film, preferably a silicon oxide film and a silicon nitride film.
  • the back side of the substrate can be ground using a process such as chemical mechanical polishing (CMP), etc. till the via holes get exposed to form through holes.
  • CMP chemical mechanical polishing
  • an insulating layer is formed on the back side of the substrate and on the internal surfaces of the through holes.
  • the insulating layer includes any one or both of an oxide film and a nitride film, preferably a silicon oxide film and a silicon nitride film.
  • a metal layer (170) is formed by plating to fill the via holes (150) which have the insulating layer (160) on their surfaces and cover the electrode pads (120). Accordingly, the metal layer is formed in such a way that it can be connected electrically to the electrode pads.
  • the plating can be performed after forming a seed layer of a predetermined thickness on the insulating layer (160) by sputtering, etc.
  • the back side of the wafer substrate (140) is ground until the conductive materials are exposed, as shown in Fig. 8. Upon completion of the grinding, the metals in the via holes (150) make through hole-interconnected electrodes penetrating the wafer substrate (140).
  • the back side of the wafer substrate (140) is selectively etched so that the through hole-interconnected electrodes (171) protrude at a predetermined height from the etched back side of the wafer substrate.
  • the back side of the wafer substrate can be etched to expose the conductive materials by a height of 50/M or less than 50/M from the etched back side of the wafer substrate, and preferably, by a height of 10/M or less than 10/M therefrom.
  • an insulating layer (180) is formed on the back side of the wafer substrate (140) by dry oxidation or wet oxidation.
  • the insulating layer (180) includes any one or both of an oxide film or a nitride film. At this time, it is preferable that the insulating layer (180) has a thickness of the height by which the through hole- interconnected electrodes protrude from the back side of the wafer substrate or less than the height.
  • solder ball bumps can be formed using methods such as the two following processes.
  • Figs. 12 to 16 show processes for forming solder ball bumps in accordance with a first embodiment of the present invention.
  • a photoresist (PR) (210) is coated on the patterned PSR and patterned to expose the through hole-interconnected electrodes (171).
  • the via holes (150) are formed adjacent to the electrode pads (120) on the surface of an image sensor and filled with metal and the via holes filled with metals are used to make through hole-interconnected electrodes which penetrate the wafer substrate to the back side thereof.
  • the present invention enables the wafer to be directly mounted on a rigid printed circuit board (RPCB) or a flexible printed circuit board (FPCB).
  • RPCB rigid printed circuit board
  • FPCB flexible printed circuit board
  • the present invention enables the shortest interconnection of the wafer and a printed circuit board.
  • the present invention can minimize resistance from the interconnection by wire bonding, minimize a power loss and speed up signal transfer.
  • solder pastes (220) are printed on the exposed through hole-interconnected electrode, using a screen printing technique. And then the solder pastes are caused to reflow to have a ball type, as shown in Fig. 14.
  • the PR (210) on the back side of the substrate is removed and the metal layer (170) on the front side of the substrate, which has been plated to fill the via holes, is planarized to expose the film (130). Then, the film (130) is removed.
  • solder pastes are caused to reflow to form ball type bumps and the surfaces of the bumps is cleaned and planarized. This causes removal of impurities and increased contacting surface area, thus leading to the improved conductivity.
  • Figs. 17 to 25 show processes for forming solder ball bumps in accordance with a second embodiment of the present invention.
  • the patterned PSR (190) is hardened by a curing process.
  • the PSR patterning is made for electrical contact between through hole-interconnected electrodes and the redistribution of the solder bump pads extended from the electrodes (171) on the back side of the wafer.
  • via holes (150) are formed adjacent to electrode pads (120) on the surface of an image sensor and filled with metal and the via holes filled with metals are used to make through hole-interconnected electrodes which penetrate the wafer substrate to the back side thereof.
  • the present invention enables the wafer to be directly mounted on a rigid printed circuit board (RPCB) or a flexible printed circuit board (FPCB).
  • RPCB rigid printed circuit board
  • FPCB flexible printed circuit board
  • the present invention enables the shortest interconnection of the wafer and a printed circuit board.
  • the present invention can minimize resistance from the interconnection by wire bonding, minimize a power loss and speed up signal transfer.
  • a barrier layer (200) is deposited on the whole surface of the patterned PSR (190), to form the leads extended from the through hole-interconnected electrodes (171).
  • the barrier layer is a stacked ball limiting metallurgy (BLM) or under bump metallurgy (UBM).
  • BLM stacked ball limiting metallurgy
  • UBM under bump metallurgy
  • a barrier layer (200) is formed between electrode pads (120) of Al or its alloys and solder ball bumps (220) which are to be formed in the following step, and the barrier layer improves adhesion of the through hole-interconnected electrodes (171) and the solder ball bumps (220), preventing diffusion between them.
  • the barrier layer is called a BLM, since such barrier layer has an enormous effect on the shape of solder ball bumps (220).
  • the barrier layer in accordance with the present invention can include Cu/Cr/Cu or
  • Cr/Cu/Au Cr/Cu/Au.
  • a Cr layer shows an excellent adhesion to electrode pads (120) made of Al materials, a Cu layer prevents diffusion of solders of solder ball bunps, and an Au layer blocks oxidation of Cu.
  • the barrier layer (200) is planarized such that the part thereof formed on the PSR (190) is removed.
  • the coated thick photoresist PR
  • the coated thick photoresist PR
  • solder pastes (220) are printed in Fig. 20 and then caused to reflow in Fig. 21.
  • the PR (210) is removed to form solder ball bumps (220) in a ball type, as shown in Fig. 22.
  • the metal layer (170) which has been plated to fill the via holes (150) is planarized till the film (130), which can be a PR or a dry film resist (DFR), is exposed. And then the exposed film (130) is removed.
  • the wafer is diced along a dicing line a— a' to singulate the wafer to the chips.
  • Fig. 25 shows an image sensor processed for wafer level chip scale packaging by means of through hole interconnection is completed.
  • the technology for fabricating the image sensors with such through hole interconnection is named as the "J-connection technology.”
  • a film instead of a cover glass according to conventional technologies, is used for protecting an image sensor.
  • the film which includes a PR or a EFR, is coated on the front side of a wafer substrate, and removed immediately before dicing of the wafer. Accordingly, the present invention can prevent the light loss which would be generated in the case of using a cover glass, thereby blocking a decrease in an image sensor' sensitivity and image quality.
  • the present invention in which no cover glass is used and the back side of a wafer substrate is ground, it is possible to produce a packaged image sensor of which whole thickness is only about 100/M to 300/M and use the packaged image sensor to fabricate a microminiaturized camera module of which height is the smallest and cross x width is in a chip scale.
  • Figs. 26 to 30 show processes for forming stud bumps in accordance with another embodiment of the present invention.
  • the wafer substrate processed using the steps described above referring to Figs. 3 through 7 is ground from its back side until the metal is exposed to form through hole-interconnected electrodes. Upon completion of grinding, only the substrate is selectively ground.
  • the back side of the substrate can be etched such that the through hole-interconnected electrodes protrude by a height of 50/M or less than 50/M from the back side of the substrate, and more preferably, by a height of about 10/M to about 30/M. And then, an insulating layer (180) is formed.
  • a photosensitive resist (PSR) (190) is coated and patterned to expose the through hole (171).
  • stud bumps (240) are formed on the through hole-interconnected electrodes using a plating technique, as shown in Fig. 28.
  • the stud ball bumps (240) can include Cu/Sn/Au, and the stud bumps (240) have a height which makes the stud bumps higher than the PSR (190).
  • the metal layer (170) on the front side of the substrate is planarized and then the film (130) is removed. After that, the substrate is diced along a dicing line a— a' to form the individual image sensor chips, as shown in Fig. 30.

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Abstract

The present invention relates to a wafer level chip scale package of an image sensor by means of through hole interconnection and a method for manufacturing the same, in which through hole-interconnected electrodes, through holes filled with metals, are induced to the back side of a wafer substrate. In this structure, a length of wiring can be minimized to decrease a power loss and speed up signal transfer. A wafer level chip scale package of an image sensor by means of through hole interconnection in accordance with one embodiment of the present invention comprises: an image sensor for converting light from outside to an electrical signal, the image sensor being located on the front side of a wafer substrate; the electrode pads for outputting the electrical signal made in the image sensor, the electrode pads being located on the wafer substrate and extending near or into a dicing street; a through hole-interconnected electrode for transferring the electrical signal outputted from the electrode pads to the back side of the wafer substrate; and bumps on the through hole interconnected electrode. We call the technology in the present invention as 'J-connection technology'.

Description

Description
WAFER LEVEL CHIP SCALE PACKAGE OF AN IMAGE SENSOR BY MEANS OF THROUGH HOLE INTERCONNECTION AND METHOD FOR MANUFACTURING THE SAME Technical Field
[1] The present invention relates to an image sensor and a method for manufacturing the same and, more particularly, to a wafer level chip scale package of an image sensor for a camera module, which is used for portable appliances such as a cellular phone, a mobile communication terminal, etc., and a method for manufacturing the same.
[2]
Background Art
[3] Generally, an image sensor is a semiconductor module for converting an optical image to an electric signal and used to store an image signal and transfer it to a display device. Image sensors are roughly classified into two classes, i.e., one is a charge- coupled device (CCD) and the other is a complementary metal oxide semiconductor (CMOS). The CCD image sensor transfers an electric charge by continually controlling a depth of a potential well in the direction of the charge transfer. The CMOS image sensor performs an image sensing by using one or more transistor and a photo diode included in a pixel unit cell, wherein the photo diode acts as a photo sensor.
[4] The image sensors such as CCD image sensors and CMOS image sensors have been widely used for cameras of cellular phones or personal digital assistances (PDAs), etc. Recently, portable devices such as cellular phones are required to be made smaller and thinner so that they can be carried conveniently. Accordingly, camera modules for use in such cellular phones need to have a height and a length x width size as small as possible, and if possible, in a sensor chip size.
[5] An image sensor chip is bonded to the upper part of a printed circuit board (PCB) in the last process for packaging, and the packaged image sensor is assembled in a camera.
[6] Modularization of an image sensor can not be easily performed using general methods, since an image-sensing window and electrode pads for input/output signals from the image-sensing window are formed on a same plane. Thus, it is required to modularize a camera on a PCB through the methods such as die bonding, wire bonding, etc. In this regard, a camera module packaged using the conventional processes has an increased height and size, and thus it is difficult to make a portable device with a built-in camera module, in the recent trend of smaller and thinner portable devices.
[7] A wafer level chip scale package (WL-CSP) method has been developed as one modularization method for solving such size problems.
[8] In a WL-CSP method, a sensor chip is bonded with a flexible printed circuit board
(FPCB) or a rigid printed circuit board (RPCB) using an anisotropic conductive film (ACF). According to the WL-CSP method, bumps are located on the electrode pads formed on a sensor chip at a wafer level, and then, an ACF and a PCB are processed to have holes of the size corresponding to the sensing units which have been formed on the sensor chip. Then, the sensor chip, the ACF and the PCB are placed in layers and bonded with heat and pressure to form a camera module.
[9] But, in case of bonding methods using an ACF, fine wiring in the limited side land of the window is required when a PCB is produced since the PCB is to be bonded on bump pads formed on a sensor using an ACF. In addition, the debris made in the time of making a hole to form a window on a PCB remain and mitigate assembly yield of modules. Besides, bonding methods using an ACF have other disadvantages.
[10] Especially, the processes of forming a window on an ACF and pre-bonding of an image sensor and a PCB using the window can not be automated easily and the processes are performed manually, which results in a decrease in a production yield.
[11] Fig. 1 is a cross-sectional view of an image sensor processed for packaging using a conventional technology.
[12] For solving the problems of wire bonding, Shellcase, an Israeli corporation, has developed a technology. According to the technology of Shellcase, epoxy (13) is used to attach a first cover glass (14) to the front side of a silicon wafer (11) on which electrode pads (19) and a sensing unit (12) have been formed. Next, the back side of the silicon wafer (11) is ground to remove a predetermined depth of the back side and etched to expose the electrode pads (19). When the electrode pads (19) are exposed, a second cover glass (15) is attached and etched to expose the electrode pads (19). After that, copper is sputtered so that the electrode pads (19) can be connected electrically to the back side of the silicon wafer.
[13] Next, after a photolithographic method is used to form external electrodes over the whole surface of the copper film from the electrode pads to the back side of the silicon wafer, an insulating layer (17) is made. The insulating layer (17) is selectively etched to expose the external electrodes, and then solder ball bunps (16) are formed. And a packaged image sensor is completed by dicing the silicon wafer along a dicing line (18). Such processes for packaging image sensors have disadvantages in that a photolithographic method is difficult to be used to form electrode pads on the back side of a silicon wafer due to copper sputtered to the inclined plane formed by etching. And also, a price increase from use of expensive glass substrates is one of the disadvantages of the processes.
[14] Fig. 2 is a cross-sectional view of an image sensor processed for packaging using another conventional technology.
[15] Referring to Fig. 2, a silicon wafer (21) is formed to have electrode pads (22) and image sensors (23) on its surface, and a cover glass (24) is attached to the front side of the silicon wafer. The back side of the silicon wafer (21) is ground to a predetermined depth, and then the silicon wafer corresponding to the underneath of the electrode pads on the front side is selectively etched from the back side using a deep reactive ion etching method, until the electrode pads (22) on the front side of the silicon wafer (21) are exposed. In this way, via holes (27) are formed. The via holes (27) are filled with metal using electroplating or electroless plating, and on the via holes filled with metal are solder ball bumps (25) formed. After that, the silicon wafer is diced along a dicing line (26) to complete a packaged image sensor. In this case, however, it is difficult to form via holes (27) at the specific positions of back side of the silicon wafer (21) so that they are located under the corresponding electrode pads (22).
[16] In addition, the conventional techniques described above incorporate attachment of a cover glass for protection of a sensor and simple processes. In the conventional techniques, a cover glass reflects or absorbs a part of the light entering a sensor from the outside, which results in a light loss and accordingly, a decrease in a sensor' sensitivity. Moreover, since a size of pixel is recently getting miniaturized and high- definition CMOS image sensors with over 2 megapixels have been mainly developed, such light loss from the cover glass is an even bigger problem to a sensor' sensitivity, and also, a sensor chip packaged using a cover glass is expensive because of a high price of cover glass used therefor.
[17]
Disclosure of Invention Technical Problem [18] The present invention has been proposed in order to overcome the above-described problems in the related art. It is, therefore, an object of the present invention to provide a wafer level chip scale (size) package of an image sensor by means of through hole interconnection and a method for manufacturing the same, in which through hole- interconnected electrodes, through holes filled with metals, are induced to the back side of a wafer substrate. In this structure, a length of wiring can be minimized to decrease a power loss and speed up signal transfer.
[19]
Technical Solution
[20] In accordance with one aspect of the present invention, there is provided a wafer level chip scale package of an image sensor by means of through hole interconnection, comprising: an image sensor for converting light from outside to electrical signals, the image sensor being located on the front side of a wafer substrate; electrode pads for outputting the electrical signals made in the image sensor, the electrode pads being located on the wafer substrate and extending near or into a dicing street; through hole- interconnected electrodes for transferring the electrical signals outputted from the electrode pads to the back side of the wafer substrate; and bumps on the through hole- interconnected electrodes.
[21] In accordance with another aspect of the present invention, there is provided a method for manufacturing a wafer level chip package of an image sensor by means of through hole interconnection, the method comprising the steps of: forming an image sensor and electrode pads on a wafer substrate so that the electrode pads extend near or into a dicing street; forming via holes adjacently to the electrode pads; forming an insulating layer on the internal surfaces of the via holes and filling the via holes with conductive material; grinding and etching the back side of the wafer substrate to expose the conductive material of the via holes; forming an insulating layer on the back side of the wafer substrate; and forming bumps on the conductive material.
[22] In accordance with another aspect of the present invention, there is provided a method for manufacturing a wafer level chip scale package of an image sensor by means of through hole interconnection, the method comprising the steps of: forming an image sensor and electrode pads on an wafer substrate so that the electrode pads extend near or into a dicing street; forming via holes adjacently to the electrode pads; grinding the back side of the wafer substrate till the via holes are exposed to form through holes; forming an insulating layer on the back side of the wafer substrate and on the internal surfaces of the through holes, and filling the through holes with conductive material; and forming bumps on the conductive material. [23]
Advantageous Effects
[24] The present invention has advantageous effects in that it does not use a cover glass for protecting an image sensor, and thus reduce a height and a price of a packaged image sensor. [25] Also, the present invention has advantageous effects in that it can minimize a wiring length in a way that an electrode is filled in a via hole which has been formed through a wafer substrate and then the electrode is induced to the back side of the wafer substrate, and according to the minimization of a wiring length, it can block a power loss and speed up signal transfer. [26] Especially, the present invention has remarkable advantageous effects in that it can prevent the light loss, which would be generated in the case of using a cover glass, and thus reduce a decrease in an image sensor' sensitivity and image quality, in spite of miniaturization of a high-definition image sensor. [27]
Brief Description of the Drawings [28] Figs. 1 and 2 are cross-sectional views of image sensors processed for packaging using conventional technologies; [29] Figs. 3 to 11 illustrate processes for manufacturing a wafer substrate before formation of bumps, in accordance with the present invention; [30] Figs. 12 to 16 show processes for forming solder ball bumps in accordance with a first embodiment of the present invention; [31] Figs. 17 to 25 show processes for forming solder ball bumps in accordance with a second embodiment of the present invention; and [32] Figs. 26 to 30 show processes for forming stud bumps in accordance with another embodiment of the present invention. [33]
[34] <Description on main reference numerals >
[35] 110: image sensor 120: electrode pad
[36] 130: film 140: wafer substrate
[37] 150: via hole 160, 180: insulating layer
[38] 170: metal layer 190: photosensitive resist (PSR)
[39] 200: barrier layer 220: solder paste [40]
Mode for the Invention
[41] The terms and words used in the specification and the claims should not be limitedly construed with ordinary or lexical meaning. Rather, they should be construed with the meaning and the conceptions according to the idea of the present invention, abiding by the principle that an inventor can properly define the conception of terms so as to describe his or her own invention with the best manner.
[42] While the present invention has been described with reference to particular illustrative embodiments, it is not to be restricted by the embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing form the scope and the spirit of the present invention. Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[43] Figs. 3 to 30 illustrate wafer level chip scale packages of an image sensor by means of through hole interconnection and methods for manufacturing the same, in accordance with embodiments of the present invention.
[44] Referring to Figs 3 and 4, a sensor is formed on an epi-layer (not shown) of the upper part of a substrate (140), and on the individual pixels of the sensor, plural electrode pads (120) and plural CMOS image sensors (110) with micro lenses (not shown) of organic materials are formed. The substrate (140), for example, can be a silicon wafer substrate.
[45] According to one embodiment of the present invention, the electrode pads are extended in the directions to dicing lines. They can be formed to extend near or into a dicing street, a region which will be removed by dicing a substrate along a dicing line. For such extension, the electrode pads can be increased in their lengths. Also, such extension can be made by forming additional electrode pads, which are electrically connected to the original electrode pads of a CMOS image sensor (110), near or into a dicing street. At this time, the electrode pads additionally formed have areas equal to or bigger than those of the original electrode pads.
[46] First, as shown in Fig.3, a film (130) is attached to the front side of the wafer substrate (140). The film in accordance with the present invention can be photoresist (PR) or dry film resist (DFR).
[47] After the film (130) is attached to the front side of the wafer substrate (140), light is illuminated onto the film through a mask (not shown) with formed patterns and then the film is developed. In this way, the patterns are formed to expose a part of each of the electrode pads (120) and a part of the wafer substrate, as shown in Fig. 4. The region in a dotted square, "Dicing street" represents the part to be removed by dicing.
[48] The exposed parts of each of the electrode pads (120) and the wafer substrate have an oxide film (not shown) on their surfaces. The oxide film is partially removed, which is for forming via holes near a dicing street so that they contact the electrode pads.
[49] Next, as shown in Fig 5a, the exposed parts of the front side of the wafer substrate
(140) located adjacently to the electrode pads (120) are wet etched or dry etched to form via holes (150) having a diameter of from several or several tens of μm and a depth within the range of about 100/M to about 300/M.
[50] In accordance with an embodiment of the present invention, dry etching for forming the via holes (150) can be performed by deep reactive ion etching (deep RIE).
[51] At the time of the etching, only the wafer substrate can be selectively etched because an aluminum (Al) layer exposed on the surfaces of the electrode pads (120) protects the electrode pads from deep RIE.
[52] Fig. 5b shows a part of the front side of the wafer substrate (140) from which via holes (150) have been formed. From Fig. 5b, it is noted that the electrode pads (120) and the via holes (150) are located adjacently on the front side of the wafer substrate.
[53] Fig. 5c shows a part of the front side of the wafer substrate (140) with through hole- interconnected electrodes (171) which will be formed. Referring to Fig. 5c, in addition to the oxide film on the wafer substrate, the oxide film on the surface of each of the electrode pads (120) is etched partially to expose their Al layers. And the via holes are formed from the parts of the wafer substrate from which the oxide film has been etched, and thus the via holes (150) are located adjacently to the electrode pads (120). Accordingly, through hole-interconnected electrodes (171) which will be described below can be connected electrically to lateral sides and the front sides of the electrode pads.
[54] Referring to Fig. 6, an insulating layer (160) is formed on the internal surfaces of the via holes (150) using a plasma-enhanced chemical vapor deposition (PECVD) technique, a dry oxidation technique or a wet oxidation technique. The insulating layer can include any one or both of an oxide film and a nitride film, preferably a silicon oxide film and a silicon nitride film.
[55] According to another embodiment of the present invention, after the via holes (150) being formed, the back side of the substrate can be ground using a process such as chemical mechanical polishing (CMP), etc. till the via holes get exposed to form through holes. After that, an insulating layer is formed on the back side of the substrate and on the internal surfaces of the through holes. The insulating layer includes any one or both of an oxide film and a nitride film, preferably a silicon oxide film and a silicon nitride film.
[56] Referring to Fig. 7, a metal layer (170) is formed by plating to fill the via holes (150) which have the insulating layer (160) on their surfaces and cover the electrode pads (120). Accordingly, the metal layer is formed in such a way that it can be connected electrically to the electrode pads.
[57] In accordance with the embodiments of the present invention, if the metal layer (170) is plated over the front sides of the electrode pads (120) in a stacked form, a contact resistance of the electrode pads (120) and the metal layer (170) formed by plating can be reduced, because the electrically contacting area thereof is increased.
[58] It is preferable to use a metal with an excellent conductivity such as gold, copper, etc. for the metal layer (170) in accordance with the present invention. Meanwhile, the plating can be performed after forming a seed layer of a predetermined thickness on the insulating layer (160) by sputtering, etc.
[59] After the via holes (150) are filled with conductive materials, the back side of the wafer substrate (140) is ground until the conductive materials are exposed, as shown in Fig. 8. Upon completion of the grinding, the metals in the via holes (150) make through hole-interconnected electrodes penetrating the wafer substrate (140).
[60] Next, referring to Fig. 9, the back side of the wafer substrate (140) is selectively etched so that the through hole-interconnected electrodes (171) protrude at a predetermined height from the etched back side of the wafer substrate. In accordance with the present invention, the back side of the wafer substrate can be etched to expose the conductive materials by a height of 50/M or less than 50/M from the etched back side of the wafer substrate, and preferably, by a height of 10/M or less than 10/M therefrom.
[61] After that, referring to Fig. 10, an insulating layer (180) is formed on the back side of the wafer substrate (140) by dry oxidation or wet oxidation. The insulating layer (180) includes any one or both of an oxide film or a nitride film. At this time, it is preferable that the insulating layer (180) has a thickness of the height by which the through hole- interconnected electrodes protrude from the back side of the wafer substrate or less than the height.
[62] Referring to Fig. 11, after the insulating layer (180) is formed, a photosensitive resist
(PSR) (190) is coated and then patterned to expose the through hole-interconnected electrodes (171). After that, bumps are formed on the through hole-interconnected electrodes (171). The bumps in accordance with the present invention can be solder ball bumps or stud bumps. Solder ball bumps can be formed using methods such as the two following processes.
[63] Figs. 12 to 16 show processes for forming solder ball bumps in accordance with a first embodiment of the present invention.
[64] Referring to Fig. 12, a photoresist (PR) (210) is coated on the patterned PSR and patterned to expose the through hole-interconnected electrodes (171).
[65] As described above, in the present invention, the via holes (150) are formed adjacent to the electrode pads (120) on the surface of an image sensor and filled with metal and the via holes filled with metals are used to make through hole-interconnected electrodes which penetrate the wafer substrate to the back side thereof. So, the present invention enables the wafer to be directly mounted on a rigid printed circuit board (RPCB) or a flexible printed circuit board (FPCB). In other words, the present invention enables the shortest interconnection of the wafer and a printed circuit board. In addition, due to the direct interconnection, the present invention can minimize resistance from the interconnection by wire bonding, minimize a power loss and speed up signal transfer.
[66] Referring to Fig. 13, to form the solder ball bumps, solder pastes (220) are printed on the exposed through hole-interconnected electrode, using a screen printing technique. And then the solder pastes are caused to reflow to have a ball type, as shown in Fig. 14. Referring to Fig. 15, the PR (210) on the back side of the substrate is removed and the metal layer (170) on the front side of the substrate, which has been plated to fill the via holes, is planarized to expose the film (130). Then, the film (130) is removed.
[67] In accordance with the embodiment of the present invention, solder pastes are caused to reflow to form ball type bumps and the surfaces of the bumps is cleaned and planarized. This causes removal of impurities and increased contacting surface area, thus leading to the improved conductivity.
[68] Referring to Fig. 16, after the film (130) is removed, the wafer is singulated to the individual chips by dicing the wafer along a dicing line a — a' Now, an image sensor processed for wafer level chip scale packaging by means of through hole interconnection is completed.
[69] Figs. 17 to 25 show processes for forming solder ball bumps in accordance with a second embodiment of the present invention.
[70] The patterned PSR (190) is hardened by a curing process. The PSR patterning is made for electrical contact between through hole-interconnected electrodes and the redistribution of the solder bump pads extended from the electrodes (171) on the back side of the wafer.
[71] As described above, in the present invention, via holes (150) are formed adjacent to electrode pads (120) on the surface of an image sensor and filled with metal and the via holes filled with metals are used to make through hole-interconnected electrodes which penetrate the wafer substrate to the back side thereof. So, the present invention enables the wafer to be directly mounted on a rigid printed circuit board (RPCB) or a flexible printed circuit board (FPCB). In other words, the present invention enables the shortest interconnection of the wafer and a printed circuit board. In addition, due to the direct interconnection, the present invention can minimize resistance from the interconnection by wire bonding, minimize a power loss and speed up signal transfer.
[72] Referring to Fig. 17, a barrier layer (200) is deposited on the whole surface of the patterned PSR (190), to form the leads extended from the through hole-interconnected electrodes (171). The barrier layer is a stacked ball limiting metallurgy (BLM) or under bump metallurgy (UBM). In large scale integrated circuits, a barrier layer (200) is formed between electrode pads (120) of Al or its alloys and solder ball bumps (220) which are to be formed in the following step, and the barrier layer improves adhesion of the through hole-interconnected electrodes (171) and the solder ball bumps (220), preventing diffusion between them. Especially, the barrier layer is called a BLM, since such barrier layer has an enormous effect on the shape of solder ball bumps (220).
[73] The barrier layer in accordance with the present invention can include Cu/Cr/Cu or
Cr/Cu/Au. In the case of Cr/Cu/Au, a Cr layer shows an excellent adhesion to electrode pads (120) made of Al materials, a Cu layer prevents diffusion of solders of solder ball bunps, and an Au layer blocks oxidation of Cu.
[74] Referring to Fig. 18, after the barrier layer (200) is deposited, the barrier layer (200) is planarized such that the part thereof formed on the PSR (190) is removed.
[75] Referring to Fig. 19, the coated thick photoresist (PR) is patterned to expose the deposited barrier layer. Referring to Figs. 20 and 21, solder pastes (220) are printed in Fig. 20 and then caused to reflow in Fig. 21. After that, the PR (210) is removed to form solder ball bumps (220) in a ball type, as shown in Fig. 22.
[76] Next, referring to Fig. 23, the metal layer (170) which has been plated to fill the via holes (150) is planarized till the film (130), which can be a PR or a dry film resist (DFR), is exposed. And then the exposed film (130) is removed. Referring to Fig. 24, the wafer is diced along a dicing line a— a' to singulate the wafer to the chips. Fig. 25 shows an image sensor processed for wafer level chip scale packaging by means of through hole interconnection is completed. The technology for fabricating the image sensors with such through hole interconnection is named as the "J-connection technology."
[77] In accordance with the present invention, a film, instead of a cover glass according to conventional technologies, is used for protecting an image sensor. The film, which includes a PR or a EFR, is coated on the front side of a wafer substrate, and removed immediately before dicing of the wafer. Accordingly, the present invention can prevent the light loss which would be generated in the case of using a cover glass, thereby blocking a decrease in an image sensor' sensitivity and image quality. Especially, according to the present invention, in which no cover glass is used and the back side of a wafer substrate is ground, it is possible to produce a packaged image sensor of which whole thickness is only about 100/M to 300/M and use the packaged image sensor to fabricate a microminiaturized camera module of which height is the smallest and cross x width is in a chip scale.
[78] Figs. 26 to 30 show processes for forming stud bumps in accordance with another embodiment of the present invention.
[79] Referring to Fig. 26, the wafer substrate processed using the steps described above referring to Figs. 3 through 7 is ground from its back side until the metal is exposed to form through hole-interconnected electrodes. Upon completion of grinding, only the substrate is selectively ground. In accordance with the present invention, the back side of the substrate can be etched such that the through hole-interconnected electrodes protrude by a height of 50/M or less than 50/M from the back side of the substrate, and more preferably, by a height of about 10/M to about 30/M. And then, an insulating layer (180) is formed.
[80] Next, referring to Fig. 27, a photosensitive resist (PSR) (190) is coated and patterned to expose the through hole (171). And then, stud bumps (240) are formed on the through hole-interconnected electrodes using a plating technique, as shown in Fig. 28. At this time, the stud ball bumps (240) can include Cu/Sn/Au, and the stud bumps (240) have a height which makes the stud bumps higher than the PSR (190).
[81] Referring to Fig. 29, after the stud bumps (240) are formed, the metal layer (170) on the front side of the substrate is planarized and then the film (130) is removed. After that, the substrate is diced along a dicing line a— a' to form the individual image sensor chips, as shown in Fig. 30.
[82] While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.

Claims

Claims
[1] A wafer level chip scale package of an image sensor by means of through hole interconnection, comprising: an image sensor for converting light from outside to electrical signals, the image sensor being located on the front side of a wafer substrate; electrode pads for outputting the electrical signals made in the image sensor, the electrode pads being located on the wafer substrate and extending near or into a dicing street; through hole-interconnected electrodes for transferring the electrical signals outputted from the electrode pads to the back side of the wafer substrate; and bumps on the through hole-interconnected electrodes. [2] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 1, wherein the through hole-interconnected electrode is formed by etching a part of the front side of the wafer substrate to form a via hole and filling the via hole with conductive material, the part of the front side of the wafer substrate being adjacent to the electrode pad. [3] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 2, the conductive material formed in the via hole is extended to partially or entirely cover a lateral side or the front side of the electrode pad adjacent to the via hole. [4] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 3, an oxide film is formed on the internal surface of the via hole. [5] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 2, wherein the via hole is filled with the conductive material by a plating process. [6] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 2, wherein the via hole has a depth ranging from about
100/M to about 300/M. [7] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 1, wherein the bump is a solder ball bump or a stud bump. [8] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 1, further comprising a barrier layer for improving adhesion of the through hole-interconnected electrode to the bump and preventing diffusion therebetween. [9] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 8, wherein the barrier layer includes ball limiting metallurgy (BLM) or under bunp metallurgy (UBM). [10] The wafer level chip scale package of an image sensor by means of through hole interconnection of claim 8, wherein the barrier layer uses any one of Cu/Cr/Cu and Cr/Cu/Au. [11] A method for manufacturing a wafer level chip package of an image sensor by means of through hole interconnection, the method comprising the steps of: forming an image sensor and electrode pads on a wafer substrate so that the electrode pads extend near or into a dicing street; forming via holes adjacently to the electrode pads; forming an insulating layer on the internal surfaces of the via holes and filling the via holes with conductive material; grinding and etching the back side of the wafer substrate to expose the conductive material of the via holes; forming an insulating layer on the back side of the wafer substrate; and forming bumps on the conductive material. [12] A method for manufacturing a wafer level chip scale package of an image sensor by means of through hole interconnection, the method comprising the steps of: forming an image sensor and electrode pads on a wafer substrate so that the electrode pads extend near or into a dicing street; forming via holes adjacently to the electrode pads; grinding the back side of the wafer substrate till the via holes are exposed to form through holes; forming an insulating layer on the back side of the wafer substrate and on the internal surfaces of the through holes, and filling the through holes with conductive material; and forming bumps on the conductive material. [13] The method of claim 11, wherein the etching of the back side of the wafer substrate is performed to expose the conductive material by a height of 50/M or less than 50/M from the etched back side of the wafer substrate. [14] The method of claim 11 or claim 12, wherein the step of forming via holes adjacently to the electrode pads comprises: forming a film on the front side of the wafer substrate on which the image sensor and the electrode pads have been formed; patterning the film to expose a part of each of the electrode pads and a part of the wafer substrate; and etching the part of the wafer substrate adjacent to the electrode pads. [15] The method of claim 14, wherein the film is a photoresist (PR) or a dry film resist (DFR). [16] The method of claim 11 or claim 12, wherein the step of forming bumps on the conductive material comprises the steps of: patterning a photosensitive resist (PSR) formed on the back side of the wafer substrate to expose the conductive material; patterning a photoresist (PR) formed on the whole surface of the PSR to expose the conductive material; coating solder pastes on the conductive material; applying a reflow process to the solder pastes to form solder ball bumps; cleaning the solder ball bumps; and planarizing the surfaces of the solder ball bumps. [17] The method of claim 11 or claim 12, wherein the step of forming bumps on the conductive material comprises the steps of: patterning a photosensitive resist (PSR) formed on the back side of the wafer substrate; depositing a barrier layer on the whole surface of the PSR; planarizing the barrier layer to expose the PSR; patterning a formed photoresist (PR) to expose the barrier layer; coating solder pastes on the barrier layer; and applying a reflow process to the solder pastes. [18] The method of claim 11 or claim 12, wherein the step of forming bumps on the conductive material comprises the steps of: patterning a photosensitive resist (PSR) formed on the back side of the wafer substrate to expose the conductive material; patterning a photoresist (PR) formed on the whole surface of the PSR to expose the conductive material; and forming stud bumps on the conductive material. [19] The method of claim 18, wherein the stud bump is formed by placing any one or more than one of Cu, Sn and Au in layers. [20] The method of claim 11 or claim 12, wherein the via hole has a depth within the range of about lOOμm to about 300/M.
PCT/KR2008/002837 2007-05-21 2008-05-21 Wafer level chip scale package of an image sensor by means of through hole interconnection and method for manufacturing the same WO2008143461A2 (en)

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