TWI442535B - Electronics device package and fabrication method thereof - Google Patents

Description

Electronic component package and manufacturing method thereof

The present invention relates to an electronic component package, and more particularly to an electronic component package fabricated using a wafer scale package (WSP) process and a method of fabricating the same.

The photo-sensing integrated circuit plays an important role in capturing optical sensing elements. These integrated circuit components have been widely used, for example, in digital cameras (DCs) and digital video cameras (digital cameras). In consumer electronics and portable electronic components such as recorders and cell phones.

Figure 1 shows a cross-sectional view of a conventional image sensor package 1. In Fig. 1, a substrate 2 is formed with a photosensitive member 4 and a bonding pad 6 thereon, and a cover 8 is disposed above the substrate 2. As shown in FIG. 1 , a carrier board 9 is attached to the substrate 2 , and a solder ball 12 is disposed on the back surface of the carrier board 9 , and the bonding pad 6 is electrically connected by a conductive layer 10 . The photosensitive element 4 can sense light passing through the cover 8 through its front surface to generate a signal, and the conductive layer 10 transmits the signal to the solder ball 12 and an external circuit.

An embodiment of the present invention provides an electronic component package. The electronic component package includes: a semiconductor wafer having a first The substrate, a support block spaced apart from the first substrate by a predetermined distance, and a bonding pad having a surface spanning the first substrate and the support block. In another embodiment, the first substrate has a first surface and an opposite second surface, wherein the second surface serves as a light receiving surface, and the first surface serves as a backlight surface and includes a photosensitive element region. . The electronic component package may further include: a second substrate bonded to the backlight surface of the first substrate; a first encapsulation layer covering the light receiving surface of the first substrate; and a second encapsulation layer covering the second substrate a wire layer formed on the second encapsulation layer and extending to the side of the bonding pad and the support block to electrically connect the bonding pad; and a conductive bump disposed on the second encapsulation layer and electrically The above wire layers are connected sexually.

In the above electronic component package, since there is an insulating layer between the support block and the first substrate, the support block and the first substrate are isolated, and the bonding pad may straddle the insulating layer. Therefore, the wire layer formed on the side of the support block does not affect the photosensitive member. Furthermore, since the above electronic component has a support block, it can increase the structural strength (structural strength of the T contact) between the wire layer and the bonding pad. Thereby, the structural strength of the entire electronic component package can be enhanced.

Another embodiment of the present invention provides a method of fabricating an electronic component package. The manufacturing method of the electronic component package includes: providing a wafer having a substrate including a plurality of die regions to carry or form a plurality of semiconductor wafers, and a plurality of bonding pads are formed on the substrate, and Performing a wafer level packaging process on the substrate includes: patterning the substrate to isolate a support block in each of the die regions, such that the support block and the substrate Separate the distance and expose the bond pads. The above manufacturing method further comprises forming a pattern opening in the substrate by the patterning step to expose the bonding pad.

In the above manufacturing method, the semiconductor wafer includes a photovoltaic element, and the wafer level packaging process further includes: the substrate is a first substrate having a first surface and an opposite second surface, wherein the first surface serves as a backlight a second surface as a light emitting surface or a light receiving surface; a first encapsulating layer disposed to cover the light emitting surface or the light receiving surface of the first substrate; bonding the backlight surface of the first substrate to a second substrate; The second substrate is separated by a position of a predetermined scribe line of the two grain sections to form a plurality of carrier plates corresponding to the die regions.

In the above manufacturing method, the wafer level packaging process further includes: forming an insulating layer to cover at least the side surface of the carrier plate; and providing a second encapsulation layer to cover the second substrate and the insulating layer; Positioning the predetermined scribe line of the grain interval to form a channel recess and exposing the surface of the first encapsulation layer; forming a wire layer on the second encapsulation layer, and extending along the channel notch to the bonding pad and the support On the side of the block, the bonding pad is electrically connected; a conductive bump is disposed on the second encapsulation layer, and the wire layer is electrically connected; and the first encapsulation layer is separated along the predetermined dicing street.

In the above method of fabricating the electronic component package, since the pattern opening can simultaneously isolate the photovoltaic element and provide the opening for detecting the photovoltaic element, the step of additionally isolating or making the opening is not required, so that the manufacturing process can be shortened and simplified.

The concept and the specific implementation of the present invention will be described in detail by way of the embodiments. In the drawings or the description, elements that are the same or the same parts are given the same symbols. Moreover, in the drawings, the shape or thickness of the elements of the embodiments may be expanded to simplify or facilitate the marking. It will be appreciated that elements not shown or described may be in a variety of forms known to those skilled in the art.

The present invention is described with respect to an embodiment in which an image sensor package, such as a back side illumination (BSI) sensing element, is fabricated. However, it can be understood that in the package embodiment of the present invention, it can be applied to various integrated circuits including active or passive elements, digital circuits or analog circuits. Electronic components, for example, related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or physical quantities such as heat, light, and pressure. Change to measure the physical sensor (Physical Sensor). In particular, wafer scale package (WSP) processes can be used for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Accelerators, gyroscopes, micro actuators, surface acoustic waves Semiconductor wafers such as devices), ink sensors, or ink printer heads are packaged.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to an electronic component package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices.

2-11 are schematic views showing the fabrication of an image sensing device package in accordance with an embodiment of the present invention. Figure 12 is a flow chart showing the fabrication of an image sensing device package in accordance with an embodiment of the present invention.

As shown in FIG. 2, a wafer or a wafer substrate is provided, which includes a first substrate 100 on which photosensitive elements 102 are formed, and the first substrate 100 is here. A plurality of bonding pads 104 are formed on the upper side. The photosensitive element 102 is electrically connected to the bonding pad 104, thereby transmitting a signal to a terminal contact (not shown). Next, a passivation layer 110 is formed on the first substrate 100 and covers the bonding pad 104 and the photosensitive element 102.

In FIG. 2, the first substrate 100 may be divided into a plurality of photosensitive regions 106 and non-photo-sensitive regions 108. The photosensitive element region 106 Refers to the area where the photosensitive element 102 is formed, and the non-photosensitive element area 108 refers to the area where the photosensitive element 102 is not formed (or the position of the two photosensitive element sections), and the non-sensitive element area 108 may also be referred to as a predetermined scribe line. (predetermined scribe line), used to define the position of the subsequent individual crystal grains to be cut. Further, the above-described non-photosensitive element region 108 surrounds the photosensitive element region 106. In addition, the above-described photosensitive element region 106 may also be referred to as a grain region.

In an embodiment, the first substrate 100 may be a germanium or other suitable semiconductor substrate. The photosensitive element 102 may be a complementary metal oxide semiconductor (CMOS) or charge-couple device (CCD) for sensing or capturing an image or image. In addition, the bonding pad 104 may also be referred to as an extension pad or a conductive pad, and may preferably be copper (copper), aluminum (Al) or other suitable metal material.

As shown in FIG. 3, a second substrate 112, such as a germanium or other suitable semiconductor substrate, is provided. Next, the first substrate 100 is flipped over and bonded to the surface of the second substrate 112 such that the photosensitive element 102 It may be between the first and second substrates 100 and 112. Thereafter, the first substrate 100 is thinned from the back surface of the first substrate 100 to a suitable thickness by, for example, etching, milling, grinding, or polishing. The above-described photosensitive element 102 can sense light incident through the back surface of the first substrate 100. That is, the first substrate 100 is thinned to a thickness that allows sufficient light to pass through, so that the light-emitting element 102 can sense the incident light, thereby generating a signal. according to Therefore, the thickness of the first substrate 100 after the polishing is sufficient as long as it allows sufficient light to pass through and the photosensitive element 102 generates a signal, which is not limited herein.

The front surface of the first substrate 100 refers to the surface on which the bonding pad 104 or the photosensitive element 102 is formed, which may be referred to as a light back surface, and the opposite surface (the back surface of the first substrate 100) may also be referred to as It is a light incident surface. It is worth mentioning that in another embodiment of the photovoltaic element such as a light-emitting diode, the back surface of the first substrate 100 may also be referred to as a light-emitting surface.

Figure 4 shows a partial top view of the first substrate 100 after a patterning step. As shown in FIG. 4, after the thinning step is completed, the first substrate 100 is patterned by a photolithography/etching process to form a patterned opening 114 on the first substrate 100. In order to expose a portion of the bonding pad 104 described above. Moreover, the first substrate 100 in the photosensitive element region 106 and the first substrate 100 in the non-photosensitive element region 108 can be isolated by the pattern opening 114 at the same time, which is hereinafter referred to as the isolated first substrate 101. In addition, after the patterning step, the first substrate 100 or the wafer is isolated from a plurality of semiconductor crystals A.

In FIG. 4, the pattern opening 114 may include a first opening 114a, a second opening 114b, and a groove 114c that communicates with the first opening 114a and the second opening 114b. The first opening 114a is a substantially exposed portion of the bond pad 104 to provide detection within the photosensitive element region 106. The opening of the photosensitive element 102. The second opening 114b is substantially corresponding to the first opening 114a, and the second opening 114b has a length that is substantially the same as the length of the first opening 114a. The trench 114c is located between the photosensitive element region 106 and the non-photosensitive element region 108 or the predetermined dicing street for isolating the first substrate 100 in the photosensitive element region 106 and the first substrate 101 in the non-photosensitive element region 108. . It can be understood that the pattern opening 114 can be any shape design, as long as the bonding pad can be exposed at the same time, and the component region is isolated. Therefore, the design of the pattern opening and the fourth figure are not used to limit the present invention. .

Fig. 5 is a cross-sectional view showing the image sensing element package as shown in Fig. 4 taken along line A-A'. As shown in FIG. 5, a pattern opening 114 is formed in the first substrate 100 to expose a portion of the bonding pad 104. Furthermore, the first substrate 100 and the first substrate 101 can be isolated from each other by the pattern opening 114 described above. Since the pattern opening 114 can simultaneously expose the bond pad 104 and isolate the photosensitive element region 106, additional isolation or formation of the opening for detection may be eliminated.

As shown in FIG. 6, a color filter 116 is formed on the back surface of the first substrate 100 and corresponds to the photosensitive element 102. Next, a micro-lens 118 is disposed on the color filter 116. In one embodiment, the microlens 118 may preferably be a phenolic resin, a melamine resin, an epoxy or other suitable material.

As shown in FIG. 7, an upper packaging layer 120 or a covering plate is disposed on the back of the first substrate 100. On the surface. In one embodiment, first, the upper encapsulation layer 120 is provided, and then a spacer 122 is formed on the encapsulation layer 120. Thereafter, a bonding layer 124 is formed on the spacer layer 122, and the upper encapsulation layer 120 is bonded to the first substrate 100 to cover the back surface of the first substrate 100. The upper encapsulation layer 120 may be, for example, glass, quartz, opal, plastic or any other transparent substrate that allows light to enter and exit. It is worth mentioning that a filter and/or an anti-reflective layer may be selectively formed on the upper encapsulation layer.

The spacer layer 122 may be an epoxy, a solder mask or other suitable insulating material, such as a cerium oxide layer of an inorganic material, a cerium nitride layer, a cerium oxynitride layer, a metal oxide or Combination, or polyimine resin (PI), butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons ), accrylates, etc., and the spacer layer 122 may be by a coating method such as spin coating, spray coating or curtain coating, or other suitable Deposition methods, such as liquid phase deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD) ), plasma enhanced chemical vapor deposition (PECVD), rapid thermal chemical vapor deposition (rapid) Thermal-CVD (RTCVD) or atmospheric pressure chemical vapor deposition (APCVD) is formed to isolate environmental pollution or prevent moisture intrusion.

The bonding layer 124 may include a polymer film or one or more adhesives, such as an epoxidized resin or a polyurethane, and is used to bond the upper encapsulation layer 120 and the spacer layer 122 to the first layer. Substrate 100. In addition, it should be noted that, although not shown in the drawings, the color filter 116, the bonding layer 124 or the spacer layer 122 may be filled in the pattern opening 114 to isolate the first substrate 100 and the first An insulator of the substrate 101.

As shown in FIG. 8, after the above steps are completed, a notch is formed at a position along a predetermined scribe line between the respective photosensitive element regions (or die regions) by a lithography/etching process. A notch 126 is interposed in the second substrate 112 to separate the second substrate 112, and a plurality of carrier plates corresponding to the photosensitive element regions are formed. Next, an insulating layer 128 is formed to cover the side surface of the second substrate 112 and the back surface thereof, and a lower packaging layer 130 is disposed on the back surface of the second substrate 112 to cover the second substrate. 112 and insulating layer 128.

In an embodiment, the insulating layer 128 may be an epoxy resin, a solder resist layer or other suitable insulating material, such as a cerium oxide layer of an inorganic material, a tantalum nitride layer, a cerium oxynitride layer, a metal oxide or The combination may be a polyimine resin, an organic high-molecular material, a benzocyclobutene, a parylene, a naphthalene polymer, a fluorocarbon, an acrylate, or the like, and the spacer layer 122 may be coated by, for example, Spin coating, spray coating or curtain coating Cloth, or other suitable deposition methods, such as liquid deposition, physical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure chemistry A vapor deposition is formed to isolate the second substrate 112 from the subsequently formed wire layer.

The lower encapsulation layer 130 can be used to carry the first substrate 100 and the second substrate 112, and the lower encapsulation layer 130 can be a substrate having a high thermal conductivity, such as a germanium substrate or a metal substrate, but is not limited thereto.

As shown in FIG. 9, after the lower encapsulation layer 130 is disposed, an insulating layer 132 is selectively formed on the lower encapsulation layer 130. Thereafter, a scoring step is performed to form a channel notch 134 and a supporting brick 101a. In one embodiment, the scoring step is performed along the predetermined scribe line location by, for example, notching equipment to form the channel recess 134 and expose the surface of the upper encapsulation layer 120. Since there is an isolated first substrate 101 at the position of the dicing street (as shown in Fig. 8), when the scoring step is performed, the first substrate 101 is cut so that part of the first substrate 101 is removed. And the remaining portion of the first substrate 101, that is, the above-described support block 101a.

It is worth noting that since there is a first substrate 101 in the cutting walkway, when the scoring step is performed, the structural strength of the package body can be increased, thereby avoiding damage caused by the scoring step, such as cracking of components. In addition, the material of the support block 101a is not limited to 矽, and the material thereof may be similar to the material of the first substrate 100.

As shown in Figure 10, a conductive trace is formed. The layer 136 is on the back surface of the lower package layer 130 and extends along the via recess 134 to the side of the bonding pad 104 and the support block 101a to electrically connect the bonding pads 104. In one embodiment, the deposition is, for example, copper, aluminum, silver (silver), nickel (nickel), or alloys thereof, for example by electroplating or sputtering. The conductive material layer is on the lower encapsulation layer 130, and the conductive material layer extends on the side of the lower encapsulation layer 130, the insulating layer 128, the bonding pad 104 and the support block 101a, and is electrically connected to the bottom of the channel recess 134. Bond pad 104. Thereafter, the above-mentioned conductive material layer is patterned by, for example, photolithography/etching to form the wiring layer 136.

It is worth mentioning that, by the step of patterning the conductive material layer, the position of the subsequently formed conductive bump can be redistributed, for example, the conductive bump can be extended from the peripheral region of the lower package layer to the back of the entire lower package layer. Therefore, the wire layer 136 can also be referred to as a redistribution layer. In addition, in another embodiment, the wire layer 136 may be a doped polysilicon, a single crystal germanium or a conductive glass layer, or a deposited layer of an annealed metal material of titanium, molybdenum, chromium or titanium tungsten. .

Furthermore, the support block 101a is isolated from the first substrate 100 by the pattern opening 114 filled with the insulating layer. Therefore, the wire layer 136 formed on the side of the support block 101a does not affect the photosensitive member.

In FIG. 10, a protective layer 138, such as a solder mask, is applied over the wire layer 136 and a conductive bump is formed. The (conductive bump) 140 is on the lower package layer 130 and electrically connected to the wiring layer 136. In an embodiment, after the protective layer 138 is formed, the protective layer 138 is patterned to form an opening exposing a portion of the wiring layer 136, and then, by electroplating or screen printing, A solder is filled in the opening and a re-flow process is performed to form a conductive bump 140 such as a solder ball or a solder paste. After the above steps are completed, the upper encapsulation layer 120 is then separated along the predetermined dicing street by a dicing blade to cut an image sensing element package 150 as shown in FIG.

Figure 11 shows a cross-sectional view of an image sensing device package 150 in accordance with an embodiment of the present invention. In FIG. 11, a semiconductor wafer having a first substrate 100, a support block 101a spaced apart from the first substrate 100 by a predetermined distance, and a bonding pad 104 having a surface spanning the first The substrate 100 and the support block 101a. As shown in FIG. 11, the first substrate 100 has a first surface and an opposite second surface, and a photosensitive element 102 is formed on the first surface of the first substrate 100. A second substrate 112 is bonded to the first surface of the first substrate 100, and an upper encapsulation layer 120 and a lower encapsulation layer 130 respectively cover the second surface of the first substrate 100 and the second substrate 112. Referring to FIG. 11 , a wire layer 136 is formed on the back surface of the lower package layer 130 and extends to the side of the bonding pad 104 and the support pad 101 a to electrically connect the bonding pad 104 and a conductive bump. The 140 is disposed on the back surface of the lower encapsulation layer 130 and electrically connected to the wiring layer 136.

In an embodiment, the second surface of the first substrate 100 can be used as a second surface. As a light receiving surface, the first surface on which the photosensitive element 102 is formed can serve as a backlight surface. The external light can pass through the light receiving surface to the photosensitive element 102, so that the photosensitive element 102 can sense the light passing through the first substrate 100 and generate a signal, and then the signal can be transmitted through the bonding pad 104 and the wire layer 136. To the conductive bumps 140.

It is noted that the support block is coplanar with the first substrate, and an insulating layer is formed between the support block and the first substrate to isolate the support block from the first substrate, and the bonding pad is spanned therethrough. On the insulation layer. Therefore, the wire layer formed on the side of the support block does not affect the photosensitive member. In addition, since the support block is disposed on the bonding pad (the position where the T contacts), the structural strength between the wire layer and the bonding pad (or the structural strength of the T contact) can be increased, thereby enhancing the overall image sensing device package. Structural strength.

Figure 12 is a flow chart showing the fabrication of an image sensing device package in accordance with an embodiment of the present invention. As shown in Fig. 12, first, a wafer is provided which includes a first substrate having a plurality of photosensitive element regions, and a plurality of bonding pads are formed on the first substrate, as by step S5. Next, the first substrate is bonded to a second substrate, as by step S10. Thereafter, the first substrate is thinned as by step S15. After being thinned, a pattern opening is formed in the first substrate to isolate a support block from the first substrate and expose a portion of the bonding pads, as in step S20. Next, a color filter and a microlens are sequentially formed on the back surface of the first substrate, as in step S25. Thereafter, an upper encapsulation layer is disposed over the first substrate, and a recess is formed in the second substrate to separate the second substrate, as in steps S30 and S35. Then, set The encapsulation layer is placed on the back surface of the second substrate as shown in step S35.

After completing the above steps, a scoring step is performed to form a channel recess to expose the surface of the encapsulation layer, as by step S45. Thereafter, a wire layer is formed on the back surface of the lower package layer, and extends along the channel recess to the side of the support block and the bonding pad, and is electrically connected to the bonding pad, as in step S50. Next, a conductive bump is disposed on the back surface of the lower package layer, and the above-mentioned wire layer is electrically connected, as in step S55. Then, a cutting step is performed, such as step S60, to complete the fabrication of the image sensing device package.

Since the pattern opening can simultaneously reach the exposed bonding pad for providing the purpose of detecting the photosensitive element and isolating the first substrate forming the photosensitive element region, the manufacturing process can be shortened and simplified.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

1‧‧‧Image sensing device package

2‧‧‧Base

4‧‧‧Photosensitive elements

6‧‧‧Join pad

8‧‧‧ Cover

9‧‧‧Loading board

10‧‧‧ Conductive layer

12‧‧‧ solder balls

100‧‧‧ first base

101‧‧‧The first substrate for isolation

101a‧‧‧Support block

102‧‧‧Photosensitive elements

104‧‧‧Material pads

106‧‧‧Photosensitive element area

108‧‧‧ Non-photosensitive element area

110‧‧‧Protective layer

112‧‧‧Second substrate

114‧‧‧ pattern opening

114a‧‧‧first opening

114b‧‧‧second opening

114c‧‧‧ trench

116‧‧‧Color filters

118‧‧‧Microlens

120‧‧‧Upper encapsulation layer

122‧‧‧ spacer

124‧‧‧Connection layer

126‧‧‧ notch

128‧‧‧Insulation

130‧‧‧Under the encapsulation layer

132‧‧‧Insulation

134‧‧‧channel notch

136‧‧‧ wire layer

138‧‧‧protection layer

140‧‧‧Electrical bumps

150‧‧‧Image sensing device package

1 is a cross-sectional view showing a conventional image sensing device package; FIGS. 2-11 are schematic views showing the fabrication of an image sensing device package according to an embodiment of the present invention; and FIG. 12 is a view showing an embodiment of the present invention. A flow chart for fabricating an image sensing device package.

100‧‧‧ first base

101a‧‧‧Support block

102‧‧‧Photosensitive elements

104‧‧‧Material pads

112‧‧‧second substrate

114‧‧‧ pattern opening

116‧‧‧Color filters

118‧‧‧Microlens

120‧‧‧Upper encapsulation layer

122‧‧‧ spacer

124‧‧‧Connection layer

128‧‧‧Insulation

130‧‧‧Under the encapsulation layer

136‧‧‧ wire layer

138‧‧‧protection layer

140‧‧‧Electrical bumps

150‧‧‧Image sensing device package

Claims (16)

An electronic component package comprising: a semiconductor wafer having a substrate; a support block spaced apart from the substrate by a predetermined distance; and a bond pad having a surface spanning the substrate and the support block. The electronic component package of claim 1, wherein the support block is coplanar with the substrate. The electronic component package of claim 1, further comprising an insulating layer between the support block and the substrate to isolate the substrate from the support block, and the bonding pad spans the insulating layer on. The electronic component package of claim 1, wherein the support block and the substrate are made of the same material. The electronic component package of claim 4, wherein the support block is made of a tantalum material. The electronic component package of claim 1, further comprising a wire layer in contact with the support block and a side surface of the bonding pad. The electronic component package of claim 1, further comprising an encapsulation layer covering the semiconductor wafer and the support block. The electronic component package of claim 7, wherein the encapsulation layer further comprises a spacer layer between the semiconductor wafer and the support block. The electronic component package according to claim 1, wherein the electronic component package is a backlight image sensing device package, comprising: The substrate of the semiconductor wafer has a light-receiving surface and a backlight surface, and the backlight surface includes a photosensitive element region; a second substrate is bonded to the backlight surface of the first substrate; An encapsulation layer covering the light receiving surface of the first substrate; a second encapsulation layer covering the second substrate; a wire layer formed on the second encapsulation layer and extending to the bonding pad and the side of the support block The electrically conductive bump is electrically connected to the bonding pad; and a conductive bump is disposed on the second encapsulation layer and electrically connected to the wiring layer. A method of fabricating an electronic component package, comprising: providing a wafer having a substrate including a plurality of die regions to carry or form a plurality of semiconductor wafers, and a plurality of bonding pads are formed on the substrate; The substrate implements a wafer level packaging process comprising: patterning the substrate to isolate a support block from each of the die regions such that the support block is spaced from the substrate by a predetermined distance and exposing the bond pads. The method of manufacturing the electronic component package of claim 10, wherein the substrate comprises a first surface and an opposite second surface, the bonding pads are formed on the first surface of the substrate, and the A second surface of the substrate is patterned to isolate the support block and form a patterned opening to expose the bond pad. The method of fabricating an electronic component package according to claim 11, wherein the semiconductor wafer comprises a photovoltaic component, and the wafer level package further comprises: The substrate is a first substrate, and the first surface is a backlight surface, and the opposite second surface is a light emitting surface or a light receiving surface; a first encapsulating layer is disposed to cover the light emitting surface or the light receiving surface of the first substrate Bonding the back surface of the first substrate to a second substrate; and separating the second substrate along a position of one of the two grain sections to form a plurality of carrier plates corresponding to the die regions. The method of fabricating an electronic component package according to claim 12, wherein the wafer level packaging process further comprises: forming an insulating layer to cover at least sides of the carrier plates; and providing a second encapsulation layer And covering the second substrate and the insulating layer; forming a channel recess at a position of the predetermined scribe line in the two die sections; forming a wire layer on the second package layer, and extending along the channel notch To the bonding pad and the side of the supporting block, electrically connecting the bonding pad; disposing a conductive bump on the second encapsulation layer and electrically connecting the wire layer; and separating the predetermined cutting path The first encapsulation layer. The method of fabricating the electronic component package of claim 13, wherein the wafer level packaging process further comprises: forming the pattern opening between the support block and the first substrate; and forming an insulating layer, To fill the pattern opening. The method of manufacturing the electronic component package of claim 14, wherein before forming the first encapsulation layer, further comprising: forming a color filter on the light-emitting surface or the light-receiving surface of the first substrate, Corresponding to the electronic component; and forming a spacer layer between the first encapsulation layer and the support block and the first substrate; wherein the color filter or the spacer layer fills the pattern opening to serve as an insulation Floor. The method of fabricating an electronic component package according to claim 15, wherein before the forming the first encapsulation layer, further comprises thinning the light-receiving surface or the light-emitting surface of the first substrate.