WO2008123049A1 - Method for film formation, resin composition for use in the method, structure having insulating film, process for producing the structure, and electronic component - Google Patents

Method for film formation, resin composition for use in the method, structure having insulating film, process for producing the structure, and electronic component Download PDF

Info

Publication number
WO2008123049A1
WO2008123049A1 PCT/JP2008/054916 JP2008054916W WO2008123049A1 WO 2008123049 A1 WO2008123049 A1 WO 2008123049A1 JP 2008054916 W JP2008054916 W JP 2008054916W WO 2008123049 A1 WO2008123049 A1 WO 2008123049A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
resin composition
coating
film formation
pore
Prior art date
Application number
PCT/JP2008/054916
Other languages
French (fr)
Japanese (ja)
Inventor
Ryuichi Okuda
Takayoshi Tanabe
Hirofumi Goto
Original Assignee
Jsr Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007307985A external-priority patent/JP2009133924A/en
Application filed by Jsr Corporation filed Critical Jsr Corporation
Publication of WO2008123049A1 publication Critical patent/WO2008123049A1/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/022—Quinonediazides
    • G03F7/023—Macromolecular quinonediazides; Macromolecular additives, e.g. binders
    • G03F7/0233—Macromolecular quinonediazides; Macromolecular additives, e.g. binders characterised by the polymeric binders or the macromolecular additives other than the macromolecular quinonediazides
    • G03F7/0236—Condensation products of carbonyl compounds and phenolic compounds, e.g. novolak resins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Materials For Photolithography (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

This invention provides a method for film formation, which can easily form, with high accuracy, an even film on an inner wall face or a bottom face in a fine pore or groove part having a bottom provided on, for example, on a stepped silicon substrate, and a resin composition for use in the method, a structure having an insulating film, a process for producing the structure, and an electronic component. The method for film formation comprises [1] a solvent coating step of coating a solvent (13) on a stepped substrate (1) having at least one of (a) a pore part (11) having an opening part area of 25 to 10000 µm2 and a depth of 10 to 200 µm and (b) a groove part (12) having an opening part line width of 5 to 200 µm and a depth of 10 to 200 µm, [2] a resin composition coating step of coating a positive-working photosensitive resin composition onto the stepped substrate (1) so as to come into contact with the solvent (13) within the pore part (11) and the groove part (12), and [3] a drying step of drying the coating film (14). Further, a film (16) containing a resin component is formed on the inner wall face and bottom face in the pore part (11) and the groove part (12).
PCT/JP2008/054916 2007-03-30 2008-03-17 Method for film formation, resin composition for use in the method, structure having insulating film, process for producing the structure, and electronic component WO2008123049A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007094364 2007-03-30
JP2007-094364 2007-03-30
JP2007-307985 2007-11-28
JP2007307985A JP2009133924A (en) 2007-11-28 2007-11-28 Method for film formation and positive photosensitive resin composition for use in the same

Publications (1)

Publication Number Publication Date
WO2008123049A1 true WO2008123049A1 (en) 2008-10-16

Family

ID=39830551

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/054916 WO2008123049A1 (en) 2007-03-30 2008-03-17 Method for film formation, resin composition for use in the method, structure having insulating film, process for producing the structure, and electronic component

Country Status (2)

Country Link
TW (1) TW200905397A (en)
WO (1) WO2008123049A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009150918A1 (en) * 2008-06-11 2009-12-17 Jsr株式会社 Structure having insulating coating film, method for producing the same, positive photosensitive resin composition and electronic device
WO2010047264A1 (en) * 2008-10-20 2010-04-29 住友ベークライト株式会社 Positive photosensitive resin composition for spray coating and method for producing through electrode using same
WO2012036000A1 (en) * 2010-09-16 2012-03-22 日立化成工業株式会社 Positive photosensitive resin composition, method of creating resist pattern, and electronic component
NL2014598A (en) * 2015-04-08 2016-10-12 Suss Microtec Lithography Gmbh Method for coating a substrate.
CN110461085A (en) * 2019-07-24 2019-11-15 沪士电子股份有限公司 A kind of wiring board and preparation method thereof may be implemented in crimping component in stepped groove

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103309152B (en) * 2012-03-13 2018-08-28 东京应化工业株式会社 Forming method, pattern forming method, solar cell and the eurymeric corrosion-resistant composition of resist pattern
JP6420793B2 (en) * 2016-06-09 2018-11-07 株式会社タムラ製作所 Method for forming cured coating film

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5660432A (en) * 1979-10-23 1981-05-25 Fuji Photo Film Co Ltd Photosolubilizing composition
JPS6458375A (en) * 1987-08-28 1989-03-06 Matsushita Electric Ind Co Ltd Method for applying resist
JPH01273031A (en) * 1988-04-26 1989-10-31 Mitsubishi Kasei Corp Resist composition for curtain coater application
JPH03268384A (en) * 1989-02-23 1991-11-29 Matsushita Electric Works Ltd Manufacture of wiring board provided with through hole
JPH04218049A (en) * 1990-07-20 1992-08-07 Matsushita Electric Works Ltd Resist composition
JPH06180499A (en) * 1992-12-14 1994-06-28 Matsushita Electric Works Ltd Liquid resist composition
JPH07320999A (en) * 1993-03-25 1995-12-08 Tokyo Electron Ltd Method and apparatus for coating
JP2003233183A (en) * 2001-12-03 2003-08-22 Showa Denko Kk Photosensitive resin composition, production process for photosensitive resin film, and production process for printed wiring board
WO2004114020A1 (en) * 2003-06-20 2004-12-29 Zeon Corporation Radiation-sensitive resin composition and method for forming pattern using the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5660432A (en) * 1979-10-23 1981-05-25 Fuji Photo Film Co Ltd Photosolubilizing composition
JPS6458375A (en) * 1987-08-28 1989-03-06 Matsushita Electric Ind Co Ltd Method for applying resist
JPH01273031A (en) * 1988-04-26 1989-10-31 Mitsubishi Kasei Corp Resist composition for curtain coater application
JPH03268384A (en) * 1989-02-23 1991-11-29 Matsushita Electric Works Ltd Manufacture of wiring board provided with through hole
JPH04218049A (en) * 1990-07-20 1992-08-07 Matsushita Electric Works Ltd Resist composition
JPH06180499A (en) * 1992-12-14 1994-06-28 Matsushita Electric Works Ltd Liquid resist composition
JPH07320999A (en) * 1993-03-25 1995-12-08 Tokyo Electron Ltd Method and apparatus for coating
JP2003233183A (en) * 2001-12-03 2003-08-22 Showa Denko Kk Photosensitive resin composition, production process for photosensitive resin film, and production process for printed wiring board
WO2004114020A1 (en) * 2003-06-20 2004-12-29 Zeon Corporation Radiation-sensitive resin composition and method for forming pattern using the same

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009150918A1 (en) * 2008-06-11 2009-12-17 Jsr株式会社 Structure having insulating coating film, method for producing the same, positive photosensitive resin composition and electronic device
JP5246259B2 (en) * 2008-06-11 2013-07-24 Ｊｓｒ株式会社 Structure having insulating film and method for producing the same, positive photosensitive resin composition, and electronic component
JP5545217B2 (en) * 2008-10-20 2014-07-09 住友ベークライト株式会社 Positive photosensitive resin composition for spray coating and method for producing through electrode using the same
WO2010047264A1 (en) * 2008-10-20 2010-04-29 住友ベークライト株式会社 Positive photosensitive resin composition for spray coating and method for producing through electrode using same
US9005876B2 (en) 2008-10-20 2015-04-14 Sumitomo Bakelite Co., Ltd. Positive photosensitive resin composition for spray coating and method for producing through electrode using the same
US8836089B2 (en) 2010-09-16 2014-09-16 Hitachi Chemical Company, Ltd. Positive photosensitive resin composition, method of creating resist pattern, and electronic component
CN103097954A (en) * 2010-09-16 2013-05-08 日立化成株式会社 Positive photosensitive resin composition, method of creating resist pattern, and electronic component
WO2012036000A1 (en) * 2010-09-16 2012-03-22 日立化成工業株式会社 Positive photosensitive resin composition, method of creating resist pattern, and electronic component
JP5915532B2 (en) * 2010-09-16 2016-05-11 日立化成株式会社 Positive photosensitive resin composition, method for producing resist pattern, and electronic component
NL2014598A (en) * 2015-04-08 2016-10-12 Suss Microtec Lithography Gmbh Method for coating a substrate.
US9799554B2 (en) 2015-04-08 2017-10-24 Suss Microtec Lithography Gmbh Method for coating a substrate
AT516988A3 (en) * 2015-04-08 2018-04-15 Suss Microtec Lithography Gmbh Method for coating a substrate
AT516988B1 (en) * 2015-04-08 2022-10-15 Suss Microtec Lithography Gmbh Process for coating a substrate
CN110461085A (en) * 2019-07-24 2019-11-15 沪士电子股份有限公司 A kind of wiring board and preparation method thereof may be implemented in crimping component in stepped groove
CN110461085B (en) * 2019-07-24 2021-05-11 沪士电子股份有限公司 Circuit board capable of realizing crimping of components in stepped groove and manufacturing method thereof

Also Published As

Publication number Publication date
TW200905397A (en) 2009-02-01

Similar Documents

Publication Publication Date Title
WO2008123049A1 (en) Method for film formation, resin composition for use in the method, structure having insulating film, process for producing the structure, and electronic component
TW200705564A (en) Method for manufacturing a narrow structure on an integrated circuit
EP2062950A3 (en) Topcoat composition, alkali developer-soluble topcoat film using the composition and pattern forming method using the same
WO2005009632A3 (en) Methods for forming tunable molecular gradients on substrates
WO2004101177A3 (en) Method for coating substrates with a carbon-based material
WO2003069381A3 (en) Optical component comprising submicron hollow spaces
WO2008017472A3 (en) Method for the production of a porous, ceramic surface layer
WO2007080427A3 (en) Method of making microneedles
WO2006004929A3 (en) Electrochemical deposition method utilizing microdroplets of solution
ATE557419T1 (en) METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT
DE50312189D1 (en) Nanoimprint-resist
WO2006101995A3 (en) Inorganic coatings for optical and other applications
WO2008093579A1 (en) Multilayer body, method for producing substrate, substrate and semiconductor device
EP2040521A3 (en) Method of manufacturing substrate
TW200608047A (en) Optical film coating
WO2009057764A1 (en) Etching method and method for manufacturing optical/electronic device using the same
ATE484609T1 (en) METHOD FOR PRODUCING A FUNCTIONAL LAYER
WO2009077538A3 (en) Process of assembly with buried marks
WO2009005042A1 (en) Metal material, method for producing the same, and electrical electronic component using the same
WO2009001665A1 (en) Metal layer laminate with metal surface roughened layer and process for producing the same
WO2007025521A3 (en) Method for the production of a semiconductor component comprising a planar contact, and semiconductor component
WO2006055310A3 (en) Article with patterned layer on surface
TW200723354A (en) Material for forming adhesion reinforcing layer, adhesion reinforcing layer, semiconductor device, and manufacturing method thereof
DK2140945T3 (en) Process for producing organic thin film
WO2006033852A3 (en) Structured surface using ablatable radiation sensitive material

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08722310

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08722310

Country of ref document: EP

Kind code of ref document: A1