WO2007079660A1

WO2007079660A1 - Processor chip and memory controlling system and method thereof

Info

Publication number: WO2007079660A1
Application number: PCT/CN2006/003725
Authority: WO
Inventors: Jun Hu; Zhanbing Huang; Jieming Huang; Xiaomin Wu
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2006-01-06
Filing date: 2006-12-30
Publication date: 2007-07-19
Also published as: CN1873604A; CN100346285C

Abstract

A processor chip is disclosed. The processor chip comprises at least two controllers connected to the system bus of the processor respectively and a bus selector connected to the said controllers. The controllers receive the signal from the system bus of the processor and control the read/write processing for the external memory of the processor. The bus selector comprises a interface for exchanging the data with the external memory of the processor. One of the said controllers is a hard disk controller. The hard disk controller receives the signal from the system bus of the processor and controls the read/write processing between the processor and the external hard disk. It is further disclosed a memory controlling system implemented based on the said processor chip and a method thereof. The invention reduces the amount of the package pins by implementing the multiplexing of the data exchange modes, so as to reduce the volume of the chip package.

Description

Processor chip and storage control system and method

This application claims priority to Chinese Patent Application No. 200610032786.0, entitled "Processor Chip and Storage Control System and Method", filed on January 6, 2006, the entire contents of which is incorporated herein by reference. In the application.

Technical field

The present invention relates to a data storage technology, and in particular, to a processor chip and a storage control system and method.

Background technique

Hard disks are an indispensable peripheral for most CPU systems, and the design of their controllers is a key technology in CPU system design. There are many types of interfaces for hard disks. The integrated drive electronics (IDE) interface type hard disk, referred to as IDE hard disk for short, is the most widely used because of its mature production technology and lowest cost. However, the interface of the IDE hard disk is integrated into the central processor CPU chip. At least 28 chip control pins are needed. Moreover, there are many other types of memory coexisting with the IDE hard disk in the CPU chip peripheral device, such as Static Random Access Memory (SRAM), Flash Flash, Read Only Memory (Read Only Memory). Called ROM), etc., they also use a large number of chip control pins. As a result, the number of pins is too large and the chip package is too large, which is a serious problem for the increasingly miniaturized electronic handheld products. Therefore, the multiplexing of the IDE hard disk and other memory data lines and address lines is a good way for the CPU chip to reduce the pins and reduce the package.

Currently, a prior art solution is shown in Figure 1: All external memory is controlled in unison through a common, configurable static RAM (SRAM) controller on the system bus. In this solution, the SRAM controller is designed with timing registers that can be configured to configure the correct access timing for different memory types by configuring the timing registers. Therefore, external memory including IDE hard disk, Flash memory, Compact Flash (CF) memory and ROM/SRAM memory does not need to separately package control pins in the chip, but is allocated according to a certain access timing. Data is exchanged between the data line and the address line to reduce the number of control pins.

However, the above technical solutions have the following technical defects:

First, the timing of the SRAM control is relative to the single, which is the general SRAM timing. For the IDE hard disk, only the programmable input/output can be applied to match the SRAM timing. Input/Output, referred to as PIO) mode data exchange.

At present, the way of data exchange between the hard disk and the CPU mainly includes PIO mode and direct memory access.

Enhanced version of Direct Memory Access (DMA) mode - advanced direct memory access

(Ultra Direct Memory Access, abbreviated as UDMA) mode.

The ΡΙΟ mode is a data exchange mode for reading and writing data by executing an I/O port instruction by the CPU, and is the earliest hard disk data transmission mode, and is divided into PIO mode 0, PIO mode 1, and PIO mode 2. Five modes, PIO mode 3 and PIO mode 4. Since the data transmission rate ranges from 3.3 megabytes/second to 16.6 megabytes/second, the data transmission rate is relatively low; and the data transmission between the hard disk and the memory is controlled by the CPU, resulting in CPU occupancy. Very high, when transferring a large amount of data, the system will be suspended due to excessive CPU resources, and other operations cannot be performed. Therefore, the PIO mode is limited by the low transmission rate and extremely high CPU resource occupancy.

The DMA mode is a data exchange mode for directly accessing data from a memory without going through a CPU: the CPU issues an instruction to the DMA controller, and causes the DMA controller to process the number of transfers. After the data transfer is completed, the DMA controller again Information is fed back to the CPU. This does not overly rely on the CPU, which greatly reduces the CPU resource occupancy and can greatly save system resources. However, the difference in transmission speed between DMA mode and PIO mode is not very obvious: DMA mode is divided into single-byte DMA and multi-byte DMA, and the maximum transmission rate that can be achieved is only 16.6 megabytes. /second. To overcome this shortcoming, the DMA mode of operation used by the hard disk has now largely eliminated single-byte DMA and multi-byte DMA, while using the new UDMA mode.

The UDMA mode is based on the 16-bit multi-byte DMA mode. It is an enhanced version of the DMA mode. Based on the advantages of the DMA mode, a 16-bit Cyclic Redundancy Check (Cyclic Redundancy Check) is added. Called CRC), which improves the accuracy and security of the data transmission process. Moreover, the data transfer speed has been greatly improved, and its current maximum bandwidth has reached 133 megabytes/second.

Since the data exchange speed of the hard disk determines the access speed of the electronic device, the hard disk can only support

The W ριο mode undoubtedly limits the data storage speed of electronic devices. With the increasing bandwidth of multimedia applications such as high-definition television signals, the UDMA mode is not supported and obviously cannot meet the needs of high-bandwidth applications.

Second, the SRAM cannot implement dynamic alternate access to the controlled memory. If it is necessary to switch to a different memory, the timing register needs to be reconfigured. For example, if the multimedia chip is plugged in at the same time A Flash and an IDE hard disk, the multimedia chip can not achieve alternate access of the Flash and multimedia IDE hard disk, it is necessary to reconfigure the timing register to switch by CPU intervention.

It can be seen that the disadvantages of the prior art are as follows: 1) Since the SRAM cannot implement dynamic alternate access of the control memory, if it is necessary to switch to a different control memory, the timing register needs to be reconfigured by the processor, resulting in a high CPU occupancy rate. , the data transmission rate is low; 2) Although the UDMA mode can greatly improve the data transmission rate and adapt to the high bandwidth requirement, however, as the bandwidth of multimedia applications such as high-definition television signals is gradually increased, if the electronic device does not support the UDMA mode, it is obviously impossible. Adapt to high bandwidth applications.

Summary of the invention

The technical problem to be solved by the embodiments of the present invention is to provide a processor chip and a processor chip-based storage control system and method, which solve the problems of high CPU occupancy and low data transmission rate in the prior art.

To solve the above technical problem, an embodiment of the present invention provides a processor chip, including: at least two controllers respectively connected to a processor system bus for receiving a processor system bus signal and controlling reading of an external memory of the processor Write

a bus selector, which is respectively connected to the controller, the bus selector includes an interface, and the controller exchanges data with the external memory of the processor through the interface;

One of the controllers is a hard disk controller for receiving a processor system bus signal and controlling reading and writing of an external hard disk of the processor.

In addition, an embodiment of the present invention further provides a storage control system, including:

At least two memories for storing data, one of the memories being a hard disk;

Processor chip

Sharing the main line, connecting the processor chip and the memory;

The processor chip includes:

At least two controllers are respectively connected to the processor system bus for receiving the processor system bus signals and controlling the reading and writing of the external memory of the processor;

One of the controllers is a hard disk controller for receiving processor system bus signals and controlling the processor Reading and writing of the hard disk of the department.

In addition, an embodiment of the present invention further provides a storage control method, where the method includes the following steps:

A. The bus selector receives the bus request signal of the controller, confirms that the shared bus is released, sends a bus enable signal to the controller, and the shared bus communicates with the controller and the memory controlled by the controller;

B. When the connected controller is a hard disk controller, determine a current data exchange mode, and select a control unit corresponding to the data exchange mode, and then the control unit controls the hard disk to perform data reading and writing;

C. When the connected controller is a non-hard disk controller, the controller directly controls the corresponding memory to read and write data.

According to the foregoing technical solution, the embodiment of the present invention implements the support of the UDMA access mode of the IDE hard disk while supporting the PIO mode by setting the hard disk controller in the system; or realizing the hard disk of the CPU system by setting the bus selector in the system. Dynamic sharing of the controller's data address with other memory controllers; or by encapsulating the controller including the hard disk controller and the bus selector in the processor chip, and only exchanging data with the external memory of the chip through the interface of the bus The chip package pin is reduced, thereby reducing the package volume; and in the memory control method provided by the present invention, the bus release signal received during the clock cycle is set to be invalid by the controller, ensuring that the predetermined clock cycle is within a predetermined clock cycle. Can pass data completely. Therefore, the problem in the prior art that the CPU occupation rate is high, the data transmission rate is low, and the high bandwidth application cannot be adapted is solved.

DRAWINGS

1 is a schematic diagram of a technical solution of a multimedia processor in the prior art;

2 is a block diagram of a storage control system according to an embodiment of the present invention;

Figure 3 is a system block diagram of the hard disk controller of Figure 2;

4 is a system block diagram of Embodiment 2 of a storage control system according to an embodiment of the present invention; FIG. 5 is a general flowchart of a storage control method according to an embodiment of the present invention;

6 is a flowchart of a working process of a hard disk controller in a storage control method according to an embodiment of the present invention; FIG. 8 is a flowchart of a write operation of a hard disk controller in a storage control method according to an embodiment of the present invention; A flowchart of a read operation of the hard disk controller in the storage control method. detailed description

The invention will be further described in detail below with reference to the drawings and embodiments.

In order to achieve multiplexing of multiple data exchange modes while reducing processor package pins, the present invention The embodiment provides a processor chip, see part A in FIG. 2, which includes at least two controllers respectively connected to the processor system bus, one of the controllers is a hard disk controller, and further includes a bus selector. And respectively connected to the controller, the bus selector includes an interface, and the controller exchanges data with the outside of the chip through the interface.

The main functions of each part of the processor chip are:

The controller is configured to receive a processor bus signal, and control the reading and writing of the external memory. In the first embodiment, the processor is a CPU and includes two controllers: the first controller is an IDE hard controller 21, and the second controller is an SRAM controller 22. The IDE hard disk controller 21 and the SRAM controller 22 receive commands from the CPU system bus to control the reading and writing of the hard disk and other memories, respectively.

A bus selector for controlling the selection of the IDE hard disk controller 21 and the SRAM controller 22, determining the right to use the interface, connecting the IDE hard disk controller 21 with the hard disk it controls, or connecting the SRAM controller 22 with other memories.

As shown in FIG. 2, an embodiment of the present invention further provides a storage control system including a processor chip, a shared bus, and at least two memories. The shared bus connects the processor chip and the paralleled memory.

In this embodiment, the processor chip is a CPU chip, and the shared bus is a data and address sharing main line. The memory is SRAM/ROM memory 32, flash memory 33 and IDE hard disk respectively. The main functions of each part of the storage control system are:

The CPU chip includes an IDE hard disk controller 21, and the second controller is an SRAM controller 22 and a bus selector 1. The IDE hard disk controller 21 receives commands from the CPU system bus to control the storage of the IDE hard disk 31, and the SRAM controller 22 receives commands from the CPU system bus, and follows the timing controllers of the SRAM controller in the SRAM/ROM memory 32 and the flash 33. Perform storage control. The bus selector 1 is connected to the IDE hard disk controller 21 and the SRAM controller 22 via a controller bus, respectively, to control the routing of the IDE hard disk controller 21 and the SRAM controller 22; the bus selector 1 is connected to the data and address sharing bus through the interface. Further, it is connected to the IDE hard disk 31, the SRAM/ROM memory 32, and the flash memory 33. The bus selector determines the right to use the interface by the controller, and the controller uses the right to determine the data and address sharing bus, connects the IDE hard disk controller 21 with the IDE hard disk 31, or connects the SRAM controller 22 and the SRAM/ROM memory 32 and Flash memory 33. By introducing the IDE hard disk controller 21 and performing the routing of the bus selector 1, it overcomes the drawback that the dynamic sharing of the data and the address sharing bus cannot be realized by using only the SRAM controller with simple timing.

The hard disk controller is not limited to the IDE hard disk controller 21 in this embodiment. For example, a small computer system interface (SCSI) type hard disk controller is also suitable for the present invention.

In this embodiment, the second controller may be a flash controller, a compressed flash controller, or a ROM controller.

Please refer to FIG. 3 , which is a system block diagram of an embodiment of an IDE hard disk controller according to Embodiment 1 of the present invention, which includes a PIO control unit 211 connected to a CPU system bus for receiving a CPU system bus signal, and performing commands in a PIO mode. Data transmission control, realizing operation of the hard disk PIO mode; UDMA control unit 212, connected to the CPU system bus, for receiving CPU system bus signals, performing data transmission control in UDMA mode, realizing operation of hard disk UDMA mode; logic unit 213 And respectively connected to the PIO control unit 211 and the UDMA control unit 212 for distinguishing the hard disk PIO mode and the hard disk UDMA mode, and strobing the corresponding PIO control unit or UDMA control unit, which can be transmitted by the strobe PIO control unit or the UDMA control unit The manner of the line is performed; the interface unit 214 is respectively connected to the PIO control unit 211, the UDMA control unit 212 and the bus selector 1 for acquiring and releasing the control right of the shared bus; further comprising a timing unit 215, respectively, and the PIO control The unit 211 is connected to the UDMA control unit 212 for providing a hard disk PIO. Type and timing parameters to achieve the hard disk UDMA mode, implement support for different core clock settings.

The PIO control unit 211 and the UDMA control unit 212 are both connected to the CPU system bus to acquire system commands and data. However, specifically, the PIO control unit 211 controls the transmission of commands and data, but the UDMA control unit 212 only controls the transmission of data. That is, the transmission of the system command must first be performed by the PIO control unit 211.

Through the above embodiments of the present invention, multiplexing support for the PIO mode and the UDMA mode can be realized.

In the embodiment of the present invention, the processor chip is not limited to the above two controllers, and may include a plurality of controllers, and the routing of the shared bus is unified by the bus selector.

Referring to FIG. 4, it is a second embodiment of a processor chip according to an embodiment of the present invention. Adding a flash controller based on FIG. 2 specifically includes: a bus selector 1, an IDE hard disk controller 21, an SRAM controller 22, and a flash controller 23, wherein the flash controller 23 is responsible for the read/write control of the flash. The bus selector 1 is responsible for routing of the DE hard disk controller 21, the SRAM controller 22, and the flash controller 23. For the function and function of each device in this embodiment, please refer to the above, and details are not described herein again.

In this embodiment, a compressed flash controller or a ROM controller may also be included. In general, there will be no two identical controllers, so as to avoid wasting space and resources.

In addition, an embodiment of the present invention further provides a storage control method, and a flowchart thereof is shown in FIG. 5, where the method includes the following steps:

Step 101: The bus selector receives a bus request signal of the controller; that is, the controller needs to control the reading and writing of the memory, and sends a bus request signal to the bus selector, and the bus selector receives the bus request signal;

Step 102: The bus selector determines whether the shared bus is occupied, if the shared bus is occupied, step 103 is performed, otherwise step 104 is performed;

Step 103: The bus selector sends a bus release signal to the controller occupying the shared bus, and the occupied controller is required to release the shared bus.

In order to ensure the fair competition of each device and the integrity of the data processing, the controller receiving the bus release instruction sets the bus release instruction to be invalid if it is still within a predetermined time period, for example, data is performed in UDMA mode. When transmitting, the preset time is one CPU clock cycle to satisfy the UDMA's ability to completely perform data transmission of at least one CPU clock.

This step can also include the following steps:

Step 1031: If the controller occupying the shared bus is still within a predetermined time period, the bus release signal is set to be invalid;

Step 1032: The controller occupying the shared bus enters a pause after a time period, and releases the shared bus.

Step 1033: The bus selector detects whether the shared bus is released. If yes, step 104 is performed, otherwise step 1033 is re-executed until it is confirmed that the shared bus is released.

In this step, the detection operation of the bus selector may not be performed, but the release completion instruction is issued by the controller occupying the shared bus, and the bus selector executes step 104 after receiving the release completion instruction. Step 104: After the bus controller occupies the shared bus, the bus selector sends a bus enable signal to the requesting controller;

Step 105: Connect the controller and the memory controlled by the shared bus through the shared bus; the controller is divided into a hard disk controller and a non-hard disk controller, when the connected controller is a hard disk controller, step 106 is performed, otherwise step 107 is performed;

Step 106: The hard disk controller determines the current data exchange working mode. If it is the UDMA mode, select the corresponding internal unit to control the read and write access of the hard disk by using the UDMA mode. If it is the PIO mode, select the corresponding internal unit to control the hard disk with the PIO mode. Read and write access, and end the read and write access process;

Step 107: The non-hard disk controller controls the read and write access of the memory and ends the process.

6 is a flowchart of a read/write control process performed by a hard disk controller when a hard disk controller is allowed to use a shared bus in the storage control method according to an embodiment of the present invention, including the following steps:

Step 201: The hard disk controller acquires a shared bus.

Step 202, the hard disk controller logic unit identifies the working mode of the hard disk storage, in the PIO mode, step 203 is performed, and if it is the UDMA mode, step 204 is performed;

Step 203, the logic unit strobes the line of the PIO control unit, performs PIO read and write access control, and performs step 209;

Step 204: The logic unit strobes the line of the PIO control unit, and sends a UDMA transmission instruction to the hard disk storage by using a PIO mode;

Step 205, strobing the line of the UDMA control unit; that is, the hard disk memory transmitting and receiving the feedback instruction indicates that the UDMA mode can be applied, and after receiving the feedback command from the hard disk memory, the logic unit strobes the line of the UDMA control unit;

Step 206, the UDMA control unit determines the UDMA mode type, if it is a write access, step 207 is performed, otherwise step 208 is performed;

Step 207: Perform write access control in a UDMA mode.

Step 208: Perform read access control in a UDMA mode.

Step 209, the read/write data exchange is completed, and the process ends.

The following embodiment details the process of read and write access control in UDMA mode.

Please refer to FIG. 7, which is a complete diagram of write access control in the UDMA mode according to an embodiment of the present invention. The flow chart includes the following steps:

Step 401, the bus selector receives the bus request signal sent by the hard disk controller; Step 402, the bus selector determines whether the data and address sharing bus is occupied, and if so, after performing step 403, step 404 is performed; otherwise, step 404 is performed;

Step 403: The bus selector sends a bus release signal to a controller that occupies the data and address sharing bus.

Step 404: After the bus selector detects that the data and the address sharing bus are dry or idle, return a bus enable signal to the hard disk controller.

Step 405: The bus selector connects the hard disk controller to the data and address sharing bus through the interface;

Step 406: The hard disk controller logic unit identifies that the working mode of the hard disk storage is a UDMA mode, and sends a UDMA transmission instruction by using a PIO controller.

Step 407: When the hard disk memory recognizes the command and prepares the UDMA data transmission, a hard disk interrupt signal is generated. After receiving the interrupt signal, the processor queries the status register of the hard disk to confirm that the hard disk controller can perform UDMA data transmission. The processor switches the logic unit to a logic value corresponding to the UDMA mode, and selects the operation mode configuration register as a write operation;

Step 408, the logic unit strobes the UDMA control unit;

Step 409: The operation mode configuration register sends an operation instruction to the UDMA control unit, and the UDMA control unit recognizes the operation instruction as a write operation instruction;

Step 410, the UDMA control unit determines whether the UDMA write initialization has been performed, if yes, step 415 is performed, otherwise step 411 is performed;

Step 411, performing UDMA write initialization;

Step 412, the UDMA control unit detects whether a bus release signal is received, if the step 413 is performed, otherwise step 415 is performed;

Step 413, the UDMA control unit enters a write pause state, and releases the shared bus.

Step 414, issue a bus request instruction, and re-execute step 401;

Step 415, the UDMA control unit performs write and transfer data of one CPU clock;

Step 416: Determine whether the write transmission ends. If yes, go to step 417. Otherwise, go to step 412. Step 417: Send the cyclic redundancy code check and end. That is to say, in the UDMA write control state machine, the determination condition of entering the host pause state increases the valid condition of the bus release signal, and once the condition is met, the host pause state is entered, and the associated clock and data are suspended. . When the UDMA access ends, the data address bus is actively acquired. At this time, the host pause state to the data transfer state is exited, and the data is continuously sent to the IDE hard disk until the UDMA write transfer is completed and the check CRC is sent.

Referring to FIG. 8, a complete flow diagram of read access control in UDMA mode according to an embodiment of the present invention includes the following steps:

Step 501: The bus selector receives a bus request signal sent by the hard disk controller.

Step 502, the bus selector determines whether the data and address sharing bus is occupied, if yes, step 503 is followed by step 504, otherwise step 504 is performed;

Step 503: The bus selector sends a bus release signal to a controller that occupies the data and address sharing bus.

Step 504: After the bus selector detects that the data and the address sharing bus are released or idle, returning a bus enable signal to the hard disk controller;

Step 505: The bus selector connects the hard disk controller to the data and address sharing bus. Step 506: The hard disk controller logic unit identifies that the working mode of the hard disk memory is a UDMA mode, and sends a DMA transfer instruction through the PIO controller.

Step 507: When the hard disk memory recognizes the command and prepares the UDMA data transmission, the hard disk interrupt signal is generated. After receiving the interrupt signal, the processor queries the status register of the hard disk to confirm that the hard disk controller can perform UDMA data transmission. The processor switches the logic unit to a logic value corresponding to the UDMA mode, and selects the operation mode configuration register as a read operation;

Step 508, the logic unit strobes the UDMA control unit;

Step 509: The operation mode configuration register sends an operation instruction to the UDMA control unit, and the UDMA control unit recognizes the operation instruction as a read operation instruction;

Step 510, the control unit determines whether the UDMA read initialization has been performed, and if so, step 517 is performed, otherwise step 511 is performed;

Step 511, performing UDMA read initialization;

Step 512, the control unit detects whether a bus front-end signal is received, and if so, step 513 is performed, otherwise step 517 is performed; Step 513, the UDMA control unit sets the DMA ready signal to be invalid;

Step 514, continue to receive 0-2 data according to the setting; if the rate mode is increased, more data can be received.

Step 515, the UDMA control unit enters a read pause state, releasing the shared bus;

Step 516, issue a bus request instruction, and re-execute step 501;

Step 517, UDMA performs read and transfer data of one CPU clock;

Step 518: Determine whether the read transmission ends, and if yes, perform step 519, otherwise perform steps

512;

Step 519, sending a cyclic redundancy code check, and ending.

That is to say, in the UDMA working mode, in the UDMA read control state machine, the judgment condition of entering the host pause state increases the condition that the bus release signal is valid, and once the condition is judged, the main side on the IDE bus is established. The DMA ready signal is disabled. After continuing to receive 0-2 16-bit data from the IDE hard disk, it enters the host's pause state until the SRMA access ends and reacquires the data address bus. After re-entering the transfer state, the IDE bus is used. The upper main DMA ready signal is asserted and the IDE hard drive continues to send data to the IDE hard disk controller.

It can be seen that the IDE hard disk controller supporting the data address sharing in the embodiment of the present invention not only supports the original PIO mode, but also supports the more efficient UDMA mode, and realizes the data address line of the IDE hard disk controller and other memories. Dynamic coexistence. That is to say, the embodiment of the present invention enables the IDE hard disk controller to simultaneously implement the transmission of the PIO mode and the U MA mode in the case of multiplexing the data lines and the address lines with other storage controllers, thereby solving the CPU in the prior art. High occupancy, low data transfer rates, and the problem of not being able to accommodate high bandwidth applications. The invention reduces the number of package pins on the basis of realizing multiple data exchange mode multiplexing, thereby reducing the chip package volume.

It should be noted that the above embodiments are only intended to illustrate the technical solutions of the present invention and are not intended to be limiting, and the present invention will be described in detail with reference to the preferred embodiments. Modifications or equivalents are made without departing from the spirit and scope of the invention.

Claims

Rights request

A processor chip, comprising:

a bus selector, respectively connected to the controller, wherein the bus selector includes an interface, and the controller exchanges data with the external memory of the processor through the interface;

2. The processor chip of claim 1, wherein the hard disk controller comprises an IDE hard disk controller.

The processor chip according to claim 1 or 2, wherein the hard disk controller comprises:

Programmable input and output PIO control unit, connected to the system bus of the processor chip, is used to receive the system bus signal of the processor chip, and performs command and data transmission control in the PIO mode;

a direct memory access UDMA control unit, connected to the bus of the processor chip system, for receiving a system bus signal of the processor chip, and performing data transmission control in a UDMA mode;

a logic unit, respectively connected to the PIO control unit and the UDMA control unit, for distinguishing between a hard disk PIO mode and a hard disk UDMA mode, and strobing a corresponding PIO control unit or a UDMA control unit;

An interface unit, respectively connected to the PIO control unit, the UDMA control unit, and the bus selector, for receiving a bus enable signal and a bus release signal sent by the bus selector to acquire and release the bus selection Control of the interface.

The processor chip according to claim 3, wherein the hard disk controller further comprises:

The timing unit is respectively connected to the PIO control unit and the UDMA control unit, and is configured to provide an implementation timing of the hard disk PIO mode and the hard disk UDMA mode.

The processor chip according to claim 1, wherein the controller comprises: a flash memory controller, a compressed flash controller, an SRAM controller or a ROM controller.

6. A storage control system, comprising: At least two memories for storing data, one of the memories being a hard disk;

Processor chip

Sharing the main line, connecting the processor chip and the memory;

The processor chip includes:

One of the controllers is a hard disk controller for receiving a processor system bus signal and controlling reading and writing of the hard disk external to the processor.

7. The storage control system according to claim 6, wherein the hard disk controller is an IDE hard disk controller; and the hard disk is an IDE hard disk.

The storage control system according to claim 6 or 7, wherein the hard disk controller comprises:

a PIO control unit, connected to the processor system bus, for receiving a processor system bus signal, and performing command and data transmission control in a PIO mode;

a UDMA control unit, connected to the bus of the processor system, for receiving a system bus signal of the processor, and performing data transmission control in a UDMA mode;

a logic unit, respectively connected to the PIO control unit and the UDMA control unit, for distinguishing between a PIO mode and a UDMA mode, and stroking a corresponding PIO control unit or a UDMA control unit;

An interface unit, respectively connected to the PIO control unit and the UDMA control unit and the bus selector, for receiving a bus enable signal and a bus release signal sent by the bus selector, to acquire and dry the data Control of the bus shared with the address.

The storage control system according to claim 8, wherein the hard disk controller further comprises:

10. The storage control system of claim 9, wherein the controller comprises: Flash controller, compressed flash controller, SRAM controller or ROM controller.

11. A storage control method, comprising the steps of:

The storage control method according to claim 11, wherein the confirming the shared bus release specifically includes:

The bus selector determines whether the shared bus is occupied, and if so, sends a bus release signal to a controller occupying the shared bus; if the controller occupying the shared bus is still within a predetermined time period, the bus is The release signal is set to inactive and the shared bus is released when the time period is over.

The storage control method according to claim 11, wherein the specific implementation process of the step B includes:

Bl, the logic unit in the hard disk controller identifies the working mode of the hard disk memory, if it is the PIO mode, step B2 is performed, if it is the UDMA mode, step B3 is performed;

B2, the logic unit strobes the PIO control unit, and the PIO control unit performs PIO mode read and write access control, and ends;

B3, the logic unit strobes the line of the PIO control unit, and sends a UDMA transmission instruction to the hard disk storage;

B4. After receiving the feedback command from the hard disk storage, the UDMA control unit is strobed; B5, the UDMA control unit performs UDMA mode read/write access control.

The storage control method according to claim 13, wherein the specific implementation process of the step B4 includes:

When the hard disk memory recognizes the transfer instruction and prepares the UDMA data transmission, generates a hard disk interrupt signal. When the processor receives the hard disk interrupt signal, queries the hard disk status register to confirm that the hard disk controller performs UDMA data transmission, and switches the location. Logic unit to UDMA mode The logical value should be, and the operating mode configuration register is selected as the write operation.

The storage control method according to claim 14, wherein the specific implementation process of the step B5 includes:

The operation mode configuration register sends an operation instruction to the UDMA control unit, the UDMA control unit recognizes that the operation instruction is a write operation instruction, determines whether a write initialization has been performed, and if not, performs write initialization;

The UDMA control unit detects whether a bus release signal is received;

If a bus release signal is received, the UDMA control unit enters a write suspend state, releases the shared bus, and issues a bus request signal;

If the bus release signal is not received, the UDMA control unit performs a write transfer of one clock cycle of data;

When the write transfer ends, a cyclic redundancy check is sent.

The storage control method according to claim 14, wherein the step B5 includes:

The operation mode configuration register sends an operation instruction to the UDMA control unit, the UDMA control unit recognizes that the operation instruction is a read operation instruction, determines whether to perform over-read initialization, and if not, performs read initialization;

The UDMA control unit detects whether a bus release signal is received;

If the bus release signal is received, the UDMA control unit sets the DMA ready signal to be invalid, continues 0-2 data, enters the read pause state, and releases the shared bus;

If the bus release signal is not received, the UDMA control unit performs a read transfer of data for one clock cycle;

When the read transmission ends, a cyclic redundancy check is sent.