JPS581454B2 - Input/output control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control method suitable for use in an information processing system in which a plurality of input/output devices with different bus interfaces are connected.

When connecting input/output devices with different bus interfaces to an information processing device consisting of a CPU, main memory, and multiple input/output devices connected via a system bus, prepare distinguishable hardware and connect via this. Therefore, control of interrupts, data transfer, etc. becomes complicated.

That is, as shown in FIG. 1, an information processing device including a CPU 2, a main memory 3, and input/output devices 4 and 5 and having a certain bus interface is provided with an input/output device 6 having a different interface from the input/output devices 4 and 5. , 7 is connected to the system bus 1 via input/output adapters 8 and 9.

The input/output adapters 8 and 9 are connected to the input/output device 6.
, 7, and it is necessary to prepare the same number of input/output devices each time an input/output device with a different interface is added.

Therefore, the amount of hardware has increased, control has become complicated, and it has become expensive.

The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to commonly and efficiently control a plurality of input/output devices using one adapter when connecting input/output devices with different bus interfaces to a certain information processing device. The purpose of this invention is to provide an input/output control method that reduces the amount of hardware and simplifies control.

In addition, by dividing the functions between the adapter's hardware and firmware, giving priority to data transfer that requires speed using the hardware, and realizing command and interrupt processing using the firmware, a flexible input/output control method is provided. The purpose is also to

Hereinafter, embodiments of the present invention will be described in detail using FIG. 2 and subsequent figures.

FIG. 2 is a diagram showing an example of a connection configuration of an information processing apparatus to which the present invention is adopted.

In the figure, one adapter device 12 is connected to the system bus 14 as one of the input/output devices 13 originally included in the information processing device, and is an input/output device 16 having a different interface from the input/output device 13 described above. ,17,18(
(connected to the system bus 15), serves as a controller that controls the delivery of input/output commands or interrupts issued from the CPU 11.

19 is a main memory. FIG. 3 is a block diagram showing a schematic internal configuration of the adapter device 12 in FIG. 2. As shown in FIG.

The adapter device 12 is controlled by a microprocessor 121 and serves as a controller for data communication between devices with different bus interfaces.

This adapter device 12 includes a microprocessor 121 serving as a control center, and a ROM 1 22 that stores firmware.
In addition to being used for work, the input/output devices 16, 1
RAM where interrupt requests issued from 7 and 18 are stored
1 23, a bus control section 124 that controls the interface with the CPU 11, and a bus control section 125 that controls the interface with the input/output devices 16, 17, and 18.

126 is data transfer hardware.

Data transfer hardware 126 is shown in detail in FIG. 4 and will not be described here.

Note that the firmware is defined in the ROM 122 and has control procedures programmed in advance using the software language of the microprocessor 121, and is defined in the ROM 122.
It is activated by U11, and the microprocessor 121 reads and executes it.

The adapter device port is located between system buses 14 and 15 and is accessed by both CPU 11 and input/output devices 16, 17, and 18.

At this time, the adapter device 12 transfers input/output commands,
Performs three basic operations: input/output interrupt transfer and data transfer.

These three basic operations will be explained below.

First, command transfer will be explained.

When the CPU 11 outputs input/output commands to the input/output devices 16, 17, and 18, it simultaneously outputs a channel number and command data onto the system bus 14.

When the adapter device 12 recognizes that the channel number specified by the input/output command corresponds to one of the input/output devices 16, 17, and 18 connected to the system bus 15, At the same time, the command data is loaded into the command register and the channel number is loaded into the channel register.

(The command register and channel register built into the adapter device 12 are not shown.) When the microprocessor 121 receives a command request, control by the firmware is started, and the contents loaded in the above registers are stored in the RAM 123. Saved to a fixed address.

When the adapter device 12 receives an input/output command from the CPU 11, it sets the channel number and command register of the input/output command in a built-in register as described above, and then stores it in a fixed area of the RAM 123 by firmware.

Channel and command data are stored serially in this fixed area starting from the beginning.

In the adapter device 12, command reception is processed with top priority.

Therefore, even if the microprocessor 121 is processing other interrupts or the like, when a command request is received, the command is immediately taken in.

When the firmware built into the adapter device 12 recognizes that an input/output command is being output to the input/output devices 16, 17, and 18 connected to the system bus 15, it starts the control described below.

First, the adapter device 12 issues an external interrupt to the CPU 11, and the upper bits (AH, L) set in both the address and length registers of the CPU 11 are sent.
Read the contents of H).

Further, the upper 4 bits of the read AH are already stored in the RAM 123.
Set the fetched channel number to a fixed address in the data register.

After this, in order to specify the addresses of the input/output devices 16, 17, and 18, the addresses are set in the address registers, and the interrupt mode (REG WR
ITE) to interrupt the system bus 15.

This allows the address AH of the CPU to be transferred to the address register (AH) built into the input/output devices 16, 17, and 18.

It is assumed that the address/data/control register is built into the adapter device 12 as an input/output register.

Similarly, an external interrupt is performed to read the lower address AL and write it to the address register built into the adapter device 12.

In the same step, the upper LH and lower LL lengths are taken into the respective registers of the input/output devices 16, 17, and 18.

After this, the adapter device 12 connects the input/output devices 16, 17, 1
8 is activated for input/output, and the command transfer to the system bus 15 is completed.

Next, interrupts will be explained.

I/O devices 16, 1 connected to the system bus 15
7 and 18 interrupt the adapter device 12, and thereafter, the adapter device 12 interrupts the CPU 11 when necessary.

By the way, the input/output device 1 connected to the system bus 15
6, 17, and 18 are determined whether interrupts are possible or not based on the level of the module level.

Each device 11, 1 3, 1 including the adapter device 12
Module level registers are built into modules 6, 17, and 18, and interrupt levels are set in these registers.

For the adapter device 12, input/output devices 16, 17, 18
The module level of is 1 (ML=1), 2 (ML=2)
There are two types of interrupts:

When the input/output devices 16, 17, and 18 are initialized, module level 1 is written to all channels by the adapter device 12.

If an interrupt occurs, it will be interrupted at this module level.

Further, when a mask reset command is issued from the CPU 11 to the input/output devices 16, 17, and 18, the adapter device 1
If the interrupt is not received by input/output device 2, input/output device 1
Write module level 2 to 6, 17, and 18.

In addition, input/output devices 16, 17, 1 that perform external interrupts
8 writes module level 2 by itself when interrupting.

Furthermore, it is assumed that when the CPU 11 receives an interrupt from the adapter device 12, module level 1 is written to all channels.

In the initial state, the module level of the adapter device 12 is "0".

Input/output devices 16, 17 connected to the system bus 15,
When an interrupt occurs from 18, the adapter device 12 compares its own module level set in the built-in module level register with the module levels of the input/output devices 16, 17, and 18, and determines that its own level is smaller. The interrupt will be accepted only in this case.

and its own module level register input/output device 1
6, 17, and 18, and set it as the module level of the adapter device 12.

Here, when an interrupt is accepted, it is masked and processing is performed such that interrupts issued from other sources are not accepted.

The adapter device 12 sends an RE to the input/output devices 16, 17, 18 for which the interrupt has been accepted in order to read the device status of the input/output devices 16, 17, 18.
Perform G READ (status read) and import into the RAM 24 built into the adapter device 12.

Thereafter, the adapter device 12 interrupts the CPU 11.

Here, if the interrupt is not accepted, the RAM 123
Save the necessary information in the judgment area of
A resume interrupt signal (RINT; a signal that notifies an input/output device whose interrupt has been rejected that the interrupt is permitted) is output to prompt another interrupt.

The adapter device 12 informs the CPU 11 of the channel number,
Issue an interrupt using the status as a parameter.

If the interrupt is not accepted here, the information saved in a specific area of the RAM 123 is read out and the interrupt is repeated.

Finally, the data transfer operation will be explained.

The above command transfer and input/output interrupt transfer are managed by firmware, but this data transfer is controlled by hardware.

By transferring the command, the channel address and length are set in the input/output control unit (DMA) of the CPU 11, and the input/output devices 16, 17, and 18 connected to the system bus 15 are also set with the same address and length. Address and length are set in built-in registers.

When the CPU 11 completes one dialog (operations from issuing a request to returning a response) with the adapter device 12 via the system bus 14, it counts up the address of the built-in register (CPU) and counts down the length.

Input/output devices 1 to 6 also connected to the system bus 15
, 17, and 18 also count up/down the values of the built-in registers, respectively.

This is repeated, and when the data transfer is completed, an END interrupt is issued to the CPU 11, and the process ends.

FIG. 4 is a block diagram showing an embodiment of the data transfer hardware 126, and FIG. 5 is a timing chart showing its operation timing.

Input/output devices 16, 17 connected to the system bus 15,
When data transfer is performed from 18, input/output device 16
, 17, 18 are MM READ on the system bus 15
, MM WRITE via any of the control signal lines (CNT0 to CNT3), and a dialog is sent to the adapter device 12.

The adapter device 12 sets one of the flip-flops 41 and 42 provided for each READ/WRITE, and sends an attention signal (
Sends ATN (a signal indicating that an interrupt has occurred from the input/output devices 16, 17, and 18).

At this time, the channel number is set in the upper bits of the address sent from the input/output devices 16, 17, and 18, and the C
When the PU11 receives an interrupt, the CPU11 sends an interrupt signal (TACK;
A signal indicating that requests 7 and 18 have been accepted is sent.

As a result, the AND gate 44 is turned on, and at the same time, the channel number and attention status (A
T S 0 , ATS1, ATS2), data (DA
7 to DA0) to the CPU 11.

When the dialog from the CPU 11 ends, an end signal (E
ATN) is sent to the adapter device 12.

This signal resets the flip-flop 51, outputs a synchronization signal (SSYN; a signal indicating the end of a bus cycle) onto the system bus 15, and
Finish the bus dialogue by 7 and 18.

When reading data from MM (main memory 19), EAT
N (a signal that notifies that the adapter device 12 receives the TACK signal from the CPU 11 and sends the interrupt type, channel number, device number, etc. to the CPU 11), the data obtained from the main memory 19 is stored in the adapter device 12. It is assumed that the data is saved in the data register of 1 and held until the bus dialog by the input/output devices 16, 17, and 18 is completed.

In the figure, 52 to 57 indicate AND gates, and 58 and 59 indicate OR gates.

As explained above, the present invention provides flexibility by controlling data transfer that requires speed using hardware, and controlling command transfer from the CPU and interrupt processing from input/output devices using firmware. One adapter device can efficiently control input/output devices with different interfaces.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a connection configuration of a conventional information processing device, FIG. 2 is a diagram showing an example of a connection configuration of an information processing device according to the present invention, and FIG. 3 is an internal configuration of the adapter device shown in FIG. 2. FIG. 4 is a circuit diagram showing a configuration example of data transfer hardware built into the adapter device, and FIG. 5 is a timing chart showing the data transfer operation. 11...CPU, 12...Adapter device, 13...
・I/O device with a certain interface, 14, 15
...System bus, 16,17,18...I/O devices with different interfaces.

Claims (1)

[Claims] Controls the delivery of input/output commands issued from the CPU and interrupts issued from the input/output device when connecting input/output devices with different interfaces to a system that includes an I CPU and a first bus and has a certain bus interface. A unique adapter consisting of an interface controller built into a processor unit, and transfer hardware that is separated from the processor unit and controls data transfer between the device connected to the first bus and the input/output device. The device is attached to the above CP
By connecting to the first bus as one of the input/output devices of the system including U, the adapter device controls interrupts and data transfer of a plurality of input/output devices connected to the adapter device via the second bus. An input/output control method characterized by: