JP2001056793A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the working ratio of a CPU and to improve the throughput of the entire device in inexpensive high-versatility configuration. SOLUTION: This information processor is provided with a bus 45, input/ output means 420-4215 connected to the bus 45 for inputting/outputting data, a CPU 33 for controlling each of the parts of the device and controlling the data input/output of the input/output means 420-4215 by acquiring the right of use of the bus 45, DMAC 37-40 for controlling the data input/output of the input/output means 420-4215 by acquiring the right of use of the bus 45 and a crossbar switch 44 for supplying four of request signals REQ0-REQ15, which are outputted from the input/output means 420-4215, showing the acquisition request of the right of use of the bus 45 to any one of DMAC 37-40 at a maximum.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a central processing unit (CPU), a memory, a plurality of input / output means, a bus, and a plurality of direct memory access devices. The present invention relates to an information processing apparatus that includes a controller (DMAC) and performs data transfer and other processing between a memory and each input / output unit and between input / output units.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of an electrical configuration of a first conventional information processing apparatus 1 and external devices 2 to 4 connected thereto. Information processing device 1 of this example
A central processing unit (CPU) 5, an arbiter 6, a memory 7, direct memory access controllers (DMACs) 8 to 11, input / output units 12 to 15, and a bus 16 on the same chip. It is constituted by the formed one-chip microcomputer. CPU5
, Memory 7, DMACs 8-11, input / output means 12
To 15 are connected to each other via a bus 16.
Examples of the external devices 2 to 4 include an external storage device such as a floppy disk driver (FDD) and a hard disk driver (HDD), an input device such as a keyboard, a mouse, and a touch pen, and an output device such as a display and a printer. Communication means such as a modem and the like. The input / output means 12 to 15 include, for example, an A / D converter, a serial interface, and a parallel interface.

The arbiter 6 sends a bus from the DMACs 8-11.
A request signal DREQ indicating a request to acquire 16 use rights₀~ D
REQ₃Is supplied to the CPU 5 when any of
No. BREQ and the DMACs 8-11 are reserved.
Priority given to the request signal DREQ₀~ DREQ
₃DMAC8 ~
11 and the bus 16 permitted by the CPU 5
Decide whether to pass the usage right and use the bus 16 from the CPU 5
Permission signal BGNT indicating that the right is granted is supplied
DMACs 8-determined to pass the right to use bus 16
11 is granted permission to use the bus 16
Permission signal DGNT indicating₀~ DGNT ₃Supply.
DMACs 8 to 11 are one-to-one with input / output units 12 to 15.
Yes, and buses from corresponding input / output means 12-15
Request signal REQ indicating a request to acquire 16 use rights ₀~ RE
Q₃Is supplied to the arbiter 6
No. REQ₀~ REQ₃Request signal DREQ corresponding to₀~
DREQ₃Arbiter 6 and bus 16
Permission signal DGNT indicating that the use right acquisition has been permitted
₀~ DGNT₃Is supplied. Obtained right to use bus 16
In any of the DMACs 8 to 11, the corresponding
Between the input / output means and the memory 7 or other input / output means
Data transfer using the bus 16 is performed.

[0004] According to such a configuration, even during the execution of the CPU5 program, by supplying a request signal DREQ ₀ ~DREQ ₃ from DMAC8~11 to the arbiter 6, the arbiter 6 of each DMAC8~11 The right to use the bus 16 is transferred to one of the DMACs 8 to 11 based on the priority, the delay in the supply of the request signals DREQ _{0 to} DREQ ₃ , the supply state, and the like.
1 can use the bus 16 effectively in parallel,
The operating rate of U5 increases, and the overall throughput improves.

FIG. 7 shows an information processing apparatus 21 as a second conventional example disclosed in Japanese Patent Application Laid-Open No. 8-202648.
FIG. 4 is a block diagram showing an example of an electrical configuration of external devices 2 to 4 connected to the device. In this figure, parts corresponding to the respective parts in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. In the information processing apparatus 21 shown in FIG. 7, the arbiter 6, the DMACs 8 to 11 and the input / output means 12 to 12 shown in FIG.
15 and the DMAC 22 and the input / output means 23 to 26
Is newly provided. Information processing device 21 of this example
Is constituted by a one-chip microcomputer in which a CPU 5, a memory 7, a DMAC 22, input / output means 23 to 26, and a bus 16 are formed on the same chip. CPU 5, memory 7, DMAC 22,
The input / output units 23 to 26 are connected to each other via the bus 16. The memory 7 has, for each of the same number of channels as the number of input / output means, a transfer source address indicating a corresponding address on a memory map of the input / output means as a data transfer source, and an input / output means as a data transfer destination. A management table is provided in which a transfer destination address indicating a corresponding address on the memory map and a data transfer count are stored. On the other hand, the DMAC 22 is provided with a group of registers for storing a source address, a destination address, and the number of transfers for one channel.

The DMAC 22 outputs a request signal DRE indicating a request to acquire the right to use the bus 16 from the input / output means 23 to 26.
When any one of Q _{0 to} DREQ ₃ is input, a channel is selected based on a priority order or the like previously assigned to the channel corresponding to each of the input / output units 23 to 26, and the transfer source address and transfer of the selected channel are selected. After reading the destination address and the number of transfers from the management table of the memory 7 and storing them in an internal register group, a request signal BREQ is supplied to the CPU 5,
When the permission signal BACK is supplied from the CPU 5, the bus 16 is sent to the input / output means 23 to 26 corresponding to the selected channel.
Permission signal DACK indicating that the use right acquisition of the
_{0 to} DACK ₃ are supplied. In the DMAC 22, data transfer using the bus 16 is performed between the input / output unit that has acquired the right to use the bus 16 and the memory 7 or another input / output unit. According to such a configuration, the circuit scale is smaller than in the first conventional example.

[0007]

By the way, in the above-mentioned first conventional information processing apparatus, for example, 64 to 12 input / output means such as a telephone electronic exchange are used.
In the case where a large number of DMACs need to be provided, a large number of DMACs must be provided correspondingly, resulting in a disadvantage that the circuit scale becomes large. Moreover,
Even if a large number of DMACs are provided, the bus 1
6 has a limit on the data transfer speed, and in practice, not all input / output means output request signals at the same time, and only a few input / output means output request signals at the same time. Circuit is not used effectively,
Performance is not good. On the other hand, in the information processing apparatus of the second conventional example, even when a large number of input / output units are provided, only one DMAC may be provided. You can only transfer. Therefore, when several input / output units output request signals simultaneously and frequently, channel selection,
Memory 7 for information such as the transfer source address of the selected channel
The number of processes that must be performed in addition to the actual data transfer, such as reading data from and reading data from the registers inside the DMAC 22, increases, and a bus is used for the processes. As a result, the bus utilization of the CPU 5 is hindered, so that the operation rate of the CPU 5 is low, and the overall throughput is reduced. In addition, for a plurality of channels in which the DMAC 22 sets priorities in advance, a channel is selected, information such as a transfer source address of the selected channel is read from the memory 7 and stored in a register group inside the DMAC 22. In order to meet the needs of users, it is time-consuming to verify at the time of design because processing is complicated and malfunctions are likely to occur, and if the number of channels is different, all algorithms must be rebuilt. In such a case, an information processing apparatus must be developed for each number of channels, which requires a development cost and a development period.

The present invention has been made in view of the above circumstances, and provides an information processing apparatus capable of increasing the operation rate of a CPU and improving the throughput of the entire apparatus with an inexpensive and highly versatile configuration. It is intended to be.

[0009]

In order to solve the above problems, an information processing apparatus according to the present invention is connected to at least one bus and the at least one bus to receive data. It controls n output units (n is an integer of 2 or more) and each unit of the device, and acquires the right to use at least one bus to control data input / output in the input / output units. Control means for controlling the data input / output of the input / output means by acquiring the right to use the at least one bus (m is an integer and 2 ≦ m <
n), and among the request signals output from the input / output means and indicating the request to acquire the right to use at least one bus, up to m data transfer control means. And switching means for supplying to any of the above.

According to a second aspect of the present invention, there is provided the information processing apparatus according to the first aspect, wherein the switching unit includes the m data transfer control units out of the request signals output from the input / output unit. And outputs the logical sum of the request signals not supplied to any of the data transfer control means as the interrupt signal. When the interrupt signal is supplied, the control means outputs the most of the m data transfer control means. If the data transfer control means that is not used is selected and the data transfer is being performed in the input / output means controlling the data input / output, the data transfer control means interrupts the data transfer and controls the switching means. Thus, the data transfer control means is supplied with a new request signal, and the request signal which has been supplied to the data transfer control means is added to the logical sum.

According to a third aspect of the present invention, in the information processing apparatus of the second aspect, an acknowledge signal output from the m data transfer control means and indicating that data transfer has been performed is activated. A number-of-use information register in which numbers assigned to the m data transfer control means are stored in the order of time in which the data transfer control means become old, And selecting the least used data transfer control means.

According to a fourth aspect of the present invention, there is provided the information processing apparatus according to the second aspect, wherein the data transfer control means, which is output from the m data transfer control means, is currently performing data transfer. A counter that counts the period during which the busy signal that is active during operation is inactive, and a usage information register that stores a number assigned to the data transfer control unit having the largest count value Wherein the control means selects the least used data transfer control means based on the contents stored in the use status information register.

According to a fifth aspect of the present invention, there is provided the information processing apparatus according to the second aspect, wherein the data transfer control means output from the m data transfer control means is currently performing data transfer. A counter for counting a period during which the busy signal that becomes active during operation is inactive, a number assigned to the data transfer control means having the largest count value, and Numbers respectively assigned to the m data transfer control means are stored in the order of temporal age at which the acknowledge signal output from the data transfer control means and indicating that data transfer has been performed becomes active. The control means, based on the contents stored in the usage information register, It is characterized by selecting over data transfer control means.

According to a sixth aspect of the present invention, there is provided the information processing apparatus according to any one of the first to fifth aspects.
The data transfer control means has individual storage means for storing information relating to data input / output control in the input / output means controlling data input / output, respectively. The entire storage means for storing information about each of the
If data transfer is being performed in the input / output means in which the least-used data transfer control means controls data input / output, the data transfer is interrupted and a new request signal is supplied to the data transfer control means. When controlling the data input / output in the input / output means supplying the new request signal, the information on the data input / output control stored in the individual storage means of the data transfer control means is stored in the entire storage means. After temporarily evacuating to a corresponding storage area, information relating to data input / output control in the input / output unit supplying the new request signal in the overall storage unit is read and stored in the individual storage unit. I have.

According to a seventh aspect of the present invention, there is provided the information processing apparatus according to the sixth aspect, wherein information relating to data input / output control in the input / output unit is read from the overall storage unit, and then read to the overall storage unit. It is characterized in that rewriting of the stored information is prohibited.

The invention according to claim 8 relates to the information processing apparatus according to any one of claims 1 to 7, wherein the at least one bus, the n input / output units, and the control unit The means, the m data transfer control means, and the switching means are constituted by a one-chip microcomputer formed on the same chip.

According to a ninth aspect of the present invention, there is provided the information processing apparatus according to the eighth aspect, wherein the switching means comprises n pieces of n request signals from the n pieces of input / output means. The input lines, (m + 1) output lines, m lines connected to the m data transfer control means and one line connected to the control means, the n input lines, and the (m +
1) n × (m +) provided at the intersection with the output lines
1) transistors.
(M + 1) transistors are turned on / off under the control of the control means, and at most m of the n input lines are connected to any one of the m output lines and the m data lines are connected. The above m connected to the transfer control means
Each of the input lines not connected to any of the output lines is constituted by a crossbar switch connected to the remaining one output line.

The invention according to claim 10 is the invention according to claim 8.
Or, according to the information processing apparatus described in 9, the bus includes the 1
At least one bus provided inside the chip microcomputer or the one-chip microcomputer
It is characterized by comprising at least one bus or both buses provided outside the computer.

[0019] The eleventh aspect of the present invention relates to the first to the first aspects.
0, the data input and output of the n input / output units are each given a priority in advance, and the control unit sets the priority based on the priority. It is characterized in that the switching means is controlled to supply up to m of the request signals output from the input / output means to any of the m data transfer control means.

The invention according to claim 12 is the first invention.
12. The information processing apparatus according to any one of claims 1 to 11, wherein the control means or the data transfer control means obtains a right to use a part of the at least one bus and performs data input / output in the input / output means. Is controlled.

[0021]

According to the configuration of the present invention, the operating rate of the CPU can be increased with a low-cost and highly versatile configuration, and the throughput of the entire apparatus can be improved.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 shows an information processing apparatus 31 according to an embodiment of the present invention and external apparatuses 32 ₁ to 32 ₁ connected thereto.
32 is a block diagram showing an _{15 cases} electrical configuration of. The information processing device 31 of this example includes a CPU 33 and a register group 3
4, arbiter 35, memory 36, DMAC 37 to
40, an interrupt controller 41, and input / output means 42 ₀ to
42 _15, and usage management means 43, the crossbar switch 44 is constituted by a 1-chip microcomputer in which a bus 45 is formed on the same chip. A CPU 33, a register group 34, a memory 36,
DMACs 37 to 40, an interrupt controller 41, input / output means 42 _{0 to} 42 ₁₅ , a use state management means 43,
The crossbar switch 44 is connected to each other via a bus 45. As the external devices 32 _{1 to} 32 ₁₅ , for example, external storage devices such as FDDs and HDDs, keyboards,
There are input means such as a mouse and a touch pen, output means such as a display and a printer, and communication means such as a modem. Also,
As the input / output means 42 _{0 to} 42 ₁₅ , for example, A / D
Converter, serial interface, parallel
There is an interface etc.

The CPU 33 controls each part of the apparatus, and receives an interrupt request signal IREQ ₀ from the interrupt controller 41.
Or, when the IREQ ₁ is supplied, the interrupt processing is executed, the request signal BREQ is supplied to the arbiter 35, and
The arbiter 35 receives a permission signal BGNT indicating that acquisition of the right to use the bus 45 has been permitted. As shown in FIG. 2, the register group 34 includes a crossbar switch control register 34a, a base pointer register 34b, a semaphore register 34c, and other registers. The crossbar switch control register 34a stores C
Data for controlling the crossbar switch 44 is set by the PU 33. Base pointer register 34b
Stores the start address of the management table secured in the memory 36. When the CPU 33 accesses the management table, first, the base pointer register 34b
Is read, and the desired address of the management table is accessed based on the value obtained by adding the values of the channel offset and the register offset to the start address stored in the management table. Note that, in the description of the operation of the apparatus described later, the CPU 3
The reading of the starting address from the base pointer register 34b and the addition of the channel offset and the register offset when the 3 accesses the management table are not particularly described. Semaphore register 34c
Are executed by the CPU 33 and the DMAC 37 to
This register is used for exclusive control to prevent the contents of the management table from being rewritten without consistency due to contention with the data transfer by 40. In addition,
The semaphore register 34c may be provided in a predetermined storage area of the memory 36.

The arbiter 35 includes a CPU 33 and a DMAC.
When the request signal indicating a request for acquiring use right of bus 45 from 37 to 40 BREQ and DREQ ₀ ~DREQ ₃ is input, pre-granted priority to each DMAC37～40, request signal BREQ and DREQ ₀ ~DREQ ₃ , the CPU 33 or the DMACs 37 to 40 determine whether to grant the right to use the bus 45, based on the supply speed and supply state of the CPU 3 and the operation state of the CPU 33.
A permission signal BGNT or DGNT ₀ indicating that acquisition of the right to use the bus 45 has been permitted to the DMAC 33 or the DMACs 37 to 40.
~DGNT ₃ supplies the.

The memory 36 stores various data and the above-mentioned management table is secured. In the management table, 16 terminals corresponding to the number of input terminals of the crossbar switch 44, that is, the number of input / output units 42 _{0 to} 42 ₁₅ are stored.
For each of the channels (referred to as request channels) 0 to 15, a source address indicating the corresponding address on the memory map of the input / output means or the memory 36 as a data transfer source, and a data transfer destination. Input / output means or memory 36
The transfer destination address indicating the corresponding address on the memory map, the number of data transfers, and the mode of data transfer are stored, and various status bits are stored.

The data transfer mode includes a single transfer mode, a single step transfer mode, and a block transfer mode. In single transfer mode, DMAC is 1
This is a transfer mode in which the right to use the bus 45, which has been obtained so far, is abandoned every time data transfer is completed. single·
The step transfer mode is the same as the single transfer mode in that the DMAC relinquishes the right to use the bus 45 acquired so far each time one data transfer is completed. Until the number of transfers of the request channel becomes 0, it refers to a transfer mode in which data transfer of the request channel is performed. In the block transfer mode, once the DMAC accepts a data transfer request, data transfer of the request channel is performed until the number of transfers of the enabled request channel becomes 0. This is a transfer mode in which the request channel is not changed and the byte cycle of the CPU 33 cannot be interrupted even when there is a request for data transfer of a request channel having a higher priority. The various status bits include information indicating which request channel is allocated to which DMAC 37 to 40, information regarding the priority of each request channel, and the like.

The DMACs 37 to 40 output a request signal S indicating a data transfer request output from the crossbar switch 44.
REQ _{0 to} SREQ ₃ are provided in one-to-one correspondence, and when the corresponding request signals SREQ _{0 to} SREQ ₃ are supplied, the request signal SREQ is sent to the arbiter 35.
_{0 to} SREQ ₃ corresponding to the request signals DREQ _{0 to} DREQ
Supplies Q _3, permission signals DGNT ₀ ~ indicating that the use right acquisition of the bus 45 from the arbiter 35 is permitted
DGNT ₃ is supplied. Corresponding enable signal DGNT
Data transfer by the DMACs 37 to 40 after the supply of _{0 to} DGNT ₃ will be described later. Also, each DMA
C37 to 40 each include the corresponding channel (this is DM
A channel), a transfer source address register storing a transfer source address, a transfer destination address register storing a transfer destination address, a transfer count register storing a transfer count, and the DMA channel performing the current data transfer. Transfer state register that stores a transfer state indicating whether or not data is transferred, the transfer mode described above, the data size when reading data from the input / output means or the memory 36 (8 bits, 16 bits, 32 bits ,
64 bits), data size (any of 8 bits, 16 bits, 32 bits, 64 bits) when writing data to the input / output means or the memory 36 to which the data is transferred, information on endian, funneling, etc. Is provided.

Furthermore, each of the DMACs 37 to 40
The busy signals BUSY _{0 to} BUSY ₃ that become active when the MAC is currently performing data transfer are supplied to the use state management unit 43, and the acknowledge signals DACK _{0 to} DACK ₃ indicating that the data transfer has been performed are transmitted.
After the data transfer of one arbitrary unit (reading of data from the transfer source and writing of data to the transfer destination) is completed, the data is supplied to the use state management unit 43. Also, each DMAC 37
40 to the interrupt controller 41 supply completion signals DONE _{0 to} DONE ₃ indicating completion or interruption of data transfer.

In response to an interrupt request based on an interrupt signal INT from the crossbar switch 44, the interrupt controller 41 supplies an interrupt request signal IREQ ₀ to the CPU 33 and complete signals DONE ₀ from the DMACs 37 to 40.
An interrupt request signal IREQ ₁ is supplied to the CPU 33 in response to an interrupt request based on DONE ₃ . Interrupt request signal IR
If the EQ ₀ is supplied, CPU 33, without checking the interrupt factor immediately executes an interrupt process. Further, the interrupt controller 41 outputs completion signals DONE _{0 to} DONE ₃
The CPU 33 has an interrupt information register for storing the number assigned to the DMAC that has supplied the data, and checks the interrupt factor with reference to the interrupt information register, that is, which DMAC performs the transfer. Detect if it has finished.

The usage status management means 43 stores a usage status information record.
And an acknowledge signal DACK₀~ D
ACK₃Is attached to each DMAC 37-40 that supplied
The given numbers 0 to 3 are converted to an acknowledge signal DACK.₀~
DACK₃Became active in order of temporal age (L
RU: Least Recently Used register
And supplied from each DMAC 37-40.
Busy signal BUSY ₀~ BUSY₃Is non-active
Cow counting the average value of each period
DMAC with the largest count value
The given number is stored in the usage information register. CP
U33 refers to the above-mentioned use status register, and
The usage status of 37 to 40 is grasped.
DACK₀~ DACK₃The time when the
DMAs stored in the usage information register in order of age
Of each DMAC 37-40 based on the number of C37-40.
The mode to grasp the usage status is called LRU mode, and it is used
The count value of the counter stored in the status information register is
Each DMAC 37- based on the largest DMAC number
The mode that grasps the usage status of 40 is called the BUSY mode
U. In other words, the CPU 33 has four DMACs 37 to 4
0 is already used, and the input / output
When a request signal REQ is newly supplied from any of the above,
Suspend data transfer by any DMAC
The input / output means that supplied the request signal REQ to the
It is necessary to assign to the DMAC whose transmission has been interrupted.
At this time, if the least used DMAC is selected,
Efficient data transfer, a decision tool for that
Look at the usage register to get the fee.

The crossbar switch 44 is, as shown in FIG.
And 16 input lines 46₀~ 46_FifteenAnd 5 out
Force line 47₀~ 47₄And the input line 46₀~ 46
_FifteenAnd output line 47₀~ 47₄Provided at the intersection with
80 transistors 48₀~ 48₇₉And each input line
46₀~ 46_FifteenIs inserted between the input terminal of
16 pull-up resistors 49₀~ 49_FifteenAnd from
It is abbreviated. Input line 46₀~ 46_FifteenIn
Input / output means 42₀~ 42_FifteenFrom the request signal REQ₀~ R
EQ_FifteenIs applied and the CPU 33
Switch according to the value set in the switch control register 34a.
Transistor 48₀~ 48₃, 48₅~ 48₈, ..., 48
₇₅~ 48₇₈Is turned on / off and the input line 46₀~
46_{1 5}Of the output lines 47₀~ 47₃of
Connected to any one of the request signals SREQ₀~ SREQ₃
Is output as Further, the crossbar is controlled by the CPU 33.
According to the value set in the switch control register 34a,
Transistor 48₄, 48₉, ..., 48₇₉Is on / o
During the initialization process, the input line 46₀~ 46
_FifteenAre output lines 47₄Connected with the request
No. REQ₀~ REQ _FifteenIs ORed as an interrupt signal INT.
The output line 47 is normally output.₀~ 47₃of
Input line 46 not connected to any₀~ 46
_FifteenAre output lines 47₄Connected with the request
No. SREQ₀~ SREQ₃Requests not output as
Signal REQ₀~ REQ_FifteenIs ORed with the interrupt signal INT
And output. The above structure of the crossbar switch 44 is
The input / output means 42₀~ 42_FifteenOutput stage is open
Assume the case of collector type or open drain type
But the input / output means 42₀~ 42_FifteenOutput stage
In the case of the tem pole type, the output line 47₄Multiple
When output lines are connected, problems such as short circuits may occur.
There is a fear that it will be frustrated. In that case, provide some circuit elements and
Defects need to be resolved.
Since it does not directly relate to the invention, the description thereof will be omitted.

Next, the operation of the information processing apparatus having the above configuration will be described with reference to the flowchart shown in FIG. In the following description, the input / output means 42 _{0 to} 42 ₄
From a period and intervals shown in FIG. 5, the request signal _REQ 0 ~
The operation performed by the CPU 33 and the like when REQ ₄ is output will be described. In this case, the CPU 33
The usage status of the four DMACs 37 to 40 is grasped in the U mode. First, an initialization process is performed. Step S
In P1, the CPU 33 executes an initialization process for initializing each unit of the device. In other words, the CPU 33
After securing a management table for 16 request channels in a predetermined storage area, the storage contents are cleared and initialized to a state without inconsistency. Similarly, the CPU 33
After securing a transfer source address register, a transfer destination address register, a transfer count register, a transfer status register, and a transfer mode register in the register group provided in C37 to C40, the stored contents are cleared, and there is no contradiction. Initialize to Then, CPU 33, by setting the predetermined value to the crossbar switch control register 34a, the transistors ₄₈ 0 _{to 48} 3 shown in FIG. 3, ₄₈ 5 ~
48 _{8, ...,} dissipate off none of the 48 _{75-48 78,} transistor _{48 4,} 48 9, ..., _{48 79}
Both were on the, none of input lines ₄₆ 0 _{to 46 15} of the crossbar switch 44 is connected to the output line 47 _4, so that the logical OR of the request signal _REQ 0 _{~REQ 15} is outputted as an interrupt signal INT To Further, C
The PU 33 clears the contents stored in the interrupt information register provided inside the interrupt controller 41 and the usage state information register provided inside the usage state management means 43, and initializes the state to a consistent state. . This completes the initialization processing.

In step SP2, the CPU 33
A start process for starting data transfer by the MACs 37 to 40 is executed. That is, the CPU 33 first reads, modifies, writes, and writes data to obtain the right to access the management table provided in the memory 36.
In the cycle, the value “0” is read from the semaphore register 34 c constituting the register group 34, then the value “1” is written into the semaphore register 34 c and the transfer source is stored in a predetermined storage area of the management table for each request channel. Information such as an address, a transfer destination address, a transfer count, a transfer state, and a transfer mode is written. Thereafter, the CPU 33 writes the value “0” to the semaphore register 34c in order to release the access right to the management table. That is, access right exclusion processing is performed using the semaphore register 34c, thereby preventing the contents of the management table from being erroneously rewritten. Therefore, neither the DMAC nor the CPU 33 can obtain the access right to the management table repeatedly, and the contents of the management table are not changed before and after the data transfer. If the access right to the management table cannot be obtained, C
Both the PU 33 and the DMAC store the value “1” in the semaphore register 34 c.
To give up access to the management table.

Next, a transfer setup process is executed. At step SP3, the CPU 33
2 _0-42 to run the ₁₅ setup. That is,
Setup of the input and output means _{42 0-42 15,} the output means _{42 0-42 15} is a process for the state can start data transfer immediately. For example, if a certain input / output means 42 is a SCSI (Small Computer System
rface) is a parallel interface based on the standard, and when the external device 32 connected thereto is an HDD,
The PU 33 transfers a data read command or a data write command for the data transfer target sector to the input / output means 42 and performs data read or data write setup. Thus, the input / output means 42 can output the request signal REQ at any time. This completes the transfer setup process. With these settings, the external device starts processing data. The input means receives a data input request from these external devices and generates a request signal REQ to perform data transfer. This request signal is transmitted to the interrupt controller 41 via the crossbar switch 44 if the actual DMA channel has not been allocated yet. The interrupt controller interrupts the CPU 33 and requests the DMA transfer engine to perform an allocation process.

If there is an interrupt, an interrupt process is executed. This
The process of (1) is the actual assignment and opening of the DMA transfer channel.
Release and end processing. Step SP
In step 4, the CPU 33 issues an interrupt from the interrupt controller 41.
Request signal IREQ₀Or IREQ₁Is supplied or not
Judge. If the result of this determination is "NO",
Check for interrupts. And the interrupt controller 41
Interrupt request signal IREQ ₀Or IREQ₁Is supplied
And the result of the determination in step SP4 is "YES", and C
The PU 33 proceeds to Step SP5. In this case,
In the initialization process of step SP1, the cross bus shown in FIG.
Input line 46 of switch 44₀~ 46_FifteenAny of
Output line 47₄And the request signal REQ₀~ RE
Q_FifteenIs output as an interrupt signal INT.
It has become. Therefore, for example, as shown in FIG.
Time t₀Input / output means 42₀To memory 36
Input / output means to transfer data to a predetermined storage area
Step 42₀From the request signal REQ₀Is activated
When supplied to the loss bar switch 44, the request signal REQ₀
Is output as an interrupt signal INT, and the interrupt controller 4
1 is supplied. Thereby, the interrupt controller 41
Is an interrupt request signal IREQ to the CPU 33.₀To supply
As a result, the determination result of step SP4 becomes "YES", and C
The PU 33 proceeds to Step SP5.

At step SP5, the CPU 33 sends the interrupt request signal supplied from the interrupt controller 41 to each DM.
Completion signals DONE _{0 to} DONE ₃ from ACs 37 to 40
Is determined to be an interrupt request signal IREQ ₁ corresponding to an interrupt request based on If the result of this determination is “YES”, the CPU 33 proceeds to step SP11. on the other hand,
If the decision result in the step SP5 is "NO", that is, the request signal REQ to which the DMAC is not assigned is supplied, and the interrupt request signal IR
If the EQ ₀ is supplied, CPU 33 proceeds to step SP6. In this case, since the interrupt request signal IREQ ₀ is supplied from the interrupt controller 41, the result of the determination in step SP5 is “NO”, and the CPU 33 proceeds to step SP6.

In step SP6, the CPU 33 refers to the use state information register provided inside the use state management means 43 and grasps the use state of each of the DMACs 37 to 40. Select In this case, since data transfer is not performed in all DMACs 37 to 40, no value is written in the usage information register.
It is assumed that the MAC 37 has been selected. At step SP7, the CPU 33 selects the D selected at step SP6.
It is determined whether the MAC is currently in a data transfer state.
That is, the CPU 33 refers to the transfer state register provided inside the DMAC selected in the process of step SP6 to check whether or not the DMA channel is currently performing data transfer. ,
That is, if the result of the determination in step SP7 is "YES", the flow proceeds to step SP8. On the other hand, step SP6
If the DMAC selected in the processing of step (3) is not currently in the data transfer state, that is, the determination result of step SP7 is "NO"
In this case, nothing is performed, and the process proceeds to step SP9. In this case, since data transfer has not been performed in all DMACs 37 to 40, the result of the determination in step SP7 is "N
O ", the CPU 33 does nothing and proceeds to step SP9.
Proceed to.

At step SP8, the selected DMAC
Suspends the data transfer process being executed and saves information (transfer source address, transfer destination address, etc.) of the interrupted transfer channel to the management table for use in other data transfer processes. The CPU 33 saves the information of a certain request channel stored in the register group provided inside the DMAC selected in the processing of step SP6, in order to save the information of the corresponding request channel in the management table provided inside the memory 36. Write to storage area. In this case, similarly to the processing in step SP3 described above, the CPU 33 firstly performs a read-modify-write-write operation to obtain an access right to the management table provided in the memory 36.
After reading the value “0” from the semaphore register 34 c constituting the register group 34 in the cycle, the value “1” is written into the semaphore register 34 c, and the value is written to the register group provided inside the DMAC selected in the process of step SP6. Information such as the stored transfer source address, transfer destination address, transfer count, transfer state, and transfer mode of a certain request channel is written to a predetermined storage area of the management table. After this, CPU3
3 is to release the access right to the management table,
Write the value "0" to the semaphore register 34c.

In step SP9, the CPU 33 first reads the value "0" from the semaphore register 34c in a read-modify-write cycle in order to acquire the right to access the management table, and then stores the value in the semaphore register 34c. The value “1” is written, and information such as the transfer source address is read from the storage area of the management table of the request channel corresponding to the input / output means that supplied the request signal REQ.
The information such as the transfer source address stored in the register group provided inside the DMAC selected in step SP6 and stored in the storage area corresponding to the request channel in the management table is not rewritten during data transfer. In order to do so, lock data indicating write-protection is written. Thereafter, the CPU 33 writes the value “0” to the semaphore register 34c in order to release the access right to the management table. In the present case, because of supplying the request signal REQ ₀ is output means 42 _0, the request channel corresponding a request channel 0. Therefore, CPU3
3 reads information such as a transfer source address from a storage area corresponding to the request channel 0 in the management table, and
The lock data is stored in each of the 37 register groups and the lock data is written in the storage area corresponding to the request channel 0 in the management table.

In step SP10, CPU 33, by setting the predetermined value to the crossbar switch control register 34a constituting the register group 34, the transistor ₄₈ 0-4 constituting the crossbar switch 44 shown in FIG. 3
₈₇₉ is turned on / off, and the request signal REQ that has been supplied to the DMAC selected in the processing of step SP6 has been supplied.
Output line ₄₇ one of the _{0 ~REQ 15 0 ~47 3}
The cleavage from either, causes output as an interrupt signal INT connected to the output line 47 _4, Step SP
The request signal RE corresponding to the interrupt request signal IREQ ₀ determined to have been supplied from the interrupt controller 41 in the processing of step 4
Any of Q _{0 to} REQ ₁₅ is output to output lines 47 _{0 to} 47
₃ to request signals SREQ _{0 to} SREQ
₃ and output it to the DMAC selected in the process of step SP6, and then terminate this interrupt process. In the present case, a DMAC37 is was selected in the processing in step SP6, the input-output unit 42 ₀ is to correspond to the interrupt request signal IREQ ₀ which is determined to have been supplied from the interrupt controller 41 in the process of step SP4 is a request signal REQ _0, and since the DMAC37 not supplied any request signals _REQ 0 _{~REQ 15} ever, by setting the predetermined value to the crossbar switch control register 34a by CPU 33, the request signal REQ
₀ is output from the crossbar switch 44 as the request signal SREQ ₀ and supplied to the DMAC 37.

Next, a data transfer process is executed. DM
AC37 receives a request signal SRE from the crossbar switch 44.
When Q ₀ is supplied, the data transfer operation is started.
The request signal DREQ ₀ is activated and supplied to the arbiter 35. When the request signal DREQ ₀ is input, the arbiter 35 determines the priority of each of the DMACs 37 to 40 and the CP.
Based on the operating state of U33, determines whether to permit the use right of the bus 45, when it is determined to allow the use right acquisition of the bus 45 DMAC37 supplies a permission signal DGNT ₀ to DMAC37. The DMAC 37 outputs the permission signal D
When GNT ₀ is supplied, data is read from the source of data indicated by the source address written in the source address register with the data size written in the transfer mode register, and written to the destination address register. The data indicated by the transfer destination address is written to the transfer destination. In this case, the DMAC 37 subtracts the data size from the transfer count written in the transfer count register for each data transfer, and completes if the value of the transfer count register has reached the data transfer end value. Signal D
ONE ₀ is supplied to the interrupt controller 41. Thereby, the interrupt controller 41 responds to the interrupt request based on the completion signal DONE ₀ from the DMAC 37 by the CPU 33.
DMAC 37 which supplied an interrupt request signal IREQ ₁ to the CPU and supplied a completion signal DONE ₀ to the interrupt information register.
Is stored.

The DMAC 37 supplies the busy signal BUSY ₀ as active to the use state management means 43 during the data transfer operation, for example, when reading the transfer source address written in the transfer source address register, and acknowledges the busy signal. After the data transfer of the signal DACK ₀ in one arbitrary unit (reading of data from the transfer source and writing of data to the transfer destination) is completed, the use state management unit 43
Supply to As a result, the usage status management means 43
Acknowledge signal DACK ₀ supplied from MAC 37
The number 0 assigned to the DMAC 37 is stored in the usage status information register based on the fact that the acknowledge signal DACK ₀ has become active, and the busy signal BUSY ₀ is inactive (see FIG. 5 (1)). in the example), the counter for counting the approximate period from time t ₀ to time t ₅₎ starts counting.
This ends the data transfer process.

When the data transfer process is completed, a completion signal DONE ₀ is supplied to the interrupt controller 41, and the interrupt process is executed. Both steps SP4 and SP5 become "YES", and step SP11 which is a management table update process is executed. In step SP11, the CPU
33 reads the number assigned to the DMAC stored in the interrupt information register provided inside the interrupt controller 41, and recognizes that the data transfer has been completed by the DMAC. Then, the CPU 33 releases the assignment of the transfer channel to the DMAC for which the data transfer has been completed, and stores the information of a certain request channel stored in the register group provided therein to the management table provided in the memory 36. After writing to the storage area of the corresponding request channel, the lock data is erased and the lock is released. in this case,
As in the processing of step SP3 described above, the CPU 33
First, to gain access to the management table,
In the read-modify-write cycle, after reading the value "0" from the semaphore register 34c, the value "1" is written to the semaphore register 34c, and the value is stored in a register group provided inside the DMAC after the data transfer is completed. The information such as the transfer source address of a certain request channel is written in the management table. Thereafter, the CPU 33 releases the semaphore register 3 to release the access right to the management table.
Write the value "0" to 4c.

The subsequent, as shown in FIG. 5 (2) to (4), the other input-output means ₄₂ 1 to 42 _3, respectively from the time t
_1, when the request signal _REQ 1 _{~REQ 3} became active is sequentially supplied to the crossbar switch 44 at time _{t 2} and time _{t 3,} the process of step SP4~SP10 described above, the request signal _REQ 1 _{~REQ 3} There through the crossbar switch 44 are sequentially supplied to the other DMAC38～40, the transfer source or transfer destination data transfer output means ₄₂ 1 to 42 ₃ with each DMAC38～40 performed. That is, up to four request signals REQ, 4
DMACs 37 to 40 each have four request signals RE
Since it is involved in data transfer corresponding to Q, the data transfer can be performed independently for the four input / output means without any trouble.

Next, the time _{t 4} in a state that is already used any of the four DMAC37～40, the request signal REQ ₄ from input unit 42 ₄ becomes active (FIG. 5
(Refer to (5)) Data transfer after that will be described. Output from the output means 42 ₄ request signal REQ ₄
Crossbar switch 44 is active in but time t ₄
, The request signal REQ ₄ is output as an interrupt signal INT and supplied to the interrupt controller 41. Thus, the interrupt controller 41, since supply an interrupt request signal IREQ ₀ to CPU 33, CPU 33 refers to the usage information register provided in the use status management means 43, each DMAC37~40 After grasping the usage status, the DMAC that has not performed the data transfer most is selected. In this case, as can be seen from FIGS. 5A to 5D, the request signal REQ ₀ is the oldest and non-active, and the request signal REQ ₀ is supplied to the DMAC 37. No. 0 assigned to the DMAC 37 must be stored as the oldest one in the usage status information register. So, CPU
33 selects the DMAC 37 as the DMAC that has not performed the data transfer most.

Next, the current DMAC 37 outputs the request signal REQ.
_{Since the} data transfer is being performed for the request channel 0 corresponding to 0, the data transfer must be temporarily stopped. However, the transfer source address of the request channel 4 corresponding to the request signal REQ ₄ to be transferred from now on is stored in the register group of the DMAC 37. Overwriting information such as this will make it impossible to resume the data transfer of the request channel 0 corresponding to the request signal REQ ₀ that has been temporarily interrupted after the data transfer is completed. It is necessary to temporarily save information such as the transfer source address of the request channel 0 corresponding to the signal REQ ₀ to a predetermined storage area of the corresponding management table. Therefore, CPU3
3 is the DMAC3 in the processing of step SP8.
The information of the request channel 0 stored in the register group 7 is
Write to the storage area of the request channel 0 in the management table.
In this case, the CPU 33 first reads the value "0" from the semaphore register 34c in a read-modify-write cycle in order to acquire the right to access the management table, and then stores the value "1" in the semaphore register 34c. Write, the information such as the transfer source address of the request channel 0 stored in the register group of the DMAC 37 is written in a predetermined storage area of the management table. Thereafter, the CPU 33 writes the value “0” to the semaphore register 34c in order to release the access right to the management table.

Next, the CPU 33 first sets the management table
In order to gain access to the
In the write cycle, the semaphore register 34c
After reading the value "0", the value "0" is stored in the semaphore register 34c.
Write 1 "and request signal REQ₄I / O hands that supplied
Step 42₄Of management table of request channel 4 corresponding to
Reads information such as the transfer source address from the storage area,
The information is stored in the register group of the AC 37 and the management table
Stored in the storage area corresponding to the request channel 4
Information such as the source address is rewritten during data transfer.
Write the lock data to make sure it does not exist. this
Thereafter, the CPU 33 releases the access right to the management table.
Write the value "0" to the semaphore register 34c
No. Then, the CPU 33 forms the register group 34
Set a predetermined value in the crossbar switch control register 34a
By doing so, the crossbar switch 44 shown in FIG.
Transistor 48 to be formed₀~ 48₇₉On / off
And the request signal REQ ₄Request signal SREQ₀As DM
AC37 and the request signal REQ₀Interrupt
It is supplied to the interrupt controller 41 as a signal INT.
The subsequent processing of the DMAC 37 is described in
Force means 42₀The description is omitted because it is almost the same as
Abbreviate.

Next, become a time _{t 5,} request signal REQ ₀
If but becomes active again, as can be seen from FIG. 5 (1) to (4), the request signal REQ ₂ has oldest becomes inactive, the request signal REQ ₂ is DMAC39
, The usage status information register of the usage status management means 43 stores the number 2 assigned to the DMAC 39.
Must be remembered as the oldest. Therefore, the CPU 33 selects the DMAC 39 as the DMAC that has not performed the data transfer most. Therefore, DM
Request channel 2 stored in the register group of AC39
Information is temporarily saved to the management table, temporarily suspended,
After the writing of the management table of the saved request channel 0 had information to the register group DMAC39 is performed, the output means 42 ₀ transfer source in DMAC39, a memory 36 the data transfer is resumed destination You. Similarly, if the time t _6, the request suspended data transfer channels 0 and the data transfer request channel 2 resume is performed, if the time t _7, suspended the requested data transfer request channel 2 resumption of the data transfer channel 0 is performed, if the time t _8, the request suspended data transfer channel 4 and resuming data transfer request channel 2 is performed. Hereinafter, the same applies.

Then, at time t ₉ , the data transfer of the request channel 1 ends, so that the DMAC 38 supplies the completion signal DONE ₁ to the interrupt controller 41. Thereby, the interrupt controller 41 responds to the interrupt request based on the completion signal DONE ₁ from the DMAC 38 by
The DMA which supplied the interrupt request signal IREQ ₁ to the U33 and supplied the completion signal DONE ₁ to the interrupt information register
The number 1 assigned to C38 is stored. Therefore, C
The PU 33 reads the number 0 assigned to the DMAC 38 stored in the interrupt information register of the interrupt controller 41, and recognizes that the data transfer has been completed by the DMAC 38. Then, the CPU 33 releases the assignment to the DMAC 38 to which the data transfer has been completed, and then, in order to acquire the access right to the management table, executes the read modify
In the write cycle, the value from the semaphore register 34c is read.
After reading "0", the value "1" is stored in the semaphore register 34c.
And writes information such as the transfer source address of the request channel 1 stored in the register group of the DMAC 38 to the management table. Thereafter, the CPU 33 releases the semaphore register 34c to release the access right to the management table.
After the value "0" is written in the register, the lock data is erased and the lock is released.

As described above, according to the configuration of this example, the number of DMACs is smaller than the number of
Even when the request signal REQ is supplied in a number equal to or greater than the number of C, the use state management means 43 grasps the least used DMAC, and can be manufactured by the same manufacturing method as the memory, and the crossbar with extremely few malfunctions can be manufactured. Using the switch,
Since the newly supplied request signal REQ is supplied to the least used DMAC, data transfer using the DMAC can be efficiently performed with a cheap and simple configuration. Comparing the configuration of this example with a configuration in which 16 DMACs are provided corresponding to 16 input / output units in the first conventional example, the circuit scale can be reduced to about 1/4 to 1/3. . In particular, when the number of simultaneously supplied request signals REQ is four or less, C is only used when switching the crossbar switch 44 and rewriting information such as the source address.
Since only the PU is involved, the operating rate of the CPU can be increased, and the throughput of the entire apparatus can be improved. Further, even when the number of request signals REQ supplied simultaneously is five or more, as shown in FIGS. 5 (2) and (4),
A DMAC that is performing data transfer with a high transfer rate can perform efficient data transfer because the data transfer is not interrupted. Further, according to the configuration of this example, even when the number of input / output means is increased or the number of DMACs is increased, an algorithm or the like is constructed from the beginning as in the second conventional example. It is not necessary to correct the input line 46, which constitutes the crossbar switch 44,
Since only a few modifications such as increasing the number of output lines 47 and transistors 48 and securing the storage area of the management table of the memory 36 are sufficient, the versatility is high, and the development cost and the development period are reduced. Further, according to the configuration of this example, the information such as the transfer source address stored in the management table is not rewritten during the data transfer or the data transfer is interrupted by using the semaphore register 34c and the lock data. Therefore, consistency of information can be maintained, and interruption and restart of data transfer can be performed accurately and easily.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and changes in the design and the like can be made without departing from the gist of the present invention. Even if there is, it is included in the present invention. For example, in the above-described embodiment, an example in which four DMACs are provided has been described. However, the present invention is not limited to this. For example, two to eight DMACs may be provided depending on the number of input / output units. In the above-described embodiment, the example in which the CPU 33 grasps the usage status of the four DMACs 37 to 40 in the LRU mode has been described. However, the present invention is not limited to this.
Using the BUSY mode, the usage status of AC37-40
Or you may make it grasp | ascertain by combining LRU mode and BUSY mode.

In the above-described embodiment, the interrupt controller 41 is provided, and when a request signal REQ is newly supplied to more than the number of DMACs 37 to 40, the DMAC
Has been described, the data transfer by any of the input / output means that has newly supplied the request signal REQ is executed by temporarily suspending the data transfer in any one of the above. However, the present invention is not limited to this. For example, even if a request signal REQ is newly supplied without providing the interrupt controller 41, if all four DMACs are transferring data, the data by the input / output means that supplied the request signal REQ is Reserve transfer 4
When data transfer is completed in any of the DMACs, the data transfer by the input / output means may be started. Even in this case, it is possible to effectively use the four DMACs. In the above-described embodiment, the request signal REQ is output again for the input / output means in which the data transfer is temporarily interrupted by the interrupt processing, and only when the request signal REQ is given priority over other request signals REQ, Although the example in which the transfer is restarted has been described, the present invention is not limited to this. For example, when the acknowledge signal ACK becomes non-active in any DMAC,
Instead of waiting for the output of the request signal REQ, the temporarily suspended data transfer of the input / output means may be restarted preferentially.

[0053] In the above embodiment, input-output means _{42 0-42} but ₁₅ not specifically granted priority to, not limited to this, pre-output means ₄₂ 0-42
_{15 as well} as an external device having a high data transfer speed, for example, an HDD (transfer speed of about 50 Mb
/ S) or the like may be configured to connect to the input / output means 42 having a higher priority. In this case, the request signal REQ supplied from the input / output unit 42 having a higher priority is fixedly supplied to a predetermined DMAC, and even if the request signal REQ is supplied from another input / output unit, the DMAC is surrendered. If it is not configured, more efficient data transfer can be performed. Further, in the above-described embodiment, an example has been described in which all four DMACs have the same function. However, the present invention is not limited to this. For example, the data size (8 bits , 16 bits, 32 bits, etc.). Further, in the above-described embodiment, an example has been described in which the management table is provided inside the memory 36. However, the present invention is not limited to this, and the management table may constitute the register group 34.

In the above-described embodiment, an example in which one bus 45 is provided inside the information processing apparatus 31 has been described. However, the present invention is not limited to this, and two or more buses may be provided. An external bus is provided outside the external bus 31 so that data can be transferred between the memory and the input / output means connected to the external bus and the memory 36 and the input / output means 42 _{0 to} 42 ₁₅ connected to the bus 45. May be. In this case, the external bus may be configured to be used in parallel with the bus 45, or may be configured to be connected in series and used.
Further, in the above-described embodiment, an example has been described in which the right to use the entire bus 45 is acquired.
5 are provided with a plurality of gates,
Under the control of the U33 or the DMACs 37 to 40, a certain DMAC may acquire only a necessary portion of the bus 45 and transfer the data. Taking as an example the configuration shown in FIG. 1, when the data transfer between the input and output means 42 ₁ and the input-output unit 42 _2, of the bus 45, the memory 3
6, since the input and output unit 42 ₀ is not used portions connected, the gate provided between the input and output means 42 ₀ and output means 42 _1, DMAC37 is closed the gate, the input and output of bus 45 and the data transfer has won only use right of a portion means 42 ₁ and the output means 42 ₂ is connected, C is the portion of DMAC37 has not won the bus 45
The PU 33 may use it.

Further, in the above-described embodiment, the example in which the information processing apparatus 31 is constituted by a one-chip microcomputer has been described. However, the present invention is not limited to this.
AC37~40, memory 36 and input and output means ₄₂ 0-42
_{15 and the} like are replaced with stand-alone type devices, and the bus 45 is made up of a cable, so that the entire device is connected to a local area network (LA).
N) or the like. Also,
In the above embodiment, the CPU 33 and the DMAC 37 to
Although an example having a master-slave relationship with 40 has been shown, the present invention is not limited to this. By replacing the DMACs 37 to 40 with a digital signal processor (DSP) or the like,
A configuration in which parallel processing is performed may be adopted.

[0056]

As described above, according to the structure of the present invention, although the number m of the data transfer control means is smaller than the number n of the input / output means, the output from the input / output means by the switching means. Of the request signals, up to m request signals are flexibly supplied to any of the m data transfer control means, so that data transfer using the data transfer control means can be efficiently performed with an inexpensive and simple configuration. It can be carried out. In particular,
When the number of simultaneously supplied request signals is less than m,
Since the control means is involved only when the switching means is switched, the operation rate of the control means can be increased, and the throughput of the entire apparatus can be improved. Further, according to another configuration of the present invention, when an interrupt signal is supplied from the switching unit as a logical sum of the request signals not supplied to any of the m data transfer control units, the control unit performs , Selecting the least used data transfer control means from the m data transfer control means, interrupting data transfer in the input / output means controlling the data input / output by the data transfer control means, Controlling the means to supply a new request signal to the data transfer control means and adding the request signal that has been supplied to the data transfer control means to the logical sum, so that the transfer speed is reduced. Data transfer in the data transfer control means that is used quickly and frequently is not interrupted, and efficient data transfer can be performed.

Further, according to another configuration of the present invention, after reading information relating to data input / output control in the input / output means from the entire storage means, rewriting of information stored in the entire storage means is inhibited. Since the information stored in the overall storage means is not rewritten during data transfer or during data transfer interruption, information consistency can be maintained, and data transfer interruption and restart can be performed accurately and It can be done easily. Further, according to another configuration of the present invention, the switching means includes: n input lines to which n request signals from n input / output means are applied;
Books are connected to m data transfer control means, and one is provided at the intersection of (m + 1) output lines connected to the control means, n input lines and (m + 1) output lines. Since it is composed of n × (m + 1) transistors, even if the number of input / output means is increased or the number of data transfer control means is increased, an algorithm or the like is reconstructed from the beginning. There is no need to increase the number of input lines, output lines, and transistors that constitute the switching means, so verification at the time of design is extremely easy, versatility is high, development costs and development time are small. I'm done.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an information processing apparatus according to an embodiment of the present invention and a plurality of external devices connected thereto.

FIG. 2 is a block diagram illustrating an example of a configuration of a register group.

FIG. 3 is a circuit diagram illustrating an example of a configuration of a crossbar switch.

FIG. 4 is a flowchart for explaining an example of the operation of the device.

FIG. 5 is a timing chart for explaining an example of the operation of the device.

FIG. 6 is a block diagram showing an example of an electrical configuration of a first conventional information processing apparatus and a plurality of external devices connected thereto.

FIG. 7 is a block diagram showing an example of an electrical configuration of a second conventional information processing apparatus and a plurality of external devices connected thereto.

[Explanation of symbols]

Reference Signs List 31 information processing device 32 _{1 to} 32 ₁₅ external device 33 CPU (control means) 34 register group 35 arbiter 36 memory 37 to 40 DMAC (data transfer control means) 41 interrupt controller 42 _{0 to} 42 ₁₅ input / output means 43 use state management Means 44 Crossbar switch (switching means) 45 Bus

Claims (12)

[Claims] At least one bus, n (n is an integer of 2 or more) input / output means connected to the at least one bus for inputting / outputting data, and controlling each unit of the apparatus. Control means for acquiring the right to use the at least one bus and controlling data input / output in the input / output means; and acquiring data for the right to use the at least one bus and inputting / outputting data in the input / output means (M is an integer and satisfies 2 ≦ m <n) data transfer control means, and a request signal output from the input / output means and indicating a request to acquire the right to use the at least one bus A switching unit for supplying up to m data transfer control units to any of the m data transfer control units. 2. The switching means outputs, as an interrupt signal, a logical sum of request signals, which are not supplied to any of the m data transfer control means, among the request signals output from the input / output means. The control means, when the interrupt signal is supplied,
If the least used data transfer control means is selected from the m data transfer control means, and the data transfer control means controls the data input / output, the data transfer is performed by the input / output means. For example, interrupting this, controlling the switching means to supply a new request signal to the data transfer control means, and adding the request signal previously supplied to the data transfer control means to the logical sum. The information processing apparatus according to claim 1, wherein: 3. The m data transfer control means are provided with an acknowledgment signal output from the m data transfer control means in the order of time when the acknowledge signal becomes active. A use status information register in which an assigned number is stored, wherein the control unit selects the least used data transfer control unit based on the storage content of the use status information register. The information processing apparatus according to claim 2, wherein: 4. A busy signal output from the m data transfer control means, which is active when the data transfer control means is currently performing data transfer and is in operation, is non-active. A counter for counting each period, and a usage information register in which a number assigned to the data transfer control means having the largest count value is stored, wherein the control means stores the content of the usage information register in 3. The information processing apparatus according to claim 2, wherein the least-used data transfer control means is selected based on the data transfer control means. 5. A busy signal output from the m data transfer control means, which is currently performing data transfer and becomes active when the data transfer control means is operating, is non-active. A counter that counts each period and a number assigned to the data transfer control unit with the largest count value are stored,
Numbers respectively assigned to the m data transfer control units in the order of temporal aging at which the acknowledge signal output from the m data transfer control units indicating that data transfer has been performed become active are provided. 3. The storage device according to claim 2, further comprising: a use status information register that is stored, wherein the control unit selects the least used data transfer control unit based on the storage content of the use status information register. An information processing apparatus according to claim 1. 6. The m data transfer control means has individual storage means for storing information relating to data input / output control in input / output means controlling data input / output, respectively, and the n data transfer control means comprises: An overall storage unit in which information relating to data input / output control in the output unit is stored, wherein the control unit controls data transfer in the input / output unit in which the least used data transfer control unit controls data input / output. If this is performed, this is interrupted, and the data transfer control means is supplied with a new request signal to control the data input / output in the input / output means supplying the new request signal. After temporarily saving the information relating to the data input / output control stored in the individual storage means of the data transfer control means to the corresponding storage area of the overall storage means 6. The information processing apparatus according to claim 1, wherein information relating to data input / output control in the input / output unit supplying the new request signal in the overall storage unit is read and stored in the individual storage unit. An information processing apparatus according to claim 1. 7. After reading information relating to data input / output control in said input / output means from said overall storage means,
7. The information processing apparatus according to claim 6, wherein rewriting of the information stored in the overall storage unit is prohibited. 8. The at least one bus, the n input / output means, the control means, the m data transfer control means, and the switching means are formed on a same chip. 8. A device according to claim 1, wherein said one-chip microcomputer is used.
An information processing apparatus according to claim 1. 9. The switching means is connected to n input lines to which n request signals from the n input / output means are applied, and m are connected to the m data transfer control means,
One (m + 1) output lines connected to the control means, and n × (m + 1) transistors provided at the intersection of the n input lines and the (m + 1) output lines. Wherein the n × (m + 1) transistors are turned on / off under the control of the control means, and at most m of the n input lines are connected to any of the m output lines. And a crossbar switch in which any of the input lines not connected to any of the m output lines connected to the m data transfer control means is connected to the remaining one output line. 9. The information processing apparatus according to claim 8, wherein the information processing is performed. 10. The bus may include at least one bus provided inside the one-chip microcomputer and / or at least one bus provided outside the one-chip microcomputer. The information processing apparatus according to claim 8, wherein the information processing apparatus comprises a bus. 11. A priority order is set in advance for each of the data input / output in said n input / output means,
The control unit controls the switching unit based on the priority order, and causes up to m of the request signals output from the input / output unit to be supplied to any of the m data transfer control units. The information processing apparatus according to claim 1, wherein: 12. The data transfer control means according to claim 12, wherein said control means or said data transfer control means obtains a right to use a part of said at least one bus and controls data input / output in said input / output means. 12. The information processing device according to any one of 1 to 11.