WO2007049356A1

WO2007049356A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2007049356A1
Application number: PCT/JP2005/019931
Authority: WO
Inventors: Tomoko Higashino; Chuichi Miyazaki
Original assignee: Renesas Technology Corp.
Priority date: 2005-10-28
Filing date: 2005-10-28
Publication date: 2007-05-03

Abstract

On a main plane of a wafer (1), a plurality of chip areas (1A’) separated from each other by scribe areas (SA) having a width of several μm are formed. A planar shape of the chip area (1A’) is rectangular with chamfered corner sections. The scribe area (SA) in an area in contact with the corner section has a wider width compared with widths of other areas, and has a TEG (2) arranged thereon. To divide the wafer (1) into chips, a laser dicing method is employed for irradiating the scribe area (SA) with a laser beam and forming a breaking layer inside the wafer (1) along the scribe line (SA).

Description

Specification

Semiconductor device and manufacturing method thereof

Technical field

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a dicing technique for dividing a semiconductor wafer into semiconductor chips.

Background art

In the manufacturing process of a semiconductor device, a measurement unit (TEG: Test Element Group) including a test element in a lattice area called a scribe area on a main surface of a semiconductor wafer (hereinafter referred to as wafer) is used. The integrated circuit formed in each chip region is inspected for characteristics. When the characteristic inspection using this TEG is completed, the wafer is cut along the scribe area, and each chip area is separated into semiconductor chips (hereinafter referred to as chips). For cutting the wafer, a cutting tool called a dicing blade having a disk shape with a width of several tens of meters (micrometers) is used. Therefore, the width of the scribe area provided on the wafer is currently set to a width of about 80 m to 200 m in consideration of tolerances at the time of cutting.

In recent years, with the reduction in size and weight of information storage media such as mobile phones and digital cameras, the thickness of chips incorporated therein has been reduced. Also, from the viewpoint of improving the operation speed of integrated circuits, copper (Cu) is used as the wiring material, and a material (low dielectric constant film) having a lower dielectric constant than silicon oxide is used as the interlayer insulating film material. Increasing number of semiconductor products.

However, when such a thin wafer is cut with a dicing blade, chipping (chips) easily occurs on the edge of the chip. In the cutting process using a dicing blade, pure water is used for the purpose of cooling and cleaning the wafer. This pure water may enter the cutting surface force chip and corrode the Cu wiring. In addition, the low dielectric constant film has poor adhesion to other interlayer insulation films, and the inside is porous, so it cannot be cut accurately with a dicing blade, or peeling occurs at the interface between films. May occur.

[0005] Therefore, in order to improve such problems, a dicing method using a laser was developed. Has been. This method is a method of cutting a wafer by irradiating a laser beam along a scribe area of a single crystal silicon wafer and selectively forming a fractured layer inside the wafer. According to this laser dicing method, not only the above-mentioned problems can be improved, but also the wafer can be cut with a width of several μm, so that the width of the scribe area can be reduced to 10 μm or less. The effect of increasing the number of chips that can be obtained from wafers of the same size can also be expected.

[0006] Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2004-221286) discloses a method in which a laser beam is irradiated to a scribe area in which a dummy wiring layer is formed to form a molten region (fracture layer) inside the wafer.

In addition, a technology for dividing wafers into chips by cracking or expanding methods is disclosed. The dummy wiring layer is formed for the purpose of making the laser irradiation region uniform and making it easier to absorb the laser.

Patent Document 1: Japanese Patent Application Laid-Open No. 2004-221286

Disclosure of the invention

Problems to be solved by the invention

According to the study by the present inventor, the following problems arise when trying to switch the wafer cutting from the blade dicing method to the laser dicing method.

[0008] As described above, a TEG for inspecting the characteristics of the integrated circuit formed in each chip region is arranged in the scribe area of the wafer. In the inspection process, a probe (probe) is applied to the TEG to inspect the characteristics, but considering the diameter of the probe, the width of the TEG is required to be at least about several tens of meters. It is difficult to reduce.

In other words, the width of the scribe area is limited by the size of the TEG and cannot be reduced to a width that can be cut by a laser (10 μm or less), so even if the laser dicing method is introduced at present I can hardly expect an increase in the number of chips acquired.

[0010] Further, when a scribe area having a width of about several tens of μm is cut with a laser, if a fractured layer is formed in a region overlapping the TEG in a plane, the chip region is divided into TEGs when dividing each chip region by the expanding method. A whisker-like conductor wire is formed. This is because the TEG is formed of a metal pattern, and a fracture layer is formed in a silicon region made of a material different from that of the TEG. Therefore, when extending by the expanding method, cracks running from the fractured layer are difficult to be transmitted to the TEG. Therefore, in order to separate the chip from the TEG, the laser must be scanned twice along both sides of the TEG per scribe area, resulting in a complicated cutting process. .

An object of the present invention is to provide a technique capable of increasing the number of chips that can be obtained from a wafer of the same size.

Another object of the present invention is to provide a technique for quickly cutting a wafer by a laser dicing method.

Another object of the present invention is to provide a technique for improving the mounting density of a package in which a plurality of chips are stacked.

[0014] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Means for solving the problem

[0015] Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

The present invention includes a reader main body and a reader antenna connected to the reader main body, and for wireless IC tags that read data of a wireless IC tag using microwaves transmitted from the reader main body. A reader, wherein the reader antenna is a ceramic antenna.

The invention's effect

[0017] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

[0018] The width of the scribe area can be cut with a laser while securing a region for arranging the TEG.

Since it can be narrowed to 10 m or less, it is possible to increase the number of chips that can be obtained from a wafer of the same diameter.

Brief Description of Drawings

FIG. 1 is an overall plan view of a semiconductor wafer used in an embodiment of the present invention.

2 is an enlarged plan view showing a chip region of the semiconductor wafer shown in FIG. 3 is an enlarged plan view showing a chip region of the semiconductor wafer shown in FIG.

FIG. 4 is a sectional view showing a semiconductor wafer cutting step according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a semiconductor wafer cutting step following FIG. 4.

FIG. 6 is a cross-sectional view showing a semiconductor wafer cutting step following FIG. 5.

FIG. 7 is a perspective view showing a semiconductor wafer cutting step continued from FIG. 5.

FIG. 8 is a perspective view showing a semiconductor wafer cutting process continued from FIGS. 6 and 7. FIG.

FIG. 9 is a cross-sectional view showing a semiconductor wafer cutting step following FIGS. 6 and 7.

FIG. 10 is a cross-sectional view showing a semiconductor wafer cutting step following FIGS. 8 and 9.

FIG. 11 is a perspective view showing a semiconductor wafer cutting step continued from FIGS. 8 and 9. FIG.

12 is a cross-sectional view showing a semiconductor chip peeling step subsequent to FIGS. 10 and 11. FIG.

FIG. 13 is a cross-sectional view showing a semiconductor chip mounting process following FIG. 12.

FIG. 14 is a plan view showing a semiconductor chip mounting process following FIG. 12.

FIG. 15 is a cross-sectional view showing a step of mounting the semiconductor chip following FIG. 13 and FIG.

FIG. 16 is a cross-sectional view showing the mounting process of the semiconductor chip following FIG. 13 and FIG.

FIG. 17 is a cross-sectional view showing a step of mounting the semiconductor chip following FIG. 15 and FIG.

FIG. 18 is a plan view showing another example of a semiconductor chip mounting method.

FIG. 19 is a plan view showing another example of a semiconductor chip cutting method.

20 is a cross-sectional view showing the vicinity of a corner portion of the semiconductor chip along the line A-B in FIG.

FIG. 21 is a plan view showing another example of the planar shape of the semiconductor chip.

FIG. 22 is a plan view showing another example of a semiconductor chip mounting method.

FIG. 23 is a plan view showing another example of a semiconductor chip mounting method.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

[0021] (Embodiment 1)

First, a semiconductor wafer (hereinafter simply referred to as a wafer) 1 as shown in FIG. 1 is prepared. This The wafer 1 is made of, for example, single crystal silicon having a diameter of 300 mm and a thickness force of 50 μm to 800 μm, and its main surface is partitioned in a lattice shape by a plurality of chip regions 1A ′. An integrated circuit is built in each chip region 1A ′ by a well-known semiconductor manufacturing process. The semiconductor manufacturing process includes a film forming process, an impurity ion implantation process, a photolithographic process, an etching process, a metallization process, a cleaning process, and an inspection process between the processes. In the final step of the semiconductor manufacturing process, the quality of each chip region 1A ′ is determined by an electrical test using a probe. Hereinafter, a case where a memory circuit is formed in each chip region 1A ′ will be described.

2 and 3 are partially enlarged plan views of the main surface of the wafer 1. FIG. FIG. 2 is an enlarged plan view showing about four chip areas 1A ′, and FIG. 3 is an enlarged plan view showing about one chip area 1A ′.

[0023] Each chip region 1A 'is separated from other chip regions 1A' by a grid-like scribe area SA extending in the X direction and the Y direction orthogonal thereto! . When cutting a wafer using a dicing blade, the width of the scribe area was set to about 80 μm to 200 μm in consideration of the width of the dicing blade. In contrast, in the present embodiment, as will be described later, since the wafer 1 is cut using a laser, the width of the scribing area SA is determined by taking a dicing blade in both the X and Y directions in consideration of the diameter of the laser beam. It is set to a few meters narrower than the case of use. Thus, when the wafer 1 is cut using a laser, the diameter of the laser beam is much narrower than the width of the dicing blade, so that the width of the scribe area SA can be greatly reduced.

[0024] The chip regions 1A 'separated from each other by the scribe area SA have a substantially rectangular planar shape, and a plurality of bonding pads constituting external connection terminals of the memory circuit are located near the short sides. BP is arranged in a row. In the chip area 1A ', four corners are chamfered. Therefore, the area where the scribe area SA extending in the X direction and the scribe area SA extending in the Y direction intersect (the area that touches the corner of the chip area 1 A ′) is the width of the scribe area SA is another area. Compared to

[0025] TEG2 is arranged in the above-mentioned intersection region of scribe area SA (region in contact with the corner of chip region 1A '). This TEG2 is a memo formed in the chip area 1A '. It is configured to include a predetermined number of measuring elements for evaluating the characteristics of the re-circuit and a predetermined number of nodes electrically connected to these measuring elements via wiring. It is electrically connected to any one of the four chip areas 1A ′. In the final step of the semiconductor manufacturing process, a probe is applied to the TEG2 pad to evaluate the characteristics of the memory circuit and determine the quality of each chip area 1A '. As described above, the TEG2 pad needs a space enough to contact the probe, and therefore has a diameter of at least several tens of μm.

As described above, in the wafer 1 according to the present embodiment, the width of the scribe area SA is set to about several μm. That is, the width of the scribe area SA is set narrower than the width of TEG2. Therefore, TEG2 cannot be placed in the scribe area SA as it is. Therefore, the corner area of chip area 1A 'is chamfered, and the width of scribe line SA in the area in contact with this corner area is made wider than in other areas, thereby securing a space for placing TEG2. . TEG2 is arranged at a position several m away from the corner of chip area 1A '. In this way, the width of the scribe area can be narrowed to a laser-cuttable width (less than 10 m) without being restricted by the TEG dimensions. The interval between the extended chip areas 1A ′ can be reduced. This can increase the number of chips acquired.

[0027] Normally, in the scribe area SA, in addition to the above TEG2, alignment marks for aligning the photomask and the chip area 1A 'in the photolithography process are also arranged. However, if alignment marks are arranged in the scribe area SA as in the case of TEG2, the arrangement interval of each chip area 1A ′ cannot be reduced. Therefore, when the alignment mark is arranged in the scribe area SA, it is desirable to arrange the alignment mark in an area in contact with a part of the corner of the chip area 1A ′ as in the case of TEG2.

[0028] Next, a method for cutting the wafer 1 and separating the chip regions 1A 'from each other will be described. In order to cut the wafer 1, first, the back surface of the wafer 1 is ground to reduce its thickness to about 50 to 60 m. To make wafer 1 thinner, attach a backgrind tape for integrated circuit protection to the main surface of wafer 1 and grind the back side with a grinder. To do. Thereafter, the damaged layer generated in the wafer 1 by this grinding is removed by a method such as wet etching, dry polishing, or plasma etching.

Next, after the back grind tape is peeled off from the main surface of the wafer 1, the wafer 1 is placed on a flat glass substrate 3 as shown in FIG. At this time, in order to securely fix the wafer 1 on the glass substrate 3, for example, the wafer 1 is attached to the glass substrate 3 via a tape coated with an ultraviolet curable pressure sensitive adhesive. Alternatively, a suction port penetrating the upper and lower surfaces of the glass substrate 3 may be provided, and the wafer 1 may be adhered to the glass substrate 3 by a vacuum suction method. Here, if TEG2 and alignment mark are arranged in scribe area SA, the laser beam will be shielded by TEG2 and alignment mark, so that a fracture layer may be formed inside wafer 1. Have difficulty. However, as described above, the TEG 2 and alignment mark chamfer the corner portion of the chip region 1A ′ and place it in the region in contact with the corner portion. It is possible to form a crushing layer in the interior of the UENO 1 even when the surface side force is irradiated. When the wafer 1 is placed on the glass substrate 3, any surface may be directed upward, but the case where the wafer 1 is placed on the glass substrate 3 with the back surface facing upward will be described below.

[0030] Next, by using an image recognition means such as an infrared camera, the pattern of the chip area 1A and the scribe area SA on the main surface of the wafer 1 is recognized, and the laser scanning area is determined based on the recognition data. To do. Since the wafer 1 is extremely thin, the pattern can be recognized not only from the main surface side but also from the back surface side.

Subsequently, the laser beam LB emitted from the laser generator 30 is irradiated onto the wafer 1 while scanning along the scribe line SA. When irradiating the wafer 1 with the laser beam LB, as shown in FIG. 4, a laser generator 30 is disposed above the wafer 1 and the laser beam LB is irradiated from the back side of the wafer 1. Alternatively, the laser generator 30 may be disposed below the glass substrate 3 and the main surface side of the wafer 1 may be irradiated with the laser beam LB that has passed through the glass substrate 3. For the laser beam LB, for example, a YAG laser having a wavelength of 1064 nm is used, and the center of the wafer 1 in the thickness direction is aligned and irradiated. As a result, a fractured layer 31 is formed inside the wafer 1 along the scribe line SA.

[0032] As described above, the laser beam LB is scanned along the corner portion of the chip region 1A. At this time, the laser beam LB is irradiated to the gap between the chip region 1A ′ and TEG2. As a result, a crushing layer can be formed inside the wafer 1 along the corner portion, and TEG2 can be separated from the chip area 1A ′ when the chip areas 1A ′ are separated from each other in the later process. .

Next, as shown in FIG. 5, one surface of a die attach film 4 is attached to the back surface of the wafer 1 fixed to the glass substrate 3, and a dicing tape is attached to the other surface of the die attach film 4. Paste 5 In addition, the wafer ring 6 is attached to the periphery of the dicing tape 5. The wafer ring 6 is a jig for holding the dicing tape 5 and applying a horizontal tension to the dicing tape 5.

[0034] The die attach film 4 is a film-like adhesive having a thickness of 20 to about L 00 m that serves as an adhesive layer when a chip separated from the wafer 1 is mounted on a wiring board or another chip. . On the other hand, the dicing tape 5 has a tackiness by applying an ultraviolet curable pressure sensitive adhesive or the like on one side of a tape substrate made of polyolefin (PO), polyvinyl chloride (PVC) or the like. The tape is about 90m to 120m thick. Conventionally, when dicing tape 5 is used to cut a wafer with a dicing blade, the dicing tape 5 is pasted on the back surface of the wafer and used as it is!

Next, as shown in FIGS. 6 and 7, the glass substrate 3 is removed from the wafer 1. When the wafer 1 is attached to the glass substrate 3 using an ultraviolet curable pressure sensitive adhesive, the adhesive is irradiated with ultraviolet rays. In this way, the pressure-sensitive adhesive is cured and the adhesive strength is reduced, so that the glass substrate 3 can be easily removed from the wafer 1.

Next, as shown in FIGS. 8 and 9, the dicing tape 5 to which the wafer 1 is bonded is positioned horizontally on the support ring 11 of the pickup device 10 and bonded to the peripheral portion of the dicing tape 5. The expanded wafer ring 6 is held by the expanding ring 12. FIG. 8 is an external perspective view of the pick-up device 10, and FIG. 9 is a schematic cross-sectional view showing the positional relationship between the wafer ring 6, the support ring 11 and the expanding ring 12. As shown in FIG. 9, on the inner side of the support ring 11, a suction piece 13 for pushing the chip 1 upward is disposed.

Next, as shown in FIG. 10, by lowering the expanding ring 12 of the pickup device 10, the weno bonded to the peripheral portion of the dicing tape 5 and the ring 6 are pushed downward. Lower. In this way, the dicing tape 5 is stretched in the horizontal direction without slack under the strong tension from the center to the periphery. As a result of separation of the chip regions 1A ′ from each other along the fractured layer formed in the scribe area SA of the wafer 1 by this tension, as shown in FIGS. 10 and 11, a plurality of separated chips 1 are formed. can get. At this time, the die attach film 4 on the back surface of the wafer 1 is also stretched together with the dicing tape 5 and separated in units of chips, so that the die attach of the same size as the chip 1 is placed on the back surface of the chip 1 that has been separated. Film 4 remains. On the other hand, TEG2 arranged in the intersecting area of the scribe area SA (the area in contact with the corner of the chip area 1A ') is separated from the chip area 1A', and therefore does not remain in the chip 1. Therefore, the planar shape of the diced chip 1 is a rectangle with chamfered corners.

Next, as shown in FIG. 12, the suction piece 13 is disposed immediately below one chip 1 and the suction collet 14 is brought into close contact with the upper surface of the chip 1. At the center of the bottom surface of the suction collet 14, there is provided a suction port 14a in which the inside is depressurized, so that only one chip 1 to be peeled can be selectively sucked and held. Subsequently, the dicing tape 5 is irradiated with ultraviolet rays. By rubbing in this way, the pressure-sensitive adhesive applied to the dicing tape 5 is cured and the adhesive strength is lowered, so that the die attach film 4 can be easily peeled off from the dicing tape 5. Next, the suction piece 13 is pushed upward, and the suction collet 14 is moved upward to peel off the chip 1 and the die attach film 4 from the dicing tape 5.

[0039] In this way, the chip 1 peeled from the dicing tape 5 is adsorbed and held by the adsorption collet 14, and conveyed to the next process (pellet attaching process). As shown in FIG. 13 and FIG. After being mounted on the wiring board 17A via the die attach film 4, it is electrically connected to the electrode 16 of the wiring board 17A via the Au wire 15.

[0040] When the suction collet 14 that has transported the chip 1 to the pelletizing process returns to the pickup device 10, the second chip 1 is peeled off from the dicing tape 5 in accordance with the procedure described above, and the pelletizing process is performed again. Be transported. Then, as shown in FIG. 15 and FIG. 16, after being mounted on the first chip 1 via the die attach film 4, it is electrically connected to the electrode 16 of the wiring board 17A via the Au wire 15. Is done. Next, as shown in Figure 17, The package 19 is completed by sealing the chip 1 and the Au wire 15 on the substrate 17A with the resin 18. The package 19 shown in the figure is an example in which two chips 1 are stacked, but one or a plurality of chips 1 can be sequentially stacked on the second chip 1 in accordance with the procedure described above.

As described above, in the present embodiment, the corner portion of the chip region 1A ′ of the wafer 1 is chamfered, and the TEG 2 is arranged in the scribe area SA in the region in contact with the corner portion. As a result, the width of the scribe area SA can be narrowed to a width that can be cut by a laser (10 m or less) while securing a region where the TEG 2 is arranged, so that it can be obtained from the wafer 1 having the same diameter. The number of chips 1 can be increased.

[0042] Further, by reducing the width of the scribe area SA to a width that can be cut by a laser, the chip area 1A 'and TEG2 can be obtained by scanning the laser beam only once around the chip area 1A'. Therefore, it is possible to quickly cut the wafer and 1 with a laser.

Further, as shown in FIG. 17, the package 19 in which the chip 1 mounted on the wiring board 17 is sealed with the grease 18 is caused by the difference in thermal expansion coefficient between the wiring board 17 and the chip 1. The fact that stress is easily applied to 1 contributes to a decrease in the reliability of the package 19. In particular, the corner portion of chip 1 has a large thermal stress because the amount of expansion and contraction due to heat that the distance of the center force of chip 1 is long is maximized. The chip 1 of the present embodiment has a corner portion that is chamfered, so that the distance from the center portion to the corner portion is substantially shorter than a chip of the same diameter that is not chamfered. Accordingly, the thermal stress concentrated on the corner portion of the chip 1 is reduced correspondingly, so that the reliability of the knock 19 can be improved.

[0044] Further, by chamfering the corner portion of chip 1 and shortening the distance from the center portion to the corner portion, the area of wiring board 17B on which chip 1 is mounted is reduced as shown in FIG. The effect of increasing the packaging density of the knock can also be obtained.

[0045] (Embodiment 2)

In the first embodiment, the force for separating the chip 1 and the TEG 2 may be cut so that the TEG 2 remains in the corner portion of the chip 1 as shown in FIG. Chip 1 corner When TEG2 is left in a part, the planar shape of chip 1 is apparently rectangular, but the planar shape of the region that substantially functions as chip 1 is chamfered at the corner as in the previous embodiment. It becomes a rectangle.

FIG. 20 is a cross-sectional view showing the vicinity of the corner portion of chip 1 along the line AB in FIG. A one-dot chain line C in the figure indicates a chamfered area, the chip 1 is on the left side, and the scribe area SA is on the right side. Around the periphery of the chip 1 is formed a guard ring 20 having a metal layer force in the same layer as the wiring of the integrated circuit formed in the chip 1. The guard ring 20 is formed so as to surround the entire peripheral portion of the chip 1, and prevents moisture and foreign matter from entering the inside of the chip 1 from the end of the chip 1.

[0047] According to the present embodiment in which the wafer 1 is cut so that the TEG2 remains in the corner portion of the chip 1, it is only necessary to scan the laser in the X direction and the Y direction in FIG. Compared to the first embodiment, the laser scanning distance is shortened, and the wafer 1 can be cut more quickly by the laser.

Further, as described above, the package 19 in which the chip 1 mounted on the wiring board 17 is sealed with the resin 18 is attached to the chip 1 due to the difference in thermal expansion coefficient between the wiring board 17 and the chip 1. Stress tends to be applied, especially stress tends to concentrate on the corner of the chip 1 where the center force distance is long. However, as shown in FIG. 19, what is arranged at the corner of chip 1 is TEG2 and alignment marks. Since TEG2 and alignment mark are necessary wiring in the manufacturing process, the reliability of package 19 will not be reduced even if TEG2 and alignment mark are damaged by thermal stress after sealing is completed. .

[0049] While the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. There's nothing wrong!

In the above embodiment, the case where the wafer on which the memory circuit is formed is cut has been described. However, the present invention is not limited to this, and the nonvolatile memory circuit in which the bonding pad is formed on one short side. Of course, the present invention can be applied to cutting various wafers on which logic circuits having bonding pads formed on a plurality of sides are formed.

[0051] In the embodiment, the wafer irradiated with the laser is attached to the dicing tape, The chips are separated by stretching the dicing tape, but the method for separating the chips is not limited to this. For example, after irradiating a laser to the scribe area of the wafer, the chip may be singulated by bending the wafer from the scribe area.

[0052] The planar shape of the chip to be cut by the laser is not limited to a quadrangle whose corners are chamfered, but may be a polygon other than a quadrangle. For example, FIG. 21 is a plan view of the chip 1B cut so that the planar shape is an octagon. FIG. 22 is a plan view in which the chip 1C cut so that the planar shape is circular is mounted on a circular wiring board 17C. FIG. 23 is a plan view in which the circular chip 1C shown in FIG. 22 is mounted on the wiring board 17D in multiple stages. In this way, by adopting the laser cutting method, it is possible to easily obtain a chip having an arbitrary planar shape, so that it is possible to mount a plurality of chips on a wiring board at a high density, and to mount a package. The density can be improved. Industrial applicability

The present invention can be applied to the manufacture of a semiconductor device having a semiconductor wafer cutting process using a laser.

Claims

The scope of the claims

[1] (a) A semiconductor in which a plurality of scribe areas and a plurality of chip regions separated from each other by the plurality of scribe areas are provided on a main surface, and an integrated circuit is formed in each of the plurality of chip regions. Preparing a wafer;

(b) irradiating the scribe area with a laser to form a crushed layer inside the semiconductor wafer along the scribe area;

(c) cutting the semiconductor wafer from the crushing layer as a starting point, separating the plurality of chip regions from each other and dividing them into individual pieces, thereby obtaining a plurality of semiconductor chips. And

A planar shape of the chip region is a quadrangle with a corner portion chamfered, and a TEG used for characteristic inspection of the integrated circuit is disposed in the scribe area in the region in contact with the corner portion. Device manufacturing method.

[2] The method of manufacturing a semiconductor device according to [1], wherein the scribe area has a width of 10 m or less excluding a region in contact with the corner portion.

[3] The semiconductor device according to [1], further comprising a step of reducing a thickness of the semiconductor wafer by grinding a back surface of the semiconductor wafer prior to the step (b). Manufacturing method.

[4] After the step (c),

(d) mounting the semiconductor chip on a wiring board;

2. The method of manufacturing a semiconductor device according to claim 1, further comprising: (e) a step of sealing the semiconductor chip mounted on the wiring board.

[5] The step (c) includes a step of separating and dividing the plurality of chip regions from each other by stretching a tape attached to a back surface of the semiconductor wafer. 1. A method for manufacturing a semiconductor device according to 1.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the planar shape of the semiconductor chip is a quadrangle with chamfered corners.

[7] The planar shape of the semiconductor chip is a quadrangle,

A guard ring surrounding the integrated circuit is formed on the periphery of the semiconductor chip, The planar shape of the guard ring is a quadrangle with a chamfered portion near the corner of the semiconductor chip,

2. The method of manufacturing a semiconductor device according to claim 1, wherein the TEG is disposed at the corner portion outside the guard ring.

[8] A semiconductor device comprising a wiring board and a semiconductor chip mounted on the wiring board, wherein the planar shape of the semiconductor chip is a quadrangle with a corner portion chamfered.

[9] A wiring board and a semiconductor chip mounted on the wiring board, and the planar shape of the semiconductor chip is a quadrangle in which a TEG is arranged at a corner, and a guard that surrounds the periphery of the semiconductor chip The semiconductor device according to claim 1, wherein a planar shape of the ring is a quadrangular shape in which the vicinity of the corner portion is chamfered, and the TEG is disposed outside the guard ring.

[10] (a) A step of preparing a semiconductor wafer in which a scribe area and a plurality of chip regions separated from each other by the scribe area are provided on a main surface, and an integrated circuit is formed in each of the plurality of chip regions. When,

(b) cutting the semiconductor wafer along the scribe area, separating the plurality of chip regions from each other, and dividing the chip into individual pieces, thereby obtaining a plurality of semiconductor chips. Because

A method for manufacturing a semiconductor device, wherein the planar shape of the semiconductor chip is a quadrangle with a corner portion chamfered.

[11] The step (b) includes a step of forming a fracture layer inside the semiconductor wafer along the scribe area by irradiating a laser along the scribe area, and starting from the crushed layer. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of cutting the semiconductor wafer.

[12] (a) A main surface includes a plurality of scribe areas extending in a first direction and a second direction intersecting the first direction, and a plurality of chip regions separated from each other by the plurality of scribe areas. Providing a semiconductor wafer having an integrated circuit formed in each of the plurality of chip regions; and (b) irradiating the scribe area with a laser, and forming a crushed layer inside the semiconductor wafer in the region irradiated with the laser;

The planar shape of the chip region is circular or polygonal,

A TEG used for characteristic inspection of the integrated circuit is disposed in a region where a scribe area extending in the first direction and a scribe area extending in the second direction intersect. Manufacturing method.

After the step (c),

(d) mounting the semiconductor chip on a wiring board;

13. The method for manufacturing a semiconductor device according to claim 12, further comprising: (e) a step of resin-sealing the semiconductor chip mounted on the wiring board.