WO2007013386A1 - Method for inspecting semiconductor device, semiconductor device, semiconductor integrated circuit, method and equipment for testing semiconductor integrated circuit - Google Patents

Abstract

It is required to perform inspection for guaranteeing the quality of a semiconductor product at a place dedicated to inspection in order to perform a plurality of inspections, but since these inspection processes require enormous time, rate of inspection cost to unit price of a chip becomes high. At least any one of wafer carrying process, waiting process, assembling process, and carrying process of assembly is included from completion of diffusion of semiconductor products to shipment thereof, and inspection is performed while allocating a wafer state inspection process and a package state inspection process to any processes. Inspection equipment employing this inspection method comprises a means for recording inspection progress information when the inspection is completed during any process or inspection is interrupted during the process and performing the remaining inspection in the process by referring to the inspection progress information.

Description

 Specification

 Semiconductor device inspection method, semiconductor device, semiconductor integrated circuit, semiconductor integrated circuit test method, and test apparatus

 Technical field

 [0001] The present invention provides a semiconductor device, an inspection method thereof, and an inspection apparatus. More specifically, an inspection method for a semiconductor device, a semiconductor device, and a semiconductor that can eliminate the inspection process at a fixed location by allocating the inspection process at a conventional fixed location to a process such as transportation and standby. The present invention relates to a test method and a test apparatus for integrated circuits and semiconductor integrated circuits.

 Background art

 FIG. 54 shows the conventional semiconductor product diffusion completion 101 to product shipment 108. For example, the PCM measurement process 104, the wafer condition inspection process 105, the assembly process 106, and the knock condition inspection process 107 are shown in 2100. There is a transfer step 102 and a standby step 103 between the steps.

 [0003] In particular, in the inspection processes 105 and 107 described above, an inspection for assuring the quality of the semiconductor product is performed at a place dedicated to the inspection. The time required to perform these inspections requires an enormous amount of time, the number of semiconductor products to be inspected is limited, and there are many semiconductor products that are waiting for inspection in the standby process.

 Patent Document 1: US20020171449A1 (TEST SYSTEM AND MANUFACTURING OF SEMI CONDUCTOR DEVICE)

 Patent Document 2: US65945834Al (SEMICONDUCTOR WAFER PACKAGE.METHOD AN D APPARATUS FORCONNECTING TESTING IC TERMINALS OF SEMICONDUC TOR WAFER AND PROBE TERMINALS, TESTING

 Patent Document 3: US20010046168A1 (STRUCTURES FOR WAFER LEVEL TEST AND B URN- IN

 Disclosure of the invention

Problems to be solved by the invention [0004] In order to perform the above-mentioned multiple inspections, it is necessary to perform inspections to assure the quality of the semiconductor product at a place dedicated to the inspections. The proportion of inspection costs by was increasing.

[0005] Further, even though a conventional test circuit is provided in a semiconductor integrated circuit, all tests cannot be completed only by turning on the power.

[0006] Further, since all the inspection programs are built in the semiconductor integrated circuit, when the inspection programs increase, the chip area of the semiconductor integrated circuit also increases.

[0007] In addition, when an inspection program is built in, it is not easy to change the inspection program during analysis or evaluation during mass production shipment or the like.

[0008] Further, since the conventional inspection circuit does not have a circuit for storing the progress of the inspection, if the inspection is interrupted due to some power interruption, it is difficult to perform the subsequent inspection.

[0009] Also, when the inspection standard for determining the semiconductor device to be inspected may vary depending on the elapsed time from the end of a specific inspection to the start of the next inspection, from the end of a specific inspection to the start of the next inspection It is necessary to manage the elapsed time.

[0010] In addition, a semiconductor inspection apparatus for inspecting a semiconductor device is installed at a specific location, and since the semiconductor inspection apparatus itself that can measure a plurality of semiconductor integrated circuits is large, it is difficult to move the semiconductor inspection apparatus. is there. Further, inspection is impossible in a place where there is no power supply source.

[0011] Further, if an attempt is made to inspect by supplying power to all the semiconductor integrated circuits on the substrate at once, for example, when a power supply short-circuit occurs, the power supply for a non-defective product also drops and the inspection cannot be performed.

 [0012] Also, when performing non-contact inspection, it is necessary to discriminate between non-defective products and defective products in a non-contact state. Furthermore, the antenna of the radio wave transmission / reception circuit used in a non-contact state increases the chip area or the number of manufacturing. End up.

[0013] Further, in the inspection at a place where temperature control is impossible, for example, level fluctuation occurs at the time of writing / erasing, and the yield is lowered.

[0014] In addition, there are problems in the increase in inspection cost due to the increase in power supply and signal contacts in the parallel test of semiconductor integrated circuits, and in the reliability and signal noise of electrical contacts associated with multiple pins. Accordingly, an object of the present invention is to provide a semiconductor device inspection method, a semiconductor device, a semiconductor integrated circuit, a semiconductor integrated circuit test method, and a test apparatus that solve the above-described problems.

 Means for solving the problem

 [0016] In order to solve the above problems, a semiconductor device inspection method according to claim 1 of the present invention includes a wafer transfer process, a standby process, an assembly process, and an assembly process from completion of diffusion of a semiconductor product to shipment. Including at least one of the product transfer processes, the wafer state inspection process and the package state inspection process are distributed during any of the processes.

 [0017] A semiconductor device according to claim 2 is a semiconductor device having an inspection device for carrying out the semiconductor device inspection method according to claim 1 in a semiconductor integrated circuit, and the inspection device is any of the following: Record inspection progress information when inspection is completed during the process or when inspection during the process is interrupted, and the inspection in the process can be continued by referring to the inspection progress information Have means.

 [0018] In this case, if an interruption occurs during the inspection, the inspection progress information is stored, and if the interruption does not occur, the inspection is continued. If the test is applicable, store the progress information, and if the test is not applicable, continue the test. If it falls within a certain period of inspection, the test progress information is stored, and if it does not fall within a certain period of inspection, the inspection is continued. After the inspection progress information is stored, if the inspection is completed, the inspection is terminated. If not, the inspection is continued.

 [0019] A semiconductor device according to a third aspect is the semiconductor device according to the second aspect, wherein the inspection is performed by the inspection device by supplying power to the semiconductor integrated circuit.

[0020] The semiconductor device according to claim 4 is the semiconductor device according to claim 3, wherein the inspection device is

Use mask ROM.

 [0021] The semiconductor device according to claim 5 is the semiconductor device according to claim 4, wherein the inspection device uses a RAM.

[0022] The semiconductor device according to claim 6 is the semiconductor device according to claim 3, wherein the inspection device stores software for inspecting the external force of the semiconductor integrated circuit in the nonvolatile semiconductor memory inside the semiconductor integrated circuit. Transfer to device. [0023] The semiconductor device according to claim 7 uses a fuse as storage means for storing the inspection progress information in the semiconductor device according to claim 2.

[0024] The semiconductor device according to claim 8 uses a non-volatile semiconductor memory device as storage means for storing the inspection progress information in the semiconductor device according to claim 2.

[0025] The semiconductor device according to claim 9 is the semiconductor device according to claim 2, and has means for storing the inspection progress information outside.

[0026] The semiconductor device according to claim 10 uses the semiconductor memory device provided on the device for supplying power as the memory means for storing the inspection progress information in the semiconductor device according to claim 9. .

 [0027] In the semiconductor device according to claim 11, in the semiconductor device according to claim 2, the inspection progress information is a ROM address or a RAM address.

[0028] A semiconductor device according to claim 12 is the semiconductor device according to claim 2 or 9, wherein the semiconductor integrated circuit includes a counter and stores inspection progress information at a constant period.

[0029] A semiconductor device according to claim 13 is the semiconductor device according to claim 2 or 9, wherein the inspection progress information is stored in accordance with the time of the inspection.

[0030] The semiconductor device according to claim 14 is the semiconductor device according to claim 2 or 9, wherein the test progress information is fed when the power-off signal output to the semiconductor integrated circuit is activated. .

 [0031] A semiconductor device according to claim 15 is the semiconductor device according to claim 2 or 9, wherein the semiconductor device has a detection circuit at a power supply terminal in the semiconductor integrated circuit. Store information.

 In this case, when inspecting the semiconductor integrated circuit, the detection circuit detects the power supply level supplied to the power supply terminal. When the semiconductor integrated circuit falls below the first power supply determination level, the inspection progress information is stored. When it falls below the power judgment level, the inspection of the circuit to be inspected is interrupted.

[0033] The semiconductor device according to claim 16 is the semiconductor device according to claim 2, wherein the power supply path in the semiconductor integrated circuit has a capacitance, and the power supply path from the outside when the power supply is unexpectedly interrupted. Is shut off, the power supply path of the electrostatic capacitance in the semiconductor integrated circuit is opened, and the inspection progress information is stored in the meantime. [0034] In this case, when inspecting the semiconductor integrated circuit, the detection circuit detects the power level supplied to the power supply terminal, and when the level falls below the power determination level, the power path of the external force is cut off. Select the capacitance.

[0035] The semiconductor device according to claim 17 is the semiconductor device according to claim 2, wherein the power source path outside the semiconductor integrated circuit has a capacitance, which is unexpected! The power path of the power-on device is cut off, the electrostatic capacity power path outside the semiconductor integrated circuit is opened, and the inspection progress information is stored during that time.

[0036] In this case, when inspecting the semiconductor integrated circuit, the detection circuit detects the power level supplied to the power supply terminal. When the level falls below the power determination level, the power path of the external force is cut off, Select the capacitance.

[0037] A semiconductor device according to claim 18 is the semiconductor device according to claim 17, wherein a package covering the semiconductor integrated circuit is provided with a capacitance.

[0038] In this case, when the semiconductor integrated circuit is inspected, the detection circuit detects the power level supplied to the power supply terminal. When the level is lower than the power determination level, the power path of the external force is shut off, and the package static electricity is detected. Select the capacitance.

 [0039] The semiconductor device according to claim 19 is the semiconductor device according to claim 2, wherein the inspection execution time is managed, the elapsed time is grasped by comparing the inspection execution time before and after each inspection, Is variable.

 [0040] In this case, the inspection execution time is taken from the outside of the semiconductor integrated circuit to the inside, the time information is stored, the time information taken at the next inspection is taken into the semiconductor integrated circuit, and the time information before and after the taking is obtained. By subtracting, it is possible to select inspection judgment information according to the elapsed time stored in the internal memory.

 [0041] A semiconductor device according to claim 20 is the semiconductor device according to claim 19, further comprising a circuit for storing the inspection execution time of each inspection and comparing the inspection execution time of the next inspection outside the semiconductor device circuit. When the power is turned on, the semiconductor integrated circuit external force elapsed time information is transferred.

[0042] In this case, a circuit for storing the start (end) time of each inspection according to claim 19 and comparing the start (end) time of the next inspection is provided in the semiconductor inspection apparatus, and the elapsed time information is stored in the semiconductor. Accumulation Realized by transferring to the circuit.

 [0043] A semiconductor device according to claim 21 is the semiconductor device according to claim 19, further comprising a circuit in the semiconductor device circuit that stores the inspection execution time of each inspection and compares the inspection execution time of the next inspection. The elapsed time information is stored inside the semiconductor integrated circuit.

 [0044] In this case, the circuit is realized by storing a circuit for storing the start (end) time of each inspection according to claim 19 and comparing the start (end) time of the next inspection in the semiconductor integrated circuit.

 [0045] A semiconductor device according to claim 22 is the semiconductor device according to claim 3, wherein an inspection device including an RF transmitter is used as means for supplying power to the semiconductor integrated circuit. It is converted to a power source by transmitting radio waves to the RF receiver equipped in

 [0046] In this case, the semiconductor inspection apparatus and the semiconductor integrated circuit are brought into contact with each other by transmitting radio waves and supplying power to the RF power receiver installed in the semiconductor device and the semiconductor integrated circuit using the RF power supply. It is possible to inspect multiple semiconductor devices at the same time, reduce the function of the extra semiconductor inspection device, and reduce the weight and size of the device itself.

[0047] The semiconductor device according to claim 23 is the semiconductor device according to claim 6, wherein the memory card is inspected as means for externally inputting software for automatically inspecting the semiconductor integrated circuit. The test program stored in the memory card is transferred into the test target semiconductor integrated circuit, and the test is executed.

 [0048] The semiconductor device according to claim 24 is an RF transmitter as a means for inputting external power to the semiconductor device according to claim 6 for automatically inspecting the semiconductor integrated circuit. Using the apparatus equipped with the above, the inspection program is transferred to the inside of the semiconductor integrated circuit to be inspected by transmitting the electric wave to the RF receiver provided in the semiconductor integrated circuit, and the inspection is executed.

[0049] The semiconductor device according to claim 25 automatically inspects the substrate, a plurality of semiconductor integrated circuits formed on the surface of the substrate at once, and the power supply of the semiconductor integrated circuit collectively. 4. The semiconductor device according to claim 3, further comprising: a power supply wiring connected to all of the semiconductor integrated circuits, a ground wiring connected to all of the semiconductor integrated circuits, and a semiconductor integrated circuit and a power supply wiring. Or between the semiconductor integrated circuit and the ground wiring And a fuse inserted for each body integrated circuit.

 [0050] The semiconductor device according to claim 26 is the semiconductor device according to claim 24, wherein the RF receiver coil is provided on the back surface of the substrate, and the power supply wiring is provided on the substrate surface through the through hole. Connect to.

 [0051] The semiconductor device according to claim 27 is automatically inspected by collectively supplying a substrate, a plurality of semiconductor integrated circuits formed on the surface of the substrate at once, and a power supply of the semiconductor integrated circuits. 4. The semiconductor device according to claim 3, further comprising a test data storage area for storing test PASS / FAIL information, and transferring the PASS / FAIL information stored in the test data storage area. Equipped with a volatile register and a P / N junction element that determines whether or not a P / N junction current can be applied depending on the contents of the volatile register, and a non-defective product of a semiconductor integrated circuit can be identified by the P / N junction element.

 [0052] The semiconductor device according to claim 28 automatically inspects the substrate, the plurality of semiconductor integrated circuits formed on the surface of the substrate at once, and the power supply of the semiconductor integrated circuit collectively. 4. The semiconductor device according to claim 3, further comprising a test data storage area for storing test PASS / FAIL information, and transferring the PASS / FAIL information stored in the test data storage area. A volatile register, power supply wiring, and an antifuse arranged between all the semiconductor integrated circuits formed on the substrate are provided, and it is determined whether or not the antifuse can be blown depending on the contents of the volatile register. This makes it possible to identify good and defective semiconductor integrated circuits.

 [0053] The semiconductor device according to claim 29 is automatically inspected by collectively supplying a substrate, a plurality of semiconductor integrated circuits formed on the surface of the substrate at once, and a power supply of the semiconductor integrated circuits. 4. The semiconductor device according to claim 3, further comprising a test data storage area for storing test PASS / FAIL information, and transferring the PASS / FAIL information stored in the test data storage area. Equipped with a volatile register and an RF transmitter that determines whether or not to transmit radio waves according to the contents of the volatile register, it is possible to identify non-defective products of semiconductor integrated circuits with the RF transmitter.

[0054] A semiconductor device according to claim 30 is the temperature sensor for detecting the temperature at the time of writing or erasing of the semiconductor storage device and the semiconductor storage device in the semiconductor device according to claim 3. The test data storage area that stores the test circuit information, the test temperature information, the write / erase temperature information at the time of inspection of the test data storage area, and the temperature information at the time of read of the write / erase level judgment test And an inspection standard changing circuit for changing the standard of the temperature sensor, automatically storing the temperature of the temperature sensor circuit in the semiconductor memory device, and automatically correcting the inspection standard according to the temperature.

 [0055] A semiconductor integrated circuit according to claim 31 is a semiconductor integrated circuit having an inspection device using the method for inspecting a semiconductor device according to claim 1, and includes a power supply pad, a ground pad, and a self-test circuit, The pad and ground pad are used in combination with the signal pins, and the self test circuit performs a self test with the input / output signals superimposed on the power and ground pads.

 [0056] A semiconductor integrated circuit according to claim 32 is a semiconductor integrated circuit having an inspection device using the method for inspecting a semiconductor device according to claim 1, and includes an optical power conversion element, and driving power is external. It is supplied by selective irradiation to the optical power conversion element by convergent light.

 [0057] In this case, a semiconductor collector that includes an optical power conversion element such as a PN junction, and that can irradiate the optical power conversion element with converging light such as an external laser to supply power without contact. Product circuit.

 [0058] The method for testing a semiconductor integrated circuit according to claim 33 is the method for testing a semiconductor integrated circuit according to claim 32, wherein the convergent light is cut off to the semiconductor integrated circuit determined to be defective during the test. Exclude from subsequent tests.

 [0059] A semiconductor integrated circuit according to claim 34 is a semiconductor integrated circuit having an inspection apparatus using the method for inspecting a semiconductor device according to claim 1, comprising an optical power conversion element and a light emitting element, and an optical power The conversion element is responsible for supplying drive power and receiving external data, and the light emitting element is responsible for transmitting internal data.

 [0060] In the semiconductor integrated circuit according to claim 35, in the semiconductor integrated circuit according to claim 34, near-infrared light due to breakdown of a PN junction is used as a light emitting element.

[0061] A semiconductor integrated circuit test apparatus according to claim 36 is the semiconductor integrated circuit test apparatus according to claim 34, and has a light receiving sensor element for data reception, and functions of power supply and data transmission. A plurality of laser light sources, and the semiconductor integrated circuit is contactlessly tested in a wafer state. Strike.

 [0062] A semiconductor integrated circuit according to claim 37 is a semiconductor integrated circuit having an inspection device using the method for inspecting a semiconductor device according to claim 1, and includes an optical power conversion element and a wireless data transmission circuit, The optical power conversion element is responsible for supplying drive power and receiving external data, and the wireless data transmission circuit is responsible for transmitting internal data.

 [0063] In this case, an optical power conversion element such as a PN junction responsible for supply of drive power and reception of external data and a wireless data transmission circuit responsible for transmission of internal data are provided, and the output of the semiconductor integrated circuit power is provided. A semiconductor integrated circuit that enables high-speed reading when performed wirelessly, realizes high-speed and high-SN communication through data input using optical input, and enables wireless contactless testing that functions with the smallest antenna. It is.

 [0064] A semiconductor integrated circuit according to claim 38 is a semiconductor integrated circuit having an inspection device using the method for inspecting a semiconductor device according to claim 1, comprising a photoelectric power conversion element and a wireless data transmission circuit, and an optical device. The power conversion element is only responsible for supplying drive power, and the wireless data transmission circuit is responsible for transmission and reception of internal data.

 [0065] In this case, by providing a photoelectric power conversion element such as a PN junction that is responsible only for the supply of drive power, and a wireless data transmission circuit that is responsible for transmission and reception of internal data, the convergence of the convergence light of the test apparatus can be modulated. This is a semiconductor integrated circuit that is unnecessary and does not require a demodulator on the integrated circuit side.

 [0066] In the semiconductor integrated circuit according to claim 39, in the semiconductor integrated circuit according to claim 37 or 38, the wireless data transmission circuit transmits an identification ID unique to the semiconductor integrated circuit.

 [0067] The method for testing a semiconductor integrated circuit according to claim 40 is the method for testing a semiconductor integrated circuit according to claim 37, wherein the wireless data transmission circuit transmits a unique identification ID to the semiconductor integrated circuit. The identification ID is set via the optical power conversion element.

 [0068] The method for testing a semiconductor integrated circuit according to claim 41 is the method for testing a semiconductor integrated circuit according to claim 38, wherein the wireless data transmission circuit transmits a unique identification ID to the semiconductor integrated circuit. The identification ID is selected based on whether the photoelectric conversion element is irradiated with convergent light, and is set via wireless.

[0069] The semiconductor integrated circuit according to claim 42 is the semiconductor integrated circuit according to claim 39. In addition, different or unique identification IDs are formed in advance in the process steps for each chip in the wafer of the semiconductor integrated circuit.

[0070] A semiconductor integrated circuit test apparatus according to claim 43 is the semiconductor integrated circuit test apparatus according to claim 37, wherein the wireless data reception apparatus for receiving data, power supply, and data transmission are provided. The semiconductor integrated circuit is tested in a contactless manner in the wafer state.

 [0071] A test apparatus for a semiconductor integrated circuit according to claim 44 is the test apparatus for a semiconductor integrated circuit according to claim 38, and includes a plurality of radio data transmitting / receiving apparatuses for transmitting and receiving data, and a plurality of units for supplying power. The semiconductor integrated circuit is tested in a non-contact state in a wafer state.

 The invention's effect

 According to the method for inspecting a semiconductor device according to claim 1 of the present invention, any one of a wafer transfer process, a standby process, an assembly process, and an assembly transfer process that exists between product diffusion and shipment By performing the inspection by assigning the wafer state inspection process and the package state inspection process to these processes, the inspection time can be apparently “0” and the inspection cost can be reduced to zero.

 According to the semiconductor device of claim 2 of the present invention, the inspection place is fixed because the inspection progress information is stored even when the inspection is interrupted in the middle or across the process. There is no need for a dedicated inspection site, inspection can be performed in any process, the inspection process can be reduced, and the inspection cost can be reduced to zero.

 According to the semiconductor device of the third aspect of the present invention, all the inspections can be completed only by turning on the power to the inspection circuit.

 [0075] According to the semiconductor device of the fourth aspect of the present invention, the use of a mask ROM leads to a low manufacturing cost.

 According to the semiconductor device described in claim 5 of the present invention, the use of RAM makes it possible to read out the inspection program at a high speed, thereby shortening the inspection time.

According to the semiconductor device of the sixth aspect of the present invention, the inspection program can be divided and transferred to the nonvolatile semiconductor memory device in the semiconductor integrated circuit. Can be a product.

 According to the semiconductor device described in claim 7 of the present invention, it is possible to reduce the cost by using an inexpensive fuse as a storage means for storing inspection progress information.

According to the semiconductor device described in claim 8 of the present invention, the area can be reduced by using a rewritable nonvolatile semiconductor memory device as a memory means for storing the inspection progress information.

According to the semiconductor device of the ninth aspect of the present invention, since the inspection progress information is stored outside, the semiconductor integrated circuit can be reduced in area.

According to the semiconductor device of claim 10 of the present invention, since the semiconductor memory device provided on the device for supplying power is used as the memory device for storing the inspection progress information, the semiconductor integrated circuit is provided. Can be small area.

According to the semiconductor device of claim 11 of the present invention, since the inspection progress information is only the ROM address or only the RAM address, the semiconductor integrated circuit can be reduced in area.

According to the semiconductor device of the twelfth aspect of the present invention, since the inspection progress information is stored at a constant cycle, the inspection progress information can be read and the inspection can be continued.

According to the semiconductor device of the thirteenth aspect of the present invention, since the inspection progress information is stored at the time of the inspection, the inspection progress information can be read and the inspection can be continued.

According to the semiconductor device of the fourteenth aspect of the present invention, since the inspection progress information is stored when the power-off signal is activated, the inspection progress information can be read and the inspection can be continued.

[0086] According to the semiconductor device of the fifteenth aspect of the present invention, even if the power supply is interrupted in the middle, erroneous writing of the detection progress information can be prevented, and the inspection can be performed without degrading the inspection quality.

According to the semiconductor device of the sixteenth aspect of the present invention, the inspection can be continued by using the capacitance in the semiconductor integrated circuit even if the power supply is interrupted in the middle.

According to the semiconductor device described in claim 17 of the present invention, even when the power supply is interrupted in the middle, the inspection can be continued by using the capacitance outside the semiconductor integrated circuit. Further, since the electrostatic capacity is outside the semiconductor integrated circuit, the capacity can be increased. Furthermore, the chip area can be reduced.

According to the semiconductor device of the eighteenth aspect of the present invention, even if the power supply is interrupted halfway, the inspection can be continued by using the capacitance of the package. Further chip area Can be suppressed.

 According to the semiconductor device of claim 19 of the present invention, even when the inspection is executed at an arbitrary time between a plurality of processes, the time at which the inspection is executed is stored, and the difference is calculated. It is possible to grasp the elapsed time information and automatically change the inspection standard according to the elapsed time to prevent margin of the inspection standard and to prevent a decrease in yield.

 [0091] According to the semiconductor device of claim 20 of the present invention, by providing the semiconductor inspection apparatus itself with a circuit for subtracting the elapsed time from the previous inspection to the next inspection, the time management of the entire semiconductor device is performed. And the circuit area of the semiconductor integrated circuit itself can be reduced.

 [0092] According to the semiconductor device of claim 21 of the present invention, by providing the semiconductor integrated circuit with a circuit for subtracting the elapsed time from the previous test to the next test, the time management of the semiconductor integrated circuit alone In addition, it is possible to reduce useless terminals that do not need to transmit a signal for storing the inspection time outside the semiconductor integrated circuit.

 [0093] According to the semiconductor device of claim 22 of the present invention, since the power is supplied to the semiconductor device using the RF power supply, the terminal of the semiconductor integrated circuit and the semiconductor inspection device do not come into contact with each other. The size of the inspection apparatus can be reduced, and a plurality of semiconductor devices can be accommodated. In addition, since the size of the semiconductor inspection apparatus is small, it can be easily carried and inspected while moving. Furthermore, by using a single battery as the power source for the RF power supply, it is possible to inspect even where there is no power source.

 [0094] According to the semiconductor device of claim 23 of the present invention, a memory card that can be attached to the semiconductor inspection apparatus is used for the program for operating the BIST circuit included in the semiconductor integrated circuit. The developer can easily change the program, and the inspection program can be changed and the program can be changed when analyzing and evaluating during mass production.

 According to the semiconductor device of claim 24 of the present invention, even if the power supply means is performed in a non-contact manner by transferring an inspection program into the semiconductor integrated circuit using an RF transmitter, the semiconductor device There is no need to make contact with the input / output pad that does not route wiring for transferring the inspection program to the device and the semiconductor integrated circuit.

According to the semiconductor device of claim 25 of the present invention, the antifuse is provided between the power supply wiring and all the semiconductor integrated circuits formed on the substrate, so that the power supply is short-circuited. When an overcurrent flows, a defective semiconductor integrated circuit such as a power supply short circuit is disconnected from the common power supply wiring, and a drop in power supply voltage of a good semiconductor integrated circuit can be prevented.

 According to the semiconductor device of claim 26 of the present invention, an RF coil is formed on the back surface of the substrate to receive a radio wave transmitted from the radio wave transmitter, and a voltage is supplied to the power supply wiring on the substrate surface. By providing a through-hole for this purpose, it is possible to eliminate the layout area of the RF coil that previously occupied a large area, so the number of semiconductor integrated circuits formed on a small chip or substrate can be reduced. No!

 [0098] According to the semiconductor device of claim 27 of the present invention, a test data storage area for storing inspection PASS / FAIL information, and a volatile memory for transferring the PASS / FAIL information stored in the test data storage area. And a P / N junction element that determines whether or not to pass a P / N junction current depending on the contents of the volatile register and PASS / FAIL information without sending the result of automatic inspection to an external device. For example, only non-defective products can be assembled in an assembly system (not shown) equipped with an emission device as it is after non-contact inspection.

 [0099] Specifically, the emission pattern due to the heat of the diode in the P / N junction element on the semiconductor integrated circuit formed on the substrate by the emission device is taken for each substrate, and only non-defective products are diced according to the information. After picking up the product, it is possible to assemble only good products.

 [0100] According to the semiconductor device of claim 28 of the present invention, a test data storage area for storing inspection PASS / FAIL information and a volatile memory for transferring the PASS / FAIL information stored in the test data storage area. By providing an anti-fuse between each register, power supply wiring, and all the semiconductor integrated circuits formed on the substrate, for example, the anti-fuse is blown when Fail information is stored in the volatile register. Therefore, PASS / FAIL information can be divided without sending the result of automatic inspection to an external device.For example, it is possible to assemble only non-defective products in an assembly device system equipped with a pattern recognition device as it is after non-contact inspection. It becomes.

[0101] Specifically, it is possible to assemble only non-defective products by fetching a fuse pattern for each board using a pattern recognition device, dicing only non-defective products according to the information, and picking them up. [0102] According to the semiconductor device of claim 29 of the present invention, a test data storage area for storing inspection PASS / FAIL information, and a volatile memory for transferring the PASS / FAIL information stored in the test data storage area. Since it is possible to know the result of automatic inspection in a non-contact state by providing an RF transmitter circuit that determines whether or not to transmit radio waves according to the contents of the volatile register and the volatile register, for example, as it is after the non-contact inspection Only a good product can be stowed in an assembly system equipped with a radio wave receiver.

 [0103] More specifically, it is possible to assemble only non-defective products by capturing the radio wave transmission pattern transmitted from the RF transmitter circuit by the radio wave receiving device for each substrate, dicing only the non-defective products according to the information, and picking up.

 According to the semiconductor device of claim 30 of the present invention, a temperature detection circuit that detects a temperature at the time of inspection, a test data storage area that stores information such as an inspection temperature, and an inspection of the test data storage area It is equipped with an inspection standard changing circuit that changes the inspection standard based on the temperature information at the time of writing / erasing and the temperature information at the time of reading of the writing / erasing level judgment inspection, so that it can be stored at the time of transportation or in the warehouse. Inspection at a place where temperature control is not possible is possible.

 [0105] According to claim 31, the semiconductor integrated circuit can be tested with the minimum number of contacts of the power supply pad and the ground pad. The number of contacts can be greatly reduced, and high-parallel tests can be performed with inexpensive hardware, resulting in a reduction in test costs. In addition, since the number of contacts is significantly reduced, it is possible to suppress a decrease in yield due to contact failure.

 [0106] According to claim 32, non-contact power supply is possible, noise in the power supply system caused by the test device such as interface wiring can be completely eliminated, and the quality of the parallel test is improved. Can do.

[0107] According to claim 33, it is possible to easily cut off the power to a defective chip on the wafer, and to eliminate the temperature rise, noise,! Can

Can improve the quality of parallel testing.

[0108] According to claims 34 and 35, the power supply and the input / output data can be communicated in a non-contact manner, and the power supply noise caused by the test apparatus and the noise caused by the operation of the pad circuit are completely eliminated. Can be eliminated. In addition, by using a light emitting element with a PN junction, the light emitting element can be integrated at a low cost by a normal CM OS process.

[0109] According to claim 36, there is provided an architecture of a test apparatus capable of realizing a parallel test.

 [0110] According to claim 37, since the output of the semiconductor integrated circuit is performed wirelessly, integration time is not required as compared with the light emitting element of the PN junction, and high-speed reading is possible. Data input to the semiconductor integrated circuit is low noise and high bandwidth due to optical input. In addition, since the radio circuit of the semiconductor integrated circuit is dedicated for transmission, it can be equipped with the smallest antenna, and the increase in the chip area due to the antenna can be minimized.

[0111] According to claim 38, it is possible to use an inexpensive light source that does not require modulation of convergent light, and the cost of the test apparatus can be reduced. Also, a costly optical signal demodulator is not required on the semiconductor integrated circuit side.

[0112] According to claim 39, in the non-contact parallel test of the semiconductor integrated circuit equipped with the wireless transmission function, it is possible to identify the integrated circuit that is the transmission data transmission source.

[0113] According to claims 40 and 41, it is possible to completely eliminate the possibility of erroneous writing in the setting of the identification ID in the non-contact parallel test.

 According to claim 42, the identification I is obtained by incorporating the identification ID into the semiconductor integrated circuit.

The process of setting D can be omitted. Even if it is in a state after dicing, the position on the wafer can be easily identified.

[0114] According to claim 43, a non-contact parallel test of a semiconductor integrated circuit can be realized.

[0115] According to claim 44, a non-contact parallel test of a semiconductor integrated circuit can be realized.

 In addition, an inexpensive high-power light source that does not require modulation of convergent light can be used.

 Brief Description of Drawings

FIG. 1 is a flowchart showing Embodiment 1 of the present invention.

 FIG. 2 is a flowchart showing Embodiment 2 of the present invention.

 FIG. 3 is a block diagram showing Embodiment 3 of the present invention.

 FIG. 4 is a circuit configuration diagram showing Embodiment 3 of the present invention.

FIG. 5 is a circuit configuration diagram showing Embodiment 3 of the present invention. [Figure 6] Figure 6 shows instructions from MaskROM

 FIG. 7 is a diagram showing an inspection program according to Embodiment 3 of the present invention.

 FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

9) FIG. 9 is a circuit configuration diagram showing Embodiment 4 of the present invention.

 FIG. 10 is an explanatory diagram of an external device in the fourth embodiment of the present invention.

 FIG. 11 is an explanatory diagram of an external device in Embodiment 4 of the present invention.

 FIG. 12 is a block diagram showing a fifth embodiment of the present invention.

[13] FIG. 13 is a circuit configuration diagram showing Embodiment 5 of the present invention.

 FIG. 14 is an explanatory diagram of an external device in the fifth embodiment of the present invention.

 FIG. 15 is an explanatory diagram of an external device according to the fifth embodiment of the present invention.

[16] FIG. 16 is a circuit configuration diagram showing Embodiment 6 of the present invention.

17] FIG. 17 is an explanatory diagram of the detection circuit in the sixth embodiment of the present invention.

 [FIG. 18] FIG. 18 is a graph showing the transition of the power supply level in the sixth embodiment of the present invention. 圆 19] FIG. 19 is a circuit configuration diagram showing the seventh embodiment of the present invention.

 FIG. 20 is an explanatory diagram of a detection circuit in the seventh embodiment of the present invention.

 [FIG. 21] FIG. 21 is a graph showing the transition of the power supply level in the seventh embodiment of the present invention. [22] FIG. 22 is a circuit configuration diagram showing the eighth embodiment of the present invention.

[23] FIG. 23 is a circuit configuration diagram showing another example of the eighth embodiment of the present invention.

24] FIG. 24 is a circuit configuration diagram showing Embodiment 9 of the present invention.

25] FIG. 25 is a circuit configuration diagram showing another example of the ninth embodiment of the present invention.

26] FIG. 26 is a circuit configuration diagram showing another example of the ninth embodiment of the present invention.

[27] FIG. 27 is a circuit configuration diagram showing the tenth embodiment of the present invention.

圆 28] FIG. 28 is a circuit configuration diagram showing another example of the tenth embodiment of the present invention. 圆 29] FIG. 29 is a circuit configuration diagram showing another example of the tenth embodiment of the present invention. 圆 30] FIG. Circuit configuration diagram showing Embodiment 10 of the present invention

[31] FIG. 31 is a circuit configuration diagram showing the eleventh embodiment of the present invention.

32] FIG. 32 is a block diagram showing the twelfth embodiment of the present invention and an enlarged view of the main part. 圆 33] FIG. 33 is a block diagram showing the thirteenth embodiment of the present invention and an enlarged sectional view of the main part. [34] FIG. 34 is a circuit configuration diagram showing Embodiment 14 of the present invention.

 FIG. 35 is a block diagram of a P / N junction element showing Embodiment 14 of the present invention.

 FIG. 36 is an enlarged cross-sectional view of FIG.

37] FIG. 37 is a block diagram showing the fifteenth embodiment of the present invention and an enlarged view of the main part.

38] FIG. 38 is a circuit configuration diagram showing Embodiment 15 of the present invention.

[39] FIG. 39 is a block diagram showing the sixteenth embodiment of the present invention and an enlarged view of the main part.

40] FIG. 40 is a circuit configuration diagram showing Embodiment 16 of the present invention.

[41] FIG. 41 is a circuit configuration diagram showing Embodiment 17 of the present invention.

42] FIG. 42 is a block diagram of the temperature detection circuit in the embodiment 17 of the present invention.

 [FIG. 43] FIG. 43 is a block diagram of the inspection standard changing means in Embodiment 17 of the present invention. 圆 44] FIG. 44 is a circuit configuration diagram showing Embodiment 18 of the present invention.

 FIG. 45 is a waveform diagram showing an input signal from the test apparatus in Embodiment 18 of the present invention.

 FIG. 46 is a waveform diagram showing an output signal to the test apparatus in Embodiment 18 of the present invention.

[47] FIG. 47 is a circuit configuration diagram showing Embodiment 19 of the present invention.

48] FIG. 48 is a circuit configuration diagram showing Embodiment 20 of the present invention.

49] FIG. 49 is a circuit configuration diagram showing Embodiment 21 of the present invention.

 FIG. 50 is a sectional view of a test apparatus showing Embodiment 22 of the present invention.

 FIG. 51 is a top view of FIG.

52] FIG. 52 is a sectional view of a test apparatus showing Embodiment 23 of the present invention.

[Figure 53] Figure 53 is a top view of Figure 52

[Fig.54] Flow chart showing a conventional example

Explanation of symbols

101 Completed wafer diffusion

102 Transport process

103 Standby process

104 PCM measurement process 105 Wafer condition inspection process

 106 Assembly process

 107 Knocking condition inspection process

 108 Product shipment

 200 Flow chart showing the flow of inspection

201 Inspection started

 202 Inspection progress information reference

 203 Interruption of inspection

 204 Inspection milestones

 205 Period of inspection

 206 Inspection progress information memory

 207 Inspection finished

 301 Semiconductor integrated circuit

 303 External device

 400 Inspection methods

 401 Circuit under test

 402 Advance information storage means

 403 Counting means

 404 inspection professional storage means

 405 Power receiving means

 406 Power supply means

 500 information communication means

 600 inspection professional receiving means

 601 Inspection Pro Transmission Means

 800 Semiconductor integrated circuit

 801 Power supply terminal

 802 detection circuit

806 A / D converter 807 judgment circuit

 808 Graph showing power supply level transition

809 Power supply level transition

810 First power judgment level

811 Second power judgment level

902 detection circuit

903 multiplexer

904 capacitance

909 judgment circuit

 910 Graph showing power level transition

911 Power supply level transition

912 Power judgment level

913 packages

914 leads

 1000 Semiconductor integrated circuit

1001 Clock for current time transfer

1002 Time information storage memory

 1003 Latch circuit that captures time information storage memory information

 1004 Latch circuit that captures current time information from external power of semiconductor integrated circuit

1005 Subtracting circuit that subtracts 1004, 1005 latched information

 1006 Memory for storing the address of inspection program storage memory

 1007 Program counter

 1008 Inspection program storage memory

 1009 Instruction register

 1010 Control circuit

 1011 Peripheral circuit

 1012 Instruction address storage memory

1012 Semiconductor inspection equipment 1013 Elapsed time arithmetic circuit provided in semiconductor inspection apparatus 1100 Semiconductor inspection apparatus

1101 Multiple semiconductor devices

1102 Semiconductor devices

 1103 Semiconductor integrated circuit with RF power receiver

1104 RF power transmitter

1105 battery

1106 outlet

 1107 Multiple semiconductor devices

1108 RF power receiver

1109 Semiconductor device fixtures

1110 VSS power supply port

1111 VDD power supply port

1200 Semiconductor inspection equipment

1201 Multiple semiconductor devices

1202 Semiconductor devices

 1203 Semiconductor integrated circuit with RF transceiver

 1204 RF transceiver

 1205 Memory card entry

 1206 Memory card

1300,1331,1341 Semiconductor devices

1301,1332,1342 Ueno, etc.

1302,1333,1343 Semiconductor integrated circuit

1303, 1334, 1344 Power supply wiring

1304,1335,1345 Ground wiring

1305,1338,1348 Antifuse

1306 RF coil

1307 Through hole 1308 Insulating film

 1309, 1336, 1346, 1351 Nonvolatile semiconductor memory devices such as flash memory

1310 Memory array

 1311 User area memory array

 1312 Test data storage area

 1313 Address decoder

 1314 Read / write circuit

 1315 Rewrite control circuit

 1316 PASS / FAIL Data write control circuit

 1317 Power circuit

 1318 Inspection and control circuit

 1319 Command decoder

 1320 Data MUX

 1 ό21 Data Processing Unit

 1322, 1339, 1349 Volatile registers

 1323 P / N Junction element

 1324 Address counter

 1325 I / O data bus

 1326 output bus

 1327 Input bus

 1328 Address bus

 1329 Transistors

 1330 diode

 1337, 1347 Memory part

 1340 resistance

 1350 RF transmitter circuit

 1352 Temperature detection circuit

1353 Temperature information data write control circuit 1354 Inspection standard change circuit

 1355 Thermal sensors such as diodes

 1356 A / D Converter

 1357 Register to store A / D converter result

1358 Power supply level change register

 1359 Booster circuit

1360 Regulator

 2100 Conventional flow from completion of diffusion to product shipment

BEST MODE FOR CARRYING OUT THE INVENTION

 The best mode for carrying out the present invention will be described below with reference to the drawings.

(Embodiment 1)

 Hereinafter, Embodiment 1 of the present invention will be described with reference to FIG. In Fig. 1, 100 is the flow from the completion of diffusion to product shipment, 101 is the completion of wafer diffusion, 102 is the transfer process, 103 is the standby process for the next process, 104 is the PCM (Process Control Module) of the wafer PCM measurement process to measure, 105 is a wafer state inspection process to inspect in the wafer state, 106 is an assembly process to seal in the package, 107 is a package state inspection process to inspect the product sealed in the package, 108 is It is a product shipment. The wafer condition inspection process 105 and the package condition inspection process 107, which were conventionally performed in a fixed location, are assigned to the transfer process 102, standby process 103, PCM measurement process 104, and assembly process 106, and the wafer is then inspected. The condition inspection process 105 and the package condition inspection process 107 are eliminated.

(Embodiment 2)

Hereinafter, Embodiment 2 of the present invention will be described with reference to FIG. 200 in FIG. 2 is a flowchart showing the flow of inspection, 201 is inspection inspection information reference, 202 is inspection start, 203 is inspection interruption, 204 is inspection milestone, 205 is inspection period, 206 is inspection Progress information storage, 207 is the end of the examination. After the power is turned on, the inspection progress information 201 is referred to, and the inspection start 202 is obtained. If an interruption 203 occurs during the inspection, the inspection progress information is stored in the inspection progress information storage 206, and if the interruption 203 does not occur, the inspection is continued. Inspection milestone 204 If this is the case, the test progress information is stored in the test progress information storage 206, and the test is continued if it does not correspond to the test point 204. If the inspection period is 205, the inspection progress information is stored in the inspection progress information storage 206. If the inspection period 205 is not satisfied, the inspection is continued. After the test progress information is stored in the test progress information storage 206, if the test is completed 207, the test is completed. If the test is not completed 207, the test is continued.

(Embodiment 3)

 An outline of the third embodiment of the present invention will be described with reference to FIG. 301 is a semiconductor integrated circuit, 3 03 is an external device, 400 is an inspection means, 401 is a circuit to be inspected, 402 is a progress information storage means, 403 is a counting means, 404 is an inspection program storage means (hereinafter referred to as an inspection program storage means) 405 is a power receiving means, and 406 is a power supplying means. The power source 405 in the semiconductor integrated circuit 301 receives the power source generated by the power supply unit 406 in the external device 303. When the power receiving means 405 receives the power supply, the inspection means 400 reads the progress information of the inspection from the advance information storage means 402, and uses the advance information to access the inspection pro storage means 404 and read the inspection program. The inspection target circuit 401 is inspected. The progress information is written to the advance information storage means 402 when the signal is output from the counting means 403, when the inspection means 400 executes the advance information write command, and when the power receiving means 405 outputs a power shutoff signal. If you do.

The specific progress information reading and inspection procedure of the apparatus of this embodiment will be described with reference to FIG. When receiving power from the power supply means 406, the power receiving means 405 supplies power to a POR (POWER ON RESET circuit) in the inspection means 400. A reset signal is output to POI ^ ¾CTRL (CON TROL circuit), and CTRL reads the ROM address from the PC storage fuse in progress information storage means 402 and sets it in the PC (PROGRAM COUNTER circuit). The instruction is read from MaskROM which is inspection pro storage means 404 and set in IR (INSTR UCTION RESISTER circuit). Although not shown, a RAM may be placed between MaskROM and IR for memory hierarchy. As shown in Fig. 6, the instruction consists of OP CODE, test number, input pattern, and expected value. OP CODE is sent to CTRL, test number is sent to progress information storage means 402, and input pattern is sent to the circuit under test 401. The expected value is sent to CMP (COMPARE circuit). Output from test target circuit 401 The value is compared with the expected value by CMP, and the result is written in the inspection result storage fuse corresponding to the test number in the progress information storage means 402. When the instruction read from the Mask ROM which is the inspection program storage unit 404 indicates the end of the inspection, it is written in the inspection end storage fuse corresponding to the end of the inspection in the advance information storage unit 402.

 [0120] Three types of writing of specific progress information of the apparatus of this embodiment will be described with reference to Figs. FIG. 7 shows an inspection program stored in the Mask ROM which is the inspection program storage means 404. First, when the CTRL in the inspection unit 400 receives a reset signal from the POR, the counting unit 403 is operated. The counting means 403 outputs a progress information write signal to the CTRL at regular intervals, and the CTRL stores the ROM address in the PC storage fuse in the progress information storage means 402. The second is that the CTRL detects the power shutoff in the power receiving means 405 and also stores the ROM address when the power shutoff signal is received. Third, the ROM address is stored when the progress information write command shown in Figure 7 is executed.

 As a specific example of the progress information storage means 402, a force using a fuse in FIG. 4 can be used as shown in FIG.

 (Embodiment 4)

 An outline of the fourth embodiment of the present invention will be described with reference to FIG. 500 is an advanced information communication means. In the third embodiment, the progress information storage unit 402 exists in the semiconductor integrated circuit 301, but in the fourth embodiment, the progress information storage means 402 is placed in the external device 303.

 [0122] A specific example of the apparatus of the present embodiment will be described with reference to Figs. A specific example of the advance information storage means 402 uses a fuse or a nonvolatile memory (FIGS. 10 and 11). Access to the progress information storage means 402 in the external device 303 is performed via the progress information communication means 500 in the semiconductor integrated circuit 301 and the progress information communication means 500 in the external device 303.

 In the fourth embodiment, since the progress information storage means 402 is provided in the external device 303, the area of the semiconductor integrated circuit 301 can be reduced and the storage capacity can be increased.

 (Embodiment 5)

An outline of the fifth embodiment of the present invention will be described with reference to FIG. Reference numeral 600 denotes inspection professional reception means, and reference numeral 601 denotes inspection professional transmission means. In the third embodiment, the inspection program is stored in the Mask ROM serving as the inspection program storage means 404 in the semiconductor integrated circuit 301. In the fifth embodiment, an inspection program is placed in the external device 303 and transmitted to the semiconductor integrated circuit 301.

 [0124] A specific inspection program transfer procedure of the apparatus of the present embodiment will be described with reference to FIGS. A specific example of the inspection program storage means 404 in the semiconductor integrated circuit 301 uses a nonvolatile memory, and a specific example of the inspection program storage means 404 in the external device 303 uses a fuse or a nonvolatile memory (FIGS. 14 and 15). When the power receiving means 405 receives the power, it supplies power to the POR in the inspection means 400. POR outputs a reset signal to CTRL, CTR L reads ROM address and inspection program number from PC storage fuse in 402, sets ROM address to PC, and receives inspection program number Set to 600. The inspection professional receiving means 600 requests the inspection professional transmission means 601 to transmit the inspection program corresponding to the inspection program number. The inspection professional transmission means 601 reads the inspection program corresponding to the inspection program number from the inspection professional storage means 404 in the external device 303 and transmits it to the inspection professional reception means 600. The inspection port receiving means 600 writes the received inspection program into the inspection professional storage means 404 in the semiconductor integrated circuit 301. Thereafter, the instruction is read from the non-volatile memory which is the inspection professional storage means 404 and set in the IR. An instruction requesting transmission of the next inspection program is inserted in the last line of the inspection program.

In the fifth embodiment, since the inspection program storage means 404 is provided in the external device 303 and the inspection program is divided and transmitted, the semiconductor integrated circuit 301 can be reduced in area, and the inspection program The storage capacity can be increased.

 (Embodiment 6)

Hereinafter, Embodiment 6 of the present invention will be described with reference to FIG. In FIG. 16, 301 is a semiconductor integrated circuit, 400 is an inspection means, 401 is an inspection target circuit, 402 is a progress information storage means, 801 is a power supply terminal, 802 is a detection circuit, and FIG. 17 illustrates the detection circuit 802. 806 is an A / D converter, 807 is a decision circuit, 808 in FIG. 18 is a graph showing the transition of the power level, the horizontal axis is time [t], and the vertical axis is the power level [V 809 is the transition of the power level, 810 is the first power judgment level, and 811 is the second power judgment level [0126] When inspecting the semiconductor integrated circuit 301, the power supply level supplied to the power supply terminal 801 is detected by the detection circuit 802, and the A / D converter 806 of the detection circuit 802 converts the power supply level into a control signal, and the determination circuit 807 determines the transition 809 of the power supply level. When the power level transition 809 falls below the first power judgment level 810, the inspection progress information 402 is stored through the inspection means 400, and when the power level transition 809 falls below the second power judgment level 811, the tester The inspection of the circuit under test 401 is interrupted through the stage 400. The reason for the difference in the power judgment level is that the advance information is stored at the first power judgment level 810 to prevent erroneous writing to the advance information storage means, and the second power judgment level. This is because the inspection quality is not degraded by interrupting the inspection at 811.

 (Embodiment 7)

 The seventh embodiment of the present invention will be described below with reference to FIG. In FIG. 19, 301 is a semiconductor integrated circuit, 400 is an inspection means, 401 is a circuit to be inspected, 402 is a progress information storage means, 801 is a power supply terminal, 902 is a detection circuit, 903 is a multiplexer, 904 is a capacitance, 20 is a diagram for explaining the detection circuit 902, 806 is an A / D converter, 909 is a determination circuit, 911 in FIG. 21 is a graph showing the transition of the power level, the horizontal axis is time [t], vertical The axis shows the power level [V], 911 is the power level transition, and 912 is the power judgment level.

[0127] When inspecting the semiconductor integrated circuit 301, the power supply level supplied to the power supply terminal 801 is detected by the detection circuit 902, and the A / D converter 806 of the detection circuit 902 converts the power supply level into a control signal, and the determination circuit 909 determines the transition 911 of the power level. When the power supply level transition 911 falls below the power supply judgment level 912, the detection circuit 902 selects the electrostatic capacitance 904 in the semiconductor integrated circuit through the multiplexer 903.

 (Embodiment 8)

 Embodiment 8 of the present invention will be described below with reference to FIG. In FIG. 22, 301 is a semiconductor integrated circuit, 400 is an inspection means, 401 is an inspection target circuit, 402 is a progress information storage means, 801 is a power supply terminal, 902 is a detection circuit, 903 is a multiplexer, and 904 is a capacitance. . Force using the detection circuit 902 and the graph 910 (FIG. 21) showing the transition of the power supply level The explanation of the figure is omitted here.

[0128] When inspecting the semiconductor integrated circuit 301, the power supply level supplied to the power supply terminal 801 is detected. The circuit 902 detects the force, the A / D converter 806 of the detection circuit 902 converts the power level into a control signal, and the determination circuit 909 determines the transition 911 of the power level. When the power supply level transition 911 falls below the power judgment level 912, the detection circuit 902 selects the capacitance 904 outside the semiconductor integrated circuit through the multiplexer 903.

 Next, another example of the eighth embodiment of the present invention will be described with reference to FIG. In FIG. 23, 301 is a semiconductor integrated circuit, 400 is an inspection means, 401 is a circuit to be inspected, 402 is a progress information storage means, 801 is a power supply terminal, 902 is a detection circuit, 903 is a multiplexer, and 904 is a capacitance. 913 is a package, and 914 is a lead. Force using the detection circuit 902 and the graph 910 showing the transition of the power supply level The explanation of the figure is omitted here.

 [0130] When inspecting the semiconductor integrated circuit 301, the power supply level supplied to the power supply terminal 801 is detected by the detection circuit 902, and the A / D converter 806 of the detection circuit 902 converts the power supply level into a control signal, and the determination circuit 909 determines the transition 911 of the power level. When the power supply level transition 911 falls below the power judgment level 912, the detection circuit 902 selects the capacitance 904 on the lead 914 of the package 913 through the multiplexer 903.

 (Embodiment 9)

 24 and 25 show circuit configuration examples for managing the inspection elapsed time information according to the ninth embodiment corresponding to claim 19 of the present invention.

 [0131] In FIG. 24, 1000 is a circuit for managing the inspection elapsed time information in claim 19 inside the semiconductor integrated circuit, 1001 is a circuit showing current time information, 1002 is the current 1001 inside the semiconductor integrated circuit Memory that stores time information, 1003 is a latch circuit that captures the information in the 1002 time storage memory, 1004 is a latch circuit that captures the current time information of 1001, 1005 is the time information captured by the circuit in the latches 1003 and 1004 Subtraction circuit for subtraction, 1006 is a memory for storing address information to be loaded into the program counter of 1007, 1008 is a memory for storing an inspection program, 1009 is an instruction register, 1010 is a control circuit, 1011 is using time-lapse information Peripheral circuit operating.

[0132] Specifically, the current time information 1001 converted to hexadecimal (binary) is connected to the latch circuit 1004 that owns the number that can capture the time information, and latches when the internal signal ACTLAT becomes active. Time information is captured in the circuit 1004. At the same time, memory for time storage 100 The time information of the time storage memory 1002 is taken into the latch circuit 1003 connected to 2. The information of the latch circuits 1003 and 1004 is obtained by the subtraction circuit 1005 to obtain the difference between the current time information of the latch circuit 1004 and the time information stored in front of the latch circuit 1003. The subtracted result has a logical structure that points to one address value stored in the address storage memory 1006. The address information pointed to by the address storage memory 1006 is loaded into the program counter 1007 when the internal signal ACTADR becomes active, and the data in the memory 1008 that stores the test program pointed to by the program counter 1007 is read into the instruction register 1009. Then, the instruction is decoded by the control circuit 1010, and the peripheral circuit 1011 performs the operation over time. The information in the time storage memory 1002 is rewritten to the information captured in the latch circuit 1004 when the internal signal AC TEW becomes active.

On the other hand, in FIG. 25, the instruction address storage memory 1012 functions in the same way as the instruction register 1009 in FIG. 24, but the instruction address storage memory 1012 is a dedicated instruction register for the inspection elapsed time information. Further, the test elapsed time information processed by the subtraction circuit 1005 has a logical structure that directly points to the instruction register. Therefore, the signal can be transmitted to the control circuit 1010 without going through the program counter 1007 and the program storage memory 1008 shown in FIG.

 Further, FIG. 26 shows an example of the case where the circuit 1013 for processing time lapse information is moved from the semiconductor integrated circuit 1 000 to the semiconductor inspection apparatus 1012, and the operation itself performs the same operation as described above. .

 (Embodiment 10)

 27 to 30 show circuit configuration examples of the semiconductor inspection apparatus provided with the RF power supply according to the tenth embodiment corresponding to claim 22 of the present invention.

In FIG. 27, 1100 is a semiconductor inspection device, 1101 is a plurality of semiconductor devices, 1102 is a semiconductor device, 1103 is a semiconductor integrated circuit equipped with an RF power receiver, 1104 is an RF power transmitter, and 1105ί. is there. In FIGS. 28 and 29, there are a plurality of semiconductor device groups such as 1106ί. In FIG. 30, 1108 is an RF power receiver, 1109 is a semiconductor device fixture, 1110 is a VSS power supply port, and 1111 is a VDD power supply port. Specifically, according to FIGS. 27 to 28, an RF power transmitter 1104 is provided in the semiconductor inspection apparatus, and a battery is provided in the semiconductor inspection apparatus 1100 as its power supply source. Alternatively, an outlet 1106 is provided to obtain the semiconductor inspection apparatus 1100 from the outside. The RF power transmitter 1104 provided in the semiconductor detection device 1100 transmits electric waves to the semiconductor integrated circuit 1103 provided with the RF power receiver, whereby the semiconductor integrated circuit 1103 can obtain power. Since power is supplied to the semiconductor device 1102 in a non-contact manner using the RF power source transmitter 1104, a plurality of semiconductor devices can be provided in the semiconductor inspection device ₁₁₀₀ .

 Furthermore, according to FIG. 29, one RF power transmitter 1104 and one battery 1105 or outlet 1 106 may be provided in a plurality of semiconductor device groups 1107 in which one or more semiconductor devices 1101 are collected. Is possible. FIG. 30 shows a case where an RF power transmitter 1104 is provided outside the semiconductor inspection apparatus.

 (Embodiment 11)

 FIG. 31 shows an embodiment of the present invention corresponding to claim 23 of the present invention because the test program for automatically inspecting an external force is input by using an RF transmitter by inserting a memory card into the inspection device. An example of the circuit configuration is shown.

 In FIG. 31, 1200 is a semiconductor inspection device, 1201 is a plurality of semiconductor devices, 1202 is a semiconductor device, 1203 is a semiconductor integrated circuit equipped with an RF transceiver, 1204 is an RF transceiver, 1205 is a memory card inlet, Reference numeral 1206 denotes a memory card.

 [0139] Specifically, the inspection program is transferred to the semiconductor integrated circuit 1203 equipped with the RF transceiver by the RF transceiver 1204. When power is first applied to the semiconductor integrated circuit, the program transfer permission is granted. The signal is transferred from the RF transmitter / receiver installed in the semiconductor integrated circuit 1203 to the RF transmitter / receiver 1204, and the program transfer permission signal is transferred to the memory card 1206 inserted into the memory card insertion slot 1205 and stored in the memory card 1206. The transferred inspection program is transferred to the semiconductor integrated circuit 1203 equipped with the RF transceiver via the RF transceiver 1204, and the semiconductor integrated circuit 1203 can automatically perform the inspection using the inspection program. I can do it.

 (Embodiment 12)

FIG. 32 shows the configuration of the semiconductor device according to the twelfth embodiment of the present invention. [0140] Hereinafter, a semiconductor device according to a twelfth embodiment of the present invention will be described with reference to FIG.

[0141] In FIG. 32, 1300 is a semiconductor device, 1301 is a substrate such as a wafer, 1302 is a semiconductor integrated circuit formed on the substrate 1301, 1303 is a power supply wiring that collectively supplies power to the semiconductor integrated circuit 1302, Reference numeral 1304 denotes a ground wiring for collectively grounding the semiconductor integrated circuit 1302, and 1305 denotes an antifuse formed between the semiconductor integrated circuit 1302 and the power supply wiring 1303.

 In this embodiment, an example in which an antifuse is formed between the semiconductor integrated circuit 1302 and the power supply wiring 1303 will be described.

[0143] The semiconductor integrated circuit 1302 formed on the substrate 1301 supplies, for example, 1.8 V to the power supply wiring 1303 and supplies 0 V to the ground wiring 1304, for example. In the display), all the semiconductor integrated circuits on the substrate 1301 are inspected collectively.

 [0144] At this time, when a defective semiconductor integrated circuit such as a short circuit of the power supply terminal exists, since the power supply wiring 1303 is common, all the power supply voltages of the semiconductor integrated circuit are lowered and cannot be inspected.

 [0145] Here, the antifuse 1305 provided between the power supply wiring 1303 and every semiconductor integrated circuit 1302 formed on the substrate 1301 has a common power supply wiring because it breaks when an overcurrent flows due to a power supply short circuit or the like. A semiconductor integrated circuit which is defective from 1303 is separated. With this configuration, it is possible to prevent a power supply voltage drop. Note that an antifuse may be formed between the semiconductor integrated circuit 1302 and the ground wiring 1304.

 (Embodiment 13)

 FIG. 33 shows the configuration of the semiconductor device according to the thirteenth embodiment of the present invention.

The semiconductor device according to the thirteenth embodiment of the present invention is described below with reference to FIG.

[0147] In FIG. 33, 1306 is an RF coiner, 1307 is a through hole connecting the power supply line 1303 and the RF coiner 1306, and 1308 is a protective insulating film for forming a through hole.

[0148] RF coil formed on the back surface of the substrate 1301 by radio waves transmitted from a radio wave transmitter (not shown)

The signal is received at 1306 and a voltage is supplied to the power supply wiring 1303 formed on the surface of the substrate 1301 through the through hole 1307 on the surface of the substrate 1301. [0149] With this configuration, the arrangement area of the RF coil 1306, which previously occupied a large area, can be eliminated, so that the number of semiconductor integrated circuits 1302 formed on a small chip or substrate 1301 is not reduced. ,.

 (Embodiment 14)

 FIG. 34 shows the configuration of the semiconductor memory device according to the fourteenth embodiment of the present invention.

FIGS. 35 and 36 show the configuration of the P / N junction element according to Embodiment 14 of the present invention.

 Embodiment 14 of the semiconductor memory device of the present invention will be described below with reference to FIG. 34 and FIGS.

 [0151] In FIG. 34, 1309 is a non-volatile semiconductor memory device such as a flash memory, 1310 is a memory array, 1311 is a user area memory array used by the user, and 1312 is test data storage for storing PASS / FAIL information for inspection, etc. Area, 1313 is an address decoder, 1314 is a read / write circuit that senses when reading / verifying the drain of the memory cell during read / write, and a high voltage is applied during write, 1315 is a rewrite control circuit, 1316 is a PASS / FAIL Data write control circuit that automatically writes test PASS / FAIL information to the test data storage area 1312, 1317 is a power supply circuit such as a booster circuit that generates high voltage, and 1318 includes a rewrite algorithm controller and test circuit Inspection and control circuit, 1319 is command decoder, 1320 is data MUX including data input / output switching circuit, 1321 is write Generate expected value at the time of generation and rewriting of judgment data and judge PASS / FAIL DPU 1322 stores test data immediately after test PASS / FAIL information is written in test data storage area 1312 and at power on Inspection of area 1312 A volatile register that transfers and stores PASS / FAIL information, 1323 is a P / N junction element that determines whether or not to pass a P / N junction current according to the data stored in volatile register 1322, and 1324 is Address counter that generates addresses internally, 1325 is the input / output data bus of the flash memory 1309, 1326 is the output bus that is output from the read / write circuit 1314, 1327 is the external read data, the read data from the DPU1321, etc. This is an input bus that is input to the write circuit 1314.

[0152] In FIGS. 35 and 36 !, 1329ί is a transistor, and 1330ί is a die.

Here, the nonvolatile semiconductor device is described as a flash memory. First, in a normal rewrite operation of the flash memory 1309, a write / erase command and a write address and write data in the case of writing are input to the address bus 1328 and the input / output data bus 1325 from the outside. In the case of a block erase command, the divided block address of the memory array 1310 is input. The command decoder 1319 decodes the input command, and the control circuit 1318 including the rewrite algorithm controller sends an algorithm command to the rewrite control circuit 1315. The algorithm here is write and write verify, erase and erase verify. In response to the instruction, the rewrite control circuit 1315 instructs the power supply circuit 1317 according to the algorithm and the power supply circuit 1317 supplies the voltage necessary for rewrite to the memory array 1310 through the address decoder 1313 and the read / write circuit 1 314. Do by supplying. On the other hand, the DPU1321 rewrites the write data at the time of writing and "1" data at the time of erasing as the expected value. Since the memory array 1310 is divided into blocks when erasing, the address counter 1324 automatically generates an address according to the erasure area at the time of verifying the erase. Similarly, the address counter 1324 automatically generates an address according to the write address range at the time of verifying when writing a plurality of addresses at the same time as the page write.

 On the other hand, during the inspection, the operation enters the inspection mode when power is supplied from the outside in the state of the wafer, and the inspection is automatically performed according to the inspection flow of the inspection and control circuit 1318.

[0156] For example, the operation of the automatic write check will be described. The check and control circuit 1318 issues a write command. Upon receiving the command, the rewrite control circuit 1315 instructs the power supply circuit 1317 to specify the necessary voltage. The power supply circuit 1317 supplies a voltage necessary for rewriting to the memory array 1310 through the address decoder 1313 and the read / write circuit 1314. The difference from normal writing is that the address and data are generated internally by the address counter 1324 and the data by the DPU1321 instead of inputting the address and data by external force. As a result of the automatic inspection as described above, for example, when a rewrite fails, Fail information is sent from the DPU 1321 to the inspection and control circuit 1318, and the inspection stops there. Next, the inspection and control circuit 1318 sends a command to the PASS / FAIL Data write control circuit 1316. Upon receiving this command, the PASS / FAIL Data write control circuit 1316 receives the power supply circuit 131. The power supply circuit 1317 supplies the write voltage to the test data storage area 1312 through the address decoder 1313 and the read / write circuit 1314 by instructing the voltage required for writing to 7, and the PASS / FAIL information is supplied to the test data storage area 1312. Write to. Immediately after this, the inspection and control circuit 1318 issues a command to transfer the FAIL data stored in the test data storage area 1312 to the volatile register 1322. This FAIL Data is transferred to the volatile register 1322 when the power is turned on. The data stored in the volatile register 1322 is input to the P / N junction element 1323 and the inspection and control circuit 1318. When this Fail Data is input, the inspection and control circuit 1318 locks the flash memory 1309 so that the entire circuit does not operate even when power is supplied.

FIGS. 35 and 36 show the configuration and device structure of the P / N junction element 1323. As described above, the data stored in the volatile register 1322 is input to the gate of the transistor 1329. The transistor 1329 is activated and connected to the voltage supplied from the diode 1330 and the power supply circuit 1317. This voltage is higher than the breakdown voltage of the diode 1330. When breakdown current flows through the diode 1330, heat is generated. By detecting the generation of this heat with, for example, an emission device, it is possible to make a PASS / FAIL determination, and it is possible to determine whether or not the assembly device system is equipped with the emission device.

[0158] The inspection end force or not can also be detected by the presence or absence of heat generation based on whether or not the entire circuit is stopped.

[0159] With such a configuration, the PASS / FAIL information can be divided without sending the result of automatic inspection to an external device. For example, a stand-alone device system with an emission device as it is after non-contact inspection ( It is possible to make only good products (not shown).

 [0160] Specifically, the P / N junction element 1323 on the semiconductor integrated circuit formed on the substrate by the emission device captures the light emission pattern due to the heat of the diode 1330 in the 1323 for each substrate, and only non-defective products according to the information Assembling only good products by picking up after dicing.

 [0161] In this example, the write test is taken as an example, but the PASS / FAIL information of other tests is also stored in the test data storage area 1312 in the same manner.

(Embodiment 15) FIG. 37 shows the configuration of the semiconductor device according to the fifteenth embodiment of the present invention.

FIG. 38 shows a configuration of the semiconductor memory device according to the fifteenth embodiment of the present invention.

Hereinafter, a semiconductor memory device according to a fifteenth embodiment of the present invention will be described with reference to FIGS. 37 and 38.

 In FIG. 37, 1331 is the semiconductor device according to the fifteenth embodiment of the present invention, 1332 is a substrate such as a wafer, 1333 is the semiconductor integrated circuit according to the fifteenth embodiment formed on the substrate 1332, and 1334 is the semiconductor integrated circuit Power supply wiring for supplying power to the circuit 1333 at once, 1335 is ground wiring for grounding the semiconductor integrated circuit 1332 at once, 1336 is a nonvolatile semiconductor memory device such as the flash memory of Embodiment 15, and 1337 is The memory section of the semiconductor memory device 1336, 1338 is an anti-fuse formed between the semiconductor integrated circuit 1333 and the power supply wiring 1334, 1339 is immediately after the test PASS / FAIL information is written in the test data storage area 1312 and the power supply Test data storage area 1312 at the time of startup A volatile register that transfers and stores PASS / FAIL information, 1340 is a resistor that controls the current flowing through the antifuse 1338.

In FIG. 38, 1310 is a memory array, 1311 is a user area memory array used by the user, 1312 is a test data storage area for storing PASS / FAIL information of inspection, 13 13 is an address decoder, 1314 is read and read Sense at read / verify for memory cell drain during write, read / write circuit that applies high voltage during write, 1315 is rewrite control circuit, 1316 is test data storage area 1312 PASS / FAIL for inspection PASS / FAIL Data write control circuit that automatically writes information, 1317 is a power supply circuit such as a booster circuit that generates a high voltage, 1318 is a test and control circuit including a rewrite algorithm controller and test circuit, and 1319 is a command decoder 1320: Data MUX including data input / output switching circuit, 1321: Generates write data and generates expected value when rewriting PASS / FAIL judgment DPU, 1324 is the address counter that generates the address internally, 1325 is the input / output data bus of the flash memory 1309, 1326 is the output bus output from the read / write circuit 1314, 1327 is the external data write data And an input bus for inputting write data from the DPU 1321 to the read / write circuit 1314. [0166] The normal rewriting and inspection are the same as in the fourteenth embodiment.

 [0167] Here, if the fail information of the inspection is stored in the volatile register 1339, the volatile register 1

The ground wiring 1335 is electrically connected through the power supply 339 and the resistor 1340. At this time, current flows through the antifuse 1338 so that it is blown, and Pass / Fan determination is possible depending on whether or not the antifuse 1338 is blown.

[0168] Further, since the end of the inspection also blows the fuse as in the third embodiment of the present invention, the end of the inspection can be determined by whether or not this fuse is blown.

[0169] By detecting whether or not these fuses are blown by, for example, a pattern recognition device, it is possible to make a PASS / FAIL determination, and determine whether or not the assembly is performed by an assembly device system equipped with the pattern recognition device. be able to.

[0170] With such a configuration, PASS / FAIL information can be divided without sending the result of automatic inspection to an external device. For example, an assembly system with a pattern recognition device as it is after non-contact inspection (not yet) It is possible to make only good products in (Display).

[0171] Specifically, the pattern recognition device captures the fuse pattern for each board, dices only the non-defective product according to the information, and picks up the non-defective product.

(Embodiment 16)

 FIG. 39 shows the configuration of the semiconductor device according to the sixteenth embodiment of the present invention.

FIG. 40 shows the configuration of the semiconductor memory device according to the sixteenth embodiment of the present invention.

[0173] Hereinafter, a sixteenth embodiment of the semiconductor memory device of the present invention will be described with reference to FIGS. 39 and 40. FIG.

In FIG. 39, 1341 is the semiconductor device according to the sixteenth embodiment of the present invention, 1342 is a substrate such as a wafer, 1343 is the semiconductor integrated circuit according to the sixteenth embodiment formed on the substrate 1342, and 1344 is the semiconductor integrated circuit. Power supply wiring for supplying power to the circuit 1343 at once, 1345 is ground wiring for collectively grounding the semiconductor integrated circuit 1342, 1346 is a nonvolatile semiconductor memory device such as the flash memory of Embodiment 16, and 1347 is The memory section of the semiconductor memory device 1346, 1348 is an anti-fuse formed between the semiconductor integrated circuit 1343 and the power supply wiring 1344, 1349 is immediately after the test PASS / FAIL information is written in the test data storage area 1312 and the power supply Test data storage area 1312 inspection PASS / FAIL information at startup A volatile register 1350 for transferring and storing is an RF transmission circuit that determines whether or not it is capable of transmitting radio waves according to the contents of the volatile register.

[0175] In FIG. 40, 1310 is a memory array, 1311 is a user area memory array used by the user, 1312 is a test data storage area for storing PASS / FAIL information of inspection, 13 13 is an address decoder, 1314 is read and read Sense at read / verify for memory cell drain during write, read / write circuit that applies high voltage during write, 1315 is rewrite control circuit, 1316 is test data storage area 1312 PASS / FAIL for inspection PASS / FAIL Data write control circuit that automatically writes information, 1317 is a power supply circuit such as a booster circuit that generates a high voltage, 1318 is a test and control circuit including a rewrite algorithm controller and test circuit, and 1319 is a command decoder 1320: Data MUX including data input / output switching circuit, 1321: Generates write data and generates expected value when rewriting PASS / FAIL judgment DPU, 1324 is the address counter that generates the address internally, 1325 is the input / output data bus of the flash memory 1309, 1326 is the output bus output from the read / write circuit 1314, 1327 is the external data write data And an input bus for inputting write data from the DPU 1321 to the read / write circuit 1314.

Note that normal rewriting and inspection are the same as in the fourteenth and fifteenth embodiments.

Here, when the fail information of the inspection is stored in the volatile register 1349, a radio wave is transmitted from the RF transmission circuit 1350. Therefore, Pass / Fl determination is possible depending on whether or not the radio wave is transmitted.

 [0178] Further, since the radio wave is transmitted at the end of the inspection as in the fourth embodiment of the present invention, the end of the inspection can also be determined by the recognition of the radio wave.

[0179] The presence / absence of these radio wave transmissions can be recognized by, for example, an RF receiving device, and a PASS / FAIL determination can be made, so that it is possible to determine whether or not the assembling apparatus system equipped with the radio wave receiving device is used.

[0180] With such a configuration, the result of automatic inspection is divided in a non-contact state. For example, only non-defective products in a stand-up device system (not shown) equipped with a radio wave receiver as it is after non-contact inspection It becomes possible to stand up the thread. [0181] The radio wave receiving device transmits the radio wave transmission pattern transmitted from the RF transmission circuit 1350 for each board, dices only the non-defective product according to the information, and picks it up to assemble only the non-defective product.

 (Embodiment 17)

 FIG. 41 shows the configuration of a nonvolatile semiconductor memory device built in the semiconductor device according to the seventeenth embodiment of the present invention.

FIG. 42 shows the configuration of the temperature detection circuit in the nonvolatile semiconductor memory device built in the semiconductor device according to Embodiment 17 of the present invention.

FIG. 43 shows a block diagram of the inspection standard changing means in the nonvolatile semiconductor memory device built in the semiconductor device according to the seventeenth embodiment of the present invention.

[0184] Hereinafter, a semiconductor device according to a seventeenth embodiment of the present invention will be described with reference to FIGS. 41, 42, and 43. FIG.

In FIG. 41, 1351 is a nonvolatile semiconductor memory device such as a flash memory according to the seventeenth embodiment of the present invention, 1310 is a memory array, 1311 is a user area memory array used by a user, and 1312 is a PASS / FAIL check. Test data storage area for storing information, temperature, etc., 1313 is an address decoder, 1314 is a read / write sense with respect to the memory cell drain, a read / verify sense, and a write / read to which a high voltage is applied Write circuit, 1315 is a rewrite control circuit, 1317 is a power supply circuit such as a booster circuit for generating a high voltage, 1318 is a test and control circuit including a rewrite algorithm controller and a test circuit, 1319 is a command decoder, and 1320 is a data input / output switch. Data MUX 1321, including the circuit, generates the expected value when generating and rewriting the write data and determines PASS / FAIL DPU, 1323 is a P / N junction element that determines whether or not the P / N junction current flows according to the data stored in the volatile register 1322, 1324 is an address counter that internally generates an address, and 1325 is input / output data for the flash memory 1309 1326 is an output bus that is output from the read / write circuit 1314, 1327 is an input bus that inputs external write data, write data from the DPU 1321, etc. to the read / write circuit 1314, and 1352 is at the time of write erase and read Temperature detection circuit that detects temperature such as 1353 is the temperature detection circuit 1352 information for test data storage area 1 Temperature information data write control circuit that automatically writes to 312; 1354 receives test / data storage area 1312 write / erase temperature information during inspection and write / erase level judgment inspection temperature information during reading This is an inspection standard changing circuit that changes the standard.

 In FIG. 42, 1355 is a thermal sensor such as a diode, 1356 is an A / D converter that converts the voltage level of the thermal sensor 1355 into digital information, and 1357 is a register that stores the result of the A / D converter 1356. is there.

 In FIG. 43, reference numeral 1358 denotes a power supply level changing register in the inspection and control circuit 1318, reference numeral 1359 denotes a booster circuit in the power supply circuit 1317, and reference numeral 1360 denotes a regulator in the power supply circuit. The normal rewriting operation is the same as that in Embodiment 14 of the present invention.

 On the other hand, the operation at the time of inspection is to enter the inspection mode when power is supplied from the outside in the state of the wafer, and the inspection is automatically performed according to the inspection flow of the inspection and control circuit 1318.

 [0189] For example, the operation of the automatic writing test will be described. When the checking and control circuit 1318 issues a write command, the rewrite control circuit 1315 instructs the power supply circuit 1317 according to the algorithm to specify the necessary voltage. The power supply circuit 1317 supplies a voltage necessary for rewriting to the memory array 1310 through the address decoder 1313 and the read / write circuit 1314. The difference from normal writing is that the address and data are generated internally by the address counter 1324 and the data by the DPU1321 instead of inputting the address and data by external force.

 At this time, the inspection and control circuit 1318 notifies the temperature detection circuit 1352 that writing is in progress, and the temperature detection circuit 1352 measures the temperature and notifies the inspection and control circuit 1318 that the measurement is completed. The temperature information writing control circuit 1353 is activated in response to the transmission and the temperature measurement result. The temperature information write control circuit 1353 instructs the power supply circuit 1317 to specify the voltage required for writing, and the power supply circuit 1317 supplies the write voltage to the test data storage area 1312 through the address decoder 1313 and the read / write circuit 1314. Information is written into the test data storage area 1312.

[0191] Immediately after this, the inspection and control circuit 1318 sends test data to the inspection standard changing circuit 1354. The command to transfer the temperature information stored in the data storage area 1312 is issued. This temperature information is transferred to the inspection standard changing circuit 1354 even when the power is turned on. Inspection Standard change circuit 1354 specifies power supply circuit 1317 through inspection and control circuit 1318, and specifies the corrected inspection voltage level according to the temperature information at the time of writing and erasing and the reading temperature information at the time of writing and erasing. Supply.

Here, the temperature measuring means will be described with reference to FIG.

 [0193] The potential difference of Thermal Sensorl355 (hereinafter referred to as a diode) such as a diode varies depending on the temperature. This voltage value change is converted to a digital value by the A / D converter 1356. By transferring the digital value to the register 1357, the temperature information is stored in the register 1357. The inspection and control circuit 1318 writes the temperature information in the test data storage area 1312 by the above means.

 [0194] Next, the inspection standard changing means will be described with reference to FIG.

 [0195] The temperature information written in the test data storage area 1312 is transferred to the inspection standard changing circuit 1354 to regulate the voltage level of the booster circuit 1359. The regulator for changing the voltage level of the 1360 and the power supply in the control circuit The level information is converted into voltage level data of the regulator 1360 and transferred to the level change register 1358 so as to correct the temperature information and the temperature information at the time of reading. For example, the voltage level of the inspection standard at the time of level inspection after writing and erasing can be changed by the voltage level conversion data.

 [0196] With this configuration, it is possible to perform inspection at a place where temperature control is not possible, such as during transportation or storage in a warehouse.

 (Embodiment 18)

 FIG. 44 is a configuration diagram of a semiconductor integrated circuit that realizes a test using only the power supply pad and the ground pad according to the eighteenth embodiment of the present invention. In the figure, a semiconductor integrated circuit 1900 includes an internal circuit 1905, a self-test circuit 1904 for executing a self-test of the internal circuit, and a power supply modulation circuit 1906. These circuits are powered by power pad 1901 and ground pad 1 902. The internal circuit 1905 is a main circuit of the semiconductor integrated circuit, and executes a normal operation outside the integrated circuit and through a normal signal pad 1903.

Hereinafter, execution of the self-test circuit 1904 will be described. The self-test circuit Upon receiving an input signal such as a command or microcode from the tuning circuit 1906, the system is started and a test pattern is given to the internal circuit 1905 to execute the test. The test result is written back to the power supply modulation circuit 1906.

 [0198] An input signal and an output signal to the self-test circuit 1904 are superimposed on the power supply pad 1901. The concept of signal superposition on the power supply pad will be described with reference to FIGS. Figures 45 and 46 show the power supply voltage and power supply current waveforms to the power supply pad as seen from the test equipment. In the figure, the input signal of the test equipment is higher than the normal power supply potential as input signal 1907! 与 え It is given as a time series of surge-like pulses and converted into a digital signal by a comparator etc. in the power supply modulation circuit 1906 And supplied to the self-test circuit 1904. The time series of surge-like pulses is a force that appears to propagate directly to the internal circuit 1905 in the figure. Actually, it is absorbed by the power supply modulation circuit 1906 and the binos capacitor of the power supply wiring, and is hardly propagated to the internal circuit. Nah ...

 [0199] The output signal of the self-test circuit 1904 is converted into a current pulse between the power supply grounds by the power supply modulation circuit 1906, and is detected as a time-series current pulse like the output signal 1908 on the test device side. The test device converts the current pulse into a digital pulse and records the test result.

 [0200] By outputting current pulses from the inside to the outside of the semiconductor integrated circuit, a higher S / N ratio can be obtained more easily than when voltage is output. This is because a large-capacity power booster circuit is required to apply voltage pulses to the external force, and it is easy to provide these on the test device side, but it is difficult to integrate them on the circuit side.

 [0201] According to the present embodiment, a self-test of a semiconductor integrated circuit can be executed with a minimum number of pins including only a power supply pad and a ground pad. As a result, with a small number of contacts, it is possible to perform a test with a high parallel number with an inexpensive hard disk, and the test cost can be reduced. Furthermore, a decrease in yield due to contact failure can be suppressed by the minimum number of contacts.

[0202] In the present embodiment, the power supply pad is selected as the signal superimposition destination. However, even if the ground pad is selected, only the power supply voltage level becomes the ground potential, and the same effect can be obtained. . Furthermore, in this embodiment, in order to solve the problem of malfunction caused by noise mixed in the power supply pad, the potential of the input signal 1907 is sufficiently adjusted to match the power supply noise level. High reliability is achieved by setting a special time-series data pattern in the input signal 1907 and inputting only the input signal 1907 that matches the data pattern in the power modulation circuit 1906 as valid data to the self-test circuit 19004. Tests can be performed.

 (Embodiment 19)

 FIG. 47 is a configuration diagram of a semiconductor integrated circuit in which a non-contact test is realized by power supply and signal input by the optical power conversion element and signal output by the light emitting element in Embodiment 19 of the present invention. In the figure, a semiconductor integrated circuit 2000 is composed of an internal circuit 2005 in which main functions are integrated, a self-test circuit 2004 for executing a self-test of the internal circuit, a demodulating circuit 2007, an optical power conversion element 2007, and a light-emitting element 2008. The internal circuit 2005 is supplied with power from the power supply pad 2001 and the ground pad 2002 in normal operation other than the test.

 [0203] The test state will be described below. In the test state, the optical power conversion element is responsible for power supply and signal input to the self-test circuit, and the light-emitting element is responsible for signal output of the self-test circuit power.

 [0204] The optical power conversion element 2007 is formed by a PN junction that can be formed by a CMOS process, and generates electric power by irradiating convergent light such as a semiconductor laser. The irradiated focused light generates electron hole pairs in the depletion layer of the PN junction and generates electromotive force. The voltage and current drive capability is adjusted by series-parallel of PN junctions. The demodulator circuit 2006 controls the generated voltage to a constant voltage by an internal power supply regulator and supplies it to the power supply pad 2001. The converging light from the test equipment is modulated by commands to the self-test circuit 2004 and input signals such as microcode. The convergent light modulated by intensity or the like is converted into a digital signal by the detection circuit in the demodulation circuit 2006 and input to the self-test circuit 2004.

 [0205] The light emitting device 2008 controls the emission phenomenon generated from a PN junction with a thin depletion layer thickness that can be formed by a CMOS process by a transistor inserted in series. The self-test circuit 2 004 drives the light emitting element 2008 to transmit the test result and the test progress signal as a light pulse to the test apparatus. As the light emitting element, near infrared light by breakdown by PN junction may be used.

[0206] According to the present embodiment, during the test, the non-contact power supply and the input and output data This enables communication and eliminates the need for electrical contacts, which can dramatically improve the number of parallel tests. In addition, the influence of power supply noise caused by the interface board of the test equipment due to non-contact (In the conventional configuration that requires electrical contact, it is difficult to keep all DUTs at the same regulation during massively parallel testing. ) Is completely eliminated, and even in a massively parallel test, the power regulation of each non-measurement semiconductor integrated circuit (DUT) can be kept uniform, and the uniformity of the test can be guaranteed. The noise due to the operation of the pad circuit of the semiconductor integrated circuit, which is still a problem in the contact test, can be completely eliminated, and the input / output data transfer speed can be increased.

[0207] In this embodiment, since a light emitting element using a PN junction by a normal CMOS process is used as the light emitting element, an integration time of several ms level is required to receive light on the test apparatus side. Since the data volume of the test results is relatively low, even a low bit rate is practical enough. The effect of realizing a light-emitting device with an area penalty of about the smallest transistor in a normal CMOS process is great.

 [0208] Needless to say, if the light emitting element is realized by an element such as a normal laser or LED, communication at a higher bit rate is possible except for the cost. The same applies to the optical power conversion element. If a higher-speed and higher-efficiency element is used, communication at a higher bit rate can be performed except for the cost.

 [0209] Furthermore, according to the present embodiment, it is possible to easily shut off the power supply and simply exclude it from the subsequent test by simply stopping the irradiation of the convergent light to the defective chip found during the parallel test on the wafer. it can. As a result, it is possible to eliminate interference such as abnormal temperature rise and substrate noise of the defective chip to the adjacent chip, and improve test quality in the massively parallel test.

 (Embodiment 20)

 FIG. 48 is a configuration diagram of a semiconductor integrated circuit that realizes a non-contact test by power supply and signal input by the optical power conversion element and signal output by wireless data transmission in Embodiment 20 of the present invention. In the present embodiment, the light emitting element in the nineteenth embodiment is replaced with a wireless data transmission circuit.

[0210] In the figure, the semiconductor integrated circuit 3000 uses the self-test circuit 2004 output as wireless data. The signal is modulated to a high frequency by the transmission circuit 3001 and radiated from the antenna 3002. When the wireless data transmission circuit 3001 is an ordinary fine CMOS (for example, ft = 40—80 GHz can be realized with a 0.13 μm process), it can transmit several GHz. In the case of 5 GHz transmission, the antenna is about 1.5 cm in 1/4 wavelength, and if it is shortened, it can be integrated into several millimeters of semiconductor integrated circuits. Since the antenna of the test equipment can be installed in the vicinity, the transmission output and the antenna radiation efficiency will not be a problem.

 [0211] According to the present embodiment, during the test, as in the case of the nineteenth embodiment, non-contact power supply and input / output data exchange are possible, and no electrical contact is required, and the number of parallel tests is dramatically improved. be able to. In addition, since the output of semiconductor integrated circuits is performed wirelessly, integration time is not required compared to PN junction light-emitting elements, enabling faster reading. By adapting the radio only to data transfer to the test equipment, it is possible to install the smallest antenna (no reception sensitivity problem because it is not used for reception), and minimize the increase in chip area due to the antenna. be able to. The antenna 3002 can be installed on the outer periphery of the integrated circuit, on a scribe lane, or by adding a dedicated wiring layer to the top layer.

 [0212] In the case of a wireless non-contact parallel test, it is necessary to clarify the transmission source, which is different from data communication using clear light. Therefore, in this embodiment, the wireless data transmission circuit 3001 includes a semiconductor. An identification ID unique to the integrated circuit is set. All transmitted wireless data includes digital information of identification ID, and the test equipment can determine which semiconductor integrated circuit power information. This identification ID can be downloaded to the test equipment power semiconductor integrated circuit immediately before the start of the test, or can be created in the manufacturing process of the semiconductor integrated circuit. When creating a unique ID in the manufacturing process (EB drawing, fuse, etc.), it is preferable to provide redundant bits. The identification ID to be created is preferably unique at least in units of wafers, and it is most preferable in terms of defect analysis to be a unique value in lot units or completely unique values.

 (Embodiment 21)

FIG. 49 shows a semiconductor integrated circuit in which a non-contact test is realized by power supply by the optical power conversion element and signal input / output by wireless data transmission in Embodiment 21 of the present invention. It is a block diagram. In the present embodiment, the function of signal input (data reception of test equipment power) by the optical power conversion element in Embodiment 20 is replaced with a wireless data reception circuit.

 [0213] In the figure, the semiconductor integrated circuit 4000 controls the output voltage of the test optical power conversion element 2007 to a constant voltage by the power supply regulator in the smoothing circuit 4001 and supplies it to the power supply pad 2001. The input / output signals of the self-test circuit communicate with the test equipment via the antenna 4003 by the wireless data transmission / reception circuit 4002. Since it is necessary to receive wireless data from the test equipment, reception sensitivity is required, but the increase in the antenna 4003 can be minimized by increasing the wireless output of the test equipment.

 [0214] In case of wireless non-contact parallel test, it is necessary to set the identification ID for the upload signal to the test equipment. With regard to the download signal of the test equipment, an identification ID is not required for downloading microcode etc. common to all semiconductor integrated circuits, but data with an identification ID is required for individual test control. . The wireless data transmission / reception circuit 4002 reads the data identification ID and transmits it to the self-test circuit 2004 only when the identification ID matches the set value.

 [0215] The following describes how to set the identification ID when it is not created in the manufacturing process. The wireless data transmission / reception circuit 4002 is set with an identification ID, and only the identification ID setting function can be received and executed in the state. For transmission, an ID indicating that the identification ID has not been set oscillates for a certain period during irradiation of convergent light. This function is used for initial diagnosis of wireless data transmission / reception circuits. Once the identification ID is set, the identification ID does not match. The power transmission / reception circuit does not transmit the download signal including the identification ID setting to the self-test circuit.

 [0216] When the identification ID is first set by the test apparatus, only a single semiconductor integrated circuit is activated and the desired identification ID is set with or without convergent light. Once a semiconductor integrated circuit with an identification ID is set, commands can be blocked by the identification ID, so it is kept in the convergent light irradiation state. This focused light irradiation state is indispensable when the identification ID is stored in the volatile memory. This is not required if the identification ID is stored in non-volatile memory including an electrical fuse.

[0217] According to the present embodiment, during the test, the non-contact power supply and the input and output data This enables communication and eliminates the need for electrical contacts, which can dramatically improve the number of parallel tests. In addition, the test apparatus does not require modulation of the convergent light, and an inexpensive light source can be used, thereby reducing the cost. In addition, a semiconductor integrated circuit does not require an optical data demodulation circuit.

 [0218] Further, in this embodiment, in the case of a wireless test, an essential concept of identification ID and an identification ID setting protocol integrated in the wireless data transmission / reception circuit are provided.

 (Embodiment 22)

 FIGS. 50 and 51 are cross sections and top views of a test apparatus for a semiconductor integrated circuit in which a non-contact test is realized by power supply and signal input by an optical power conversion element and signal output by a light emitting element in Embodiment 22 of the present invention. It is a block diagram.

[0219] In the figure, the test apparatus is a laser source for power supply and data transmission arranged on the array so as to correspond to the semiconductor integrated circuit on the semiconductor integrated circuit wafer 5006 on the test apparatus casing 5001 and the printed circuit board 5004. It consists of a pair of a receiving optical sensor 5002 and a laser drive circuit data communication circuit 5003, a radiator / wafer holder 5007, and a control circuit 5008.

 [0220] The radiator / wafer holder 5007 absorbs the heat generated by the semiconductor integrated circuit and the photoelectric conversion element. Moreover, it is desirable to provide an opening directly under the optical power conversion element in order to suppress irregular reflection of the laser that has penetrated.

 [0221] From the opening 5005 provided in the test apparatus casing 5001, power supply by laser, data download, and upload optical signal of semiconductor integrated circuit power are delivered. Laser drive circuit—data communication circuit 5003 executes power adjustment of a laser light source, modulation of a download signal, and signal processing of an upload signal from a data light receiving sensor. The control circuit 5008 stores the data log of the control of the laser drive circuit-data communication circuit 5003, the state of the fail pass of the test of each semiconductor integrated circuit, and the progress of the processing of the test item. The test result of each semiconductor integrated circuit can be determined by referring to the data log.

[0222] According to the present embodiment, it is possible to provide a test apparatus that realizes a non-contact parallel test of a semiconductor integrated circuit by optical communication described so far. In this embodiment, a data receiving sensor is provided for each semiconductor integrated circuit. The same effect can be obtained with one configuration for each chip.

 (Embodiment 23)

 52 and 53 are configuration diagrams of a test apparatus for a semiconductor integrated circuit that realizes a non-contact test by supplying power with the optical power conversion element and signal input / output by wireless data transmission / reception in Embodiment 23 of the present invention. .

 [0223] In the figure, the test apparatus is a power supply laser light source 6002 and a laser drive circuit arranged on an array so as to correspond to a semiconductor integrated circuit on a semiconductor integrated circuit wafer 5006 on a test apparatus casing 6001 and a printed circuit board 5004. It consists of a pair of 6003, a wireless data transmission / reception circuit 6004, an antenna array 6006 of a wireless data transmission / reception circuit, a radiator / wafer holder 5007, and a control circuit 5008. The difference from the twenty-second embodiment is that wireless is used for receiving the upload signal of the semiconductor element and for the download signal to the semiconductor integrated circuit. In this embodiment, an antenna array 6006 is provided so as to cover the entire surface of the semiconductor wafer. The antenna array can concentrate the beam characteristics of transmission and reception on each semiconductor integrated circuit, receive a small upload signal with high SN, poor sensitivity, download signal with high electric field strength toward the antenna of the semiconductor integrated circuit Can be supplied.

 [0224] According to the present embodiment, it is possible to provide a test apparatus that realizes a non-contact parallel test of a semiconductor integrated circuit by wireless communication described so far. In this embodiment, it is possible to use an inexpensive light source that does not require the modulation of the convergent light.

 It goes without saying that the same effect can be obtained even if the features of Embodiment 22 are incorporated as a test apparatus.

 Industrial applicability

[0226] The method for inspecting a semiconductor device according to the present invention includes a wafer state in any one of a wafer transport process, a standby process, an assembly process, and an assembly transport process in which product diffusion power exists before shipment. By inspecting the inspection process and the package status inspection process, the inspection time can be apparently set to “0”, and the inspection progress information is stored even when the inspection is interrupted or crosses the process. Therefore, there is no need for a dedicated inspection site without fixing the inspection location, and any process can be inspected, and the number of inspection specialized processes can be reduced, thereby reducing the inspection cost to zero. Made of all semiconductors because it can _C is useful as an inspection method and inspection apparatus goods

Claims

The scope of the claims

 [I] Between the completion of the diffusion of the semiconductor product and the shipment, it includes at least one of a wafer transfer process, a standby process, an assembly process, and an assembly transfer process. A method of inspecting a semiconductor device, wherein the inspection is performed by distributing the process and the package state inspection process.

 [2] A semiconductor device having an inspection device for carrying out the semiconductor device inspection method according to claim 1 in a semiconductor integrated circuit, wherein the inspection device has completed the inspection during any one of the steps. Or the inspection progress information is recorded when the inspection in the process is interrupted, and the inspection progress information in the process can be continued by referring to the inspection progress information. A featured semiconductor device.

3. The semiconductor device according to claim 2, wherein the inspection by the inspection apparatus is performed by supplying power to the semiconductor integrated circuit.

4. The semiconductor device according to claim 3, wherein the inspection device uses a mask ROM.

5. The semiconductor device according to claim 4, wherein the inspection device uses a RAM.

6. The semiconductor device according to claim 3, wherein the inspection device transfers software for inspection from outside the semiconductor integrated circuit to a nonvolatile semiconductor memory device inside the semiconductor integrated circuit.

7. The semiconductor device according to claim 2, wherein a fuse is used as storage means for storing the inspection progress information.

 8. The semiconductor device according to claim 2, wherein a non-volatile semiconductor memory device is used as the memory means for storing the inspection progress information.

9. The semiconductor device according to claim 2, further comprising means for storing the inspection progress information outside.

10. The semiconductor device according to claim 9, wherein a semiconductor memory device provided on a device that supplies power is used as the memory means for storing the inspection progress information.

 [I I] The semiconductor device according to claim 2, wherein the inspection progress information is a ROM address or a RAM address.

 12. The semiconductor device according to claim 2, further comprising a counter inside the semiconductor integrated circuit, wherein the inspection progress information is stored at a constant cycle.

[13] The semiconductor according to claim 2 or 9, wherein the inspection progress information is stored in accordance with an inspection section. Body equipment.

 14. The semiconductor device according to claim 2, wherein the inspection progress information is stored when a power-off signal output to the semiconductor integrated circuit is activated.

15. The semiconductor device according to claim 2, further comprising a detection circuit at a power supply terminal in the semiconductor integrated circuit, wherein the inspection progress information is stored when a voltage drop is detected.

[16] The power supply path in the semiconductor integrated circuit has a capacitance. When the power supply is unexpectedly cut off, the power supply node of external power is cut off and the power supply path of the capacitance in the semiconductor integrated circuit is opened. 3. The semiconductor device according to claim 2, wherein the inspection progress information is stored during that time.

[17] The power supply path outside the semiconductor integrated circuit has a capacitance, and when the power supply is unexpectedly cut off, the power supply path outside the semiconductor integrated circuit is cut off and the capacitance outside the semiconductor integrated circuit The semiconductor device according to claim 2, wherein the power supply path is opened and the inspection progress information is stored in the meantime.

 18. The semiconductor device according to claim 17, wherein the package covering the semiconductor integrated circuit has a capacitance.

 [19] The semiconductor device according to [2], wherein the inspection execution time is managed, the elapsed time is grasped by comparing the inspection execution times before and after each inspection, and the inspection criterion is varied.

[20] A request for storing the test execution time of each test and comparing the test execution time of the next test outside the semiconductor device circuit, and transferring elapsed time information from the outside of the semiconductor integrated circuit when the power is turned on Item 20. A semiconductor device according to Item 19.

21. A test execution time of each test is stored, a circuit for comparing the test execution time of the next test is provided in the semiconductor device circuit, and elapsed time information is stored in the semiconductor integrated circuit. The semiconductor device described.

[22] Claim that, as means for turning on the power to the semiconductor integrated circuit, an inspection device equipped with an RF transmitter is used to convert the power to the power by transmitting radio waves to the RF receiver provided in the semiconductor integrated circuit. Item 4. A semiconductor device according to Item 3.

[23] As a means for inputting software for automatically inspecting the semiconductor integrated circuit from the outside, the inspection program stored in the memory card is inserted into the inspection device by inserting the memory card into the inspection device. Claim 6 that is transferred into the integrated circuit to perform the test. The semiconductor device described.

 [24] As a means for inputting software for automatically inspecting the semiconductor integrated circuit from the outside, a device including an RF transmitter is used to transmit radio waves to the RF receiver included in the semiconductor integrated circuit. 7. The semiconductor device according to claim 6, wherein the inspection program is transferred to the inside of the semiconductor integrated circuit to be inspected by transmitting the information and executed.

 [25] A claim, comprising: a substrate, a plurality of semiconductor integrated circuits formed on the surface of the substrate at once, and an inspection device that automatically performs inspection by supplying power to the semiconductor integrated circuits all at once. Item 3. A semiconductor device according to Item 3,

 A power supply wiring connected to all of the semiconductor integrated circuits, a ground wiring connected to all of the semiconductor integrated circuits, and between the semiconductor integrated circuit and the power supply wiring or between the semiconductor integrated circuit and the ground wiring. And a fuse inserted into each semiconductor integrated circuit.

26. The semiconductor device according to claim 24, wherein a coil of the RF receiver is provided on the back surface of the substrate, and is connected to the power supply wiring or the RF transceiver circuit on the substrate surface through a through hole.

[27] A claim, comprising: a substrate; a plurality of semiconductor integrated circuits formed on the surface of the substrate at once; and an inspection device that automatically performs inspection by supplying power to the semiconductor integrated circuit collectively. Item 3. A semiconductor device according to Item 3,

 Test data storage area for storing PASS / FAIL information for inspection, volatile register for transferring PASS / FAIL information stored in the test data storage area, and P / N junction current depending on the contents of the volatile register A semiconductor device comprising: a P / N junction element that determines whether the semiconductor integrated circuit is non-defective or defective by the P / N junction element.

 [28] A board, a plurality of semiconductor integrated circuits formed on the surface of the substrate at once, and an inspection device that automatically performs inspection by supplying power to the semiconductor integrated circuit all at once. Item 3. A semiconductor device according to Item 3,

Test data storage area for storing inspection PASS / FAIL information, volatile registers for transferring PASS / FAIL information stored in the test data storage area, power supply wiring, and board An antifuse disposed between all the semiconductor integrated circuits formed above, and determining whether or not the antifuse can be blown according to the contents of the volatile register. A semiconductor device characterized by being able to identify non-defective products.

 [29] A substrate, a plurality of semiconductor integrated circuits collectively formed on the surface of the substrate, and an inspection device that automatically performs inspection by supplying power to the semiconductor integrated circuits all at once. Item 3. A semiconductor device according to Item 3,

 Test data storage area that stores the PASS / FAIL information of inspection, volatile register that transfers PASS / FAIL information stored in the test data storage area, and whether to transmit radio waves depending on the contents of the volatile register A semiconductor device, wherein a non-defective product of the semiconductor integrated circuit can be identified by the RF transmitter element

[30] A semiconductor memory device, a temperature sensor circuit for detecting a temperature at the time of writing or erasing the semiconductor memory device, a test data storage area for storing information on inspection temperature, and a writing at the time of testing the test data storage area An inspection standard changing circuit that receives the temperature information at the time of reading / erasing temperature information and the temperature information at the time of reading of the writing / erasing level judgment inspection to change the inspection standard, and 4. The semiconductor device according to claim 3, wherein the semiconductor device is automatically stored and the inspection standard is automatically corrected according to the temperature.

 31. A semiconductor integrated circuit comprising an inspection device using the semiconductor device inspection method according to claim 1, comprising a power pad, a ground pad, and a self-test circuit, wherein the power pad and the ground pad are signals. A semiconductor integrated circuit, which is used in combination with a pin, and the self-test circuit performs a self-test by an input / output signal superimposed on the power supply node and the ground pad.

 [32] A semiconductor integrated circuit having an inspection apparatus using the method for inspecting a semiconductor device according to claim 1, comprising an optical power conversion element, and driving power is supplied to the optical power conversion element by external convergent light. A semiconductor integrated circuit which is supplied by selective irradiation.

[33] The method for testing a semiconductor integrated circuit according to claim 32, wherein the semiconductor integrated circuit determined to be defective during the test is configured to block the convergent light and exclude it from the subsequent tests. Integrated circuit test method.

34. A semiconductor integrated circuit comprising an inspection apparatus using the inspection method for a semiconductor device according to claim 1, comprising an optical power conversion element and a light emitting element, wherein the optical power conversion element supplies a driving power and externally. A semiconductor integrated circuit, wherein the semiconductor integrated circuit is responsible for receiving data, and the light emitting element is responsible for transmitting internal data.

 35. The semiconductor integrated circuit according to claim 34, wherein near-infrared light by PN junction breakdown is used as the light emitting element.

 36. The semiconductor integrated circuit test apparatus according to claim 34, comprising a plurality of light receiving sensor elements for receiving data, and a plurality of laser light sources responsible for power supply and data transmission, and the semiconductor integrated circuit A test apparatus for semiconductor integrated circuits, characterized in that a non-contact test is performed in a woofer state.

 [37] A semiconductor integrated circuit comprising an inspection device using the method for inspecting a semiconductor device according to claim 1, comprising an optical power conversion element and a wireless data transmission circuit, wherein the optical power conversion element supplies driving power. A semiconductor integrated circuit characterized in that it receives external data and the wireless data transmission circuit is responsible for transmission of internal data.

 [38] A semiconductor integrated circuit having an inspection apparatus using the method for inspecting a semiconductor device according to claim 1, comprising a photoelectric power conversion element and a wireless data transmission circuit, wherein the optical power conversion element has a driving power. A semiconductor integrated circuit characterized in that it is responsible only for supply and the wireless data transmission circuit is responsible for transmission and reception of internal data.

 39. The semiconductor integrated circuit according to claim 37, wherein the wireless data transmission circuit transmits an identification ID unique to the semiconductor integrated circuit.

 [40] The method for testing a semiconductor integrated circuit according to claim 37, wherein the wireless data transmission circuit sets the identification ID via an optical power conversion element when transmitting a unique identification ID to the semiconductor integrated circuit. A method for testing a semiconductor integrated circuit.

 41. The semiconductor integrated circuit test method according to claim 38, wherein when the wireless data transmission circuit transmits an identification ID unique to the semiconductor integrated circuit, the identification ID is irradiated to the optical power conversion element. A method for testing a semiconductor integrated circuit, which is selected based on the presence or absence of the device and is set via wireless.

[42] Process different or unique identification ID for each chip in a semiconductor integrated circuit wafer 40. The semiconductor integrated circuit according to claim 39, which is formed in advance in a process.

[43] The semiconductor integrated circuit test device according to claim 37, comprising: a wireless data receiving device for receiving data; and a plurality of convergent light sources for supplying power and transmitting data; A test system for semiconductor integrated circuits characterized by non-contact testing.

 [44] The semiconductor integrated circuit test device according to claim 38, comprising: a wireless data transmitting / receiving device for transmitting and receiving data; and a plurality of convergent light sources for supplying power, wherein the semiconductor integrated circuit is in a woofer state. Semiconductor integrated circuit test apparatus characterized by non-contact test