JP5153089B2 - Inspection method of semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a configuration of a standard cell for performing a circuit test of a semiconductor device.

  In recent years, various electronic devices have been required to have multiple functions. Accordingly, more functions are required for a circuit that operates an electronic device, and the scale of the circuit is increased. Conventionally, in order to easily produce a large-scale circuit, a method is used in which cells (standard cells) are separately formed according to function, individual cells are arranged by automatic layout, and the cells are connected by wiring. For example, NAND circuits, flip-flop circuits, buffer circuits, etc. are standard cells, and each standard cell is placed at an appropriate position using an automatic placement and routing tool. Make it.

  As the scale of the circuit increases, the rate of occurrence of defective portions in the circuit also increases, so a method for easily detecting defective portions with high accuracy is required. Therefore, as a circuit defect inspection method, for example, a method for easily detecting an arbitrary node potential on a circuit by automatically arranging standard cells including a voltage detection pad is proposed (Patent Document). 1).

  However, it is necessary to measure not only the voltage but also the current when performing a circuit defect inspection. If there is a current leak point in the circuit, the reliability of the circuit may be affected. In addition, when a current larger than necessary flows in the circuit due to a leak or the like, there is a possibility that the circuit is heated or damaged, power consumption is increased, or the like. Therefore, it is necessary to specify a region or wiring having a large current consumption in the circuit and correct the circuit. Particularly in the development of an RFID chip, since power consumption is related to the communication distance, it is necessary to detect a current flow in detail, find a portion with a large current consumption (defective portion), and suppress power consumption.

Therefore, as a method of measuring the current of a specific node on the circuit of the semiconductor device, a method of manually providing two or more test pads in a vacant area where there is no wiring or the like in the layout wiring area so that the pads do not contact each other. Has been proposed. The current flowing on the circuit of the semiconductor device can be measured by applying a current measuring instrument needle to each of the two test pads to create a current path between the two test pads.
JP-A-2-191359

  However, in the case of a method in which two or more test pads are manually provided so that the pads do not come into contact with each other, it is necessary to design in advance a signal line in which an overcurrent is generated from among many signal lines in the circuit. It is very difficult to select a signal line (or specify a defective part) from a number of wirings at the time of layout creation or before circuit operation. If you make a mistake in wiring selection, you need to measure signal lines that do not need to be measured. The waste of doing. This leads to delays in product development and an increase in product unit price.

  In addition, since the test pads for measuring signals must be manually provided in the free area of the wiring area after the layout pattern is created, not only the layout time is increased, but also logic errors and layout errors due to work may be caused. there were.

  In addition, since the wiring density is small and empty areas where the test pads can be provided are scattered in the circuit, the test pads are scattered in various places in the circuit. For this reason, when performing the measurement, an operation of searching for a pad to be measured and an operation of tracing the signal line are required, and the measurement operation becomes more complicated. In addition, when a space for providing a test pad is not provided on the layout, the wiring must be largely routed and the test pad must be provided at a location far from the circuit portion to be examined. This causes an increase in wiring load and an increase in parasitic capacitance, leading to attenuation of signals in the circuit and an increase in power consumption. Furthermore, noise may be easily picked up by drawing the wiring for a long time.

  In view of the above situation, it is an object to provide a standard cell that can easily find a signal line through which a large amount of current flows in a circuit to be designed and can easily measure the current in that portion. It is another object of the present invention to provide a layout method and a measurement method that can easily add or delete test pads. It is another object of the present invention to provide a layout method in which a circuit can stably operate without adding a test pad and drawing a wiring longer than necessary.

  The present invention is characterized in that standard cells having at least two test pads for current detection are arranged by an automatic layout method. The two test pads are connected by wiring, and the two test pads are used as current measurement test pads by cutting the wiring. In the present invention, the two test pads in the standard cell may be electrically connected by a wiring that interrupts a current flow path due to an overcurrent flow. In the present invention, the two test pads may be connected via a memory or an analog switch.

  The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit in which a plurality of standard cells are arranged by an automatic layout method. The first standard cell is electrically connected to at least two test pads and the first test pad. A first wiring to be connected, and a second wiring to be electrically connected to the second test pad, wherein the first test pad and the second test pad include a third wiring. The first test pad and the second standard cell are electrically connected via the first wiring, and the second test pad and the third standard cell are electrically connected to each other. Are electrically connected via the second wiring.

  The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit in which a plurality of standard cells are arranged by an automatic layout method. The first standard cell is electrically connected to at least two test pads and the first test pad. A first wiring to be connected; and a second wiring to be electrically connected to the second test pad. The first test pad and the second test pad include a memory or an analog switch. The first test pad and the second standard cell are electrically connected via the first wiring, and the second test pad and the third standard cell are electrically connected to each other. Are electrically connected via the second wiring.

  In the semiconductor integrated circuit of the present invention, in the semiconductor integrated circuit in which a plurality of standard cells are arranged in an automatic layout system, the first standard cell is electrically connected to at least two test pads and the first test pad. A first wiring to be connected and a second wiring to be electrically connected to the second test pad, and an overcurrent flows through the first test pad and the second test pad. The first test pad and the second standard cell are electrically connected via the first wiring. The second test pad and the third standard cell are electrically connected through the second wiring.

  The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit in which a plurality of standard cells are arranged by an automatic layout method. The first standard cell is electrically connected to at least two test pads and the first test pad. A first wiring to be connected; and a second wiring to be electrically connected to the second test pad, wherein the first test pad and the second test pad are not uniform in width. The first test pad and the second standard cell are electrically connected via the third wiring, and the second test pad and the second test cell are electrically connected via the third wiring. 3 is characterized in that the standard cells are electrically connected via the second wiring.

  In the semiconductor integrated circuit according to the present invention, the third wiring is partially different in resistance.

  The semiconductor integrated circuit inspection method of the present invention is a semiconductor integrated circuit inspection method in which a plurality of standard cells are arranged by an automatic layout method. The first standard cell includes at least two test pads and the first test. A first wiring electrically connected to the pad, a second wiring electrically connected to the second test pad, and the first test pad and the second test pad are electrically connected. A third wiring, wherein the first test pad and the second standard cell are electrically connected via the first wiring, and the second test pad and the third The plurality of standard cells are arranged by an automatic layout method so as to be electrically connected to the standard cell via the second wiring, the third wiring is cut, and the first wiring By contacting the current measuring terminal to Sutopaddo and the second test pad, and measuring the current flowing between the first test pad and the second test pad.

  In the semiconductor integrated circuit inspection method of the present invention, the third wiring is cut by a laser.

  In the inspection method of a semiconductor integrated circuit according to the present invention, the third wiring is disconnected when an overcurrent flows.

  According to the present invention, a signal line through which a large amount of current flows can be easily found in a circuit to be designed, and the current in that portion can be easily measured. Furthermore, it is possible to easily add or delete test pads. Further, by adding a test pad, it is possible to operate the circuit stably without routing the wiring longer than necessary.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numeral is used in different drawings. Further, in the present invention, being connected is synonymous with being electrically connected. Therefore, another element or the like may be disposed between them. Further, Embodiments 1 to 7 can be used in any combination.

(Embodiment 1)
In this embodiment mode, a layout design method for a semiconductor device of the present invention will be described with reference to the drawings. One of the standard cells shown in this embodiment has at least two test pads. A standard cell is the smallest structural unit of a circuit.

  FIG. 1 shows a schematic diagram of a standard cell of the present embodiment. The standard cell 108 in FIG. 1 includes a VDD power line 101, a GND power line 102, test pads 103 to 104, and wirings 105 to 107. Note that the VDD power line 101, the GND power line 102, the test pads 103 to 104, and the wirings 105 to 107 are formed of a conductive material. Further, the test pad 103 and the test pad 104 are electrically connected by a wiring 105. Further, the wiring 106 is connected to the test pad 103, and the wiring 107 is connected to the test pad 104. Here, the wiring 106 functions as an input port, and the wiring 107 functions as an output port. Signals can be exchanged with other standard cells and circuit blocks via the input port and the output port. In this embodiment, since the wirings 105 to 107 and the test pads 103 and 104 are provided on the same straight line, the width of the standard cell for the test pad can be reduced. By reducing the width of the standard cell, the circuit area can be reduced and the power consumption can be reduced.

A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) with the standard cell 108 as a circuit unit. Can be obtained. That is, the wirings 106 and 107 in FIG. 1 are connected to other standard cells, respectively, and the test pads 103 and 104 are electrically connected to other standard cells via the wirings 106 and 107, respectively.

  Next, a method of measuring a current at a specific terminal using the test pads 103 and 104 after configuring a desired circuit by automatic layout will be described. In the standard cell, when the test pads 103 and 104 are connected by the wiring 105, the current flowing from the input port 106 flows to the output port 107 through the test pad 103, the wiring 105 and the test pad 104. . Here, the voltage of an arbitrary terminal may be measured using the test pad 103 or the test pad 104 as a test pad for voltage measurement, and the terminal whose current is to be measured may be specified.

Then, a test pad corresponding to a terminal whose current is to be measured (here, referred to as test pads 103 and 104 (FIG. 1 )) is selected, and wiring corresponding to the two test pads (here, wiring 105 corresponds to ( 1 )) is cut using a laser or the like. As a result, the two test pads 103 and 104 are insulated. Then, a current measuring instrument is applied to each of the two insulated test pads 103 and 104 to measure the current to identify a defective portion.

  Further, in this embodiment, since it is not necessary to provide test pads in a narrow and densely lined area such as a wiring area outside the standard cell arrangement area, layout correction for providing the test pad is performed on a large scale. Therefore, it is possible to prevent layout mistakes during layout correction. Furthermore, the time spent for layout correction can be reduced. Furthermore, since the standard cell including the test pad can be arranged in the same region as other standard cells, it is possible to increase the arrangement area of the test pad. Therefore, the operation of applying the current measuring instrument needle becomes easier. Further, since the wiring other than the signal line to be measured is located far from the test pad, the possibility of damaging the other wiring when the operation of applying the needle of the current measuring device fails can be reduced.

  Further, in the present embodiment, after standard cells having two test pads are arranged in an automatic layout, the wiring connecting the two test pads is cut to isolate the test pads. Therefore, the current measurement terminals can be easily changed for each chip. By using the standard cell of this embodiment mode, it is not necessary to change the mask even when the terminal for current measurement is changed for each chip, so that a low-cost semiconductor device can be manufactured. In addition, voltage measurement can be performed in a state before the wiring between the two test pads is cut. When one test pad becomes impossible to measure by having two test pads, the other It can be measured with a test pad and can improve resistance to repeated tests.

  In the present embodiment, since a test pad for current measurement can be provided near another circuit block or standard cell, current measurement can be performed immediately after the signal is generated. In addition, since the routing wiring is shortened, the influence of signal attenuation caused by the long routing can be reduced. Further, since the possibility of noise is reduced, the circuit operation can be made more stable. It is possible to suppress an increase in parasitic capacitance and an increase in current consumption caused by a long lead wiring.

Also, there is no need for current measurement, and the work for deleting the test pad is easy. Specifically, by deleting two test pads in the standard cell, the standard cell of the present invention becomes a feed cell having a function of transmitting a signal. Since the test pad can be deleted only by changing one mask, the cost for deleting the test pad can be reduced.

(Embodiment 2)
In the present embodiment, a standard cell having a configuration different from that of the first embodiment will be described. The standard cell shown in this embodiment has a configuration in which two test pads are insulated when an overcurrent flows.

  FIG. 2 shows a schematic diagram of the standard cell of the present embodiment. The standard cell 208 in FIG. 2 includes a VDD power line 201, a GND power line 202, test pads 203 to 204, and wirings 205 to 207. Note that the VDD power line 201, the GND power line 202, the test pads 203 to 204, and the wirings 205 to 207 are formed of a conductive material. Further, the test pad 203 and the test pad 204 are electrically connected by a wiring 205. Further, the wiring 206 is connected to the test pad 203, and the wiring 207 is connected to the test pad 204. Here, the wiring 206 functions as an input port, and the wiring 207 functions as an output port. Signals can be exchanged with other standard cells and circuit blocks via the input port and the output port. In this embodiment, since the wirings 205 to 207 and the test pads 203 and 204 are provided on the same straight line, the width of the standard cell for the test pad can be reduced. By reducing the width of the standard cell, the circuit area can be reduced and the power consumption can be reduced.

  In this embodiment mode, the test pad 203 and the test pad 204 are insulated when a current (overcurrent) larger than the reference flows through the wiring 205. Therefore, the test pad of this embodiment has a configuration in which the width of the wiring 205 connecting the two test pads is not uniform and the resistance is partially different.

  A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) using the standard cell 208 as a circuit unit. Can be obtained.

  Next, a method of measuring a current at a specific terminal using the test pads 203 and 204 after configuring a desired circuit by automatic layout will be described. In the standard cell, when the test pads 203 and 204 are connected by the wiring 205, the current flowing from the input port 206 flows to the output port 207 through the test pad 203, the wiring 205, and the test pad 204. The other standard cells are supplied from the output port. Here, the voltage of an arbitrary terminal may be measured using the test pad 203 or the test pad 204 as a test pad for voltage measurement, and the terminal whose current is to be measured may be specified.

  Here, in order to simplify the description, the wiring 205 will be described by being divided into wiring areas 209, 210, and 211. Here, the wiring region 211 is formed to have a smaller width and length than the wiring regions 209 and 210. That is, the wiring regions 209 and 210 are formed wider than 211. Thereby, the wiring resistance of the wiring regions 209 and 210 can be made smaller than the wiring resistance of the wiring region 211. Since the resistance of the wiring region 211 is higher than that of the other regions, and when a large current flows through the wiring portion 211, 211 is insulated.

  Note that in this embodiment mode, a current value required for cutting the wiring 211 varies depending on the material and size of the wiring 211. This is because the amount of heat necessary to melt the wiring is proportional to the mass of the wiring, so that if the mass of the area of the wiring portion 211 is large, the amount of heat necessary to melt the wiring 211 also increases. In other words, the wiring 211 is not melted unless a larger current is applied as the mass of the wiring 211 increases, and the two test pads 203 and 204 are not insulated. In this embodiment, by utilizing this property, the size of the wiring 211, the maximum value of the current flowing through the wiring 211, the time during which the current flows, and the like can be arbitrarily set.

Here, with reference to FIG. 2B, a method of insulating between the test pad 203 and the test pad 204 of the standard cell shown in FIG. FIG. 2B is an inclined view of the portion of the wiring 205 in FIG. Here, the case where aluminum is used for the wiring 205 will be described. Aluminum has a melting point of about 600 ° C., a density of 2.9 g / cm ³ , and a specific heat of 0.88 J / g · K. In this embodiment, a process until the wiring 211 is disconnected when aluminum having a thickness d of 700 nm, a length l of 2 μm, and a width v of 2 μm is used in the wiring region 211 will be described. Here, a case where a current of 100 μA and a voltage of 5 V are supplied to the wiring 211 is considered. This value is appropriately selected from current values required for the circuit using simulation or the like.

Joule heat generated by the current flowing through the wiring portion 211 is expressed as 500 × 10 ⁻⁶ × t (J). Here, t is a time (unit: second) for supplying current. On the other hand, in order to melt the aluminum in the region of FIG. 2, Joule heat is required to raise the temperature of the aluminum to near 600 ° C., which is the melting point of aluminum, and the Joule heat is 4.287 × 10 ⁻⁹ ( J). From the above, the temperature of the wiring 211 becomes 600 ° C. or more by flowing a current of 100 μA for 10 μs. Accordingly, when a current of 100 μA is supplied for 10 μs or more, the aluminum in the wiring region 211 is melted, the wiring in the wiring region 211 is cut off, and the wiring region 209 and the wiring region 210 are insulated.

  Note that here, the size of the wiring 211 and the maximum value of the current and voltage supplied to the wiring 211 are set in advance, and the time required until the wiring 211 is cut is obtained. However, the method is limited to this method. It is not a thing. For example, the maximum value of the current and voltage supplied to the wiring 211 and the time required for cutting are set, and the size (mass, thickness, width, length, etc.) of the wiring 211 is set based on the setting. It is good also as a method.

  In this embodiment mode, the wiring through which the overcurrent flows can be cut only by operating the circuit, so that a defective portion in the circuit can be easily detected. At the time of measurement, it is not necessary to perform measurement for each test pad to identify a defective portion, so that the time required for inspecting the circuit can be greatly shortened. Further, since it is not necessary to cut the wiring connecting the two test pads using a mask change or special means, it is possible to easily detect a defective portion in the circuit.

  Further, in this embodiment, since it is not necessary to provide test pads in a narrow and densely lined area such as a wiring area outside the standard cell arrangement area, layout correction for providing the test pad is performed on a large scale. Therefore, it is possible to prevent layout mistakes during layout correction. Furthermore, the time spent for layout correction can be reduced. Furthermore, since the standard cell including the test pad can be arranged in the same region as other standard cells, it is possible to increase the arrangement area of the test pad. Therefore, the operation of applying the current measuring instrument needle becomes easier. Further, since the wiring other than the signal line to be measured is located far from the test pad, the possibility of damaging the other wiring when the operation of applying the needle of the current measuring device fails can be reduced.

  Further, in the present embodiment, after standard cells having two test pads are arranged in an automatic layout, the wiring connecting the two test pads is cut to isolate the test pads. Therefore, the current measurement terminals can be easily changed for each chip. By using the standard cell of this embodiment mode, it is not necessary to change the mask even when the terminal for current measurement is changed for each chip, so that a low-cost semiconductor device can be manufactured. In addition, voltage measurement can be performed in a state before the wiring between the two test pads is cut. When one test pad becomes impossible to measure by having two test pads, the other It can be measured with a test pad and can improve resistance to repeated tests.

  In the present embodiment, since a test pad for current measurement can be provided near another circuit block or standard cell, current measurement can be performed immediately after the signal is generated. In addition, since the routing wiring is shortened, the influence of signal attenuation caused by the long routing can be reduced. Further, since the possibility of noise is reduced, the circuit operation can be made more stable. It is possible to suppress an increase in parasitic capacitance and an increase in current consumption caused by a long lead wiring.

Also, there is no need for current measurement, and the work for deleting the test pad is easy. Specifically, by deleting two test pads in the standard cell, the standard cell of the present invention becomes a feed cell having a function of transmitting a signal. Since the test pad can be deleted only by changing one mask, the cost for deleting the test pad can be reduced.

(Embodiment 3)
In this embodiment mode, a case where a memory element is used as a wiring connecting two test pads will be described.

  FIG. 3 shows a circuit diagram of a standard cell including a memory element. A standard cell 308 shown in FIG. 3 includes a VDD power line 301, a GND power line 302, test pads 303 and 304, a memory element 305, a current input port 306 and a current output port 307.

  A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) using the standard cell 308 as a circuit unit. Can be obtained.

In this embodiment, as the memory element 305, a memory whose state changes due to heat generated by current and whose resistance changes is used. An example of such a memory is a phase change memory. In the phase change memory, when a large amount of current flows in the circuit, the heater included in the memory element generates heat, and when the amount of current is large, the amount of heat generation increases, and the substance that changes phase (Ge ₂ Sb ₂ Te ₅ ) is in an amorphous state, and the electrical resistance is increased and insulated. In the present embodiment, by utilizing this change, current measurement can be performed with the two test pads 303 and 304 insulated. Of course, the memory 305 is not limited to the phase change memory. Any device may be used as long as it can insulate only the element where a large amount of current flows and can insulate between the two test pads 303 and 304. For example, an RRAM whose resistance varies depending on the amount of current flowing can be used as the memory.

  The circuit operation of FIG. 3 will be described. The memory element 305 is conductive in the initial state. Therefore, it can be used as a normal circuit. When a large current flows through this circuit, the memory element 305 becomes non-conductive. At that time, a current measuring instrument can be applied to the two test pads 303 and 304 included in the standard cell to measure the current.

  In this embodiment mode, the wiring through which the overcurrent flows can be cut only by operating the circuit, so that a defective portion in the circuit can be easily detected. At the time of measurement, it is not necessary to perform measurement for each test pad to identify a defective portion, so that the time required for inspecting the circuit can be greatly shortened. Furthermore, since it is not necessary to cut the wiring connecting the two test pads using a mask change or special means, it is possible to easily detect a defective portion in the circuit. In addition, since a memory using a reversible reaction is used, it is possible to return a wiring that has been once insulated to its original state.

  Further, in this embodiment, since it is not necessary to provide test pads in a narrow and densely lined area such as a wiring area outside the standard cell arrangement area, layout correction for providing the test pad is performed on a large scale. Therefore, it is possible to prevent layout mistakes during layout correction. Furthermore, the time spent for layout correction can be reduced. Furthermore, since the standard cell including the test pad can be arranged in the same region as other standard cells, it is possible to increase the arrangement area of the test pad. Therefore, the operation of applying the current measuring instrument needle becomes easier. Further, since the wiring other than the signal line to be measured is located far from the test pad, the possibility of damaging the other wiring when the operation of applying the needle of the current measuring device fails can be reduced.

  Further, in the present embodiment, after standard cells having two test pads are arranged in an automatic layout, the wiring connecting the two test pads is cut to isolate the test pads. Therefore, the current measurement terminals can be easily changed for each chip. By using the standard cell of this embodiment mode, it is not necessary to change the mask even when the terminal for current measurement is changed for each chip, so that a low-cost semiconductor device can be manufactured. In addition, voltage measurement can be performed in a state before the wiring between the two test pads is cut. When one test pad becomes impossible to measure by having two test pads, the other It can be measured with a test pad and can improve resistance to repeated tests.

  In the present embodiment, since a test pad for current measurement can be provided near another circuit block or standard cell, current measurement can be performed immediately after the signal is generated. In addition, since the routing wiring is shortened, the influence of signal attenuation caused by the long routing can be reduced. Further, since the possibility of noise is reduced, the circuit operation can be made more stable. It is possible to suppress an increase in parasitic capacitance and an increase in current consumption caused by a long lead wiring.

Also, there is no need for current measurement, and the work for deleting the test pad is easy. Specifically, by deleting two test pads in the standard cell, the standard cell of the present invention becomes a feed cell having a function of transmitting a signal. Since the test pad can be deleted only by changing one mask, the cost for deleting the test pad can be reduced.

(Embodiment 4)
In the present embodiment, a configuration in which two test pads are connected via an analog switch will be described.

  FIG. 4 shows a circuit diagram of a standard cell including an analog switch. The standard cell 408 includes a VDD power line 401, a GND power line 402, a test pad 403, a test pad 404, an analog switch 409, an inverter 410, a current control signal input port 405, a current input port 406, and a current output port 407. Have

  A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) using the standard cell 408 as a circuit unit. Can be obtained.

  The circuit shown in FIG. 4 can change the connection state between the test pad 403 and the test pad 404 by the analog switch 409, that is, the conductive state and the non-conductive state. For example, when a Low signal is input to the current control signal input port 405, the analog switch 409 becomes conductive and can be used as a normal circuit. Here, when a Hi signal is input to the current control signal input port 405, the analog switch 409 is in a non-conducting state and current can be measured.

  A circuit having a desired function is obtained by arranging the standard cell 408 as a unit of the circuit in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.). be able to.

  In the present embodiment, conduction or non-conduction between two test pads can be switched by a simple method of changing a voltage signal. In this embodiment, since conduction or non-conduction between test pads is switched using a switch, conduction or non-conduction can be repeated. Samples can be used repeatedly when there are few samples for testing.

  Further, in this embodiment, since it is not necessary to provide test pads in a narrow and densely lined area such as a wiring area outside the standard cell arrangement area, layout correction for providing the test pad is performed on a large scale. Therefore, it is possible to prevent layout mistakes during layout correction. Furthermore, the time spent for layout correction can be reduced. Furthermore, since the standard cell including the test pad can be arranged in the same region as other standard cells, it is possible to increase the arrangement area of the test pad. Therefore, the operation of applying the current measuring instrument needle becomes easier. Further, since the wiring other than the signal line to be measured is located far from the test pad, the possibility of damaging the other wiring when the operation of applying the needle of the current measuring device fails can be reduced.

  Further, in the present embodiment, after standard cells having two test pads are arranged in an automatic layout, the wiring connecting the two test pads is cut to isolate the test pads. Therefore, the current measurement terminals can be easily changed for each chip. By using the standard cell of this embodiment mode, it is not necessary to change the mask even when the terminal for current measurement is changed for each chip, so that a low-cost semiconductor device can be manufactured. In addition, voltage measurement can be performed in a state before the wiring between the two test pads is cut. When one test pad becomes impossible to measure by having two test pads, the other It can be measured with a test pad and can improve resistance to repeated tests.

  In the present embodiment, since a test pad for current measurement can be provided near another circuit block or standard cell, current measurement can be performed immediately after the signal is generated. In addition, since the routing wiring is shortened, the influence of signal attenuation caused by the long routing can be reduced. Further, since the possibility of noise is reduced, the circuit operation can be made more stable. It is possible to suppress an increase in parasitic capacitance and an increase in current consumption caused by a long lead wiring.

Also, there is no need for current measurement, and the work for deleting the test pad is easy. Specifically, by deleting two test pads in the standard cell, the standard cell of the present invention becomes a feed cell having a function of transmitting a signal. Since the test pad can be deleted only by changing one mask, the cost for deleting the test pad can be reduced.

(Embodiment 5)
In this embodiment mode, a method for arranging test pads and wirings different from the above embodiment mode will be described. FIG. 5 shows the configuration of the standard cell of this embodiment.

  A standard cell 508 in FIG. 5 includes a VDD power line 501, a GND power line 502, a test pad 503, a test pad 504, and wirings 505 to 507. In this embodiment, the wirings 506 and 507, the VDD power line 501 and the GND power line 502 are arranged in parallel, and the wiring 505, the VDD power line 501 and the GND power line 502 are arranged vertically. . Note that the VDD power supply line 501, the GND power supply line 502, the test pads 503 to 504, and the wirings 505 to 507 are formed of a conductive material. The test pad 503 and the test pad 504 are electrically connected by a wiring 505. Further, the wiring 506 is connected to the test pad 503, and the wiring 507 is connected to the test pad 504. Here, the wiring 506 functions as an input port, and the wiring 507 functions as an output port. Signals can be exchanged with other standard cells and circuit blocks via the input port and the output port.

  A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) using the standard cell 508 as a circuit unit. Can be obtained.

  In this embodiment mode, the wirings 506 and 507, the VDD power supply line 501 and the GND power supply line 502 are arranged in parallel, so that the input signal and the output signal are routed in and out from the same direction. The wiring required for the wiring can be made shorter. For example, when a standard cell having a test pad is arranged in the outer peripheral region of the circuit, the lead wiring can be made shorter.

  In addition, the wirings 506 and 507 are not necessarily arranged in parallel with the VDD power supply line 501 and the GND power supply line 502, and a standard cell having a test pad is arranged at a location where the wiring is dense. The arrangement may be such that each signal line is connected to avoid a region where the wiring is dense. For example, the arrangement shown in FIG. 6 can be taken.

  A standard cell 608 shown in FIG. 6 includes a VDD power line 601, a GND power line 602, a test pad 603, a test pad 604, and wirings 605 to 607. In this embodiment, the wirings 606 and 607, the VDD power line 601 and the GND power line 602 are arranged vertically, and the wiring 605, the VDD power line 601 and the GND power line 602 are arranged in parallel. . Further, the wiring 606 and the VDD power line 601 cross each other, and the wiring 607 and the GND power line 602 cross each other. Note that the VDD power line 601, the GND power line 602, the test pads 603 to 604, and the wirings 605 to 607 are formed of a conductive material. Further, the test pad 603 and the test pad 604 are electrically connected by a wiring 605. Further, the wiring 606 is connected to the test pad 603, and the wiring 607 is connected to the test pad 604. Here, the wiring 606 functions as an input port, and the wiring 607 functions as an output port. Signals can be exchanged with other standard cells and circuit blocks via the input port and the output port.

  A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) using the standard cell 608 as a circuit unit. Can be obtained.

  In the standard cell shown in FIG. 6, since the wiring 606 and the VDD power line 601 cross each other and the wiring 607 and the GND power line 602 cross each other, the test pad 603 is enlarged in the direction of the GND power line 602. The test pad 604 can be enlarged in the direction of the VDD power supply line 603. Thereby, the work of searching for a pad at the time of measurement and the work of addressing a needle can be performed more easily. Further, in the standard cell shown in FIG. 6, since the test pads 603 and 604 are arranged in parallel with the VDD power supply line 601 and the GND power supply line 602, the test pads 603 and 604 are tested at positions away from the VDD power supply line 601 and the GND power supply line 602. Pads 603 and 604 can be arranged. Therefore, when measuring the current, it is difficult to be affected by the voltage and current supplied to the VDD power line 601 or the GND power line 602 included in the standard cell 608, and the current value can be measured more accurately.

  Note that the positions of the input port 606 and the output port 607 are not limited to those shown in FIG. 6 and may be arranged so that each wiring is most appropriately performed depending on the arrangement of the standard cell including the test pad. Good.

(Embodiment 6)
In this embodiment mode, a method for arranging test pads and wirings different from the above embodiment mode will be described. FIG. 7 shows the configuration of the standard cell of this embodiment.

  A standard cell 708 shown in FIG. 7 includes a VDD power line 701, a GND power line 702, a plurality of test pads 703 and 704, and a plurality of wirings 705 to 707. In FIG. 7, one test pad 703 and one test pad 704 are electrically connected by one wiring 705. One wiring 706 is connected to one test pad 703, and one wiring 707 is connected to one test pad 704. The test pads 703 and 704 connected by the wiring 705 constitute a set of current measurement TEG 709. Here, the wiring 706 functions as an input port, and the wiring 707 functions as an output port. Signals can be exchanged with other standard cells and circuit blocks via the input port and the output port. Note that in this embodiment, the wirings 705 to 707 are arranged on the same straight line, but are not limited to this configuration. Further, the VDD power line 701, the GND power line 702, the test pads 703 to 704, and the wirings 705 to 707 are formed of a conductive material.

  A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) using the standard cell 708 as a circuit unit. Can be obtained.

  In the standard cell shown in FIG. 7, since various signal lines can be combined into one standard cell, management of the signal lines at the time of layout becomes easy. Moreover, the trouble of searching for a pad during current measurement can be saved. Furthermore, since the distance of the test pad between different signals is not greatly separated, the movement of the stylus of the ampere meter is facilitated. In addition, by adjusting the size between the test pads, it is possible to measure a plurality of currents in a lump, and circuit verification can be promoted more efficiently.

  Another configuration may be the configuration shown in FIG. A standard cell 808 in FIG. 8 includes a VDD power line 801, a GND power line 802, a plurality of test pads 803 and 804, and a plurality of wirings 805 to 807. In FIG. 8, one test pad 803 and one test pad 804 are electrically connected by one wiring 805. One wiring 806 is connected to one test pad 803, and one wiring 807 is connected to one test pad 804. A set of current measurement TEGs 809 is constituted by the test pads 803 and 804 connected by the wiring 805. Here, the wiring 806 functions as an input port, and the wiring 807 functions as an output port. Signals can be exchanged with other standard cells and circuit blocks via the input port and the output port. Note that although the wirings 805 to 807 are arranged on the same straight line in this embodiment mode, the present invention is not limited to this structure. Further, the VDD power line 801, the GND power line 802, the test pads 803 to 804, and the wirings 805 to 807 are formed of a conductive material. In FIG. 8, it is possible to reduce an empty area in the standard cell 808 where no wiring or test pad is arranged.

  A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) using the standard cell 808 as a circuit unit. Can be obtained.

  By using the standard cell shown in FIG. 8, the area of the standard cell cell including the test pad (and the horizontal width of the standard cell) can be reduced. When it is necessary to arrange a large number of test pads in a dense wiring area, the circuit area can be reduced by using the standard cell shown in FIG. Thereby, an increase in parasitic capacitance due to the test pad can be suppressed. Furthermore, the wiring load can be reduced.

  Moreover, it is good also as a structure shown in FIG. 9 as another form. A standard cell 908 shown in FIG. 9 includes a VDD power line 901, a GND power line 902, a plurality of test pads 903 and 904, and a plurality of wirings 905 to 907. In FIG. 9, one test pad 903 and one test pad 904 are electrically connected by one wiring 905. One wiring 906 is connected to one test pad 903, and one wiring 907 is connected to one test pad 904. The test pads 903 and 904 connected by the wiring 905 constitute a set of current measurement TEG 909. Here, the wiring 906 functions as an input port, and the wiring 907 functions as an output port. Signals can be exchanged with other standard cells and circuit blocks via the input port and the output port. Further, the VDD power line 901, the GND power line 902, the test pads 903 to 904, and the wirings 905 to 907 are formed of a conductive material. Note that in this embodiment mode, the wirings 905 to 807 are arranged on the same straight line and arranged in parallel with the VDD power supply line 901 and the GND power supply line 902; however, the present invention is not limited to this structure.

  A semiconductor integrated circuit having a desired function by being arranged in an automatic layout together with other standard cells (for example, an inverter circuit, a NAND circuit, a NOR circuit, a flip-flop circuit, etc.) using the standard cell 908 as a circuit unit. Can be obtained.

  In the standard cell 908 shown in FIG. 9, the wirings 905 to 907, the VDD power supply line 901, and the GND power supply line 902 are arranged in parallel. As a result, the distance between the two test pads 903 and 904 connected by the wiring 905 and the length of the wiring in the standard cell can be reduced. Further, the wirings 906 and 907 functioning as input ports or output ports and the VDD power supply line 901 or the GND power supply line 902 do not cross within the standard cell 908. As a result, it is possible to reduce the influence of power supply noise during current measurement. Furthermore, it is possible to arrange test pads even in a region where wiring between standard cell columns is dense.

(Embodiment 7)
The semiconductor circuit manufactured using the test pad described in any of Embodiments 1 to 6 includes, for example, an RFID chip (RFID tag, IC tag, IC chip, RF) which is a semiconductor device capable of inputting and outputting data without contact. (Radio Frequency) tags, wireless tags, and electronic tags). When designing the analog circuit part, digital circuit part, etc. in the RFID chip, the standard cell including the test pad of the present invention is used to measure the current in detail, cut unnecessary power, and reduce power consumption. It becomes possible to reduce. As a circuit portion constituting the RFID chip, an integrated circuit portion (having a high frequency circuit, a power supply circuit, a reset circuit, a clock generation circuit, a data demodulation circuit, a data modulation circuit, a control circuit, a memory circuit, etc.), a power supply circuit portion (rectifier circuit) Analog circuit section (including antenna, high frequency circuit, power supply circuit, reset circuit, clock generation circuit, level shift circuit, charge pump circuit, data demodulation circuit, data modulation circuit, etc.) And a digital circuit unit (including a control circuit and a memory control circuit).

  A semiconductor device 800 illustrated in FIG. 10 has a function of communicating data without contact, and includes a high-frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and the like. A control circuit 870 which controls the circuit, a memory circuit 880, and an antenna 890 are included (FIG. 10A). The high-frequency circuit 810 is a circuit that receives a signal from the antenna 890 and outputs the signal received from the data modulation circuit 860 from the antenna 890, and the power supply circuit 820 is a circuit that generates a power supply potential from the received signal, and a reset circuit 830. Is a circuit that generates a reset signal, the clock generation circuit 840 is a circuit that generates various clock signals based on the reception signal input from the antenna 890, and the data demodulation circuit 850 demodulates the reception signal to control the circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870. As the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instruction sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

  Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 890. The wireless signal is sent to the power supply circuit 820 via the high frequency circuit 810, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter, demodulated signal). Further, a signal and a demodulated signal that have passed through the reset circuit 830 and the clock generation circuit 840 via the high frequency circuit 810 are sent to the control circuit 870. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, information on the semiconductor device stored in the memory circuit 880 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940. Further, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890. Note that a low power supply potential (hereinafter referred to as VSS) is common in the plurality of circuits included in the semiconductor device 800, and VSS can be GND. Further, the nonvolatile semiconductor memory device of the present invention can be applied to the memory circuit 880. In the nonvolatile semiconductor memory device of the present invention, since the driving voltage can be lowered, it is possible to extend the distance in which data can be communicated without contact.

  As described above, by transmitting a signal from the reader / writer to the semiconductor device 800 and receiving the signal transmitted from the semiconductor device 800 by the reader / writer, the data of the semiconductor device can be read.

  Further, the semiconductor device 800 may be of a type in which the power supply voltage is supplied to each circuit by an electromagnetic wave without mounting the power source (battery), or each circuit is mounted by the electromagnetic wave and the power source (battery). It is good also as a type which supplies a power supply voltage to.

  Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A reader / writer 3200 is provided on the side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on the side surface of the article 3220 (FIG. 10B). When the reader / writer 3200 is held over the semiconductor device 3230 included in the product 3220, information about the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process and the history of the distribution process, is displayed on the display unit 3210. Is done. Further, when the product 3260 is conveyed by the belt conveyor, the product 3260 can be inspected using the reader / writer 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 10C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

The figure which shows the structure of the standard cell of this invention. The figure which shows the structure of the standard cell of this invention. The figure which shows the structure of the standard cell of this invention. The figure which shows the structure of the standard cell of this invention. The figure which shows the structure of the standard cell of this invention. The figure which shows the structure of the standard cell of this invention. The figure which shows the structure of the standard cell of this invention. The figure which shows the structure of the standard cell of this invention. The figure which shows the structure of the standard cell of this invention. FIG. 10 illustrates an example of a usage pattern of a semiconductor device.

Claims (6)

First and second circuits;
First and second test pads;
A first wiring that electrically connects the first circuit and the first test pad;
A second wiring that electrically connects the second circuit and the second test pad;
The first test pad and the second test pad are electrically connected via a third wiring having a narrow part and a thick part,
A current supplied from the first wiring flows in order through the first test pad, the third wiring, the second test pad, and the second wiring, and is supplied to the second circuit. After forming the integrated circuit,
When the semiconductor integrated circuit is operated and an overcurrent flows from the first wiring to the third wiring through the first test pad, the third wiring is electrically connected by the overcurrent. A method for inspecting a semiconductor integrated circuit, comprising cutting the semiconductor integrated circuit. First and second circuits;
First and second test pads;
A first wiring that electrically connects the first circuit and the first test pad;
A second wiring that electrically connects the second circuit and the second test pad;
The first test pad and the second test pad are electrically connected via a phase change memory;
The current from the first wiring flows through the first test pad, the phase change memory, the second test pad, and the second wiring in this order, and is supplied to the second circuit. After forming the circuit,
When the semiconductor integrated circuit is operated and a current of a certain level flows from the first wiring to the phase change memory via the first test pad, the phase change memory is insulated by the current of the certain level or more. ,
The first needle of the current measuring device is brought into contact with the first test pad, and the second needle of the current measuring device is brought into contact with the second test pad, so that the first circuit and the second A method for inspecting a semiconductor integrated circuit, wherein a current flowing between the circuit and the circuit is measured by the current measuring device. In claim 1 or claim 2 ,
A first power supply wiring and a second power supply wiring;
The first power supply wiring and the second power supply wiring extend in a first direction,
A straight line connecting the first wiring, the first test pad, the second test pad, and the second wiring extends in a second direction intersecting with the first direction. Circuit inspection method. In claim 1 or claim 2 ,
A first power supply wiring and a second power supply wiring;
The first power supply wiring and the second power supply wiring extend in a first direction,
The first wiring and the second wiring extend in the first direction,
A method of testing a semiconductor integrated circuit, wherein a straight line connecting the first test pad and the second test pad extends in a second direction intersecting with the first direction. In claim 1 or claim 2 ,
A first power supply wiring and a second power supply wiring;
The first power supply wiring and the second power supply wiring extend in a first direction,
The first wiring and the second wiring extend in a second direction intersecting with the first direction,
A method of testing a semiconductor integrated circuit, wherein a straight line connecting the first test pad and the second test pad extends in the first direction. In any one of Claims 1 thru | or 5 ,
An inspection method for a semiconductor integrated circuit, wherein the semiconductor integrated circuit is designed by arranging a plurality of standard cells by an automatic layout method.

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