WO2007008044A1

WO2007008044A1 - Series sampling capacitor and analog-to-digital converter using the same

Info

Publication number: WO2007008044A1
Application number: PCT/KR2006/002767
Authority: WO
Inventors: Seonghwan Cho; Sungmin Ock; Sang Hoon Lee; Joonsuk Lee
Original assignee: Fci Inc
Priority date: 2005-07-14
Filing date: 2006-07-14
Publication date: 2007-01-18
Also published as: KR20070009750A

Abstract

Provided are a structure of a series sampling capacitor, which reduces impedance of a series sampling capacitor and prevents erroneous operations of an analog-to-digital converter, and an analog-to-digital converter using the same. The structure includes: two capacitors connected in series; and a transistor which functions as a switch and is connected between a center node of the two capacitors connected in series and a common mode voltage, wherein a reset clock operates immediately before the two capacitors connected in series initially perform sampling, so that voltage at the center node can be reset based on the common mode voltage. Accordingly, erroneous operations of an analog-to-digital converter can be prevented by lowering impedance of a series sampling capacitor.

Description

SERIES SAMPLING CAPACITOR AND ANALOG-TO-DIGITAL

CONVERTER USING THE SAME

Technical Field

[1] The present invention relates to an analog-to-digital converter, and more particularly, to a structure of a sampling capacitor of an analog-to-digital converter, and an analog-to-digital converter using the same. Background Art

[2] An analog-to-digital converter (hereinafter referred to as ADC) converts an input analog signal into a digital signal, and transmits the converted signal. The ADC is an essential element for various data communication and signal processing systems.

[3] Specifications of the ADC vary depending on systems employing the ADC. With the recent development of wireless communication and portable equipment, a key issue lies in not only satisfying a system signal quality but also minimizing power cons umption.

[4] In general, op-amps associated with various sampling processes consume the maximum power among elements included in the ADC. For example, the op-amps may be included in an MDAC (multiplying digital-to-analog converter) in the case of using a pipelined ADC that is appropriate to realize a high sampling rate.

[5] In order to reduce power consumption of a circuit such as the MDAC, in the conventional method, instead of reducing power consumed in an op-amp itself, the number of op-amps used in the ADC has been reduced to lower power consumption, for example, required op-amps have been shared in response to clock signals, or the number of needed stages and resolution for each of the stages have been optimized.

[6] Power consumption of each of the op-amps depends on performance of the MDAC employing the op-amps. A sampling capacitor is one of decisive factors in realizing the performance.

[7] In the ADC, capacitance of the sampling capacitor depends on capacitor mismatch, kT/C noise, charge leakage, and linearity, etc. In particular, the capacitance thereof is mainly affected by the mismatch and the kT/C noise.

[8] When an ADC that requires a resolution as high as about 10 bits is realized in a standard digital CMOS process, in order to prevent poor performance caused by the mismatch, a capacitor needs to be larger than a specific size, resulting in power consumption of the op-amps. In particular, in many cases, a required capacitance is greater than a capacitance required for the kT/C noise.

[9] For example, in a typical process, the capacitor mismatch can be expressed as a function of area: s = a/W(W: area of capacitor, a: constant value depending on process) [10] If the ADC is a 10-bit pipeline ADC in which each stage is composed of 1.5 bits, capacitor mismatch 3s of the first stage has to be less than 2 to 10. [11] In this case, if a capacitor has a size of 60Dx60D and a density opF/Sin a process in which a α

2%D is satisfied, then its capacitance becomes 3.6pF, which is significantly greater than a capacitance of IpF required for the kT/C noise.

[12] Therefore, if power consumption of the op-amp increases in proportion to capacitance, power consumption increases by equal to or greater than 70% due to the capacitor mismatch.

[13] One of the most commonly used layout method for reducing the capacitor mismatch is a common centroid method in which capacitors are divided into unit capacitors and are disposed in a cross manner.

[14] FIG. 1 illustrates towcapacitors realized by using a typical common centroid method. By constituting a capacitor group with unit capacitors Cl and C4, and constituting another capacitor group with unit capacitors C2 and C3, mismatch between any of two unit capacitors that occurs due to first order gradient of a process is minimized. In general, the capacitor Cl and the capacitor C4, and the capacitor C2 and the capacitor C3 are connected in parallel.

[15] FIG. 2 illustrates unit capacitorsCl and C4 (or, C2 and C3) connected in parallel.

FIG. 3 illustrates unit capacitors Cl and C4, (or, C2 and C3) connected in series.

[16] Comparing FIG. 2 with FIG. 3, since the same unit capacitors are used in layout, the same effect will be caused by mismatch. Further, capacitances of series capacitors CsA and CsB are the quarter of capacitances of parallel capacitors CpA and CpB.

[17] The above result is derived from different connection manners, in which the same unit capacitors are respectively connected in parallel and in series, and this will be intuitively understood by those skilled in the art. However, the following mathematical model will also prove the above result.

[18] Capacitance of each of the unit capacitors Cl to C4 can be expressed as C =C(l+e

). Here, e is a random error that follows the standard normal distribution of e ~N(0, σ

), where average is 0, and standard deviation is s. Capacitance mismatch between the parallel capacitors CpA and CpB and capacitance mismatch between the series capacitors CsA and CsB can be respectively expressed as the following Formulas 1 and 2.

[19] [Formula 1] C ^ pA - C ^ pB C(2- ι)-C(2- e Λ - e -,- e

^ pA C(2+ _{e i}+ e₄) = e i

2+ ^₁ +

[21] [Formula 2]

[22]

[23] Here, e s and e p equally follow a distribution of N(O, σ

), and thus the two capacitors show the same matching characteristic, with one capacitance being the quadruple of the other capacitance.

[24] The following description explains difference occurring in a substantial circuit between the case of constituting a sampling capacitor by connecting two unit capacitors in series as mentioned above, and the case of using only one capacitor.

[25] FIG. 4 illustrates an MDAC circuit having a gain of 7NIW, in which a sampling capacitor is constituted by connecting two unit capacitors in series.

[26] If a random error occurs in the aforementioned manner, a voltage transfer function of the MDAC can be expressed as the following Formula 3.

[27] [Formula 3]

[28]

[29] In order for an MDAC circuit having one sampling capacitor to have the same signal characteristic as the above MDAC circuit, the sampling capacitances of the two MDAC circuits have to be the same with each other. In this case, capacitance of any one of unit capacitors of a series sampling capacitor is twice as high as that of a typical sampling capacitor (C = C 12). i sA

[30] Therefore, the mismatch occurring in a series sampling capacitor is reduced by

2 times the typical case. If the same sampling capacitor is constituted by connecting n unit capacitors in series, the mismatch is reduced by n times thereof. When the series sampling capacitor is appropriately used in a circuit such as the MDAC, a sampling capacitance can be significantly lower than a ca- pacitance required for the capacitor mismatch (the sampling capacitance can be lower than that of required for the kT/C noise), thereby facilitating a lower power ADC design.

[31] There are some problems in realizing the series sampling capacitor in a substantial circuit. The most serious problem lies in that a center node where unit capacitors are connected from each another has high impedance when the unit capacitors are connected in series. Furthermore, in many cases, a backward diode is connected between both ends of a capacitor by applying an antenna rule in an actual process. Accordingly, when the MDAC operates, the center node of the unit capacitors may have voltage bootstrapped due to the high impedance, which may cause erroneous operations of the ADC (e.g. the backward diode turns on). Disclosure of Invention Technical Problem

[32] The present invention provides a structure of a series sampling capacitor, which reduces impedance of a series sampling capacitor and prevents erroneous operations of an analog-to-digital converter, and an analog-to-digital converter using the same. Technical Solution

[33] According to an aspect of the present invention, there is provided a structure of a series sampling capacitor used for designing an analog-to-digital converter, the structure comprising: two capacitors connected in series; and a transistor which functions as a switch and is connected between a center node of the two capacitors connected in series and a common mode voltage, wherein a reset clock operates immediately before the two capacitors connected in series initially perform sampling, so that voltage at the center node can be reset based on the common mode voltage.

[34] According to another aspect of the present invention, there is provided an analog- to-digital converter using a series sampling capacitor, the analog-to-digital converter comprising: a sample/hold circuit that samples an input analog signal based on a clock frequency, and holds the signal until the next clock pulse is applied; and a plurality of stages which include a transistor functioning as a switch and connected between a center node of two capacitors connected in series and a common mode voltage, and have a series sampling capacitor structure in which a reset clock operates immediately before the two capacitors connected in series initially perform sampling, so that voltage at the center node can be reset based on the common mode voltage; a flash ADC which is connected to a last stage of the plurality of stages and processes a few bits of signals to be processed finally; and a digital error correction circuit which corrects errors of the stages and the flash ADC. Brief Description of the Drawings [35] FlG. 1 illustrates twocapacitors realized by using a typical common centroid method;

[36] FlG. 2 illustrates unit capacitors connected in parallel;

[37] FlG. 3 illustrates unit capacitors connected in series;

[38] FlG. 4 illustrates an MDAC (multiplying digital-to-analog converter )circuit having a gain of 2V/V, in which a sampling capacitor is constituted by connecting two unit capacitors in series;

[39] FlG. 5 illustrates a series sampling capacitor according to an embodiment of the present invention;

[40] FlG. 6 illustrates a simulation result of voltage change at the center node of FlG. 4;

[41] FlG. 7 illustrates an ADC (analog-to-digital converter) using a series sampling capacitor according to an embodiment of the present invention; and

[42] FlG. 8 illustrates a FET (fast-Fourier transform) result of a digital signal output from an ADC. Best Mode for Carrying Out the Invention

[43] Hereinafter, the present will be described in detail with reference to accompanying drawings.

[44] FlG. 5 illustrates a series sampling capacitor according to an embodiment of the present invention.

[45] A transistor Ml functioning as a switch is connected between a center node X of two capacitors Cl and C2 connected in series and a common mode voltage. A reset clock operates immediately before a sampling capacitor constituted by the two serially- connected capacitors Cl and C2 initially performs sampling, so that voltage at the center node X can be reset based on the common mode voltage VCM.

[46] As shown in the right side of FlG. 5, the reset clock may slightly overlap with a sampling clock. The overall performance of the ADC is not adversely affected by the above clock structure. This is because a settling time of an input voltage of a sampling capacitor depends on a settling time of an op-amp.

[47] FlG. 6 illustrates a simulation result of voltage change at the center node of FlG. 5.

[48] Referring to FlG. 6, the center node reaches the common mode voltage in a short time.

[49] FlG. 7 illustrates an ADC using a series sampling capacitor according to an embodiment of the present invention. The ADC includes a sample/hold circuit 610, a plurality of stages 620, a flash ADC 630, and a digital error correction circuit 640.

[50] The ADC is a pipeline ADC (100MHz, lObit) designed by using a 0.18D CMOS process. The stages 620 include seven 1.5-bit stages 1 to 7. The flash ADC 630 is composed of 3 bits. [51] The sample/hold circuit 610 samples an input analog signal based on a clock frequency, and holds the signal until the next clock pulse is applied.

[52] In the stages 620, the number of stages and the number of bits to be processed by each of the stages 620 vary depending on specifications required by the pipeline ADC.

[53] Each of the stages 620 operates according to a clock transfer method called a pipeline method, and includes an MDAC composed of series sampling capacitors.

[54] The flash ADC 630 is appropriate to process a smaller number of bits in a rapid speed. When the pipeline ADC is used, a few bits of signals to be processed finally are subject to the process.

[55] The digital error correction circuit 640 aggregates digital signals respectively received from the stages 620 and the flash ADC 630, and corrects errors that may occur at each of the stages 620 when a digital signal is finally constituted.

[56] FIG. 8 illustrates a FET (fast-Fourier transform) result of a digital signal output from an ADC.

[57] The simulation result shows a good signal characteristic having a 9.5-bit ENOB

(effective number of bits), a 6OdB SNDR(signal to noise and distortion ratio), and a 67dB SFDR(spurious free dynamic range) at 100MHz. In addition, power consumption is only 26mA at 1.8V, which is less than other ADCs having the same specification.

[58] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Industrial Applicability

[59] According to the present invention, erroneous operations of an analog-to-digital converter can be prevented by lowering impedance of a series sampling capacitor.

Claims

[1] A structure of a series sampling capacitor used for designing an analog-to-digital converter, the structure comprising: two capacitors connected in series; and a transistor which functions as a switch and is connected between a center node of the two capacitors connected in series and a common mode voltage, wherein a reset clock operates immediately before the two capacitors connected in series initially perform sampling, so that voltage at the center node can be reset based on the common mode voltage.

[2] The structure of claim 1, wherein the reset clock overlaps with a sampling clock in a specific portion.

[3] An analog-to-digital converter using a series sampling capacitor, the analog- to-digital converter comprising: a sample/hold circuit that samples an input analog signal based on a clock frequency, and holds the signal until the next clock pulse is applied; and a plurality of stages which include a transistor functioning as a switch and connected between a center node of two capacitors connected in series and a common mode voltage, and have a series sampling capacitor structure in which a reset clock operates immediately before the two capacitors connected in series initially perform sampling, so that voltage at the center node can be reset based on the common mode voltage; a flash ADC which is connected to a last stage of the plurality of stages and processes a few bits of signals to be processed finally; and a digital error correction circuit which corrects errors of the stages and the flash ADC.