TWI751958B - Successive-approximation register adc - Google Patents

Successive-approximation register adc Download PDF

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TWI751958B
TWI751958B TW110122830A TW110122830A TWI751958B TW I751958 B TWI751958 B TW I751958B TW 110122830 A TW110122830 A TW 110122830A TW 110122830 A TW110122830 A TW 110122830A TW I751958 B TWI751958 B TW I751958B
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significant bit
terminal
electrically connected
positive
negative
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TW110122830A
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TW202301814A (en
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王朝欽
吳孟杰
邱逸仁
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國立中山大學
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Abstract

A SAR ADC includes a sample switch unit, a MSB capacitor array, a MSB compared switch, a unity-gain amplifier unit, a LSB capacitor array, a LSB compared switch, a comparator and a SAR control unit. The MSB capacitor array is electrically connected to the sample switch unit and the MSB compared switch. The unity-gain amplifier unit is electrically connected to the sample switch unit, the MSB capacitor array, and the LSB capacitor array. The LSB compared switch is electrically connected to the LSB capacitor array. The comparator is electrically connected to the MSB compared switch, the LSB compared switch and the SAR control unit.

Description

連續漸進式類比數位轉換器Continuous Progressive Analog-to-Digital Converter

本發明是關於一種類比數位轉換器，特別是關於一種連續漸進式類比數位轉換器。The present invention relates to an analog-to-digital converter, in particular to a continuous progressive analog-to-digital converter.

連續漸進式類比數位轉換器具有低功率消耗、良好的取樣率及解析度，而廣泛地應用於有著低功率消耗需求的系統中，但由於連續漸進式類比數位轉換器是由電容陣列組成，若欲提高解析度則必須增加電容的數量，導致其整體面積較大。因此，一種具分離式電容陣列之連續漸進式類比數位轉換器透過橋接電容將原有的電容陣列分割成粗調部分及細調部分，可大量地減少使用的電容數量，且使用較少的電容數量除了可減少佈局面積外，還能降低功率消耗及電容的設定時間。但這種架構會因為橋接電容的寄生電容及製程飄移產生非線性失真的影響，導致整個連續漸進式類比數位轉換器的性能下降。此外，一般橋接電容的電容值為非整數，因此，橋接電容的電容因數值與電容陣列中的電容不同亦導致電容製程上的困難。Continuous progressive analog digital converters have low power consumption, good sampling rate and resolution, and are widely used in systems with low power consumption requirements, but because continuous progressive analog digital converters are composed of capacitor arrays, if To improve the resolution, the number of capacitors must be increased, resulting in a larger overall area. Therefore, a continuous progressive analog digitizer with a separate capacitor array divides the original capacitor array into a coarse adjustment part and a fine adjustment part by bridging capacitors, which can greatly reduce the number of capacitors used and use less capacitors In addition to reducing layout area, the number reduces power consumption and capacitor setup time. However, this kind of architecture will cause the effect of nonlinear distortion due to the parasitic capacitance of the bridge capacitor and process drift, resulting in the degradation of the performance of the entire continuous progressive analog-to-digital converter. In addition, the capacitance value of the bridge capacitor is generally non-integer. Therefore, the capacitance factor value of the bridge capacitor is different from the capacitance in the capacitor array, which also causes difficulties in the capacitor manufacturing process.

本發明主要目的在於以單位增益放大器取代橋接電容，可避免連續漸進式類比數位轉換器因為橋接電容而產生非線性失真的問題。The main purpose of the present invention is to replace the bridge capacitor with a unity gain amplifier, which can avoid the problem of nonlinear distortion caused by the bridge capacitor in the continuous progressive analog-to-digital converter.

本發明之一種連續漸進式類比數位轉換器包含一取樣開關單元、一最高有效位元電容陣列、一最高有效位元比較開關、一單位增益放大器單元、一最低有效位元電容陣列、一最低有效位元比較開關、一比較器及一連續漸進式控制單元。該取樣開關單元之一端接收一類比訊號，該最高有效位元電容陣列之一端電性連接該取樣開關單元之另一端，該最高有效位元比較開關之一端電性連接該最高有效位元電容陣列之另一端，該單位增益放大器單元之一端電性連接該取樣開關單元之另一端及該最高有效位元電容陣列之一端，該最低有效位元電容陣列之一端電性連接該單位增益放大器單元之另一端，該最低有效位元比較開關之一端電性連接該最低有效位元電容陣列之另一端，該比較器電性連接該最高有效位元比較開關之另一端及該最低有效位元比較開關之另一端，且該比較器輸出一比較訊號，該連續漸進式控制單元電性連接該比較器以接收該比較訊號，且該連續漸進式控制單元根據該比較訊號輸出複數個控制訊號至該最高有效位元電容陣列、該最高有效位元比較開關、該最低有效位元電容陣列及該最低有效位元比較開關進行控制。A continuous progressive analog-to-digital converter of the present invention includes a sampling switch unit, a most significant bit capacitor array, a most significant bit comparison switch, a unity gain amplifier unit, a least significant bit capacitor array, a least significant bit capacitor array, and a least significant bit capacitor array. Bit comparison switch, a comparator and a continuous progressive control unit. One end of the sampling switch unit receives an analog signal, one end of the most significant bit capacitor array is electrically connected to the other end of the sampling switch unit, and one end of the most significant bit comparison switch is electrically connected to the most significant bit capacitor array At the other end, one end of the unit gain amplifier unit is electrically connected to the other end of the sampling switch unit and one end of the most significant bit capacitor array, and one end of the least significant bit capacitor array is electrically connected to the unit gain amplifier unit. At the other end, one end of the least significant bit comparison switch is electrically connected to the other end of the least significant bit capacitor array, and the comparator is electrically connected to the other end of the most significant bit comparison switch and the least significant bit comparison switch the other end, and the comparator outputs a comparison signal, the continuous progressive control unit is electrically connected to the comparator to receive the comparison signal, and the continuous progressive control unit outputs a plurality of control signals according to the comparison signal to the highest The effective bit capacitor array, the most significant bit comparison switch, the least significant bit capacitor array and the least significant bit comparison switch are controlled.

本發明藉由該單位增益放大器單元連接該最高有效位元電容陣列及該最低有效位元電容陣列，可以讓該最高有效位元電容陣列的電壓經由該單位增益放大器單元傳送至該最低有效位元電容陣列，使得該連續漸進式類比數位轉換器能夠以較小的電容數達成高解析度之類比數位轉換，且使用該單位增益放大器單元取代橋接電容能夠避免非線性失真的問題，而提高該連續漸進式類比數位轉換器的線性度。The present invention uses the unity gain amplifier unit to connect the most significant bit capacitor array and the least significant bit capacitor array, so that the voltage of the most significant bit capacitor array can be transmitted to the least significant bit through the unity gain amplifier unit The capacitor array enables the continuous progressive analog-to-digital converter to achieve high-resolution analog-to-digital conversion with a smaller number of capacitors, and the use of the unity-gain amplifier unit instead of bridge capacitors can avoid the problem of nonlinear distortion and improve the continuous Linearity of progressive analog-to-digital converters.

請參閱第1圖，其為本發明之一實施例，一種連續漸進式類比數位轉換器100的功能方塊圖，該連續漸進式類比數位轉換器100具有一取樣開關單元110、一最高有效位元電容陣列120、一最高有效位元比較開關130、一單位增益放大器單元140、一最低有效位元電容陣列150、一最低有效位元比較開關160、一比較器170及一連續漸進式控制單元180。Please refer to FIG. 1 , which is a functional block diagram of a continuous progressive analog-to-digital converter 100 according to an embodiment of the present invention. The continuous progressive analog-to-digital converter 100 has a sampling switch unit 110 and a most significant bit Capacitor array 120 , a most significant bit comparison switch 130 , a unity gain amplifier unit 140 , a least significant bit capacitor array 150 , a least significant bit comparison switch 160 , a comparator 170 and a continuous progressive control unit 180 .

該取樣開關單元110之一端接收一類比訊號V i，該取樣開關單元110之另一端電性連接該最高有效位元電容陣列120之一端，該最高有效位元電容陣列120之另一端電性連接該最高有效位元比較開關130之一端，該最高有效位元比較開關130之另一端電性連接該比較器170之一端。該單位增益放大器單元140之一端電性連接該最高有效位元電容陣列120之一端及該取樣開關單元110之另一端，該單位增益放大器單元140之另一端電性連接該最低有效位元電容陣列150之一端，該最低有效位元電容陣列150之另一端電性連接該最低有效位元比較開關160之一端，該最低有效位元比較開關160之另一端電性連接該比較器170之一端，該比較器170之另一端電性連接該連續漸進式控制單元180。其中，該比較器170輸出一比較訊號S c至該連續漸進式控制單元180，且該連續漸進式控制單元180根據該比較訊號S c輸出複數個控制訊號至該最高有效位元電容陣列120、該最高有效位元比較開關130、該最低有效位元電容陣列150及該最低有效位元比較開關160進行控制，以進行各個位元的切換及比較，且該連續漸進式控制單元180輸出一數位訊號D。 One end of the sampling switch unit 110 receives an analog signal V i , the other end of the sampling switch unit 110 is electrically connected to one end of the most significant bit capacitor array 120 , and the other end of the most significant bit capacitor array 120 is electrically connected One end of the MSB comparison switch 130 and the other end of the MSB comparison switch 130 are electrically connected to one end of the comparator 170 . One end of the unity gain amplifier unit 140 is electrically connected to one end of the most significant bit capacitor array 120 and the other end of the sampling switch unit 110, and the other end of the unity gain amplifier unit 140 is electrically connected to the least significant bit capacitor array One end of 150, the other end of the least significant bit capacitor array 150 is electrically connected to one end of the least significant bit comparison switch 160, and the other end of the least significant bit comparison switch 160 is electrically connected to one end of the comparator 170, The other end of the comparator 170 is electrically connected to the continuous progressive control unit 180 . Wherein, the comparator 170 outputs a comparator signal S c continuously to the progressive control unit 180, and the control unit 180 continuously progressive outputs a plurality of control signals to the MSB capacitor array 120 according to the comparison signal S c, The most significant bit comparison switch 130, the least significant bit capacitor array 150 and the least significant bit comparison switch 160 are controlled to perform switching and comparison of each bit, and the continuous progressive control unit 180 outputs a digital signal D.

在本實施例中，當該連續漸進式類比數位轉換器100進行取樣步驟時，該取樣開關單元110導通，該類比訊號V i經由該取樣開關單元110對該最高有效位元電容陣列120進行充電，同時，該類比訊號V i並經由該取樣開關單元110及該單位增益放大器單元140對該最低有效位元電容陣列150進行充電，使該最高有效位元電容陣列120及該最低有效位元電容陣列150的電位與該類比訊號V i相同，以同步對該類比訊號V i進行取樣，而可達成降低所需之電容陣列大小之功效。其中，該最高有效位元電容陣列120為該連續漸進式類比數位轉換器100的粗調部分，該最低有效位元電容陣列150為該連續漸進式類比數位轉換器100的細調部分。 In this embodiment, when the continuous progressive analog-to-digital converter 100 performs the sampling step, the sampling switch unit 110 is turned on, and the analog signal V i is charged to the most significant bit capacitor array 120 through the sampling switch unit 110 At the same time, the analog signal V i charges the least significant bit capacitor array 150 through the sampling switch unit 110 and the unity gain amplifier unit 140, so that the most significant bit capacitor array 120 and the least significant bit capacitor array 150 than the potential of the same class signal V i, to synchronize the sampled analog signal V i, but can achieve the desired effect of reducing the size of the capacitor array. Wherein, the most significant bit capacitor array 120 is the coarse tuning part of the DAC 100 , and the least significant bit capacitor array 150 is the fine tuning part of the DAC 100 .

請參閱第2圖，其為本實施例之該連續漸進式類比數位轉換器100的電路圖，該連續漸進式類比數位轉換器100為差動輸入之具分割電容單調式SAR ADC架構。在本實施例中，該取樣開關單元110具有一正端取樣開關111及一負端取樣開關112，該正端取樣開關111之一端接收一正類比訊號V ip，該正端取樣開關111之另一端電性連接一正端最高有效位元線pLM，該負端取樣開關112之一端接收一負類比訊號V in，該負端取樣開關112之另一端電性連接一負端最高有效位元線nLM。 Please refer to FIG. 2 , which is a circuit diagram of the DAC 100 of this embodiment. The DAC 100 is a differential input monotonic SAR ADC structure with split capacitance. In this embodiment, the sampling switch unit 110 has a positive-end sampling switch 111 and a negative-end sampling switch 112 . One end of the positive-end sampling switch 111 receives a positive analog signal V ip , and the other end of the positive-end sampling switch 111 receives a positive analog signal V ip . one end of a positive terminal electrically connected to the MSB line pLM, the negative terminal of the sampling switch 112 receives one end of a negative analog signal V in, the other end of the negative terminal of the sampling switch 112 is electrically connected to a negative terminal of the MSB line nLM.

該最高有效位元電容陣列120具有複數個最高有效位元正端電容121、複數個最高有效位元正端開關122、複數個最高有效位元負端電容123及複數個最高有效位元負端開關124。該些最高有效位元正端電容121之一端電性連接該正端最高有效位元線pLM，各該最高有效位元正端電容121之另一端電性連接各該最高有效位元正端開關122之一端，各該最高有效位元正端開關122之另一端選擇性地電性連接一參考電壓端或一接地端，以由該參考電壓端接收一參考電壓Vref，或由該接地端接至零電位。該些最高有效位元負端電容123之一端電性連接該負端最高有效位元線nLM，各該最高有效位元負端電容123之另一端電性連接各該最高有效位元負端開關124之一端，各該最高有效位元負端開關124之另一端選擇性地電性連接該參考電壓端或該接地端，以由該參考電壓端接收該參考電壓Vref，或由該接地端接至零電位。本實施例共具有6個位元之最高有效位元正端電容121、最高有效位元正端開關122、最高有效位元負端電容123及最高有效位元負端開關124，但在其他實施例中，可具有不同之位元數。 The most significant bit capacitor array 120 has a plurality of most significant bit positive terminal capacitors 121, a plurality of most significant bit positive terminal switches 122, a plurality of most significant bit negative terminal capacitors 123 and a plurality of most significant bit negative terminals switch 124. One terminal of the most significant bit positive terminal capacitors 121 is electrically connected to the positive terminal most significant bit line pLM, and the other terminal of each of the most significant bit positive terminal capacitors 121 is electrically connected to each of the most significant bit positive terminal switches One end of 122, the other end of each positive terminal switch 122 of the most significant bit is selectively electrically connected to a reference voltage terminal or a ground terminal, so as to receive a reference voltage V ref from the reference voltage terminal, or from the ground terminal connected to zero potential. One end of the most significant bit negative terminal capacitors 123 is electrically connected to the negative most significant bit line nLM, and the other end of each of the most significant bit negative terminal capacitors 123 is electrically connected to each of the most significant bit negative terminal switches One end of 124, the other end of each negative terminal switch 124 of the most significant bit is selectively electrically connected to the reference voltage terminal or the ground terminal, so as to receive the reference voltage V ref from the reference voltage terminal, or to receive the reference voltage V ref from the ground terminal connected to zero potential. This embodiment has a total of 6 bits of the most significant bit positive terminal capacitor 121, the most significant bit positive terminal switch 122, the most significant bit negative terminal capacitor 123 and the most significant bit negative terminal switch 124, but in other implementations For example, different numbers of bits are possible.

該最高有效位元比較開關130具有一正端最高有效位元比較開關131及一負端最高有效位元比較開關132，該正端最高有效位元比較開關131之一端電性連接該正端最高有效位元線pLM，該正端最高有效位元比較開關131之另一端電性連接該比較器170之一正極輸入端171，該負端最高有效位元比較開關132之一端電性連接該負端最高有效位元線nLM，該負端最高有效位元比較開關132之另一端電性連接該比較器170之一負極輸入端172。 The most significant bit comparison switch 130 has a positive end MSB comparison switch 131 and a negative end MSB comparison switch 132, one end of the positive end MSB comparison switch 131 is electrically connected to the positive end MSB comparison switch 131 On the valid bit line pLM, the other end of the positive end of the MSB comparison switch 131 is electrically connected to a positive input end 171 of the comparator 170, and one end of the negative end MSB comparison switch 132 is electrically connected to the negative end A terminal MSB line nLM, the other end of the negative MSB comparison switch 132 is electrically connected to a negative input terminal 172 of the comparator 170 .

當該連續漸進式類比數位轉換器100進行取樣步驟時，該正端取樣開關111及該負端取樣開關112導通，該正端最高有效位元比較開關131及該負端最高有效位元比較開關132關閉，使得該些最高有效位元正端電容121及該些最高有效位元負端電容123累積電荷，而讓該正端最高有效位元線pLM及該負端最高有效位元線nLM的電位VipM、VinM提高至該正類比訊號Vip及該負類比訊號Vin 之電位。而當該連續漸進式類比數位轉換器100進行比較步驟時，該正端取樣開關111及該負端取樣開關112關閉，該正端最高有效位元比較開關131及該負端最高有效位元比較開關132導通，使得該正端最高有效位元線pLM及該負端最高有效位元線nLM的電位VipM、VinM傳送至該比較器170進行比對，該連續漸進式控制單元180再藉由該比較器170之該比較訊號Sc輸出控制訊號至該些最高有效位元正端開關122及該些最高有效位元負端開關124進行切換，使得該正端最高有效位元線pLM及該負端最高有效位元線nLM的電位變化能夠讓每個位元的切換符合二分搜尋法。 When the continuous progressive analog-to-digital converter 100 performs the sampling step, the positive terminal sampling switch 111 and the negative terminal sampling switch 112 are turned on, the positive terminal MSB comparison switch 131 and the negative terminal MSB comparison switch 132 is turned off, so that the most significant bit positive terminal capacitors 121 and the most significant bit negative terminal capacitors 123 accumulate charges, so that the positive terminal most significant bit line pLM and the negative terminal most significant bit line nLM The potentials V ipM and V inM are raised to the potentials of the positive analog signal V ip and the negative analog signal V in . When the continuous progressive analog-to-digital converter 100 performs the comparison step, the positive-side sampling switch 111 and the negative-side sampling switch 112 are turned off, the positive-side MSB comparison switch 131 and the negative-side MSB compare The switch 132 is turned on, so that the potentials V ipM and V inM of the positive end most significant bit line pLM and the negative end most significant bit line nLM are sent to the comparator 170 for comparison, and the continuous progressive control unit 180 borrows the The comparison signal S c of the comparator 170 outputs a control signal to the most significant bit positive terminal switches 122 and the most significant bit negative terminal switches 124 for switching, so that the positive terminal most significant bit lines pLM and The potential change of the most significant bit line nLM at the negative end enables the switching of each bit to conform to the binary search method.

請參閱第2圖，該單位增益放大器單元140具有一正端單位增益放大器141及一負端單位增益放大器142，該正端單位增益放大器141之一端電性連接該正端最高有效位元線pLM，該正端單位增益放大器141之另一端電性連接一正端最低有效位元線pLL，該負端單位增益放大器142之一端電性連接該負端最高有效位元線nLM，該負端單位增益放大器142之另一端電性連接一負端最低有效位元線nLL。請參閱第3圖，為該正端單位增益放大器141及該負端單位增益放大器142的電路圖，在本實施例中，該正端單位增益放大器141及該負端單位增益放大器142是由兩級之跨導放大器(operational transconductance amplifier，OTA)構成，具有極大的輸入阻抗且輸入電壓及輸出電壓相同的特性，而可讓該最低有效位元電容陣列150與該最高有效位元電容陣列120同時取樣。 Please refer to FIG. 2, the unity gain amplifier unit 140 has a positive terminal unity gain amplifier 141 and a negative terminal unity gain amplifier 142, and one terminal of the positive terminal unity gain amplifier 141 is electrically connected to the positive terminal most significant bit line pLM , the other end of the positive end unity gain amplifier 141 is electrically connected to a positive end least significant bit line pLL, one end of the negative end unity gain amplifier 142 is electrically connected to the negative end most significant bit line nLM, the negative end unit The other end of the gain amplifier 142 is electrically connected to a negative least significant bit line nLL. Please refer to FIG. 3, which is a circuit diagram of the positive-end unity gain amplifier 141 and the negative-end unity gain amplifier 142. In this embodiment, the positive-end unity gain amplifier 141 and the negative-end unity gain amplifier 142 are composed of two stages It is composed of an operational transconductance amplifier (OTA), which has a large input impedance and the characteristics of the same input voltage and output voltage, and can allow the least significant bit capacitor array 150 and the most significant bit capacitor array 120 to sample at the same time .

請參閱第2圖，該最低有效位元電容陣列150具有複數個最低有效位元正端電容151、複數個最低有效位元正端開關152、複數個最低有效位元負端電容153及複數個最低有效位元負端開關154。該些最低有效位元正端電容151之一端電性連接該正端最低有效位元線pLL，各該最低有效位元正端電容151之另一端電性連接各該最低有效位元正端開關152之一端，各該最低有效位元正端開關152之另一端選擇性地電性連接一次參考電壓端或一接地端，以由該次參考電壓端接收一次參考電壓V ref/2 5，或由該接地端接至零電位。該些最低有效位元負端電容153之一端電性連接該負端最低有效位元線nLL，各該最低有效位元負端電容153之另一端電性連接各該最低有效位元負端開關154之一端，各該最低有效位元負端開關154之另一端選擇性地電性連接該次參考電壓端或該接地端，以由該次參考電壓端接收該次參考電壓V ref/2 5，或由該接地端接至零電位，本實施例共具有5個位元之最低有效位元正端電容151、最低有效位元正端開關152、最低有效位元負端電容153及最低有效位元負端開關154，但在其他實施例中，可具有不同之位元數。 Please refer to FIG. 2, the least significant bit capacitor array 150 has a plurality of least significant bit positive terminal capacitors 151, a plurality of least significant bit positive terminal switches 152, a plurality of least significant bit negative terminal capacitors 153 and a plurality of LSB negative terminal switch 154 . One end of the least significant bit positive terminal capacitors 151 is electrically connected to the positive least significant bit line pLL, and the other end of each of the least significant bit positive terminal capacitors 151 is electrically connected to each of the least significant bit positive terminal switches One terminal of 152, the other terminal of each of the least significant bit positive terminal switches 152 is selectively electrically connected to a primary reference voltage terminal or a ground terminal, so as to receive the primary reference voltage V ref /2 5 from the secondary reference voltage terminal, or Connected to zero potential from this ground terminal. One end of the least significant bit negative terminal capacitors 153 is electrically connected to the negative least significant bit line nLL, and the other end of each of the least significant bit negative terminal capacitors 153 is electrically connected to each of the least significant bit negative terminal switches One end of 154, the other end of each of the least significant bit negative terminal switches 154 is selectively electrically connected to the sub-reference voltage terminal or the ground terminal, so as to receive the sub-reference voltage V ref /2 5 from the sub-reference voltage terminal , or the ground terminal is connected to zero potential, this embodiment has a total of 5 bits of least significant bit positive terminal capacitor 151, least significant bit positive terminal switch 152, least significant bit negative terminal capacitor 153 and least significant bit. The bit negative switch 154, but in other embodiments, may have a different number of bits.

由於該最低有效位元電容陣列150為該連續漸進式類比數位轉換器100的細調部分，該些最低有效位元正端電容151及該些最低有效位元負端電容153的電容值較小，而可降低整體之該連續漸進式類比數位轉換器100的面積。在本實施例中，該參考電壓V ref之電位為該次參考電壓之電位的2 5倍，或在其他實施例中，該參考電壓之電位為該次參考電壓之電位的2 n倍，n為正整數。 Since the least significant bit capacitor array 150 is the fine tuning part of the CAS 100, the capacitance values of the least significant bit positive terminal capacitors 151 and the least significant bit negative terminal capacitors 153 are relatively small , and the overall area of the DAC 100 can be reduced. In this embodiment, the potential of the reference voltage Vref is 25 times the potential of the sub-reference voltage, or in other embodiments, the potential of the reference voltage is 2n times the potential of the sub-reference voltage, n is a positive integer.

請參閱第2圖，在本實施例中，該最低有效位元比較開關160具有一正端最低有效位元比較開關161及一負端最低有效位元比較開關162，該正端最低有效位元比較開關161之一端電性連接該正端最低有效位元線pLL，該正端最低有效位元比較開關161之另一端電性連接該比較器170之該正極輸入端171。該負端最低有效位元比較開關162之一端電性連接該負端最低有效位元線nLL，該負端最低有效位元比較開關162之另一端電性連接該比較器170之該負極輸入端172。Referring to FIG. 2, in this embodiment, the least significant bit comparison switch 160 has a positive end LSB comparison switch 161 and a negative end LSB comparison switch 162. The positive end LSB comparison switch 162 One end of the comparison switch 161 is electrically connected to the positive LSB line pLL, and the other end of the positive LSB comparison switch 161 is electrically connected to the positive input terminal 171 of the comparator 170 . One end of the negative LSB comparison switch 162 is electrically connected to the negative LSB line nLL, and the other end of the negative LSB comparison switch 162 is electrically connected to the negative input terminal of the comparator 170 172.

當該連續漸進式類比數位轉換器100進行取樣步驟時，該正端取樣開關111及該負端取樣開關112導通，該正端最低有效位元比較開關161及該負端最低有效位元比較開關162關閉，使得該些最低有效位元正端電容151及該些最低有效位元負端電容153累積電荷，讓該正端最低有效位元線pLL及該負端最低有效位元線nLL的電位V ipL、V inL提高至該正類比訊號V ip及該負類比訊號V in之電位。而當該最高有效位元電容陣列120進行比較步驟時，該正端最高有效位元比較開關131及該負端最高有效位元比較開關132導通，該正端最低有效位元比較開關161及該負端最低有效位元比較開關162關閉，此時該比較器170僅比較該正端最高有效位元線pLM及該負端最高有效位元線nLM的電位V ipM、V inM。當該最高有效位元電容陣列120完成比較步驟時，該正端最高有效位元比較開關131及該負端最高有效位元比較開關132關閉，該正端最低有效位元比較開關161及該負端最低有效位元比較開關162導通，使得該正端最低有效位元線pLL及該負端最低有效位元線nLL的電位V ipL、V inL傳送至該比較器170進行比對，以進行該最低有效位元電容陣列150的比較步驟。該連續漸進式控制單元180再藉由該比較器170之該比較訊號S c輸出控制訊號至該些最低有效位元正端開關152及該些最低有效位元負端開關154進行切換，使得該正端最低有效位元線pLL及該負端最低有效位元線nLL的電位變化亦夠讓每個位元的切換符合二分搜尋法。 When the continuous progressive analog-to-digital converter 100 performs the sampling step, the positive end sampling switch 111 and the negative end sampling switch 112 are turned on, the positive end LSB comparison switch 161 and the negative end LSB comparison switch 162 is turned off, so that the least significant bit positive terminal capacitors 151 and the least significant bit negative terminal capacitors 153 accumulate charges, so that the potential of the positive terminal least significant bit line pLL and the negative terminal least significant bit line nLL V ipL and V inL are raised to the potentials of the positive analog signal V ip and the negative analog signal V in . When the MSB capacitor array 120 performs the comparison step, the positive end MSB comparison switch 131 and the negative end MSB comparison switch 132 are turned on, the positive end MSB comparison switch 161 and the negative end MSB comparison switch 161 are turned on. When the negative end LSB comparison switch 162 is turned off, the comparator 170 only compares the potentials V ipM and V inM of the positive end most significant bit line pLM and the negative end most significant bit line nLM. When the MSB capacitor array 120 completes the comparison step, the positive MSB comparison switch 131 and the negative MSB comparison switch 132 are turned off, the positive LSB comparison switch 161 and the negative MSB comparison switch 132 are turned off The LSB comparison switch 162 is turned on, so that the potentials V ipL and V inL of the LSB line pLL at the positive end and the LSB line nLL at the negative end are sent to the comparator 170 for comparison, so as to perform the comparison. Least significant bit capacitor array 150 comparison step. The continuous progressive control unit 180 then outputs a control signal to the least significant bit positive terminal switches 152 and the least significant bit negative terminal switches 154 through the comparison signal S c of the comparator 170 for switching, so that the The potential changes of the least significant bit line pLL at the positive end and the least significant bit line nLL at the negative end are also sufficient to allow the switching of each bit to comply with the binary search method.

本發明藉由該單位增益放大器單元140連接該最高有效位元電容陣列120及該最低有效位元電容陣列150，可以讓該最高有效位元電容陣列120的電壓經由該單位增益放大器單元140傳送至該最低有效位元電容陣列150，使得該連續漸進式類比數位轉換器100能夠以較小的電容數達成高解析度之類比數位轉換，且使用該單位增益放大器單元140取代橋接電容能夠避免非線性失真的問題，而提高該連續漸進式類比數位轉換器100的線性度。In the present invention, the unit gain amplifier unit 140 is connected to the most significant bit capacitor array 120 and the least significant bit capacitor array 150, so that the voltage of the most significant bit capacitor array 120 can be transmitted through the unity gain amplifier unit 140 to The least significant bit capacitor array 150 enables the DAC 100 to achieve high-resolution analog-to-digital conversion with a smaller number of capacitors, and the use of the unity gain amplifier unit 140 instead of bridge capacitors can avoid nonlinearity The problem of distortion is improved, and the linearity of the DAC 100 is improved.

本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

100:連續漸進式類比數位轉換器100: Continuous Progressive Analog-to-Digital Converter

110:取樣開關單元110: Sampling switch unit

111:正端取樣開關111: Positive sampling switch

112:負端取樣開關112: Negative end sampling switch

120:最高有效位元電容陣列120: most significant bit capacitor array

121:最高有效位元正端電容121: Most significant bit positive terminal capacitance

122:最高有效位元正端開關122: The most significant bit positive end switch

123:最高有效位元負端電容123: The most significant bit negative terminal capacitance

124:最高有效位元負端開關124: most significant bit negative end switch

130:最高有效位元比較開關130: Most significant bit comparison switch

131:正端最高有效位元比較開關131: Positive end most significant bit comparison switch

132:負端最高有效位元比較開關132: Negative end most significant bit comparison switch

140:單位增益放大器單元140: Unity Gain Amplifier Unit

141:正端單位增益放大器141: Positive Unit Gain Amplifier

142:負端單位增益放大器142: negative terminal unity gain amplifier

150:最低有效位元電容陣列150: Least significant bit capacitor array

151:最低有效位元正端電容151: Least significant bit positive terminal capacitance

152:最低有效位元正端開關152: Least significant bit positive end switch

153:最低有效位元負端電容153: Least significant bit negative terminal capacitance

154:最低有效位元負端開關154: Least significant bit negative end switch

160:最低有效位元比較開關160: LSB comparison switch

161:正端最低有效位元比較開關161: Positive Least Significant Bit Comparison Switch

162:負端最低有效位元比較開關162: Negative end least significant bit comparison switch

170:比較器170: Comparator

171:正極輸入端171: Positive input terminal

172:負極輸入端172: negative input terminal

180:連續漸進式控制單元180: Continuous Progressive Control Unit

V i:類比訊號V i : analog signal

V ip:正類比訊號V ip : Positive analog signal

V in:負類比訊號V in : negative analog signal

S c:比較訊號S c : Comparison signal

V ref:參考電壓V ref : reference voltage

V ipM:正端最高有效位元線之電位V ipM : the potential of the most significant bit line of the positive terminal

V inM:負端最高有效位元線之電位V inM : the potential of the most significant bit line at the negative end

D:數位訊號D: digital signal

V ipL:正端最低有效位元線之電位V ipL : the potential of the least significant bit line at the positive end

V inL:負端最低有效位元線之電位V inL : the potential of the least significant bit line at the negative end

pLM:正端最高有效位元線pLM: positive end most significant bit line

nLM:負端最高有效位元線nLM: negative end most significant bit line

pLL:正端最低有效位元線pLL: Positive Least Significant Bit Line

nLL:負端最低有效位元線nLL: negative end least significant bit line

第1圖：依據本發明之一實施例，一連續漸進式類比數位轉換器的功能方塊圖。 第2圖：依據本發明之一實施例，該連續漸進式類比數位轉換器的電路圖。 第3圖：依據本發明之一實施例，一單位增益放大器的電路圖。 FIG. 1 is a functional block diagram of a continuous progressive analog-to-digital converter according to an embodiment of the present invention. Figure 2: A circuit diagram of the continuous progressive analog-to-digital converter according to an embodiment of the present invention. Figure 3: A circuit diagram of a unity gain amplifier according to an embodiment of the present invention.

100:連續漸進式類比數位轉換器 100: Continuous Progressive Analog-to-Digital Converter

110:取樣開關單元 110: Sampling switch unit

120:最高有效位元電容陣列 120: most significant bit capacitor array

130:最高有效位元比較開關 130: Most significant bit comparison switch

140:單位增益放大器單元 140: Unity Gain Amplifier Unit

150:最低有效位元電容陣列 150: Least significant bit capacitor array

160:最低有效位元比較開關 160: LSB comparison switch

170:比較器 170: Comparator

180:連續漸進式控制單元 180: Continuous Progressive Control Unit

Vi:類比訊號 V i : analog signal

Sc:比較訊號 S c : Comparison signal

D:數位訊號 D: digital signal

Claims (10)

一種連續漸進式類比數位轉換器，其包含：一取樣開關單元，其一端接收一類比訊號；一最高有效位元電容陣列，其一端電性連接該取樣開關單元之另一端；一最高有效位元比較開關，其一端電性連接該最高有效位元電容陣列之另一端；一單位增益放大器單元，其一端電性連接該取樣開關單元之另一端及該最高有效位元電容陣列之一端；一最低有效位元電容陣列，其一端電性連接該單位增益放大器單元之另一端；一最低有效位元比較開關，其一端電性連接該最低有效位元電容陣列之另一端；一比較器，電性連接該最高有效位元比較開關之另一端及該最低有效位元比較開關之另一端，且該比較器輸出一比較訊號；以及一連續漸進式控制單元，電性連接該比較器以接收該比較訊號，且該連續漸進式控制單元根據該比較訊號輸出複數個控制訊號至該最高有效位元電容陣列、該最高有效位元比較開關、該最低有效位元電容陣列及該最低有效位元比較開關進行控制。 A continuous progressive analog digital converter, comprising: a sampling switch unit, one end of which receives an analog signal; a most significant bit capacitor array, one end of which is electrically connected to the other end of the sampling switch unit; a most significant bit unit a comparison switch, one end of which is electrically connected to the other end of the most significant bit capacitor array; a unity gain amplifier unit, one end of which is electrically connected to the other end of the sampling switch unit and one end of the most significant bit capacitor array; a lowest an effective bit capacitor array, one end of which is electrically connected to the other end of the unity gain amplifier unit; a least significant bit comparison switch, one end of which is electrically connected to the other end of the least significant bit capacitor array; a comparator, electrically The other end of the most significant bit comparison switch and the other end of the least significant bit comparison switch are connected, and the comparator outputs a comparison signal; and a continuous progressive control unit is electrically connected to the comparator to receive the comparison signal, and the continuous progressive control unit outputs a plurality of control signals to the most significant bit capacitor array, the most significant bit comparison switch, the least significant bit capacitor array and the least significant bit comparison switch according to the comparison signal Take control. 如請求項1之連續漸進式類比數位轉換器，其中該取樣開關單元具有一正端取樣開關及一負端取樣開關，該正端取樣開關之一端接收一正類比訊號，該正端取樣開關之另一端電性連接一正端最高有效位元線，該負端取樣開關之一端接收一負類比訊號，該負端取樣開關之另一端電性連接一負端最高有 效位元線。 The continuous progressive analog-to-digital converter of claim 1, wherein the sampling switch unit has a positive-end sampling switch and a negative-end sampling switch, one end of the positive-end sampling switch receives a positive analog signal, and the positive-end sampling switch receives a positive analog signal. The other end is electrically connected to a positive end most significant bit line, one end of the negative end sampling switch receives a negative analog signal, and the other end of the negative end sampling switch is electrically connected to a negative end most significant bit line. valid bit line. 如請求項2之連續漸進式類比數位轉換器，該最高有效位元電容陣列具有複數個最高有效位元正端電容、複數個最高有效位元正端開關、複數個最高有效位元負端電容及複數個最高有效位元負端開關，該些最高有效位元正端電容之一端電性連接該正端最高有效位元線，各該最高有效位元正端開關之一端電性連接各該最高有效位元正端電容之另一端，各該最高有效位元正端開關之另一端選擇性地電性連接一參考電壓端或一接地端，該些最高有效位元負端電容之一端電性連接該負端最高有效位元線，各該最高有效位元負端開關之一端電性連接各該最高有效位元負端電容之另一端，各該最高有效位元負端開關之另一端選擇性地電性連接該參考電壓端或該接地端。 According to the continuous progressive analog-to-digital converter of claim 2, the most significant bit capacitor array has a plurality of most significant bit positive terminal capacitors, a plurality of most significant bit positive terminal switches, and a plurality of most significant bit negative terminal capacitors and a plurality of most significant bit negative terminal switches, one end of the most significant bit positive terminal capacitors is electrically connected to the positive terminal most significant bit line, and one terminal of each of the most significant bit positive terminal switches is electrically connected to each of the The other end of the most significant bit positive terminal capacitor, the other end of each of the most significant bit positive terminal switches is selectively electrically connected to a reference voltage terminal or a ground terminal, and one terminal of the most significant bit negative terminal capacitors is electrically connected. is electrically connected to the most significant bit line of the negative terminal, one terminal of each negative terminal switch of the most significant bit is electrically connected to the other terminal of the negative terminal capacitor of each most significant bit, and the other terminal of each negative terminal switch of the most significant bit is electrically connected selectively electrically connected to the reference voltage terminal or the ground terminal. 如請求項2之連續漸進式類比數位轉換器，其中該單位增益放大器單元具有一正端單位增益放大器及一負端單位增益放大器，該正端單位增益放大器之一端電性連接該正端最高有效位元線，該正端單位增益放大器之另一端電性連接一正端最低有效位元線，該負端單位增益放大器之一端電性連接該負端最高有效位元線，該負端單位增益放大器之另一端電性連接一負端最低有效位元線。 The continuous progressive analog-to-digital converter of claim 2, wherein the unity gain amplifier unit has a positive terminal unity gain amplifier and a negative terminal unity gain amplifier, and one terminal of the positive terminal unity gain amplifier is electrically connected to the positive terminal most effective bit line, the other end of the positive end unity gain amplifier is electrically connected to a positive end least significant bit line, one end of the negative end unity gain amplifier is electrically connected to the negative end most significant bit line, the negative end unity gain The other end of the amplifier is electrically connected to a negative least significant bit line. 如請求項4之連續漸進式類比數位轉換器，該最低有效位元電容陣列具有複數個最低有效位元正端電容、複數個最低有效位元正端開關、複數個最低有效位元負端電容及複數個最低有效位元負端開關，該些最低有效位元正端電容之一端電性連接該正端最低有效位元線，各該最低有效位元正端開關之一端電性連接各該最低有效位元正端電容之另一端，各該最低有效位元正端開關之另一端選擇性地電性連接一次參考電壓端或一接地端，該些最低有效位元負端電容之一端電性連接該負端最低有效位元線，各該最低有效位元負端開關之一端電性連接各該最低有效位元負端電容之另一端，各該最低有效位元負端開關之另一端選擇性地電性連接該次參考電壓端或該接地端。According to the continuous progressive analog-digital converter of claim 4, the least significant bit capacitor array has a plurality of least significant bit positive terminal capacitors, a plurality of least significant bit positive terminal switches, and a plurality of least significant bit negative terminal capacitors and a plurality of least significant bit negative terminal switches, one terminal of the least significant bit positive terminal capacitors is electrically connected to the positive terminal least significant bit line, and one terminal of each of the least significant bit positive terminal switches is electrically connected to each of the The other end of the positive terminal capacitor of the least significant bit, the other terminal of each positive terminal switch of the least significant bit is selectively electrically connected to a primary reference voltage terminal or a ground terminal, and one terminal of the negative terminal capacitor of the least significant bit is electrically connected. is electrically connected to the least significant bit line of the negative terminal, one end of each negative terminal switch of the least significant bit is electrically connected to the other end of the negative terminal capacitor of each least significant bit, and the other terminal of each negative terminal switch of the least significant bit is electrically connected The secondary reference voltage terminal or the ground terminal is selectively electrically connected. 如請求項4之連續漸進式類比數位轉換器，其中該最高有效位元比較開關具有一正端最高有效位元比較開關及一負端最高有效位元比較開關，該正端最高有效位元比較開關之一端電性連接該正端最高有效位元線，該負端最高有效位元比較開關之一端電性連接該負端最高有效位元線。The continuous progressive analog-to-digital converter of claim 4, wherein the MSB comparison switch has a positive-side MSB comparison switch and a negative-side MSB comparison switch, the positive-side MSB comparison switch One end of the switch is electrically connected to the positive end most significant bit line, and one end of the negative end most significant bit comparison switch is electrically connected to the negative end most significant bit line. 如請求項6之連續漸進式類比數位轉換器，其中該最低有效位元比較開關具有一正端最低有效位元比較開關及一負端最低有效位元比較開關，該正端最低有效位元比較開關之一端電性連接該正端最低有效位元線，該負端最低有效位元比較開關之一端電性連接該負端最低有效位元線。The continuous progressive analog-to-digital converter of claim 6, wherein the least significant bit comparison switch has a positive end least significant bit comparison switch and a negative end least significant bit comparison switch, the positive end least significant bit comparison switch One end of the switch is electrically connected to the positive LSB line, and one end of the negative LSB comparison switch is electrically connected to the negative LSB line. 如請求項7之連續漸進式類比數位轉換器，其中該比較器具有一正極輸入端及一負極輸入端，該正極輸入端電性連接該正端最高有效位元比較開關及該正端最低有效位元比較開關，該負極輸入端電性連接負端最高有效位元比較開關及該負端最低有效位元比較開關。The continuous progressive analog-to-digital converter of claim 7, wherein the comparator has a positive input terminal and a negative input terminal, the positive input terminal is electrically connected to the positive terminal MSB comparison switch and the positive terminal least significant bit element comparison switch, the negative input terminal is electrically connected to the negative terminal most significant bit comparison switch and the negative terminal least significant bit comparison switch. 如請求項1之連續漸進式類比數位轉換器，其中該最高有效位元電容陣列可選擇性地電性連接至一參考電壓端或一接地端，以經由該參考電壓端接收一參考電壓，該最低有效位元電容陣列可選擇性地電性連接至一次參考電壓端或該接地端，以經由該次參考電壓端接收一次參考電壓，其中該參考電壓之電位為該次參考電壓之電位的2 n倍，n為正整數。 The DAC of claim 1, wherein the most significant bit capacitor array can be selectively electrically connected to a reference voltage terminal or a ground terminal to receive a reference voltage through the reference voltage terminal, the The least significant bit capacitor array can be selectively electrically connected to the primary reference voltage terminal or the ground terminal to receive the primary reference voltage through the secondary reference voltage terminal, wherein the potential of the reference voltage is 2 times the potential of the secondary reference voltage n times, where n is a positive integer. 如請求項9之連續漸進式類比數位轉換器，其中該參考電壓之電位為該次參考電壓之電位的2 5倍 The continuous progressive analog-to-digital converter of claim 9, wherein the potential of the reference voltage is 25 times the potential of the sub-reference voltage
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