WO2005091160A1

WO2005091160A1 - Activating code generation method

Info

Publication number: WO2005091160A1
Application number: PCT/JP2005/004963
Authority: WO
Inventors: Hiroshi Shimura
Original assignee: Ipflex Inc.
Priority date: 2004-03-19
Filing date: 2005-03-18
Publication date: 2005-09-29
Also published as: JP4208919B2; JPWO2005091160A1

Abstract

There is provided an activating code generation method for executing an application by a data processing device having a circuit partition where a data path is formed by connecting processing elements, whose function is controlled by setting configuration information in a memory area corresponding to the processing elements. The method includes a step fro generating layout information for mapping a data path onto the circuit partition and generating access information enabling an access to the memory area corresponding to the processing element correlated to a first parameter. It is possible to provide a user with an environment capable of freely modifying the data path processing configured by the processing elements by modifying the parameter on the source code.

Description

Specification

Activation code generation method

Technical field

The present invention relates to a method for generating a code for executing an application using a data processing device that configures a data path using a plurality of processing elements.

Background art

[0002] Japanese Patent Application Laid-Open No. 2004-40188 discloses an arithmetic circuit group including a processor, a plurality of arithmetic units, and a connection path for variably connecting the arithmetic units, and a parameter capable of changing processing specifications by parameter setting. There is described an integrated circuit characterized by including dedicated hardware, an interface between modules for connecting the processor, the arithmetic circuit group, and the dedicated hardware with parameters to each other. In this integrated circuit, processing that can be handled by changing parameters such as the number of data and accuracy of processing is executed by a combination of dedicated hardware for the processing and a parameter holding register. In addition, the contents of the parameter holding register are set by some method before operating the integrated circuit.

[0003] International Publication No. 02Z095946 discloses that a plurality of elements for performing various logical operations have a region called a matrix in which the elements are arranged two-dimensionally. There is disclosed a data processing device capable of flexibly reconfiguring a data path by a plurality of elements by switching. The configuration in which the data path can be dynamically reconfigured is not limited to this, and elements that perform appropriate logical operations (processing elements, PEs) are connected in a tree shape, and adjacent elements are connected to each other. A configuration in which the elements are connected and the elements are used as a communication path can be considered. In a data processing device that dynamically reconfigures a data path with a plurality of elements, the function of each element is provided by preparing a configuration memory for storing the configuration data of each element. Can be controlled. The processing or operation can be changed for each element by the configuration data, and the connection between elements can be changed It is also possible to control the operation and non-operation of each element.

[0004] It is possible to control processing functions or processing contents in a data path by using parameters. In a data processing device having a plurality of elements, the movement or content of processing using a data path having a plurality of elements can be controlled by changing parameters. By setting the parameter to be changed as a part of the configuration data (configuration data) in each element, the processing or movement of the data path can be controlled by changing the configuration data. Therefore, a fixed memory dedicated to parameter setting is not required. Furthermore, since the parameters of the reconfigured data path can be changed using a plurality of elements, the design time required to reconfigure the data path having different parameters can be reduced. In a data processing device that requires less time than changing the parameters or the time required to reconfigure the data path by changing the connection of the element, the function can be changed by changing the parameters. There is an advantage in that the processing time and resource consumption can be reduced by reconfiguring.

[0005] In a data processing device requiring a plurality of elements, one or more kinds of elements are prepared in order to enhance versatility, and many data paths are provided among the plurality of elements. It is configured using some elements. In order to implement a data path for realizing a certain function or process in a data processing device, the data processing device uses a plurality of elements physically arranged in a certain area in accordance with a predetermined rule. It is necessary to select the elements required to configure the data path to be used, and to determine the physical arrangement of the elements required for the target data path and the connection between those elements. The process of determining the physical placement and connection of these elements is called the placement and routing step, mapping step or layout step.

[0006] Therefore, the following steps are required to implement a certain function in a data processing device and a data path that form a data path by connecting a plurality of elements.

a. The process of designing a data path (data flowgram) to achieve the desired function. b. The process of realizing the target data path by connecting one or more types of prepared elements, that is, designing a data path for each element. c. The process of converting the target element-based data node into layout information, which is the specific element arrangement and their combination.

[0007] These steps can also be performed manually. In practice, it is necessary to adjust the timing between the elements, to arrange multiple data paths in the same area, and to determine whether the number and types of Many factors need to be taken into account, such as the need to make adjustments. Therefore, the manual does not provide layout information that can actually implement the data node. Therefore, it is performed using appropriate software.

[0008] For this reason, even if an attempt is made to change the parameters of the data path laid out in the data processing device, the location of the specific layout used to implement the data path is specified under various conditions. Quite difficult to do. In addition, even if an element is identified that often contains multiple logic gates in one element, identify which logic gate of that element is affected by the parameter that is actually changing It is almost impossible. If possible, manually analyzing layout information generated by computer design is only a waste of time, and such a design method is not practical!

For example, if the data path executes a process involving transfer between memories, the data path having the same configuration can be obtained by changing parameters such as a copy source address, a copy destination address, and a copy word number. Can be used for various purposes. However, when designing a data processing device that configures data paths with different parameters by connecting multiple elements, a method designed to actually reconfigure data paths with different parameters is used. The conclusion is that the design is much more economical. If there are some bottlenecks in reconfiguring the data path and you do not want to change the configuration of the data path, use a memory or register that is physically fixed and can be called by a program, and include wiring to that register. There is a method of laying out the data path and rewriting the contents of the memory by a program. This method not only requires extra registers for setting parameters, but also adds elements to configure the data path that performs the desired processing and connects them to registers for setting parameters. Also requires an extra data path. Therefore, the use efficiency of the element is reduced and the data path is complicated. Therefore, it is an inapplicable solution when trying to perform various processes by dynamically reconfiguring multiple data paths.

[0010] As in Japanese Patent Application Laid-Open No. 2004-40188, dedicated hardware with parameters can be provided independently of a reconfigurable circuit. However, if the reconfigurable circuit has enough elements to form a data path to be configured with dedicated hardware with parameters, the dedicated hardware with parameters will be redundant hardware. It is difficult to adopt this technology if it is required to reduce the size of data processing devices packaged in the form of LSI or ASIC, reduce power consumption, and reduce costs.

Disclosure of the invention

[0011] Therefore, in the present invention, a data processing device capable of configuring a data path using a plurality of processing elements is provided with a configuration stored in each memory corresponding to each processing element. It is an object of the present invention to provide a method for generating a code that can be easily controlled in a unit of a processing element when using a program. Then, the configuration information of each processing element can be handled freely without the user being aware of the physical address of each processing element, and the processing of the data node composed of those elements can be performed on the source code. An object of the present invention is to provide a user with an environment in which parameters can be freely changed by changing parameters.

According to the present invention, at least one circuit section in which at least one data path is formed by connecting a plurality of processing elements is provided, and configuration information is set in a memory area corresponding to each of the processing elements. Accordingly, the present invention provides a method for generating an activation code for executing an application by a data processing device in which the function of a processing element is controlled, the method including the following steps.

A. The first step in generating source code to execute at least part of the application using a first function involving a first parameter. B. A computer generates layout information for mapping a first data path for performing processing including a first function to at least one circuit section, the layout information including connection information of a plurality of processing elements. And a second step of generating access information that enables access to a memory area corresponding to a processing element related to the first parameter.

C. A third step in which the activation code is generated by the computer using at least the source code including the instruction related to the first parameter and the access information.

[0013] The activation code is executed by one data path mounted in a circuit section by the activation code, and is transferred to a memory area corresponding to an element related to a first parameter of another data path. It may access and change parameters. If the data processing device has a control unit that controls the processing element function by setting configuration information in the memory area, for example, a control processor such as RISC, the activation code Is an execution program (execution code) executed by the control unit.

[0014] The second step (layout step) includes a plurality of processing elements (hereinafter, sometimes referred to as elements) that can execute logic of appropriate scale and Z or arithmetic operation. The layout information for mapping the data path to the circuit section is generated using a computer. At this time, since the first parameter used in the source code (source program) is known in advance, the processing in the computer when generating the layout information is traced, and the processing related to the first parameter is performed. It is possible to generate access information indicating the address of the memory area of the element. The access information may be information indicating the entire memory area corresponding to each element. Further detailed access information may be a detailed address of a memory area in a word or byte unit in which some processing is performed in accordance with the first parameter in the memory area corresponding to the element.

[0015] In the generation method of the present invention, the access information to the memory area related to the first parameter is converted to a third step of generating an activation code, for example, an execution program by compiling a source code. give feedback. This allows the instruction related to the first parameter Can be converted into an activation code including information for specifically accessing a memory area affected by the first parameter. For example, a memory area affected by the first parameter can be converted into an execution code operated based on the specific address. Therefore, the user who generates the source code can describe the first parameter without being conscious of the physical address of the processing element specifically operated by the first parameter.

One preferred embodiment of the present invention is a case where the first function includes a function whose processing is changed by the first parameter. In that case, the access information includes an address of a memory area of the processing element whose processing is changed by the first parameter, and the source code includes an instruction to change the first parameter. Then, according to the present invention, a user can perform processing of a data path constituted by those processing elements without being aware of the physical addresses of the processing elements specifically operated by the first parameter on a source program. It can be changed freely by changing the first parameter.

According to the present invention, the user can freely handle the configuration information of each processing element without being aware of the physical address of the processing element. It is the most useful effect of the present invention that the parameters that change the function of the circuit can be described without stress, but the functions released as user-friendly functions according to the present invention are not limited to this. According to the present invention, software design of all processes that require access to the configuration information of the processing element is facilitated. For example, it is very easy to generate code (program) for reading and writing configuration information of a desired element for debugging purposes.

[0018] In recent years, it has been proposed to perform co-design of hardware and software at a low level in the process of designing LSIs which are becoming more and more complex. After the separation into the parts realized by software and the parts realized by software, the design process is basically independent. In the design and generation process, it has been proposed to verify the timing convergence of each other and to conduct collaborative verification to reflect the results in hardware and software. ing. However, as disclosed in the present invention, a method of generating an execution program in which the compile result of the instruction itself of the source code differs depending on the specific result of the hardware design has been proposed. What,

A program for generating, ie, compiling, the activation code of the present invention using a computer uses at least a part of an application by utilizing a first function related to a first parameter. For executing a layout process for mapping a first data node that performs a process including a first function to a circuit section of a data processing device in accordance with a source code generated to be executed by the including. Then, in the layout process, layout information including connection information of a plurality of processing elements is generated, and access information for accessing a memory area corresponding to the processing element related to the first parameter is generated.

[0020] The connrill program further includes a source code including an instruction related to the first parameter and access information, at least as inputs, for executing a process of generating an activation code of the data processing device. It may have a description. The description to be executed by the computer includes source code or instructions in a computer-executable form, an instruction group, a macro instruction, an instruction to call a module or a subroutine for performing each processing, and the like. This compiling program or program product can be recorded on a suitable recording medium such as a CD-ROM and provided, or can be provided via a computer network such as the Internet. .

Further, according to the present invention, there is provided an apparatus for generating an activation code for executing an application in a data processing apparatus having at least one circuit section, wherein at least a part of the application is provided. And a first data path for performing processing including the first function corresponding to the source code generated to be executed using the first function related to the first parameter, by at least one circuit. Layout information for mapping to partitions, including layout information including connection information of a plurality of processing elements, and access information including addresses of memory areas corresponding to processing elements related to the first parameter. , A source code including an instruction related to the first parameter, and address information. As inputs, and means for generating an activation code The present invention provides a generating device having:

[0022] The relationship between the processing element and the memory area in the circuit section of the data processing device is not particularly limited as long as the function of the processing element can be dynamically controlled by the configuration information set in the memory area. It is not necessary that the write element and the memory area are arranged at the same position. In consideration of the wiring delay, the configuration of each gate or transistor that constitutes a processing element, and the amount of information in the memory area, the processing element physically has a force including the memory area, or at least It is preferable that a memory area is arranged in the vicinity of the processing element in a group unit. In such a data processing device, the access information includes information corresponding to a physical address enabling access to the processing element itself.

[0023] In a reconfigurable data processing device having connection means for reconfiguring a data path by changing a connection of a plurality of processing elements, at least one circuit partitioning power is used. Have instructions to In the second step of generating layout information, the layout information for reconfiguring the first data path and the access for enabling access to the memory area in the reconfigured first data path are included. Generate information. Therefore, the present invention is also useful in the design and development of a data processing device that forms a fixed data path by using processing elements, and the design and development of a data processing device that forms a reconfigurable data path. It is also useful in development.

Further, the activation code generation method of the present invention reconfigures a data path at an arbitrary position as well as a data processing device that reconfigures a data path at a fixed position of at least one circuit area. It is also useful in the design and development of data processing equipment. In that case, the access information will include the relative address. In other words, if the data processing device has a means for reconfiguring the data path anywhere in the circuit section, the layout step may include a step for reconfiguring the first data node in any location. And generates the layout information and the relative address information of the memory area in the first data path reconstructed at an arbitrary location. [0025] Further, in the method of generating an activation code according to the present invention, the first function can be described in an instance format in the source code. In the second step of generating layout information, information that enables access to a memory area for each instance by using library information describing the first function in an object format, for example, memory for each instance, is used. Generate access information including the address of the area. In the third step of generating the activation code, an instruction related to the first parameter can be converted into a code for accessing a memory area corresponding to a processing element for each instance.

Brief Description of Drawings

FIG. 1 is a diagram showing an outline of a processing unit (PU).

FIG. 2 is a diagram showing an outline of a matrix.

FIG. 3 is a diagram showing an example of a processing element (PE).

FIG. 4 is a diagram showing another example of PE.

FIG. 5 is a diagram showing a configuration for loading configuration data into PEs.

FIG. 6 is a diagram showing a process of generating a program for execution.

FIG. 7 is a diagram showing an example of a DDDL code.

FIG. 8 is a diagram showing an example of access information.

FIG. 9 is a diagram showing an example of a user source program.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows an example of a data processing device that executes an application using an execution program generated according to the present invention. The data processing device 1 is a single processing unit (PU) 1 on a chip. As shown in FIG. 2, a circuit called a matrix in which a data path can be reconfigured by a plurality of processing elements (PE) 21 Block 19 is provided. The data processing device 1 further includes a control processor (RISC) 35 for supplying and controlling the configuration information (configuration data) to the PE 21 and the like, and a control processor for transmitting the configuration information. A unit (TCU) 59 and transfer paths 51-58 are provided. The transfer paths 51-58 are provided in each of the segments 10-15 in which the plurality of PEs 21 are grouped into a plurality, the input buffer 33, and the output buffer 34. These are not only supplied from RISC35 but also supplied from other PU1 etc. It also has a function to transfer the migration data to PE21. In this PU1, the TCU 59 is connected to a bus switching unit (bus interface, BSU) 36, and the RISC 35 supplies configuration data to each PE 21 via the BCU 36 via the TCU 59.

The PU 1 has two types of interfaces for inputting and outputting data inside the matrix 19. One is a direct input 31a-31c and a direct output 32a-32c, which can directly input and output data from the outside to the PE21 of the matrix 19. Multiple PU1s can be connected using direct inputs 31a-31c and direct outputs 32a-32c to further increase the real number of PE21s that make up the data node. As a result, application processing in which one chip (PU) 1 runs short of circuit elements can be dealt with by connecting a plurality of chips 1. PU1 is further provided with a configuration for supplying data to the matrix 19 using an input buffer 33 and an output buffer 34 as another input method. The input buffer 33 has four input elements LDB, and the configuration and control of the buffer 33 can be set by configuration data. The output buffer 34 is the same, has four output elements STB, and the configuration and control can be set by configuration data.

[0029] A plurality of components or interfaces are connected to the BSU 36. The configuration data can be sent to the matrix 19 by using not only the RISC 35 but also these components or interfaces. Also, the configuration data for configuring another data path inside the matrix 19 can be supplied to the PE 21. For example, external memory can provide configuration data via the SDRAM interface 37, and configuration data can also be supplied from an external processor connected to the PCI bus via the PCI bus interface 38. A DMAC 39 is connected as another component, and a general-purpose interface 40 such as an asynchronous communication device (UART) serving as a serial interface controller is connected via a bus bridge circuit 41.

The matrix 19, which is a reconfigurable circuit section, is shown in FIG. The matrix 19, as a whole, as shown in Figure 2, The circuit area is a circuit area in which a plurality of processing elements are arranged two-dimensionally in an array or a matrix. Therefore, the circuit area 19 is called a matrix. The matrix 19 of PU1 includes 368 PE21s, and is formally divided into six segments 10 to 15 to separately form a transfer path for supplying configuration data to them. However, in terms of constructing a data path from a plurality of PEs 21 and processing input data, the PEs 21 are not divided into a plurality of groups by these segments 10-15. Therefore, the PEs 21 can be flexibly connected by the wiring group 22, and a data path or a data flow extending over a plurality of segments can be freely configured.

The matrix 19 is composed of a plurality of processing elements (PEs) 21 arranged two-dimensionally in the vertical and horizontal directions, wirings 22 arranged in a grid pattern therebetween, and vertical and horizontal wirings 22 at connection points of the wirings 22. And a switching unit 23 that can freely switch the connection between the two. The function of the PE 21 may be freely set by a look-up table or the like. In this example, the PE21 has some elements such as an element for arithmetic logic operation, an element for delay, an element for memory, an element for generating an address for inputting or outputting data, and an element for inputting or outputting data. Contains functionally different elements. In PU1, multiple types of elements with an internal configuration suitable for functionally different processes are prepared, and the functionally different elements are divided into groups and arranged to improve the space efficiency of matrix 19. ing. PU1 also has the advantage that the AC characteristics and processing speed can be improved because the redundancy is reduced by arranging the elements in a certain number of functional groups.

FIG. 3 and FIG. 4 are examples of the PE 21. The PE 21 includes an internal data path area 29 whose function can be changed, and a setting unit 60 that controls the function of the internal data path area 29 based on configuration information. The internal data path area 29 and the wiring 22 are connected via input / output selectors 25 and 26. Therefore, one of the plurality of buses included in the wiring 22 is selected as the input bus and the output bus based on the configuration information, and the configuration of the data path formed by the PE 21 can be controlled by the configuration information.

The internal data path area 29a of the PE 21a shown in FIG. It has a raw circuit 28 and a selector SEL. The setting unit 60 includes a configuration memory 68 in which configuration information is stored. The function of the internal data path area 29a is controlled by the configuration information. In this PE 21a, the address generated by the address generation circuit 28 under the conditions set by the configuration information is output to the wiring 22 as an output signal do. The address signal is fed back to the PE 21a as an input signal di X or diy as it is or after being processed by another PE 21 via the row wiring and the column wiring. Then, the address selected by the selector SEL under the condition set by the configuration information is output from the matrix 19 as a data input or output address.

Therefore, the function of the PE 21a can be freely controlled by rewriting the configuration information stored in the configuration memory 68. For example, if a data path that executes processing involving transfer between memories is configured using one or more PE21a, the copy source address, copy destination address, and copy word count included in the configuration information By changing the parameters such as the above, it can be used for various purposes with the same configuration data path.

The PE 21b shown in FIG. 4 has a configuration suitable for arithmetic operations and logical operations. The internal data path unit 29b includes a shift circuit SHIFT, a mask circuit MASK, and a logical operation unit ALU. Then, as in the case of the PE 21a, the states of the shift circuit SHIFT, the mask circuit MASK, and the logical operation unit ALU are set by the configuration information stored in the configuration memory 68 of the setting unit 60. Therefore, by changing the configuration information, the input data dix and diy can be added or subtracted, compared, and a logical sum or a logical product can be calculated, and the result is output as an output signal do as a wiring (bus). 22 can be output.

FIG. 5 shows a mechanism for inputting and outputting data using the transfer path in the PE 21. Each of the transfer paths 51-56 is a wiring for serially connecting a 1-word (32-bit) register (flip-flop) provided in PE21 included in each of the segments 10-15 shown in FIG. You. Here, the transfer path 51 will be described as an example. The setting unit 60 of the PE 21 has a 32-bit register (FF) 61, and the FF 61 of the PE 21 adjacent to the front and rear by the 32-bit transfer path 51. Is connected to Therefore, in the transfer path 51, the one-word data 75 transmitted to the FF61 of one PE21 is transmitted to the FF61 of the next PE21 with one clock or one cycle delay.

The setting unit 60 includes a decoder 62 that decodes data 75 stored in the FF 61, a background operation unit 63 that operates in the background to store the data 75, and a oral data path area. And a foreground operation unit 64 in which configuration data for setting 29 are stored. The knock operation unit 63 selects three banks of the background memory 65, a selector 66 for distributing the data 75 stored in the FF 61 to each bank of the background memory 65 and a line to be directly output, and selects a bank of the memory 65. And a selector 67 capable of outputting data.

[0038] The foreground operating section 64 includes a foreground memory 68 that maintains the current configuration of the data path area 29. Therefore, this foreground memory 68 is a configuration memory that actually controls the function of the data path area 29.By rewriting a part or all of the configuration data of this memory 68, the function or operation of PE21 is It can be controlled freely within the designed range. The foreground operation unit 64 includes a selector 69 that selects and supplies data from the knock ground memory 65 or the FF 61 of the transfer path 51 to the foreground memory 68. The selectors 67 and 69 for selecting the configuration data (setting data) to be loaded into the foreground memory 68 are controlled by the second selectors 72 and 70 for selecting the selection signal, and are set to FF61 by the transfer path 51. Data and configuration data set in the foreground memory 68 can also be controlled. The selectors 67 and 69 may be controlled by a signal supplied directly from the RISC 35.

[0039] The setting unit 60 can select the data 75 to be supplied to the FF61 of the downstream PE21 from any one of the data of the FF61 of the own PE21, the data of the bank of the background memory 65, and the data of the foreground memory 68. An output selector 71 is provided. The decoder 62 switches the output selector 71 by analyzing the data 75 transferred to the FF61 of its own PE21, and selects the data 75 transferred to the FF61 of the downstream PE21. [0040] As described above, the PU1 can supply appropriate configuration data to the setting unit 60 of each PE21, and more specifically, the configuration memory 68 corresponding to the PE21 in a timely manner by the RISC 35. it can. Therefore, the data node composed of a plurality of PEs 21 can be dynamically changed. In addition, it is possible to rewrite part or all of the configuration data that controls PE21 in the foreground in units of PE21, so that the function of each PE21 can be changed without changing the data path configuration. It is possible to change the processing of the data path. Furthermore, it is also possible to read the configuration data of each PE21, and to change and rewrite part of the configuration data by RISC35, and to debug the configuration data fed back from PE21. It is also possible to use.

The hardware capable of dynamically changing the connection of the PE 21 to reconfigure the data node is not limited to this. For example, instead of using the wiring group 22 to connect the PEs 21, it is also possible to use the PEs 21 themselves as connection means and connect the PEs 21 to each other to form a changeable data path. As a method of supplying the configuration data to each PE 21, it is also possible to adopt a method of individually connecting the configuration memories of the PEs 21 to each other.

FIG. 6 shows a process of generating an execution program for executing a given user specification (application) by the PU1. The application generally indicates the tasks to be processed by PU1 or devices such as electronic devices that implement PU1, and is determined by the specifications of the user. In this example, the user specification indicating the application is given in the C source code (userO.c) 81 which is a device-independent description. First, the C source ~~ sco. ~~ (userO.c) 81 is referenced by a DDDL (Device Dependent Description Language) compiler 101 with reference to a hardware library 82 containing PU1 hardware information. Generate In this step ST-A, most of the processing described in the source code 81 is converted to be executed using the data path constituted by the PE 21 of the matrix 19 of PU1. Therefore, the DDDL source code 85 that describes the processing to be executed using the data path configured by the PE 21 in a format that depends on the device, that is, the function of the PE 21 included in the matrix 19 is used by the DDDL compiler 101. Generated. Further, a source code (userl.c) 84 including a description for controlling the matrix 19 whose data path is formed by the DDDL source code 85 is also generated by the DDDL compiler 101.

The matrix library 83 referred to by the DDDL compiler 101 has a module in which functions frequently used in a user program are described in the DDDL, so that the time required to generate the D DDL source code 85 can be reduced. it can. The functions to be modularized include, for example, functions related to input / output such as access control to a memory, and functions related to data processing such as Fourier transform. There are usually several ways to configure a data path to implement a certain function using multiple PE21s, and it takes a lot of time to select the optimal configuration. Therefore, compile time can be greatly reduced by preparing the DDDL source of the optimally configured data path in advance. In addition, by preparing DDDL sources of multiple data paths with the optimal configuration for several conditions for one function in the library 83 so that the compiler 101 can select them, it is possible to shorten the user time. You can generate a DDDL source suitable for using.

[0044] Furthermore, it is often possible to provide a DDDL source suitable for use by a user by changing a parameter of a data path for realizing a certain function. For such a function related to parameters, one or more parameters that can be changed from the user source code and DDDL code that describes a data path for realizing the function are prepared in the library 83. Therefore, in addition to the user source code 84 for realizing the user specification and the user DDDL code 85 for realizing the user specification, the DDDL compiler 101 can be used for the user source code 84 or the user DDDL code (user.dd2) 85 Or, output DDDL code (matrix. Dd2) 86 of multiple modules. Then, the user source code 84 includes an instruction for defining or changing a parameter that determines the processing of the selected DDDL code 86.

[0045] By describing the DDDL code of the module prepared in the library 83 in the object format, the functions to be realized by the module can be described in the source code (source program) 84 in the instance format. Therefore, the commands that control the parameters used in the module can be described in instance form. This Therefore, a configuration in which an instance of the same module is used in a plurality of data paths can be described very easily in a user source program.

Further, there is a case where resources of the PE 21 are insufficient because a data path (data flow) for realizing the processing requested by the user in the PU 1 is configured. In that case, it is necessary to reconfigure the data path in the matrix 19 by using the functions of the reconfigurable matrix 19 and using the PE 21 in a time-division manner. Therefore, the DDDL compiler 101 generates a plurality of data node configurations for using the PE 21 of the matrix 19 in a time-division manner, and outputs a plurality of DDDL codes describing the configuration of each data path. In addition, user source code 84 includes instructions to reconfigure the data path.

[0047] The DNA compiler 102 performs arrangement and wiring of the matrix 19 by using the user source code 84, the user DDDL code 85, and the DDDL code 86 of one or more modules as inputs. Therefore, the DNA compiler 102 maps the data path described in the DDDL code into the matrix 19 and outputs the layout information 87. In the step STB for performing this layout, when mapping the DDDL code 86 of the module in which the parameter that can be changed by the user source code 84 is defined, the access indicating the address of the configuration memory 68 of the PE 21 related to the parameter is performed. The information is output as a header file (matr ix.h) 88 together with the layout information 87. That is, in step ST-A, the user source code is executed by the DDDL compiler 101 so that at least a part of the application is executed using a function (first function) related to a certain (first) parameter. Generate 84 and DDDL source code 85. For example, in the source code 85, the specific operation of the function is determined by setting or changing parameters. In step ST-B, in addition to the layout information, access information that enables access to the configuration memory 68 corresponding to the PE 21 related to the first parameter is generated.

[0048] When the DDDL code 86 is specifically mapped by the PE21, the specific position of the PE21 for realizing the data path and the specific configuration of the gate circuit included in the PE21 are determined. . Therefore, if the DDDL code 86 includes a parameter that can be changed in advance, the specific PE21 affected by the parameter and the specific gate circuit included in the PE21 are specified, and the gate circuit is controlled. Configuration information The address of the configuration memory 68 to be stored is also specified. Alternatively, the address of the configuration memory 68 of the PE 21 affected by the parameter and the position of the word or bit affected by the parameter in the data set in the configuration memory 68 are specified.

[0049] In the matrix 19 of this example, since the configuration memory 68 is physically included in the PE21, the address of the configuration memory itself is the same as the address of the PE21 in the matrix. In a device in which one configuration memory is provided for a plurality of PEs 21, the address of the PE 21 and the address of the configuration memory may not correspond one-to-one. In that case, the access information 88 including the address where the data for controlling the PE 21 affected by the change of the parameter is stored can be generated in the common configuration memory. Before controlling the PE21 from the front, it is also possible to identify and update the addresses affected by the parameters in the configuration data. However, in many cases, the configuration data is compressed to reduce the amount of data before control at the front, and updating in the compressed state requires hardware for expansion and compression. And processing time are required, which is not preferable.

[0050] When the module 86 is used in the instance format in the user source program 84, the DNA compiler 102 maps the data path into the matrix 19 for each instance, and outputs the layout information 87 including the arrangement and wiring information. Output. At the same time, the DNA connector 102 outputs access information 88 including the address of the configuration memory of the PE 21 affected by the parameter for each data path, that is, for each instance.

Further, when a plurality of data paths need to be dynamically reconfigured in the matrix 19, the DNA compiler 102 outputs layout information 87 for reconfiguring the data paths in the matrix 19. Further, the DNA compiler 102 outputs access information 88 including the address of the configuration memory of the PE 21 affected by the parameter in the reconfigured data path.

[0052] If the PE 21 forming the matrix 19 is a single configuration, the data By configuring tapas anywhere in the matrix 19, the resources of the matrix 19 can be used more efficiently. However, the absolute position of PE21 is not determined until the data node is actually mounted on Matrix 19, and the configuration memory address of PE21 is not determined until then. Therefore, when the DNA compiler 102 generates the layout information for such PU1, the relative layout information 87 for reconfiguring the data path by the DDDL code 85 or 86 to an arbitrary place of the matrix 19 is used. And outputs access information 88 including the address of the configuration memory of PE21 affected by the parameter in the data path reconfigured anywhere. By providing PU1 with a function of processing the access information 88 based on the reference address of the matrix 19 in which the data path is mounted, it is possible to handle the access information 88 in the same way as access information including absolute addresses.

[0053] Further, the DNA compiler 102 outputs a source code (matrix, c) 89 that controls a function of changing a parameter of the modularized DDDL code 86. In this method of generating an execution program, in the user source program 88, an advanced mode is described in which an instruction for individually changing parameters related to a certain module is described, and parameters related to a certain module are changed collectively. Supports basic mode in which macro instructions can be described. Therefore, by preparing a source program 89 that defines the function to change the parameters related to the DDDL code 86 using the macro instruction described in the user source program 88, the C compiler 103 analyzes the macro instruction and executes the execution program. So that it can be generated.

The C compiler (gcc) 103 that generates an execution program converts the user source program 90, the source code 89 of the module whose data path is converted into the matrix 19, and the source code of the module contained in the C source library 91. Generates an executable code 93 as input to PU1! The user source program 90 is a source program 84 in which the access information generated in the step ST-B for generating layout information is included as a header file 88. Therefore, in the step ST-C for generating the execution program, the user source program 84 including the instruction related to the parameter, for example, the instruction for changing the noramometer, and the access information 88 are compiled. The execution program 93 is generated based on the information included in the input information of the line 103. For this reason, in the C compiler 103 that generates the execution program 93, the address of the memory to be accessed by the instruction for changing the parameter included in the user source program 84 is clear, and the configuration of the memory address is specified. An execution program 93 for writing the configuration data or rewriting the configuration data at the address of the memory is automatically generated.

[0055] The DDDL connoiler 101, DNA connoiler 102, and C connoiler 103 that execute a series of processes ST-A, ST-B, and ST-C for generating these execution programs have functions as a compiler including the above-described functions. Is recorded on a recording medium such as a CD-ROM and provided as a program product having a description for executing the program on a computer having appropriate resources. These program products can also be made available on different media such as the Internet. In addition, these program products can be provided as independent products, or can be provided as a single package.

[0056] The process ST—A of generating a device-dependent source program 84 and DDDL code 85 from the device-independent source program 81 is executed by an element to be converted into a device-dependent format. This is a process that utilizes the ideas and experiences of programmers who have many factors to consider for optimization such as allocation. Therefore, at present, semi-automatic operations are often performed by co-design with software, and are often performed manually. On the other hand, the process ST-B for performing placement and routing and the process ST-C for generating an execution program require a large number of elements to be converted and a large number of program steps. It is realistic and must be automatically generated by a computer. According to the present invention, in step ST-B, which is a hardware design field for automatically generating placement and routing by a computer, access information 88 is generated in a software design field for automatically generating an execution program by a computer. The access information 88 is used in a certain step ST. As a result, the final stage of the hardware design and the final stage of the software design can be combined, so that in the software design, the user can execute hardware-dependent instructions without clearing detailed addresses until the final stage. Use Can be used to advance the design.

FIG. 7 shows an example of the DDDL code (matrix. Dd2) 86 excerpted. In the description 86a, the DDDL source code with the macro name “cp” is defined. Parameters that can be changed are specified in object format by the description 86c.

FIG. 8 shows an example of the access information (matrix, h) 88. This access information 88 is used when the user source program _{84 describes} “matrix” defined in the DDDL code 86 with an instance name of “ _cp i” and an instruction to change the data path parameter. Output in response to the instruction. Therefore, the address of the PE21 where the parameter is used is described in the instance format of "'.'Cpl-U6" and "'.'cpl-U8 ()", and "dna-setparmphy-cp1-U6,) "And" dna-setparmphy-cp1-U8 () "define the detailed address of the memory that needs to be rewritten by the parameter.

FIG. 9 shows an excerpt of an example of the user source code (user2.c) 90 including the access information 88. In the user source code 90, the access information 88 is fetched by the header description 90a. According to the description 90b of “dna—cfgram—load3 (;)”, the configuration data of the data path “matrix” of the DDDL code 86 is loaded to the appropriate PE21 setting unit 60 of the matrix 19 that is a circuit block. . According to the description 90c of “dna_config ()”, the loaded configuration data is loaded into the foreground memory (configuration memory) 68 of the setting unit 60 of the PE 21 for configuring the data path, and the internal data path unit 29 is loaded. Control. Thus, a target data path is formed in the matrix 19, which is a circuit section.

[0060] A macro instruction 90d specifying an instance name cpl of "dna-setparmmacro-cpl (;)" sets a parameter that is open as changeable in the data path "matrix" to a predefined value of "inputl". Then, the processing by the data path "matrix" is started by the description 90e of "dna_run (;)". When the processing of the data path ends, the operation of the data path is stopped by the description 90f of “dna_stop (;)”. In this way, the process controlled by the parameters set by the description 90d is executed. Further, the configuration data is loaded into the foreground configuration memory 68 again according to the description 90g. Next, the parameter of the data path “matrix” is set to a predefined value of “input 2” by the macro instruction 90h “dna—setparmmacro—cpl (;)”, and the data path “matrix” is described by the description 90j. To start the process. This allows the same configuration data path “matrix” to operate with different parameters, without having to load new configuration data!

[0062] In the step ST—C of compiling the user source code 90 to generate the execution program 93, the C compiler 103 is changed in macro instructions 90d and 90h of “dna—setparmmacro—cp 1 (;)”. Details of these parameters can be found by referring to source code 89 of data path “matrix”. In addition, the C compiler 103 determines the detailed address of the memory in which the data to be changed according to those parameters is stored or the memory in which the data is stored is referred to by referring to the access information 88 included in the source code 90. Therefore, even if the user instruction of the user source code 90 does not clearly indicate the register or the detailed address of the memory relating to the parameter change, the C compiler 103 can execute the macro instruction 90d and 90h to change the parameter. An execution instruction for rewriting the contents of the corresponding address of the configuration memory 68 for controlling the corresponding PE 21 can be automatically generated.

In the above description, an example of generating a program (executable code) to be executed by the processor 35 for controlling the PU 1 according to the present invention is shown. However, the activation code generated by the present invention is It is not limited to the execution program of the control processor. By configuring an appropriate data path in the matrix 19, which is a reconfigurable circuit section, it is possible to give the matrix 19 a function as a control processor and control other data paths in the matrix 19. In this case, the activation code generated according to the present invention is executed in the matrix 19. Furthermore, it is also possible to embed information for changing parameters at appropriate timing and switching data path functions in the configuration information that is loaded into the control unit 60 of each PE 21 and controls the configuration of the hardware. . In this case, the configuration information also has a function as an activation code (activation code). In the above description, an example in which a source program is described in C language is described. However, a language suitable for describing another source program such as JAVA (registered trademark) can be used. It is. The application program that is the object of the present invention includes the entire software to be processed in a data processing device that can form a data path by connecting elements. This includes application programs that have been used, as well as debugging programs. Also, in the above description, the force S described in the example of a program for changing parameters is used, and the design and development of a program for debugging, including the process of reading and rewriting parameters reflecting the processing results of the data path, are also described. It is possible to apply the invention.

Industrial applicability

[0065] As described above, in the present invention, when determining a layout so that a data path that realizes a function of changing the processing content to a parameter is realized by connecting a plurality of elements. Then, access information indicating the address of the memory area where the confidential information of the processing element related to the parameter is stored is generated, and the source code is used to compile the source code to generate the activation code. This generation method is not limited to semiconductor integrated circuits including electric or electronic circuits, system LSIs, ASICs, FPGAs, etc. It can be applied to all data processing systems that can compose a data node by connecting different processing elements. Further, the present invention is also applied to a distributed data processing system in which a computing unit having an appropriate computer function such as a personal computer is connected as an element by a computer network to form a data node. It is possible to do.

Claims

The scope of the claims

[1] At least one circuit section in which at least one data node is formed by connecting a plurality of processing elements, and the configuration information is set in memory areas respectively corresponding to the processing elements. A method for generating an activation code for executing an application by a data processing device in which a function of a processing element is controlled, the method comprising:

A first step of generating source code to execute at least a portion of the application using a first function associated with a first parameter;

A computer outputs layout information for mapping a first data path for performing a process including the first function to the at least one circuit section, the layout information including connection information for the plurality of processing elements. A second step of generating access information enabling access to the memory area corresponding to the processing element related to the first parameter;

A generation method, comprising: a third step of generating the activation code by a computer using at least the source code including an instruction related to the first parameter and the access information as inputs.

[2] The data processing device has a control unit that controls the function of the processing element by setting the configuration information in the memory area.

2. The generation method according to claim 1, wherein the activation code is a program for executing the control unit.

[3] The first function includes a function in which processing is changed by the first parameter, and the access information includes a function in the memory area of the processing element in which processing is changed by the first parameter. Address,

2. The generation method according to claim 1, wherein the instruction includes an instruction to change the first parameter.

[4] The method according to claim 1, wherein the processing element physically includes the memory area.

[5] In the source code, the first function is described in an instance format, 2. The method according to claim 1, wherein in the second step, the access information that enables access to the memory area for each instance is generated using library information in which the first function is described in an object format. 3. Method.

[6] The at least one circuit section includes connection means for reconfiguring a data path by changing connections of the plurality of processing elements, and the source code includes an instruction for reconfiguring the data path. Yes,

In the second step, the layout information for reconfiguring the first data path and the access information enabling access to the memory area in the reconfigured first data path are stored. The method of claim 1, wherein the method comprises:

[7] The data processing device has means for reconfiguring a data path at an arbitrary position in the circuit section,

In the second step, the layout information for reconfiguring the first data path at an arbitrary location and the relative position of the memory area in the first data path reconfigured at an arbitrary location 7. The method according to claim 6, wherein the address information is generated.

[8] At least one circuit block in which at least one data node is formed by connecting a plurality of processing elements, and the configuration information is set in memory areas respectively corresponding to the processing elements. A program having a description for causing a computer to execute a layout process for outputting layout information in a data processing device in which a function of a processing element is controlled, and

In the layout process, a process including the first function is performed in response to a source code generated to execute at least a part of an application using a first function related to a first parameter. Generating the layout information including connection information of the plurality of processing elements to map a first data path to be performed to the at least one circuit section, and performing the processing related to the first parameter; A program for generating access information enabling access to the memory area corresponding to an element.

[9] The source code including an instruction related to the first parameter, and the access information 9. The program according to claim 8, further comprising a description for executing, on a computer, a process for generating an activation code for executing the application in the data processing device, using at least the above as an input.

[10] The first function includes a function whose processing is changed by the first parameter, and the access information includes an address of the memory area of the processing element whose processing is changed by the first parameter. Including

10. The program according to claim 9, wherein the instruction includes an instruction to change the first parameter.

[11] In the source code, the first function is described in an instance format.

9. The program according to claim 8, wherein in the layout processing, the access information that enables access to the memory area for each instance is generated using library information describing the first function in an object format.

[12] The at least one circuit section includes connection means for reconfiguring a data path by changing a connection of the plurality of processing elements, and the source code includes an instruction for reconfiguring a data path. Yes,

In the layout processing, the layout information for reconfiguring the first data path and the access information for enabling access to the memory area in the reconfigured first data path are generated. The program of claim 8.

[13] At least one circuit section in which at least one data node is formed by connecting a plurality of processing elements, and the configuration information is set in memory areas respectively corresponding to the processing elements. An apparatus for generating an activation code for executing an application by a data processing apparatus in which a function of a processing element is controlled, the apparatus comprising:

A first function that performs a process including the first function in accordance with a source code generated to execute at least a part of the application using a first function related to a first parameter; Layout information for mapping the data path of the plurality of processing elements to the at least one circuit section, the layout information including connection information of the plurality of processing elements, and the layout information corresponding to the processing element related to the first parameter. A layout method for generating access information enabling access to the memory area; Steps and

A generation device comprising: a source code including an instruction related to the first parameter; and a unit configured to generate the activation code by using at least the address information as input. The data processing device includes a control unit that controls the function of the processing element by setting the configuration information in the memory area.

14. The generator according to claim 13, wherein the activation code is a program for executing the control unit.