JPH05101141A - High-level composition device - Google Patents

Abstract

PURPOSE:To omit an extra control circuit of the input terminals of the computing element and registers of a logic circuit after composition. CONSTITUTION:This high-level composition device is equipped with a state division part 2 which divides operation, expressed by an operation function description inputted from an operation function description input part 1, by states, a variable analysis part 3 which finds a register needed in the respective states, a register list storage part 4 stored with the found registers, a merging rule library 6 which has the merging rule of the registers, a merging execution part 6 which merges the registers, and a composition part 7 which composes the logic circuit according to the merging result. Memory constitution is altered without rewriting a behavior arithmetic execution time or the overlap of a subroutine arithmetic execution time is checked to allocate hardware blocks required for a subroutine call.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-level synthesis apparatus for synthesizing a logic circuit whose behavior is represented by a behavioral function description or a behavioral description.

[0002]

2. Description of the Related Art In recent years, the scale of LSI has been increased, and accordingly, a logic synthesis system for automatically synthesizing logic circuits has been used in order to shorten the period of LSI design. When designing a logic circuit using a logic synthesis system, it is necessary to describe the behavior of the design target in a functional description language.

Conventionally, the function description language has been a register transfer level language. The register transfer level language describes the hardware configuration of registers to be designed, arithmetic units, etc., and the data flow and processing between the registers for each operation cycle (hereinafter referred to as clock cycle). To design a logic circuit using this language, specialized knowledge about hardware such as registers and arithmetic units is required.

Therefore, recently, development of a high-level synthesis apparatus by a high-level synthesis system for synthesizing a logic circuit from a behavioral function description (also referred to as a behavioral description) that describes only a behavior of a design object that does not require hardware expertise Has been done. In the behavioral function description, the behavioral specifications of the design target can be described algorithmically like a program without considering the hardware configuration.

In order to enable an algorithmically described operation to be executed by a logic circuit, a process of dividing the operation described above into an operation to be executed every clock cycle, that is, a state division Processing is required. The operation in one state is executed in one clock cycle, and a register is used to transfer operation data between different states.

In this high-level synthesis system, the process of dividing the operation of the design target represented by the behavioral function description is performed, and when the operation data is transferred between the states, the operation function description corresponding to the operation data is being performed. Allocate the variable to be operated on in the register.

In the conventional high-level synthesis apparatus, as a method of allocating variables to registers, the life times of the variables indicating whether the variables in the behavioral function description span a plurality of states are checked, and the variables whose life times do not overlap each other are examined. There is a method using graph theory in which registers are allocated by connecting each other with an edge and applying a clique division algorithm. Alternatively, there is a method using a left edge algorithm in which variables are sorted in ascending order of lifetime and variables whose lifetimes do not overlap in the sorted order are assigned to the same register one after another.

The former method is, for example, CJ Tseng.
and DP Siewiorek, "Automated Synthesis of Data P
aths in Digital Systems, "IEEE Transactions on Comp
uter-Aided Design, vol. CAD-5, pp. 379-395, July 19
There is a method listed in 86. The latter method is, for example, FJ Kurdahi and AC Parker, "REAL: A Progra.
m for Register Allocation, "in Proceeding of the 24
th ACM / IEEE Design Automation Conference, pp. 210-2
15, ACM / IEEE, June 1987.

The high-level synthesis system synthesizes a logic circuit on the basis of a register to which a variable is assigned by using such a technique. The technique is, for example, PG Pauli
n, JP Knight, and EF Girczyc, "HAL: A Multi-Par
adigm Approach to Automatic Data Path Synthesis, "i
n Proceeding of the 23rd ACM / IEEE design Automatio
n Conference, pp. 263-270, ACM / IEEE, July 1986.

However, in the above-mentioned method, since the variable is assigned to the register without considering the operation to which each variable belongs, an extra multiplexer is required for the input terminal of the arithmetic unit and the register, and the redundant logic circuit is required. Is synthesized.

For example, consider a case where a logic circuit is synthesized from a data flow after state division as shown in FIG. FIG. 19 shows a data flow after the operation represented by the operation function description is divided into states, and in this example, the operation is divided into states 1 to 3. FIG. 20 shows register allocation from this data flow using the left edge algorithm.

From this figure, it can be seen that the logic circuit to be synthesized requires four registers, for example, the register X1 in state 1 and the register Z1 in state 3 are shared. FIG. 21 shows a block diagram of a logic circuit synthesized based on this register allocation. In the logic circuit of FIG. 21, a large number of multiplexers 13 are required for the inputs of the register 11 and the arithmetic unit 12, and have a complicated circuit configuration.

On the other hand, in the conventional high-level synthesis apparatus, a memory corresponding to one-to-one is assigned to each array variable in the behavioral description and synthesis is performed. For example, each array variable aa [128], bb [12 in the behavior description of FIG.
8], a memory aa and a memory bb each having a data size of 128 are allocated.

In order to allocate one memory to these array variables aa and bb, it must be described as aabb [256]. As described above, it is very difficult to perform description using array variables in consideration of an optimal memory configuration in advance in behavioral description that does not consider parallel operation.

Therefore, in order to describe the array variable according to various memory configurations, the designer rewrites the part relating to the array variable in the behavior description each time, executes high-level synthesis, and performs the best trial and error. You have to choose one.

However, in the conventional method, it takes a lot of time and effort to rewrite the behavior description, and an error is apt to occur in the behavior description because the behavior description itself is rewritten. For this reason, it is necessary to perform verification of the behavior description again by simulation. May occur.

On the other hand, the behavioral description includes a plurality of subroutine calls and subroutines, and a method of assigning a hardware block to these is as follows.
There is a method of assigning different hardware blocks to the same subroutine call.

However, in this method, the circuit scale becomes large when the logic circuit is designed. this is,
This occurs because the description written hierarchically is made into a flat structure, and all the same subroutine calls are treated as different things.

For example, for two identical subroutines that are actually operating at times that do not overlap at all in terms of time,
Each gives two identical hardware blocks. Ideally, only one hardware block should be associated with a plurality of subroutine calls having such properties.

Therefore, a method of corresponding one hardware block to the same subroutine call can be considered. However, in this method, when the calculation times are overlapped, the parallel operation cannot be performed so much, and the circuit scale can be small, but the processing time cannot be satisfied.

Therefore, a method is conceivable in which the designer makes correspondence between these subroutine calls and the hardware. That is, the designer assigns one hardware block to the same subroutine call whose operation times do not overlap, and assigns different hardware blocks to the same subroutine call that overlaps.

However, the calculation time of the hardware block that executes the subroutine is not always constant,
It is a difficult task just to carry out a survey because it varies depending on the given data. Further, it is necessary to change the circuit part for controlling them, which results in a huge burden on the designer.

[0023]

As described above, in the conventional high-level synthesis apparatus, since the arithmetic operation to which each variable assigned to the register belongs is not taken into consideration, an extra multiplexer or the like is added to the input terminals of the arithmetic unit and the register. However, there is a problem in that redundant logic circuits are synthesized.

Further, in order to allocate various memories to the array variables in the behavioral description, the behavioral description must be rewritten, which causes a trouble and an error.

Further, in the conventional high-level synthesizer, a method of assigning different hardware blocks to a plurality of the same subroutine calls, a method of assigning one hardware block to the same subroutine calls, or a designer There was a method of allocating a hardware block by combining the above two methods by the intervention of.

However, these methods have the problems that the circuit scale becomes enormous, the processing time cannot be satisfied, and the burden on the designer increases.

The present invention eliminates the above-mentioned drawbacks of the prior art. The object of the first invention is to synthesize a logic circuit having a simple structure by eliminating the need for an extra control circuit after synthesis. It is to provide a high-level synthesizer capable of performing.

The object of the second invention is as follows.
It is an object of the present invention to provide a high-level synthesis apparatus capable of easily performing various high-level synthesis with a changed memory configuration without rewriting and without fail to obtain a high-quality high-level synthesis result.

Further, the object of the third invention is to examine the overlapping state of the operation time executed by the subroutines and allocate the necessary hardware blocks to each subroutine call, thereby enabling parallel operation and small operation. It is to provide a high-level synthesis device capable of synthesizing a large scale logic circuit.

[0030]

To achieve the above object, the high-level synthesis apparatus of the first invention is a state dividing means for dividing the operation of the logic circuit represented by the operation function description into states for each operation cycle. And a variable analysis means for analyzing a variable to be operated in the operation function description which is state-divided by the state division means and obtaining a register corresponding to the variable for each state, and the variable analysis means. And a merge execution means for allocating the register for each state so that the register is shared between different states.

The high-level synthesis apparatus according to the second aspect of the present invention is a command input means for inputting a command indicating how to allocate memory to the array variable in the behavior description, and a memory allocation command for analyzing how to allocate the input command. Analysis means, memory allocation command processing means for allocating memory for array variables according to the analyzed allocation method, and behavior description to RTL (register transfer level)
It is composed of RTL information generating means for generating information.

Further, the high-level synthesis apparatus of the third invention parses the behavioral description and parses a plurality of subroutine calls in the description to obtain an execution order relation, and a plurality of execution order relations from the obtained execution order relation. Call tree creating means for creating a tree-like hierarchical structure by the subroutine call, and operation time analyzing means for calculating the operation time of the subroutine corresponding to each subroutine call based on the execution order relationship and the hierarchical structure. A lifetime analysis means for analyzing the overlapping state of the calculation time of each subroutine, and the necessary number of hardware blocks for executing the subroutine are derived from the analyzed overlapping state of the calculation time, and the hardware block for each subroutine call. Hardware block allocation means for allocating To have.

[0033]

According to the first aspect of the present invention having the above-described structure, the register required for each state is obtained in the variable analyzing means based on the operation function description divided by the state dividing means. With reference to the merge rule considering the operation to which each variable belongs, the merge execution means executes register sharing. Then, the logic circuit is synthesized based on the shared register.

According to the second aspect of the invention, when a command indicating how to allocate the memory configuration of the synthesis circuit to the array variable in the behavior description is input, the memory allocation command analysis means analyzes it. The memory allocation command processing means allocates the memory for the array variable according to the input command, generates the RTL information, and synthesizes the logic circuit.

Furthermore, the third aspect of the invention analyzes the data and control flow from the input behavior description and creates a call tree for the subroutine. Also, the calculation time of the entire subroutine is analyzed for each subroutine. This is done bottom up using the call tree described above.

The lifetime of the subroutine (subroutine execution start time and end time) is analyzed from the obtained calculation time analysis result of the subroutine and the calculation time analysis result of other calculations. At this stage, the overlapping state of lifetimes is determined, and which subroutine is to be the same hardware block is determined.

When the behavior description includes a conditional loop or the like, the result of the lifetime analysis may be undefined. In this case, if the lifetime is treated as a variable and the same hardware block is used, , The hardware is automatically designed to wait for the execution of the subroutine until the processing by the conditional loop is completed.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

First Invention FIG. 1 shows a block diagram of an embodiment of the high-level synthesis apparatus of the first invention.

The operation function description input unit 1 inputs the operation function description into the state dividing unit 2.

The state division unit 2 divides the operation represented by the description input from the operation function description input unit 1 into the operations executed for each clock cycle. The variable analysis unit 3 analyzes a variable that is an operation target that needs to be passed between the states based on the operation function description that is divided by the state division unit 2, and obtains a register required in each state.

The register list storage unit 4 stores the registers obtained by the variable analysis unit 3.

The merge execution unit 5 merges the registers obtained by the variable analysis unit 3 based on the merge rule registered in the merge rule library 6.

The synthesizing unit 7 synthesizes a logic circuit using the merged result of register allocation.

Next, how to obtain the registers required in each state after the state division in the variable analysis unit 3 shown in FIG. 1 will be described.

FIG. 2 is a flow chart showing a processing procedure by the variable analysis unit 3.

First, analysis of variables in the first state is executed (step 101). As a result, the variable passed to the next state is registered in the register list storage unit 4 as a set of the variable name, the state number, and the operation to which the variable belongs (step 102). This operation is repeated for each state (steps 102 to 104).

This processing will be described using the data flow after state division shown in FIG.

For example, by analyzing the variables in the state 1 in which the addition operation is performed, the variables x1, x4, y
The edge corresponding to 1 crosses the boundary between state 1 and state 2. Therefore, it can be seen that these variables need to be passed to the next state 2. Perform similar analysis across states.

The registers required for each state obtained as a result are shown in FIG. The figure shows that, for example, state 1 requires registers (thick lines in the figure) corresponding to variables x1, x2, x3, and x4.

Next, a method of merging registers in the merge execution unit 5 shown in FIG. 1 will be described. A flow chart of merging is shown in FIG.

When merging, the merge rule library 6
The merge is executed by referring to the merge rule registered in. The merge rules are shown below in order of priority for rule application.

Merge Rule 1. The registers corresponding to the input variables of the same kind of operation are merged.

Merge Rule 2. The registers corresponding to the output variables of the same type of operation are merged.

Merge Rule 3. Merge registers corresponding to input variables of different operations.

Merge Rule 4. Merge the registers corresponding to the output variables of different operations.

Merge Rule 5. The registers corresponding to the input variables and output variables of the same kind of operation are merged.

Merge Rule 6. Merge the registers corresponding to the same variable.

The data flow merging method shown in FIG. 19 will be described below with reference to FIG. 4 and the merging rule.

First, by applying the merge rule 1,
Since the register x2 corresponding to the input variable x2 of the operation to be executed by one adder belongs to the state 1 and x1 belongs to the state 2, these two registers x1 and x2 can be merged (steps 201 to 203). .. As a result,
Registers x1 and x2 are merged (step 20)
4).

Similarly, since the register x3 belonging to the state 1 and the register y1 belonging to the state 2 can be merged by the merge rule 1, they are merged (step 201).
~ 204).

Next, before applying the merge rule 2, since the same variable y1 appears in the state 2, the input variable y1 to the multiplication not involved in the merge operation of the registers x3 and y1 is registered in the register list. It is deleted from the storage unit 4. Then, the registers corresponding to the output variables y1 and z1 are merged (steps 205 and 206).

Further, by applying the merge rules 5 and 6, the result of register allocation shown in FIG. 5 can be obtained.
As can be seen from FIG. 5, the register x2 used in the state 1 and the register x1 used in the state 2 are shared. Other registers are similarly shared.

When the synthesizing unit 7 synthesizes the logic circuit based on the merged result, the result is as shown in FIG. Compared to the conventional logic circuit of FIG. 21, the number of fan-outs is 1, the number of fan-ins is 1, and the number of multiplexers 13 is decreased by 1.

Second Invention FIG. 7 shows the configuration of a high-level synthesis apparatus according to the second invention.
In the following, for simplification, all the memories have a single port (data of different addresses cannot be read / written at the same time).

When the behavior description and the memory allocation command are input from the input / output device 21, the behavior description analysis unit 22 analyzes the behavior description, converts it into a data flow expression, and stores it in the design information storage unit 28.

FIG. 8 shows an example of description of the behavior description, and FIG. 9 shows an example of data flow expression corresponding to the behavior description of FIG. In these figures, the array variables of the data size 128 are aa and bb, and 3 is input to the i-th of aa and 5 is input to the i-th of bb.

Next, the memory allocation command analysis unit 23
Analyzes the memory allocation command and activates the memory allocation command processing unit 24. The memory allocation command processing unit 24 corrects the data flow expression stored in the design information storage unit 28 according to the memory allocation command analysis result.

FIG. 10 shows the memory allocation command processing unit 2
4 shows a processing flow of No. 4.

When the designer inputs a memory allocation command as shown in FIG. 11A to the behavior description shown in FIG. 8, the memory allocation command analysis unit 23 changes the command type to acat or change. First name 1
As a, name as before 2 as bb, name after as a
256 is analyzed as the abb and the changed size, and the memory allocation command processing unit 24 is activated.

The memory allocation command processing unit 24 is shown in FIG.
The process proceeds according to the process flow shown in 0. First, the name before change 1 aa, the name before change 2 bb, the name after change aab
b, the changed size 256 is obtained (step 301).
The command type is acat (step 30
2), aa in the data flow expression is replaced with aabb (step 303), and bb is 256/2 = 1 as an address
Add 28 and replace with aabb (step 30
4). As a result, the data flow expression shown in FIG. 11B is corrected. That is, aa data is set in the first half, and bb data is set in the second half.

When a memory allocation command as shown in FIG. 12 (a) is input, the memory allocation command analysis unit 23 determines that the command type is "age,"
The name before change 1 is analyzed as aa, the name before change 2 is bb, the name after change is aabb, and the size after change is 256, and the memory allocation command processing unit 24 is activated.

The memory allocation command processing unit 24 uses the name before change 1 aa, the name before change 2 bb, and the name after change aab.
b, size 256 is obtained after the change (step 30
1). Since the type of command is "age" (step 302), the address of aa in the data flow expression is left-shifted by 1 bit and then replaced with aabb (step 305). Further, after shifting the address of bb left by 1 bit, 1 is added and replaced with aabb (step 306). As a result, the data flow expression shown in FIG. 12B is corrected. By this processing, aa, bb
The data of 1 are alternately set.

The second invention can process not only these two commands but also any other commands.

In this way, after the memory is allocated, the scheduling processing unit 25 applies the data flow expression stored in the design information storage unit 28 to the operation of each state (clock cycle) as "different addresses of the same memory. Data cannot be read or written at the same time. "

In the data flow expression stored in the design information storage unit 28, the allocation processing unit 26 allocates registers to variables that need to be held across states so that the number is as small as possible, and the arithmetic operator is assigned. On the other hand, arithmetic units are assigned so that the data transfer path is as simple as possible.

Further, the RTL information generator 27 converts this result into a register transfer level language, stores it in the design information memory 28, and outputs it to the input / output device 21. As described above, the memory allocation for the array variable is realized according to the memory allocation command.

In this embodiment, one memory is allocated to two array variables, but the present invention is not limited to this. For example, what is defined as one array variable having a large data size can be divided and allocated to a plurality of memories having a small data size.

Further, when there are a plurality of array variables, the second invention is applied only to a part of the array, and for the remaining arrays, various combinations of memory allocation by the conventional method are repeatedly executed, and the best result is obtained. It is also possible to automatically select the one that has become.

Third Invention FIG. 13 is a block diagram showing the configuration of an embodiment of the high-level synthesis apparatus of the third invention.

The input behavior description 31 is analyzed by the syntax analysis unit 32 and then converted into connection data 33 representing the relationship of execution order of subroutine calls. The call tree creation unit 34 creates a call tree for the subroutine from this connection data 33.

The calculation time analysis section 35 analyzes the calculation time of the subroutine in a bottom-up manner with reference to this call tree. At this time, there is a case where the calculation time of the subroutine is indefinite. In that case, a variable is assigned and execution is continued.

Next, the subroutine lifetime analysis unit 36 analyzes the lifetime of each subroutine with reference to the calculated operation time. Based on the analysis result of the lifetime, the hardware block allocation unit 37 creates the required number of hardware blocks and the correspondence table of the subroutine calls allocated to these hardware blocks, that is, the hardware configuration 38.

FIG. 14 is an example of a behavioral description which is an input. The syntax analysis unit 32, which has received the behavior description 31, creates connection data 33. An example of the created connection data 33 is shown in FIG.

FIG. 15A shows the connection data 33 of the function called main. In this figure, the subroutines sub1 and sub3 are called in the function called main, and there is no restriction on the execution order of both.

On the other hand, FIG. 15B shows the connection data 33 of the sub1 subroutine. This is s
Sub routines sub2 and sub3 are called in the sub routine ub1, and the execution order of both indicates that the execution of sub2 must be completed first.

This connection data 33 is input to the call tree creating section 34, and a call tree is created.
This example is shown in FIG. The call tree does not represent the order of execution, only the hierarchical structure of the subroutines. In this example, sub1, in the function called main
The sub3 subroutine is called, and the sub2 and sub3 subroutines are called in the sub1 subroutine.

These call tree and connection data 33
The calculation time analysis unit 35 operates by inputting, and the calculation time of each subroutine is calculated. This computation is performed bottom-up through the call tree. According to the example,
First, the calculation time of sub2 is calculated. Since the subroutine is not called in sub2, the operation time can be calculated from the connection data 33.

Similarly, the calculation time of sub3 is calculated. Since the calculation time of the subroutine used in sub1 is now known, the calculation time of sub1 can be calculated.

The subroutine life tie analysis unit 36 analyzes each lifetime by using the result calculated in this way. The result obtained is FIG. The call tree is entered at the top for reference. For example, the lifetime of sub1 is t2 to t8.

Finally, from this result, the hardware block allocation unit 37 derives and allocates the required number of hardware blocks to each subroutine. In this example, two subroutine calls of sub3 are used, but it can be seen that there is no overlap in the lifetime of both. Therefore, it is concluded that these two subroutine calls can be executed by the same hardware block, and the logic circuit is configured to have the hardware configuration as shown in FIG.

If, in FIG. 17, the calculation times of two sub3s overlap, two hardware blocks will be allocated to sub3s.

In this example, the lifetimes of the subroutines can be determined and there is no overlap, but there are some descriptions in which the calculation of the calculation time is impossible. For example, a conditional loop is given as an example. This is because it is statically difficult to find out how many times to loop until the condition is met.

In such a case, a variable is assigned as the lifetime. In consideration of this variable time, the hardware block allocating unit 37 allocates hardware blocks to subroutines in which duplication is unlikely to occur. However, since there is no guarantee that they will not completely overlap, a control circuit for checking whether or not the processing by the conditional loop is completed is newly added to avoid this.

That is, to the hardware block assigned to the subroutine to be executed later, a control circuit for waiting until the processing by the conditional loop executed before is completed is added. This allows the circuit to be configured to avoid the use of the same hardware block at the same time.

[0096]

As described above, according to the high-level synthesis apparatus of the first aspect of the invention, the registers required for each state in the state-divided behavioral function description are obtained, and merged in consideration of the operation to which the variable belongs. Registers are merged according to the rules to synthesize logic circuits. As a result, there is no extra multiplexer at the input terminals of the arithmetic unit and the register, and a logic circuit having a simple structure can be obtained.

Further, according to the high-level synthesis apparatus of the second invention, various high-level synthesis in which the memory configuration is changed can be easily performed without rewriting the behavior description, and the best one is selected from these. This makes it possible to obtain high-quality high-level synthesis results.

Furthermore, according to the high-level synthesis apparatus of the third aspect of the present invention, the overlap of the calculation times of the subroutines is analyzed and the hardware blocks are allocated, so that parallel operation is possible and a small-scale logic circuit can be synthesized. Moreover, the burden on the designer can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a high-level synthesis apparatus according to the first invention.

FIG. 2 is a flowchart showing a processing procedure by a variable analysis unit shown in FIG.

FIG. 3 is a diagram showing a relationship between registers and states obtained by a variable analysis unit.

FIG. 4 is a flowchart showing a merging processing procedure by a merge execution unit shown in FIG. 1.

FIG. 5 is a diagram showing a result of register allocation finally obtained by a merge execution unit.

FIG. 6 is a block diagram of a logic circuit synthesized according to the first invention.

FIG. 7 is a block diagram showing a configuration of an embodiment of a high-level synthesis apparatus according to the second invention.

FIG. 8 is a descriptive diagram showing an example of a behavior description used in an example of the second invention.

9 is a data flow expression corresponding to the behavior description shown in FIG.

10 is a flowchart showing processing of a memory allocation command processing unit shown in FIG.

FIG. 11 is a diagram showing a memory allocation command and a memory allocation processing result used in the embodiment of the second invention.

FIG. 12 is a diagram showing a memory allocation command different from FIG. 11 and a memory allocation processing result.

FIG. 13 is a block diagram showing the configuration of an embodiment of a high-level synthesis apparatus according to the third invention.

FIG. 14 is an example of a behavior description used in the embodiment of the third invention.

15 is connection data created from the behavior description in FIG.

16 is a call tree created from the behavior description in FIG.

17 is a subroutine lifetime analyzed from the connection data of FIG. 15 and the call tree of FIG.

FIG. 18 is a hardware configuration diagram assigned from the subroutine lifetime of FIG. 17;

FIG. 19 is a data flow diagram showing an example of a data flow after state division used in the first invention.

FIG. 20 is a diagram showing an allocation result by a conventional register allocation method for the first invention.

FIG. 21 is a block diagram of a logic circuit synthesized by a conventional high-level synthesis device for the first invention.

[Explanation of symbols]

 1 operation function description input unit 2 state division unit 3 variable analysis unit 4 register list storage unit 5 merge execution unit 6 merge rule library 7 synthesis unit 21 input / output device 22 behavior description analysis unit 23 memory allocation command analysis unit 24 memory allocation command Processing unit 25 Scheduling processing unit 26 Allocation processing unit 27 RTL information generation unit 28 Design information storage unit 31 Behavior description 32 Syntax analysis unit 33 Connection data 34 Call tree creation unit 35 Arithmetic time analysis unit 36 Subroutine lifetime analysis unit 37 Hardware block Assignment unit 38 Hardware configuration

Claims (3)

[Claims] 1. A state dividing means for dividing an operation of a logic circuit represented by an operation function description into states for each operation cycle, and an operation target in the operation function description divided by the state dividing means. A variable analysis means for analyzing a variable and obtaining a register corresponding to the variable for each state, and a merge for allocating the register for each state obtained by the variable analysis means so as to be shared between different states A high-level synthesis apparatus having an executing means. 2. A command input means for inputting a command indicating a memory allocation method for an array variable in a behavior description, a memory allocation command analysis means for analyzing an allocation method of an input command, and an analyzed allocation method. A high-level synthesis apparatus comprising: a memory allocation command processing means for allocating a memory to an array variable in accordance therewith; and a register transfer level information generating means for generating register transfer level information from a behavior description. 3. A syntax-analyzing unit that parses a behavioral description and obtains an execution order relationship of a plurality of subroutine calls in the description, and a tree-like hierarchical structure of the plurality of subroutine calls from the obtained execution order relationship. A call tree creating means for creating, an operation time analyzing means for calculating an operation time of a subroutine corresponding to each subroutine call based on the execution order relation and the hierarchical structure, and an overlap state of the operation times of the calculated subroutines is analyzed. Deriving the required number of hardware blocks that execute the subroutine from the lifetime analysis means and the overlapped state of the analyzed operation time,
A high-level synthesis apparatus having a hardware block allocating means for allocating a hardware block to each subroutine call.