WO2004077553A1

WO2004077553A1 - Relaxation of a thin layer at a high temperature after its transfer

Info

Publication number: WO2004077553A1
Application number: PCT/IB2004/000931
Authority: WO
Inventors: Bruno Ghyselen; Carlos Mazure; Emmanuel Arene
Original assignee: S.O.I.Tec Silicon On Insulator Technologies
Priority date: 2003-02-28
Filing date: 2004-03-01
Publication date: 2004-09-10
Also published as: FR2851848B1; FR2851848A1; EP1597759A1; JP2006519489A

Abstract

The invention relates to a method for forming a relaxed or pseudo-relaxed layer on a substrate, the relaxed layer being in a material selected from among semiconductor materials, comprising the following steps: a) growing on a donor substrate (1) an elastically strained layer (2) constituted by at least a material chosen from among the semiconductor materials; b) forming on the strained layer (2), or on a receiver substrate (7), a vitreous layer (4) made of a material which is viscous above a viscosity temperature of more than about 900°C; c) bonding the receiver substrate (7) to the strained layer (2) by means of the vitreous layer (4) formed in step (b); d) removing the donor substrate (1), so as to form a structure (20) comprising the receiver substrate, the vitreous layer (4) and the strained layer (2); e) thermal treating the structure at a temperature close to or above the viscosity temperature, so as to relax at least a part of the constraints in the strained layer (2).

Description

RELAXATION OF A THIN LAYER AT A HIGH TEMPERATURE AFTER ITS TRANSFER

Field of the invention The present invention relates to the formation of a relaxed or pseudo-relaxed layer on a substrate, the relaxed layer being in a material selected from among semiconductor materials, in order to form a final structure intended for electronics, optics or Optronics such as for example a semiconductor-on-insulator structure. The present invention comprises in particular the formation of a layer strained on and by the relaxed layer.

For example, a Si layer strained by a relaxed or pseudo-relaxed SiGe layer may in this respect achieve advantageous properties such as charge carrier mobility about 100% more significant than that present within a relaxed Si layer.

We consider here that a layer is "relaxed" if the crystalline material of which it is composed has a mesh parameter approximately identical to its nominal mesh parameter, in other words to the mesh parameter of the material in its bulk form in equilibrium. Conversely, the term "strained" is applied to any layer of crystalline material whose crystalline structure is elastically strained in tension or in compression during crystal growth, such as epitaxy, forcing its mesh parameter to be appreciably different from the nominal mesh parameter of this material.

Background of the invention

The technique is known of forming a relaxed layer on a substrate, particularly by implementing a method comprising the following steps;

(1) epitaxy of a thin layer of semiconductor material on a donor substrate; (2) bonding a receiver substrate on the thin layer;

(3) removing the donor substrate.

A semiconductor-on-insulator structure can be made in this way, in which the semiconductor thickness is constituted at least partly by said thin relaxed layer and the insulating layer being usually formed during a step intermediate to step (1) and to step (2).

Relaxation of the thin layer may be obtained:

• when implementing step (1); or

• during a subsequent treatment. In the first case, a known technique is the use of a donor substrate constituted by a carrier substrate and a buffer layer, the buffer layer containing plastic deformations so that the over-epitaxied thin layer is relaxed of all strain. Such processes are for example described in the documents US 2002/0072130 and WO 99/53539. However, a buffer layer is often long and costly to obtain.

In the second case, the donor substrate does not include a buffer layer and the step (1) then consists in growing the thin layer in such a way that it is strained by the donor substrate.

In this way, for example, a SiGe layer will be grown directly ^'on a Si substrate, to a thickness such that the SiGe layer is strained overall.

A first technique of relaxing the SiGe layer, described particularly in the document by B. Hollander et al. entitled "Strain relaxation of pseudomorphic Siι_-xGe_x/Si(100) heterostructures after hydrogen or helium ion implantation for virtual substrate fabrication" (in Nuclear and Instruments and Methods in Physics Research B 175-177 (2001) 357- 367) consists in relaxing the SiGe layer, prior to the implementation of step (2), by implanting hydrogen or helium ions in the Si substrate at a set depth.

However, relaxation rates usually obtained by this first technique remain quite low relative to other techniques. Research into a second technique is notably disclosed in the document entitled "Compliant Substrates: A comparative study of the relaxation mechanisms of strained films bonded to high and low viscosity" by Hobart et al. (Journal of electronic materials, vol 29, No 7, 2000). After removing the donor substrate at step (3), thermal treatment is applied to relax or pseudo-relax a strained SiGe layer bonded at step (2) to a borophosphoro silicate glass (BPSG).

During the thermal treatment, the strained layer thus seems to relax by means of the layer of glass turned viscous at the treatment temperature.

One advantage of this technique would be to use a layer of BPSG with a fairly low viscosity temperature TG (of the order of 625°C).

However, for thermal treatments applied subsequent to the relaxation thermal treatment and at temperatures above TQ, the viscosity of the BPSG layer obtained at these temperatures may have undesired effects, particularly on the structure of the treated wafer.

Thus, for example, if transistors are made in the relaxed or pseudo- relaxed SiGe layer or in a strained Si layer epitaxied on the relaxed or pseudo-relaxed SiGe layer, at a temperature above TQ, some of the strains may relax by means of the layer of glass turned viscous, removing strains from the Si layer and adding strains in the SiGe layer.

Which is contrary to the purpose being sought here which is to retain the SiGe layer relaxations so as to strain the Si layer as far possible.

Brief description of the invention

The present invention attempts to overcome this difficulty by proposing a method for forming a relaxed or pseudo-relaxed layer on a substrate, the relaxed layer being in a material selected from among semiconductor materials, comprising the following steps: a) growing on a donor substrate an elastically strained layer constituted by at least a material chosen from among semiconductor materials; b) forming on the strained layer, or on a receiver substrate, a vitreous layer made of a material which is viscous above a viscosity temperature of more than about 900°C; c) bonding a receiver substrate to the strained layer via the vitreous layer formed in step (b); d) removing the donor substrate, so as to form a structure comprising the receiver substrate, the vitreous layer and the strained layer; e) thermal treating the structure at a temperature close to or higher than the viscosity temperature, so as to relax at least a part of the elastic constraints in the strained layer. Other characteristics of the method for forming a relaxed or pseudo-relaxed layer on a substrate are:

- the method further comprises a final step of crystal growth, on the structure, of a material chosen from among semiconductor materials, is implemented; - the step (b) comprises the two sequential operations: b1) growing a layer of semiconductor material on the strained layer; b2) applying controlled treatment to convert at least part of the layer formed in step (b1), into a material which is viscous above the viscosity temperature, thus forming the vitreous layer; - the method further comprises, prior to step (c), a formation of a bonding layer on at least one of the two bonding surfaces;

- the bonding layer is of SiO₂;

- the removal of substance at step (d) is essentially carried out by detachment at the level of an embrittlement zone present in the donor substrate, at a depth close to the thickness of the surface layer, by input of energy; - the method further comprises, prior to step (c), the formation of the embrittlement zone by implantation of atom species in the donor substrate;

- the method further comprises, prior to step (a), a step of formation of the donor substrate comprising the following operations:

• forming a porous layer on a crystalline carrier substrate;

• growing a crystalline layer on the porous layer; the carrier substrate -porous layer -crystalline layer assembly constituting the donor substrate, the porous layer constituting the embrittlement zone of the donor substrate;

- the removal of substance in step (d) comprises selective chemical etching;

- the vitreous layer formed in step (b) is electrically insulating;

- the vitreous layer formed in step (b) is of Siθ₂; - the donor substrate is of Si; and the strained layer is of Siι-_xGe_x

- the donor substrate comprises a Si bulk holding substrate (1-1 ) and a buffer structure (1-2, 1-3) adapting the lattice parameter from Si to

- the strained layer comprises a Si strained layer (2-1) and a S . _xGe_x strained layer (2-2) with x > z;

- the layer grown at step (b1 ) is in Si and the controlled treatment applied during step (b2) is a controlled thermal oxidization treatment for transforming at least a portion of the Si of the layer formed during step (b1 ) into Si0₂, thereby forming the SiO₂ vitreous layer; - step (e) comprises thermal treatment above about 900°C;

- the vitreous layer formed at step (b) is electrically insulating and the structure formed is therefore a semiconductor-on-insulator structure, the semiconductor thickness of which comprises the strained layer which has been relaxed or pseudo-relaxed in step (e); - steps of preparing for the manufacturing of components and/or steps of manufacturing components in the strained layer or in a possibly over-epitaxied layer.

Brief description of the drawings

Other aspects, purposes and advantages of the present invention will emerge more clearly from reading the following detailed description of the implementation of its preferred methods, given by way of example non-restrictively and with reference to the appended drawings in which: Figures 1a to 1 i show the different steps in a first method according to the invention.

Figures 2a to 2i show the different steps in a second method according to the invention.

Figure 3 shows an example of a source wafer, with layers to be transferred grown on a buffer structure in SiGe.

Detailed description of the invention

A first objective of the present invention consists in forming a useful relaxed or pseudo-relaxed layer on a substrate. A "useful layer" according to the invention is a layer intended to receive components for electronics, optics, or Optronics during treatments subsequent to the implementation of the method according to the invention.

A second objective of the present invention consists in forming on the relaxed or pseudo-relaxed layer a useful layer of strained material.

A third objective of the present invention is to make it possible to retain an at least relative relaxation strength of an initially strained layer, during high temperature thermal treatments.

It is in particular to be able to retain the at least relative relaxation strength of a layer of Siι_-XG_X adjacent to a vitreous layer up to a temperature of somewhere between about 900°C and about 1200°C or even at a higher temperature.

Thermal treatments of this kind may be applied during epitaxial growth on the relaxed Siι_-XG_X layer, or during other processes, such as for example the making of components in the Siι_-xGe_x layer and/or in an over- epitaxied layer, such as a strained Si layer.

The method according to the invention comprises the three main steps (1), (2) and (3) previously mentioned.

With reference to figures 1a to 1 i a preferred method according to the invention is described.

With reference to figure 1a a source wafer in accordance with the invention is shown.

The wafer 10 is constituted by a donor substrate 1 and a strained Siι_-xGe_x layer 2. In a first configuration of the donor substrate 1 , the latter is constituted entirely by monocrystalline Si which has the first mesh parameter.

This donor substrate 1 is then to advantage obtained by Czochralski growth. In a second configuration of the donor substrate 1 , the latter is a pseudo-substrate comprising an upper Si layer (not shown in figure 1), having an interface with the strained layer 2 and having a first mesh parameter at its interface with the strained layer 2.

The first mesh parameter of the upper layer is to advantage the nominal mesh parameter of Si, so that it is in a relaxed state.

The upper layer has additionally a sufficiently large thickness to be able to impose its mesh parameter on the overlying strained layer 2, without the latter significantly influencing the crystalline structure of the upper layer of the donor substrate 1. Whatever configuration is chosen for the donor substrate 1, the latter has a crystalline structure with a low density of structural defects, such as dislocations.

Preferably, the strained layer 2 is constituted only by a single thickness of Si-i_-xGe_x.

The concentration of Ge in this strained layer 2 is preferentially above 17%, i.e. a value of x above 0.17.

Since Ge has a mesh parameter about 4.2% higher than Si, the material selected to constitute this strained layer 2 thus has a second nominal mesh parameter which is appreciably higher than the first mesh parameter.

The strained layer 2 formed is then strained elastically in compression by the donor substrate 1 , in other words it is strained from having a mesh parameter appreciably lower than the second nominal mesh parameter of the material of which it is composed, and therefore from having a mesh parameter close to the first mesh parameter.

The strained layer 2 has moreover preferentially an approximately constant atomic element composition.

The strained layer 2 is to advantage formed on the donor substrate 1 by crystal growth, such as epitaxy, using known techniques such as for example LPD, Chemical Vapour Deposition (CVD) and Molecular Beam Epitaxy (MBE).

To obtain such a strained layer 2 without too many crystallographic defects, such as for example point defects or extensive defects such as dislocations, it is advantageous to choose crystalline materials constituting the donor substrate 1 and the strained layer 2 (in the vicinity of its interface with the carrier substrate 1) such that they have a sufficiently small difference between their first and their second respective nominal mesh parameters. For example, this difference in mesh parameter is typically between about 0.5% and about 1.5%, but can also have more significant values. For example, Siι-_xGe_x with x = 0.3 has a nominal mesh parameter, about 1.15% higher than that of Si.

On the other hand, it is preferable for the strained layer 2 to be of approximately constant thickness, so that it presents approximately constant intrinsic properties and/or to facilitate the future bonding with the receiver substrate 5 (as shown in figure 1 e).

To avoid relaxation of the strained layer 2 or an appearance of internal plastic deformations, its thickness must additionally remain below a critical elastic strain thickness. This critical elastic strain thickness depends mainly on the material selected for the strained layer 2 and on said mesh parameter difference with the donor substrate 1.

But it also depends on growth parameters such as the temperature at which it has been formed, on the nucleation sites from which it has been epitaxied or on the growth techniques employed (for example CVD or MBE).

For the critical thickness values for Siι__xGe_x layers, reference may be made in particular to the document entitled "High mobility Si and Ge structures" by Friedrich Schaffler ("Semiconductor Science Technology" 12 (1997) 1515-1549).

For the other materials, the man skilled in the art will refer to the prior art to learn the value of the critical elastic strain thickness of the material which he selects for the strained layer 2 formed on the donor substrate 1. Thus for a layer of Siι_-xGe_x where x is between 0.10 and 0.30 a typical thickness of between about 200A and 2000A will be chosen, preferentially between 200A and 500A adapting particularly the growth parameters.

Once formed, the strained layer 2 therefore has a mesh parameter approximately in the vicinity of that of its growth substrate 1 and has internal elastic strains in compression. With reference to figure 1c, on the strained layer 2 or on the receiver substrate 7 a vitreous layer 4 is formed.

The material constituting the vitreous layer 4 is such that it becomes viscous above a viscosity temperature TG. In the framework of this method according to the invention, a material is chosen for the composition of this vitreous layer 4, which has a high T_G temperature, of about 900°C minimum.

This high viscosity temperature will make it possible to prevent the vitreous layer 4 from becoming viscous during high temperature thermal treatments, and in this way to prevent particularly the structure 30 or 40 (with reference to figures 1 h and 1 i) formed at method end to have a part of its crystallographic structure modified with this vitreous layer 4 turned viscous.

A single thermal treatment at a temperature around or above TQ will however be applied during the method according to the invention (with reference to figure 1 h) so as to relax the strained layer 2.

And it is particularly to be able to retain the at least relative relaxation strength (which will be obtained during a step with reference to figure 1 h) of the Siι_-xGe_x layer up to a temperature of somewhere around 900°C or even at a higher temperature.

The material of the vitreous layer 4 can be one of the following materials: SiO₂, SiO_xN_y.

When a vitreous layer 4 of SiO_xN_y is formed, it is possible to advantage to play on the value of y in order to change the viscosity temperature T_G which, for this material, depends substantially on the composition of the nitrogen.

Thus when the y composition increases it is possible for the T_G of the vitreous layer to be changed typically between a T_G of roughly that of SiO₂ (which may vary around 1150°C) and a T_G of roughly that of Si₃N (which is above 1500°C).

By playing on y, it is thus possible to cover a wide range of TG. The TQ values of the vitreous layer 4, if they depend essentially on the material of the vitreous layer, may also fluctuate depending on the conditions in which it has been formed.

In one possible scenario, it will thus be possible to adapt the conditions of formation of the vitreous layer 4 in a controlled way so as to select a TQ "a la carte".

It is thus possible to play on the deposition parameters, such as the temperature, the time, the proportioning, the gaseous atmosphere potential, etc. Doping elements may thus be added to the principal gaseous elements contained in the vitrification atmosphere, such as boron and phosphorus which may have the capacity to reduce the T_G.

It is preferable for the vitreous layer 4 to be deposited before the germanium contained in the strained layer 2 can diffuse into the atmosphere, or even into the receiver substrate 7, particularly when the assembly is subjected to high temperature thermal treatment, such as

RTA annealing treatment, or a sacrificial oxidation treatment.

In a preferred embodiment of the vitreous layer 4, the following steps are implemented: (b1 ) with reference to figure 1 b, growing a layer 3 of semiconductor material on the strained layer 2; then

(b2) with reference to figure 1c, applying a controlled treatment to convert at least part of the layer formed in step (b1) into a material which is viscous above the viscosity temperature, thus forming the vitreous layer 4.

The material chosen for the layer 3 is to advantage Si so as not to modify the strain in the strained layer 2.

The thickness of the formed layer 3 is typically between 5A and about 5000A, more particularly between 10θA and about 1000A. For the same reasons as those set out above, the crystal growth at step (b1 ) of the layer 3 is preferentially implemented before diffusion of the Ge, in other words shortly after:

• the formation of the strained layer 2 if the temperature for forming the strained layer 2 is maintained;

• a rise in temperature subsequent to a drop to ambient temperature obtained immediately after the formation of the strained layer 2.

The preferential method for growing the layer 3 is a growth in situ directly in continuation of the growth of the strained layer 2.

The growth technique used at step (b1) may be an epitaxy technique LPD, CVD, or MBE.

The vitreous layer 4 may be obtained by thermal treatment in an atmosphere with a preset composition. Thus a Si layer 3 may be subject at step (b2) to a controlled thermal oxidation treatment in order to convert this layer 3 into a vitreous layer 4 of Si0₂.

During this final step, it is important to correctly proportion the oxidising treatment parameters (such as the temperature, duration, oxygen concentration, the other gases of the oxidising atmosphere, etc) in order to control the thickness of oxide formed, and to stop oxidation in the vicinity of the interface between the two layers 2 and 3.

For such thermal oxidation, a dry oxygen or water vapour atmosphere will preferably be used, at a pressure equal to or above 1 atm.

It will then be preferable to play on the duration of oxidation in order to control the oxidation of the layer 3.

However, this control may be achieved by playing on one or more other parameters, in combination or not with the time parameter. Reference may be made particularly to the document US 6 352 942 for more detail about this embodiment of such a vitreous SiO₂ layer 4 on a SiGe layer.

According to another embodiment of the vitreous layer 4, and in replacement of said two steps (b1 ) and (b2) referenced by figures 1b and 1c respectively, there is applied, immediately after the growth of the strained layer 2 (in order to prevent the diffusion of the Ge), a deposition of atom species constituted by the vitreous material using atom species deposition means. Thus, it is possible for example to deposit molecules of SiO₂ on the strained layer 2 so as to form the vitreous SiO₂ layer 4.

In an embodiment of the vitreous layer 4 alternative to the previous one, it is possible:

• to deposit firstly amorphous Si atom species so as to form an amorphous Si layer on the strained SiO₂ layer; then:

• to oxidise thermally this amorphous Si layer and thus to make a vitreous SiO₂ layer 4.

With reference to figures 1d, 1e and 1f, steps are shown of lifting the strained layer 2 and the vitreous layer 4 from the donor substrate 1 so as to transfer them to a receiver substrate 7.

To this end, the method according to the invention implements a technique composed of two main sequential steps:

• bonding the receiver substrate 7 with the donor substrate 1- strained layer 2-vitreous layer 4 assembly, at the level of the vitreous layer 4;

• removing the donor substrate 1.

With reference to figure 1e, the receiver substrate 7 is bonded to the vitreous layer 4.

Prior to bonding, an optional step of forming a bonding layer on the surface of the receiver substrate 7 may be implemented, this bonding layer having binding properties, at ambient temperature or at higher temperatures, with the material of the vitreous layer 4.

Thus, for example, forming a layer of Si0₂ on the receiver substrate 7 may improve the quality of bonding, particularly if the vitreous layer 4 is SiO₂.

This bonding layer of Si0₂ is then obtained to advantage by deposition of atom species of Si0₂ or by thermal oxidation of the surface of the receiver substrate 7 if its surface is Si.

A bonding surface preparation step is to advantage applied, prior to the bonding, in order to render these surfaces as smooth and as clean as possible.

Adapted chemical treatments for cleaning the bonding surfaces may be applied, such as light chemical etching, RCA treatment, ozonised baths, flushing operations, etc. Mechanical or mecano-chemical treatments may also be applied, such as polishing, abrasion, Chemical Mechanical Planarisation (CMP) or atom species bombardment.

Bonding as such is achieved by bringing the bonding surfaces into contact with each other. The bonds are preferentially molecular in nature making use of the hydrophilic properties of the bonding surfaces.

To assign or enhance the hydrophilic properties of the bonding surfaces, the two structures to be bonded may previously be subject to immersion operations in baths, such as for example flushing in deionised water.

The bonded assembly may additionally be annealed in order to reinforce the bonds, for example modifying the nature of the bonds, such as covalent bonds or other bonds.

Thus, where the vitreous layer 4 is of SiO₂, annealing may enhance the bonds, particularly if a bonding layer of SiO₂ has been formed prior to bonding on the receiver substrate 7. For more detail regarding bonding techniques reference may be made particularly to the document entitled "Semiconductor Wafer Bonding" (Science and technology, Interscience Technology) by Q. Y. Tong, U. Gδsele and Wiley. Once the assembly is bonded, material is preferably removed in accordance with the invention, consisting in detaching the donor substrate 1 at the level of an embrittlement zone 6 present in the donor substrate 1 , by input of energy.

With reference to figures 1d and 1e, this embrittlement zone 6 is a zone approximately parallel to the bonding surface and has brittleness in the bonds between the lower part 1A of the donor substrate 1 and the upper part 1 B of the donor substrate 1 , these brittle bonds being able to be broken under an input of energy, such as thermal or mechanical energy. According to a first embodiment of the embrittlement zone 6, a technique called Smart-Cut® is applied which comprises firstly an implantation of atom species in the donor substrate 1 , at the level of the embrittlement zone 6.

The species implanted may be hydrogen, helium, a mix of these two species or other light species.

Implantation takes place preferably just prior to bonding.

The implantation energy is selected so that the species, implanted through the surface of the vitreous layer 4, pass through the thickness of the vitreous layer 4, the thickness of the strained layer 2 and a set thickness of the upper part 1 B of the receiver substrate 1.

It is preferable to implant sufficiently deeply in the donor substrate 1 for the strained layer 2 not to be subjected to damage during the step of detaching the donor substrate 1.

The depth of implant in the donor substrate is thus typically about 1000A. The brittleness of the bonds in the embrittlement zone 6 is found principally by the choice made in proportioning the implanted species, the proportioning being thus typically between 10¹⁶ cm^"2 and 10¹⁷ cm^"2, and more exactly between about 2.10¹⁶ cm^-2 and about 7.10¹⁶ cm^"2. Detachment at the level of this embrittlement zone 6 is then usually effected by input of mechanical and/or thermal energy.

For more detail about the Smart-Cut® method, reference may be made particularly to the document entitled "Silicon-On-lnsulator Technology: Materials to VLSI, 2^nd Edition" by J.-P. Coiinge published by "Kluwer Academic Publishers", pages 50 and 51.

According to a second embodiment of the embrittlement zone 6 a technique is applied which is described particularly in the document EP 0 849 788.

The embrittlement layer 6 is here obtained before the formation of the strained layer 2, and at the time of formation of the donor substrate 1.

Making the embrittlement layer comprises the following main operations: β forming a porous layer on a carrier substrate 1A of Si; o growing a Si layer 1B on the porous layer. The carrier substrate 1A-porous layer- Si layer 1B assembly then constitutes the donor substrate 1 , and the porous layer then constitutes the embrittlement zone 6 of the donor substrate 1.

An input of energy, such as an input of thermal and/or mechanical energy, at the level of the porous embrittlement zone 6, then leads to a detachment of the carrier substrate 1 A from the layer 1 B.

The preferred technique according to the invention for removing material at the level of an embrittlement zone 6, obtained according to one of the two non-restrictive embodiments above, thus makes it possible to remove a substantial part of the donor substrate 1 rapidly and outright. It also allows the removed part 1A of the donor substrate 1 to be able to be reused in another method, such as for example a method according to the invention.

Thus, a strained layer 2 and a possible other part of a donor substrate and/or other layers may be reformed on the removed part 1A, preferably after the surface of the removed part 1A has been polished.

With reference to figure 1f, after detachment of the remaining part 1 B of the removed part 1A of the donor substrate 1 , finish material is removed allowing the remaining part 1 B to be removed. Finish techniques such as polishing, abrasion, Chemical

Mechanical Planarization (CMP), thermal RTA annealing, sacrificial oxidation, chemical etching, taken alone or in combination can be applied to remove this part 1 B and to perfect the stack (reinforcing the bonding interface, eliminating roughness, curing defects, etc.). To advantage, in removing the finish material, a selective chemical etching, taken in combination or not with mechanical means, is applied at least at the step end.

Thus, solutions based on KOH, NH₄OH (ammonium hydroxide), TMAH, EDP or HNO₃ or solutions currently being studied combining agents such as HNO₃, HN0₂H₂O₂, HF, H₂S0₄, H₂SO₂, CH3COOH, H₂0₂, and H₂O (as explained in the document WO 99/53539, page 9) may to advantage be employed in order to etch the Si part 1B selectively in respect of the strained Si-ι_-xGe_x layer 2.

After the bonding step, another technique of removal of substance without detachment and without an embrittlement zone may be applied according to the invention in order to remove the donor substrate 1.

It consists in applying chemical and/or mecano-chemical etching.

The material or materials of the donor substrate 1 to be removed may for example be etched possibly selectively, according to an "etch- back" process. This technique consists in etching the donor substrate 1 from the back side, in other words from the free surface of the donor substrate 1.

Wet etching operations implementing etching solutions adapted to the materials for removal may be applied. Dry etching operations may also be applied to remove the material, such as plasma etching or sputter etching.

The etching operation or operations may additionally be only chemical or electro-chemical or photo-electrochemical.

The etching operation or operations may be preceded by or followed by a mechanical attack on the donor substrate 1 , such as grinding, polishing, mechanical etching or sputtering with atom species.

The etching or etching operations may be accompanied by a mechanical attack, such as polishing possibly combined with action by mechanical abrasives in a CMP process. All the above-mentioned techniques for removing material from the donor substrate 1 are proposed by way of example in the present document, but do not in anyway constitute a restriction, since the invention extends to all types of techniques able to remove material from the donor substrate 1 , in accordance with the method according to the invention. With reference to figure 1g, after removal of substance a structure is obtained comprising the receiver substrate 7, the vitreous layer 4 and the strained layer 2.

With reference to figure 1 h, thermal treatment is then applied at a temperature close to or above the viscosity temperature TQ. The main purpose of this thermal treatment is to relax the strains in the strained layer 2.

Indeed thermal treatment, at a temperature above or around the viscosity temperature of the vitreous layer 4, will cause the latter layer to turn viscous, which will allow the strained layer 2 to relax at its interface with the vitreous layer 4, leading to decompression of at least some of its internal strains. Thus, where the vitreous layer 4 is of SiO₂, obtained by thermal oxidation, thermal treatment at about 1050°C minimum, preferentially at about 1200°C minimum, for a preset time will cause a relaxation or pseudo-relaxation of the strained layer 2. The thermal treatment lasts typically from a few seconds to several hours.

The strained layer 2 therefore becomes a relaxed layer 2'. Other effects of the thermal treatment on the structure may be sought, apart from the relaxation of the strained layer 2. A second objective sought when the thermal treatment is applied may additionally be to obtain a bonding reinforcement anneal between the receiver substrate 7 and the vitreous layer 4.

Indeed, since the temperature selected for the thermal treatment is above or around the viscosity temperature of the vitreous layer 4, the latter, turned temporarily viscous, may create particular and stronger adhesion bonds with the receiver substrate 7.

In the end, therefore, a structure 30 composed of relaxed Siι_-xGe_x 27vitreous layer 4/receiver substrate 7 is obtained.

This structure 30 is a Silicon Germanium On Insulator (SGOI) structure where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer 4 of SiO₂.

The layer of relaxed Si_1-xGeχ 2' of this structure then presents a surface having a surface roughness compatible with a growth of another crystalline material. A light surface treatment, such as polishing, adapted to Siι-_xGe_x may possibly be applied to improve the surface properties.

With reference to figure 1i, and in an optional step of the invention, a Si layer 11 is then grown on the relaxed Siι._xGe_x 2' layer with a thickness appreciably less than the critical strain thickness of the material of which it is composed, and which is therefore strained by the relaxed Siι__xGe_x

2'layer. In the end, therefore, a structure 40 composed of strained Si/relaxed Siι_-xGe_x 2Vvitreous layer 4/receiver substrate 7 is obtained.

This structure 40 is a Si/SGOI structure where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer 4 of SiO₂. An alternative to this method is presented with reference to figures

2a to 2i.

With reference to figures 2a to 2i, and more particularly to figure 2c, the method is the same on the whole as that described with reference to figures 1 a to 1 i, with the exception of the step of conversion of the layer 3 into a vitreous layer 4 which is here implemented in such a way that the whole layer 3 is not converted.

There thus remains a part of the Si layer 3 inserted between the vitreous layer 4 and the strained layer 2, forming an inserted layer 5.

This inserted layer 5 is made in such a way that it has a typical thickness of around 10 nm at all events very much less than that of the strained layer 2.

During the thermal treatment to relax the strain of the strained layer 2, the latter will seek to reduce its internal elastic strain energy by using the properties of viscosity of the vitreous layer 4 turned viscous, and, given that the inserted layer 5 is of less thickness relative to the overlying strained layer 2, the strained layer 2 will impose its relaxation requirement on the inserted layer 5.

The strained layer 2 thus forces the inserted layer 5 at least partially to strain. The strained layer 2 then becomes a relaxed layer 2' at least partially.

And the relaxed inserted layer 5 then becomes a strained inserted layer 5'.

A discussion about this last point will be found particularly in the document US 5 461 243, column 3, lines 28 to 42. With reference to figure 2h, this inserted strained layer 5' is retained after the thermal treatment to relax the strained layer 2.

The structure formed is then a structure 30 composed of relaxed Siι_-xGe_x/strained Si/vitreous layer 4/receiver substrate 7. This structure 30 is a SG/SOI structure, where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer 4 of SiO₂.

It is then possible to remove, for example by selective chemical etching based on HF:H₂O₂:CH₃COOH (selectivity of about 1 :1000), the relaxed Siι._xGe_x layer 2", in order to have in the end a strained Si/vitreous layer 4/receiver substrate 7 structure.

This structure is a strained SOI structure, where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer^" 4 of Si0₂.

Instead of implementing this chemical etching, a Si layer may be grown, with reference to figure 2i, repeated on the relaxed layer 2' so as to form a strained Si layer 11 , approximately identical to the one in figure 1 i.

The structure formed is then a structure 40 composed of strained Si/relaxed Siι-_xGe_x/strained Si/vitreous layer 4/receiver substrate 7.

This structure 40 is a Si/SG/SOI structure, where the vitreous layer 4 is electrically insulating, such as for example a vitreous layer 4 of Si0₂. In one particular scenario where the thermal treatment to relax the strains of the strained layer 2 is carried out at a temperature and for a time period greater respectively than a temperature and a reference time period beyond which the Ge diffuses in the Si, the Ge contained in the strained layer 2 may diffuse into the inserted strained layer 5'. This is why it is preferable to implement the relaxation of the strained SiGe layer 2 before the repeat epitaxy of the strained Si layer 11.

But, in some other cases, this diffusion effect, if it is appropriately controlled, may be sought after.

Thus, diffusion can be controlled in such a way that the Ge species are distributed uniformly in the assembly of the two layers 2 and 5, forming a single layer of Si-ι._xGe_x having a substantially uniform Ge concentration.

A discussion on this latter point will be found particularly in the document US 5 461 243, column 3, lines 48 to 58.

According to one or other of the two preferred methods according to the invention above, or according to an equivalent of these, steps with a view to making components may be integrated into or follow this method according to the invention. Thus, preparation steps for the making of components may be implemented during the method, and at a temperature of about 900°C minimum without distorting the strain factor of the relaxed layer 2' and of the strained layer 11.

They are implemented in the strained SiGe layer 2 of the SGOI structure referenced in figure 1g, in the relaxed or pseudo-relaxed SiGe layer 2' of the SGOI structure referenced in figure 1 h, or in the strained Si layer 11 of the Si/SGOI structure referenced in figure 1 i.

Local treatments may for example be undertaken intended to etch patterns in the layers, for example by lithography, by photolithography, by reactive ion etching or by any other etching with pattern masking.

In one particular case, patterns such as islets are thus etched into the strained SiGe layer 2 in order to contribute to the effective relaxation of the strained layer 2 when subsequently applying the thermal relaxation treatment. One or more steps for making components, such as transistors, in the strained Si layer 11 (or in the relaxed SiGe layer 2' where the latter is not coated with a strained Si layer 11 ) may particularly be implemented at a temperature of about 900°C minimum without distorting the strain factor of the relaxed layer 2' and of the strained layer 11. In a particular process according to the invention, component- making steps are implemented during or in continuation of the thermal treatment to relax the strained SiGe layer 2.

In a particular process according to the invention, the strained Si layer epitaxy step is implemented during or in continuation of the component making steps.

Referring to figure 3 which represents a source wafer 10 before the formation of the embrittlement zone 6 and the formation of the vitreous layer 4, an embodiment of the invention is now presented, different from the various examples previously detailed referring to figure 1 a to 1 i and 2a to 2i by the way of choosing the materials constituting the donor substrate 1 and the strained layer 2.

Indeed, the donor substrate 1 is composed of a holding substrate 1- 1 of Si and a buffer structure composed of a buffer layer 1-2 in SiGe and an upper layer 1-3 in Siι_-zGe_z.

The holding substrate 1-1 is preferably in a bulk structure of single- crystal.

The buffer layer 1 -2 can for example be constituted of a stacking of layers so that the whole composition of Ge inside the buffer layer 1-2 gradually evoluates from 0% at the interface with the holding substrate 1-2 to 100z% of Ge at the interface with the upper layer 1-3 of Siι_-zGe_z.

Contrary to the buffer layer 1-2, the upper layer 1-3 has a Ge composition constant in its thickness.

The upper layer 1-3 has a thickness sufficiently important to assign its lattice parameter to the overlied layer.

Furthermore, the upper layer 1-3 of Si-i_-2Ge_z has a relaxed structure. thus, the buffer structure (composed of the buffer layer 1 -2 and the upper layer 1-3) allows: • an adaptation of the lattice parameter between the holding substrate 1-1 of Si and the nominal lattice parameter of Si-ι_-zGe_z of the upper layer 1-3;

• a confinement of crystal defaults, the surface of the upper layer 1-3 being then without or with a few defaults. Over the donor substrate 1 , the strained layer 2 is grown by epitaxy techniques, such as CVD techniques (PECVD, MOCVD...).

Firstly, a strained Si layer 2-1 is formed on the donor substrate 1 with a thickness no more than the critical thickness beyond which a such Si layer 2-1 starts to relax its elastic strains.

A Siι_-xGe_x strained layer 2-2 is then formed on the last Si strained layer 2-1 , so as to have a thickness less than the critical thickness of Si-ι_ _xGe_x beyond which the elastic strains start to relax.

Knowledge of the respective critical thickness of Si or Si-i__xGe_x can be found for instance in "High mobility Si and Ge structures" from Friedrich Schaffler ("Semiconductor science technology" 12 (1997) 1515-1549). The x-composition of Ge in the Si-j_χGe_x layer 2-2 is greater than the z-composition of Ge in the upper layer 1-3.

If we consider here that the strained layer 2 includes the Si strained layer 2-1 and the Siι_-xGe_x layer 2-2, and that the donor substrate 1 comprises the holding substrate 1-1 , the buffer layer 1-2, and the upper layer 1-3 of Siι_-zGe_z, the previous examples, (presented referring to the previous figures) of various embodiments of manufacturing a semiconductor-on-insulator structure 30 or 40, can then be easily transposed from the source wafer 10 of the figure 3, the embrittlement zone 6 being formed in the upper layer 1-3 or in the buffer layer 1-2. Then, a selective chemical etching is processed in order to remove the remaining part of the donor substrate 1 , employing for instance etch agent as HF:H₂O₂:CH₃COOH (selectivity about 1 :1000 between SiGe and Si).

The semiconductor-on-insulator structure finally obtained (not shown) comprises successively a receiving substrate 7, a vitreous layer 4, the S -χGe_x strained layer 2-2 and the Si strained layer 2-1. Then, a thermal treatment with a temperature close to or greater than the viscosity temperature of the vitreous layer 4 previously formed, is processed.

This thermal treatment then relaxes at least partly the Siι_-xGe_x layer 2-2.

The relaxed Siι_-xGe_x layer 2-2 imposes then elastic constraint to the top Si strained layer 2-1.

Elastic constraints in the Si strained layer 2-1 (previously strained by the upper layer 1-3 of Siι_-zGe_z) are then increased by the fact that x- composition of Ge is more important than z-composition.

Thus, a semiconductor-on-insulator structure with a lattice parameter, in its semiconductor part, close to or equal to those of the Siι_ _xGe_x material in its bulk configuration, is obtained.

Contrary to the prior art, this semiconductor-on-insulator structure is not obtained from a source wafer comprising a buffer structure adapting the parameter to a S _-xGe_x, but from a buffer structure adapting the parameter to a Siι_-zGe_z with z < x.

Now, a buffer structure which adapts a lattice parameter to a Siι_ _xGe_x is thicker, comprises more stacking layers, and so is longer and more expansive to manufacture, than a buffer structure which adapts a lattice parameter to a Siι_-zGe_z.

This method according to the embodiment of the invention offers then technical and economical improvements comparing with the latter prior art. The various techniques described in the invention are proposed by way of example in the present document, but do not in anyway constitute a restriction, since the invention extends to all types of techniques able to implement a method according to the invention.

One or more epitaxies of whatever kind may be applied to the final structure (structure 30 or 40 referenced in figure 1h, 1i, 2h, 2i), such as an epitaxy of a SiGe or SiGeC layer, or an epitaxy of a strained Si or SiC layer, or successive epitaxies of SiGe or SiGeC layers and Si or strained SiC layers alternately so as to form a multilayer structure.

Once the final structure is obtained, finish treatments, comprising for example annealing, may possibly be applied. Nor is the present invention restricted to a strained SiGe layer 2, but extends also to a constitution of the strained layer 2 in other types of materials, of the lll-V or ll-VI type, or to other semiconductor materials.

In the layers of semiconductors discussed in this document, other constituents may be added thereto, such as carbon with a carbon concentration in the layer under consideration appreciably less than or equal to 50% or, more particularly with a concentration of less than or equal to 5%.

Claims

1. Method of forming a relaxed or pseudo-relaxed layer on a substrate, the relaxed layer (2') being in a material selected from among semiconductor materials, characterized in that the method comprises the following steps:

(a) growing on a donor substrate (1 ) an elastically strained layer (2) constituted by at least a material chosen from among the semiconductor materials; (b) forming on the strained layer (2), or on a receiver substrate (7), a vitreous layer (4) made of a material which becomes viscous above a viscosity temperature of more than about 900°C; (c) bonding the receiver substrate (7) to the strained layer (2) via the vitreous layer (4) formed in step (b); (d) removing the donor substrate (1), so as to form a structure comprising the receiver substrate (7), the vitreous layer (4) and the strained layer (2); (e) thermal treating the structure at a temperature close to or higher than the viscosity temperature so as to relax at least a part of the elastic constraints in the strained layer (2).

2. Method according to the previous claim, characterized in that it further comprises a final step of crystal growth, on the structure, of a material selected from among semiconductor materials.

3. Method according to one of the previous claims, characterized in that the step (b) comprises the two sequential operations:

(b1 ) growing a layer of semiconductor material on the strained layer (2);

(b2) applying controlled treatment to convert at least part of the layer formed in step (b1), into a material which is viscous above the viscosity temperature, thus forming the vitreous layer (4).

4. Method according to one of the previous claims, characterized in that it further comprises, prior to step (c), a formation of a bonding layer on at least one of the two bonding surfaces.

5. Method according to the previous claim, characterized in that the bonding layer is of SiO₂.

6. Method according to one of the previous claims, characterized in that the removal of substance at step (d) is essentially carried out by detachment at the level of an embrittlement zone present in the donor substrate (1 ), at a depth close to the thickness of the surface layer, by input of energy.

7. Method according to the previous claim, characterized in that it further comprises, prior to step (c), the formation of the embrittlement zone by implantation of atom species in the donor substrate (1).

8. Method according to claim 6, characterized in that it additionally comprises, prior to step (a), a step of formation of the donor substrate (1) comprising the following operations:

• forming a porous layer (6) on a crystalline carrier substrate (1 A); o growing a crystalline layer (1 B) on the porous layer (6); the carrier substrate (1A)-porous layer (6)-crystalline layer (1B) assembly constituting the donor substrate (1), the porous layer constituting the embrittlement zone of the donor substrate (1 ).

9. Method according to one of the previous claims, characterized in that the removal of substance in step (d) comprises selective chemical etching.

10. Method according to one of the previous claims, characterized in that the vitreous layer (4) formed in step (b) is electrically insulating.

11. Method according to the previous claim, characterized in that the vitreous layer (4) formed in step (b) is of SiO₂.

12. Method according to one of the previous claims, characterized in that:

• the donor substrate (1 ) is of Si; and • the strained layer (2) is of Siι_-xGe_x.

13. Method according to any of claims 1 to 11 , characterized in that:

• the donor substrate (1 ) comprises a Si bulk holding substrate (1- 1) and a buffer structure (1-2, 1-3) adapting the lattice parameter from Si to Siι__zGe_z;

• the strained layer (2) comprises a Si strained layer (2-1) and a Siι_-xGe_x strained layer (2-2) with x > z.

14. Method according to claim 3, claim 11 and claim 12 or 13, characterized in that:

• the layer grown in step (b1 ) is of Si;

• the controlled treatment applied in step (b2) is a controlled thermal oxidation treatment to convert at least part of the Si of the layer formed in step (b1 ) into Siθ2, thus forming the S1O2 vitreous layer (4).

15. Method according to one of the three previous claims, characterized in that step (e) comprises thermal treatment above about 900°C

16. Method according to claim 2 combined with one of the four previous claims, characterized in that the material used for growth on the structure is Si.

17. Method according to one of the previous claims, characterized in that the vitreous layer (4) formed at step (b) is electrically insulating and in that the structure formed is therefore a semiconductor-on-insulator structure, the semiconductor thickness of which comprises the strained layer (2) which has been relaxed or pseudo-relaxed in step (e).

18. Method according to one of the previous claims, characterized in that it further comprises steps of preparing for the manufacturing of components and/or steps of manufacturing components in the strained layer (2) or in a possibly over-epitaxied layer (11 ).