WO2002043153A1

WO2002043153A1 - Method for manufacturing semiconductor wafer

Info

Publication number: WO2002043153A1
Application number: PCT/JP2001/010216
Authority: WO
Inventors: Wei Feig Qu; Masanori Kimura
Original assignee: Shin-Etsu Handotai Co.,Ltd.
Priority date: 2000-11-27
Filing date: 2001-11-22
Publication date: 2002-05-30
Also published as: JP2002164520A; TWI237412B

Abstract

A method for manufacturing a semiconductor wafer wherein a semiconductor wafer having a sufficient lattice strain to enhance electron mobility and having an Si layer of less crystal defect despite of a relatively simple laminate structure is manufactured by a simple process. This manufacturing method comprises the step of epitaxially growing an SiGe layer on the surface of a first silicon single crystal wafer, the step of coupling the surface of the SiGe layer with the surface of a second wafer with an oxide film in between, and the step of thinning off the silicon single crystal wafer coupled with the second wafer to expose the Si layer with involved lattice strain.

Description

Akira Manufacturing method for semiconductor wafers

Technical field

The present invention relates to a method for manufacturing a semiconductor wafer having a silicon layer having lattice distortion. Itoda Background technology

As a technique for improving the performance of a semiconductor device using a silicon single crystal, it is effective to increase the mobility of electrons in the silicon single crystal. Therefore, a strained silicon layer (hereinafter, referred to as a strained Si layer) in which a tensile strain is inherent in a silicon single crystal having a normal lattice constant (about 5.43 angstroms) is used as, for example, an n-channel MOS transistor. Devices that improve carrier mobility by using it for the active layer and enable high-speed operation are being studied.

A method of manufacturing a semiconductor wafer having such a strained Si layer is described in, for example, Japanese Patent Application Laid-Open No. Hei 9-18999 / Japanese Patent Application Laid-Open No. Hei 11-234440. . In each of these techniques, a strained Si layer is formed by epitaxially growing a Si layer on a SiGe layer having a larger lattice constant than Si, and a sufficiently relaxed Si layer is formed. Generating strain in the Si layer using the Ge layer, and preventing dislocations from propagating during the growth of the strained Si layer so as not to generate dislocations in the Si Ge layer. It was to solve the problem.

However, the above two methods involve at least two thin film growth processes (epitaxial growth—sputtering method, etc.). Was not an easy method. This will be described in detail below.

First, a semiconductor wafer described in Japanese Patent Application Laid-Open No. 9-180999 has a strained Si layer ZSi Ge layer / Ge layer / Si layer ZS io _two layer ZS i in order from the wafer surface. As shown in Fig. 3, the manufacturing process is as follows: fabrication of SOI wafer (step 100) → epitaxial growth of Si layer (step 102) → growth of Ge layer (step 1 0 4) → S i Ge layer growth (step 1 06) → lattice relaxation heat treatment (step 1 0 8) → strained S i layer growth (step 1 10), accompanied by four epitaxy growths Was something.

The semiconductor Uweha described in JP-A-1 1 2 3 3 44 0 Patent Publication, in order from the Weha surface, the strain S i layer / C a F ₂ layer / (S i G e layer) / that S i board As shown in Fig. 4, the manufacturing process is as follows: Si wafer preparation (Step 200) → Deposition of _two layers of CaF by sputtering (Step 202) → (S i G e layer growth) (step 204) → strain S i layer growth (step 206), also in this case. It involves at least two thin film growths, and C a F ₂ Such a special layer was formed.

As described above, since the conventional method is composed of a complicated laminated structure involving many processes, the manufacturing cost is high and the versatility is lacking. Disclosure of the invention

The present invention has been made in order to solve such a problem, and has a lattice distortion sufficient to increase the mobility of electrons, despite a relatively simple laminated structure, and a crystal. A semiconductor wafer having a Si layer with few defects can be manufactured by a simple manufacturing process. It is an object of the present invention to provide a method for producing the same.

In order to achieve the above object, a first aspect of a method of manufacturing a semiconductor layer of the present invention includes: a step of epitaxially growing a SiGe layer on a surface of a first silicon single crystal layer; Bonding the surface of the SiGe layer and the surface of the second wafer through an oxide film; and reducing the thickness of the first silicon single crystal wafer bonded to the second wafer to lattice distortion. Exposing the Si layer existing therein.

A second aspect of the method for manufacturing a semiconductor wafer of the present invention is a step of epitaxially growing a Si Ge layer on a surface of a first silicon single crystal wafer; Forming an oxide film on at least one of the surface of the first silicon wafer and the surface of the second wafer; and supplying at least one of hydrogen ions and rare gas ions to the first silicon single crystal wafer through the SiGe layer. Injecting to form a microbubble layer, and after bonding the first silicon single crystal P.A.8 and the second P.A.8 through the oxide film, Removing the silicon single crystal layer 18.

In the second aspect, the step of flattening the peeled surface of the first silicon single crystal wafer thin film which has been peeled in the peeling step and moved to the second wafer is polished or heat-treated, or a combination thereof. It is preferable to provide them. The microbubble layer can be formed in a region having lattice distortion of the first silicon single crystal wafer.

In the first and second aspects, the oxide film is preferably formed on the surface of the SiGe layer by thermal oxidation. It is preferable to use a silicon single crystal wafer as the second wafer. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a flowchart showing a first embodiment of the method of the present invention. FIG. 2 is a flowchart showing a second embodiment of the method of the present invention. FIG. 3 is a flowchart showing an example of a conventional method for manufacturing a semiconductor device.

FIG. 4 is a flowchart showing another example of a conventional method for manufacturing a semiconductor device. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it goes without saying that various modifications other than the illustrated examples are possible without departing from the technical idea of the present invention. -(First embodiment)

FIG. 1 shows a manufacturing flow of the semiconductor layer 18 according to the first embodiment of the present invention. The manufacturing flow shown in FIG. 1 is basically the same as the normal manufacturing flow for manufacturing an SOI wafer by a bonding method using two silicon wafers, and the step of growing a SiGe layer (b) ).

First, first and second Si wafers W1 and W2, which are ultimately materials of the strained Si layer, are prepared [FIG. 1 (a)]. The Si wafer W1 is not particularly limited as long as it is single crystal silicon, and an Si wafer manufactured by the CZ method or the FZ method can be used. However, in order to improve the quality of the strained Si layer forming the device, it is preferable to use a wafer having few crystal defects at least near the surface of the wafer to be used. Specifically, a DZ layer was formed near the wafer surface by heat treatment. The so-called “Grown-in defects” in the single crystal were reduced (or eliminated) by adjusting the pulling conditions of the CZ method. Preferred are FZZ and FZZ. Next, a SiGe layer 10 is formed on the surface of the first Si wafer W1 by epitaxial growth [FIG. 1 (b)]. For the formation of the SiGe layer 10, for example, a molecular beam epitaxy growth apparatus or an ultra-high vacuum chemical vapor deposition (UHV-CVD) apparatus can be used.

The Ge composition of the SiGe layer 10 to be formed is preferably about 10 to 40%. If it is less than 10%, a strain Si layer having a sufficient tensile strain is not formed, and if it exceeds 40%, Si Ge due to a difference in lattice constant between Si ゥ a wafer W1 and Si Ge layer 10 is obtained. Since misfit dislocations are easily generated in the layer 10, the crystallinity of the finally formed strained Si layer is adversely affected. Further, the thickness of the SiGe layer 10 is preferably about 10 nm to 1 m. If it is less than 10 nm, a strained Si layer having a sufficient tensile strain is not formed, and if it exceeds Ιzm, device characteristics formed in the strained Si layer are deteriorated due to an increase in parasitic capacitance and the like. Even if the Si Ge layers 10 having different lattice constants are formed on the first Si wafer W 1 by the step (1), the first Si wafer W 1 has a thickness effect of the first Si wafer 10. No dislocation is generated on the side of the W1 side.

Next, an oxide film 12 is formed on the surface of the SiGe layer 10 (FIG. 1 (c)). <The oxide film may be formed by a normal thermal oxidation method or deposited by a CVD method. May be. With thermal oxidation, S i G in e layer 1 0 surface chemically From Jona S i 〇 _two layers 1 2 are formed, extra G e atoms S i G e layer 1 0 repellency The Ge concentration in the output Si Ge layer 10 becomes high. Therefore, even if the Ge composition during epitaxy growth is relatively low for the purpose of suppressing the generation of misfit dislocations, the final surface can be obtained by thermally oxidizing the surface of the SiGe layer 10. It is possible to increase the tensile strain of the strain Si layer formed at the time. Further, in order to obtain sufficient tensile strain, thermal oxidation and oxide film removal may be repeatedly performed.

Next, the oxide film 12 formed on the surface of the SiGe layer 10 and the second Si The surface of Λ ^ 2 is brought into close contact, and heat treatment is performed so that the bonding strength can withstand the subsequent thinning process [bonding heat treatment, Fig. 1 (d)]. The heat treatment conditions are not particularly limited as long as they can withstand the subsequent thinning process, but when the thinning is performed by grinding and polishing, it is about 800 to 120 hours for about 0.5 to 5 hours. It is preferable to do this.

Finally, the first Si wafer W1 is thinned to expose the strained Si layer 14 [FIG. 1 (e)]. The thickness of the strained Si layer 14 is preferably about 1 to 100 nm. If the thickness exceeds lO O nm, tensile strain due to the SiGe layer 10 may not be present. If the thickness is less than 1 nm, good device characteristics cannot be obtained and processing is difficult.

As a method for thinning the Si layer 14, in addition to grinding and polishing, after etching by acid or alkali aqueous solution, gas-phase etching using plasma, lapping, or slicing, it is divided into two parts. A polishing method can be used. Depending on these thinning methods, bonding heat treatment performed before thinning can be omitted, or bonding can be performed using an adhesive or the like.

(Second embodiment)

FIG. 2 shows a manufacturing flow of a semiconductor device 18 according to a second embodiment of the present invention. The manufacturing flow shown in FIG. 2 is basically based on ion implantation and delamination (also called hydrogen ion delamination or smart cut (registered trademark)) using two silicon wafers, and S 0 I.ゥ This is just a process flow for manufacturing an e-beam, with the addition of a step (b) for growing a SiGe layer. Note that up to the step of oxidizing the surface of the SiGe layer in FIG. 2 (FIGS. 2 (a) to 2 (c)) is the same step as FIGS. 1 (a) to 1 (c). The description will not be repeated.

The oxide film formed on the surface of the SiGe layer 10 By implanting at least one of hydrogen ions or rare gas ions (hydrogen ions 16 in FIG. 2 (d)) through the 12 and S i Ge layers 10, the first S i ゥ wafer W 1 When the microbubble layer 18 is formed [Fig. 2 (d)], the position (depth) where the microbubble layer 18 is formed is determined by the energy of hydrogen ion 16 injection. In order to generate exfoliation by subsequent exfoliation heat treatment as a boundary, an implant dose of more than 1 × 10 ¹⁶ / cm ² (eg, 5 × 10 ¹⁶ Z cm ² ) is required. In order to ensure that the outermost Si layer surface of the multilayer structure formed by peeling has a lattice strain (tensile strain), the microbubble layer 18 is formed by the first Si layer. It is preferably formed in a region having a lattice distortion of 18 W 1 (a region of 100 nm or less from the surface of the first Si wafer W 1).

Next, the oxide film 12 formed on the surface of the SiGe layer 10 is brought into close contact with the surface of the second Si wafer W2 (FIG. 2 (e)), and a heat treatment (stripping) at 500 ° C. or more is performed. By applying heat treatment, peeling occurs in the microbubble layer 18 [FIG. 2 (f)]. Thereafter, if necessary, a bonding heat treatment at a higher temperature may be performed to increase the bonding strength. Recently, a method of exfoliating at room temperature without exfoliating heat treatment by exciting the implanted hydrogen ions and implanting them in a plasma state, which is a kind of ion implantation delamination method, has been developed. Therefore, when this method is used, the peeling heat treatment can be omitted.

The surface of the strained Si layer 14 after peeling is mirror-finished but has a slight surface roughness, so it is flattened by polishing with a very small polishing allowance called Yutsu Polish (Fig. 2 (g) ]. Instead of evening polishing, flattening by heat treatment in an atmosphere of argon gas or hydrogen gas, or a combination of these methods can be used for flattening.

As the heat treatment conditions, usually when using a resistance heating type heat treatment furnace, 1100-: 1300 ° (, heat treatment of about 0.5-5 hours is suitable, and when using a RTA (Rapid Thermal Annealing) apparatus, 1100-135 ° C,: Heat treatment is preferably performed for about 120 seconds or more.

In the embodiment shown in FIG. 1 and FIG. 2, the case where the oxide film 12 is formed on the surface of the SiGe layer 10 of the first Si wafer A 1 has been exemplified. An oxide film may be formed on the Si i wafer W2, or an oxide film may be formed on both the first and second Si wafers. In addition, by using a high resistivity wafer having a resistivity of 100 Ωcm or more as the second Si wafer W2, it can be used as a semiconductor wafer for mobile communication with excellent high frequency characteristics. Can be. Further, as the second wafer W2, an insulating substrate such as a quartz substrate, a sapphire substrate, a SiC substrate, or an aluminum nitride substrate can be used.

Example

Hereinafter, the present invention will be described in more detail with reference to Examples, but it should be understood that these Examples should not be construed as limiting.

(Example 1: Corresponding to the first embodiment)

According to the procedure of the first embodiment shown in FIG. 1, a semiconductor wafer having a sufficient lattice strain was manufactured under the following conditions.

1. Used wafer (Preparation of 1st and 2nd wafers) [Fig. 1 (a)] Diameter: 200 mm, p-type, crystal orientation: 100>, l O Q 'cm

2. Growth of a SiGe layer on the surface of the first wafer (UHV-CVD equipment) [Fig. 1 (b)]

Source _{gas: G e H 4, S i} 2 H 6

Growth temperature: 700 ° C

S i G e _{_{composition:. S i 0 7 G β}} o.3 Growth layer thickness: 150 nm

3. Surface oxidation of SiGe [Fig. 1 (c)]

Oxidation conditions: 800 ° C, pyrogenic oxidation

Oxide film thickness: 100 nm

4. Joining process [Fig. 1 (d)]

Both wafers are brought into close contact at room temperature and heat treated at 100 ° C for 2 hours (oxidizing atmosphere)

5. Thinning [Fig. 1 (e)]

Surface grinding: Grind until the first S i ゥ wafer thickness is about 20 (m).

Mirror polishing: Polishing until the first Si e wafer thickness is about 4 μm.

The thickness of the first Si wafer is reduced to about 100 nm by gas-phase etching using the PAC (Plasma Assisted Chemical Etching) method. (The PACE method is described in Japanese Patent No. 25656617. Technology).

(Example 2: corresponding to the second embodiment)

According to the procedure of the second embodiment shown in FIG. 2, a semiconductor wafer having a sufficient lattice strain was manufactured under the following conditions.

1. Used wafer (Preparation of first and second wafers) [Fig. 2 (a)] Diameter 200 mm, p-type, crystal orientation 100>,> Ο Ω-cm

2. Growth of a SiGe layer on the surface of the first wafer (UHV-CVD equipment) [Fig. 2 (b)]

Source _{gas: G e H 4, S i} 2 H 6

Growth temperature: 700 ° C

¾ lea formed:. L ₀ ₈₅ G e

Growth layer thickness: 120 nm

3. Oxidation of SiGe surface [Fig. 2 (c)]

Oxidation conditions: 800 ° C, pyrogenic oxidation 0 Oxide film thickness: 100 nm

4. Hydrogen ion implantation [Fig. 2 (d)]

H ⁺ ion implantation conditions: 3 5 ke V, 8 X 1 0 16 / cm 2

5. Peeling process [Fig. 2 (e) and (f)]

Both wafers were brought into close contact at room temperature, and peeled off by heat treatment (nitrogen atmosphere) for 500 and 30 minutes. The thickness of the outermost surface Si layer of the multilayered layer 18 after peeling is about 130 nm.

6. Bonding heat treatment

800 ° C, 2 hours, nitrogen atmosphere

7. Evening polish [Fig. 2 (g)]

Polishing cost about 30 nm Industrial applicability

As described above, according to the present invention, despite having a relatively simple laminated structure, an Si layer having sufficient lattice distortion to enhance electron mobility and having few crystal defects is provided. The effect that the semiconductor wafer having the same can be manufactured by a simple manufacturing process is achieved.

Claims

The scope of the claims

1. A step of epitaxially growing a SiGe layer on the surface of the first silicon single crystal layer, and bonding the surface of the SiGe layer and the surface of the second layer via an oxide film. And a step of thinning the first silicon single crystal wafer combined with the second wafer to expose an Si layer having lattice distortion therein. Production method.

2. a step of epitaxially growing a SiGe layer on the surface of the first silicon single crystal wafer; and at least one of the surface of the SiGe layer and the surface of the second wafer. Forming a microbubble layer by implanting at least one of hydrogen ions or rare gas ions into the first silicon single crystal wafer through the SiGe layer; Removing the first silicon single crystal wafer from the microbubble layer after bonding the first silicon single crystal wafer and the second silicon wafer through the oxide film. A method for manufacturing a semiconductor wafer.

3. A step of polishing or heat-treating the peeled surface of the first silicon single-crystal wafer thin film which has been peeled and moved to the second wafer after the peeling step, or a combination thereof. The method for manufacturing a semiconductor wafer described in claim 2.

4. The method for manufacturing a semiconductor wafer according to claim 2, wherein the microbubble layer is formed in a region having a lattice distortion of the first silicon single crystal layer. .

5. The method of manufacturing a semiconductor device according to claim 1, wherein the oxide film is formed on the surface of the SiGe layer by thermal oxidation.

6. Using a silicon single crystal wafer as the second wafer The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: