WO2001043168A3 - Verfahren zum handhaben von halbleitersubstraten bei der prozessierung und/oder bearbeitung - Google Patents

Verfahren zum handhaben von halbleitersubstraten bei der prozessierung und/oder bearbeitung Download PDF

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Publication number
WO2001043168A3
WO2001043168A3 PCT/DE2000/004359 DE0004359W WO0143168A3 WO 2001043168 A3 WO2001043168 A3 WO 2001043168A3 DE 0004359 W DE0004359 W DE 0004359W WO 0143168 A3 WO0143168 A3 WO 0143168A3
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WO
WIPO (PCT)
Prior art keywords
substrate
during processing
machining
substrates during
carrier substrate
Prior art date
Application number
PCT/DE2000/004359
Other languages
English (en)
French (fr)
Other versions
WO2001043168A2 (de
Inventor
Joerg Bagdahn
Matthias Petzold
Original Assignee
Fraunhofer Ges Forschung
Joerg Bagdahn
Matthias Petzold
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Ges Forschung, Joerg Bagdahn, Matthias Petzold filed Critical Fraunhofer Ges Forschung
Publication of WO2001043168A2 publication Critical patent/WO2001043168A2/de
Publication of WO2001043168A3 publication Critical patent/WO2001043168A3/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0005—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • B28D5/0011—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing with preliminary treatment, e.g. weakening by scoring
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0005—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • B28D5/0017—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing using moving tools
    • B28D5/0023—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing using moving tools rectilinearly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Die vorliegende Erfindung betrifft ein Verfahren zum Handhaben von Halbleitersubstraten bei der Prozessierung und/oder Bearbeitung. Bei dem Verfahren wird das Halbleitersubstrat (1) mit einem Trägersubstrat (2) verbunden, auf dem Trägersubstrat (2) prozessiert und anschliessend wieder vom Trägersubstrat gelöst. Zur Trennung vom Trägersubstrat werden eine oder mehrere Schneiden (5) oder Spitzen parallel zu einer Oberfläche des Halbleitersubstrates (1) derart mit variierender Vorschubgeschwindigkeit in den Verbindungsbereich zwischen dem Halbleitersubstrat (1) und dem Trägersubstrat (2) eingeschoben, dass zunächst ein oder mehrere Anrisse in dem Verbindungsbereich erzeugt werden, die sich durch weiteres Einschieben der Schneiden (5) oder Spitzen vollständig im Verbindungsbereich ausbreiten und zur Trennung der beiden Substrate führen. Das Verfahren ermöglicht die einfache Handhabung von dünnen Halbleitersubstraten bei der Prozessierung und/oder Bearbeitung, ohne dass nennenswerte Abfallprodukte entstehen.
PCT/DE2000/004359 1999-12-07 2000-12-05 Verfahren zum handhaben von halbleitersubstraten bei der prozessierung und/oder bearbeitung WO2001043168A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19958803A DE19958803C1 (de) 1999-12-07 1999-12-07 Verfahren und Vorrichtung zum Handhaben von Halbleitersubstraten bei der Prozessierung und/oder Bearbeitung
DE19958803.1 1999-12-07

Publications (2)

Publication Number Publication Date
WO2001043168A2 WO2001043168A2 (de) 2001-06-14
WO2001043168A3 true WO2001043168A3 (de) 2001-12-27

Family

ID=7931624

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/004359 WO2001043168A2 (de) 1999-12-07 2000-12-05 Verfahren zum handhaben von halbleitersubstraten bei der prozessierung und/oder bearbeitung

Country Status (2)

Country Link
DE (1) DE19958803C1 (de)
WO (1) WO2001043168A2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2823373B1 (fr) 2001-04-10 2005-02-04 Soitec Silicon On Insulator Dispositif de coupe de couche d'un substrat, et procede associe
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
DE10294291D2 (de) * 2001-09-14 2004-07-22 Osram Opto Semiconductors Gmbh Verfahren zum Trennen zweier zusammengefügter Materialschichten
FR2835095B1 (fr) * 2002-01-22 2005-03-18 Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
DE10235814B3 (de) * 2002-08-05 2004-03-11 Infineon Technologies Ag Verfahren zur lösbaren Montage eines zu prozessierenden Halbleitersubstrats auf einem Trägerwafer
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
EP1814817B1 (de) * 2004-10-21 2011-03-23 Fujifilm Dimatix, Inc. Ätzverfahren mit Verwendung eines Opfersubstrats
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
DE102005047509B4 (de) * 2005-10-04 2017-10-26 Degotec Gmbh Vorrichtung zur Separierung eines flächigen Objektes von einem Körper, mit dem das Objekt mittels Adhäsionskraft verbunden ist
DE102005057994A1 (de) * 2005-12-05 2007-06-06 Süss Microtec Lithography Gmbh Verfahren und Vorrichtung zum Bestimmen der Bondfestigkeit gebondeter Wafer
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
DE102008041250A1 (de) * 2008-08-13 2010-02-25 Ers Electronic Gmbh Verfahren und Vorrichtung zum thermischen Bearbeiten von Kunststoffscheiben, insbesondere Moldwafern
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
DE102012112989A1 (de) * 2012-12-21 2014-06-26 Ev Group E. Thallner Gmbh Verfahren zum Aufbringen einer Temporärbondschicht

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07240355A (ja) * 1994-02-28 1995-09-12 Sumitomo Sitix Corp 接着ウエーハの剥離方法及び剥離装置
EP0926709A2 (de) * 1997-12-26 1999-06-30 Canon Kabushiki Kaisha Herstellungsmethode einer SOI Struktur
EP0951980A2 (de) * 1998-04-23 1999-10-27 Sela Semiconductor Engineering Laboratories Ltd. Kristallspaltvorrichtung
US5994207A (en) * 1997-05-12 1999-11-30 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5240546A (en) * 1991-04-26 1993-08-31 Sumitomo Electric Industries, Ltd. Apparatus for peeling semiconductor substrate
JP3257580B2 (ja) * 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法
KR0165467B1 (ko) * 1995-10-31 1999-02-01 김광호 웨이퍼 디본더 및 이를 이용한 웨이퍼 디본딩법
JPH09263500A (ja) * 1996-01-22 1997-10-07 Komatsu Electron Metals Co Ltd 貼り合わせｓｏｉウェーハの剥がし治具
JPH09260342A (ja) * 1996-03-18 1997-10-03 Mitsubishi Electric Corp 半導体装置の製造方法及び製造装置
FR2752332B1 (fr) * 1996-08-12 1998-09-11 Commissariat Energie Atomique Dispositif de decollement de plaquettes et procede de mise en oeuvre de ce dispositif

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07240355A (ja) * 1994-02-28 1995-09-12 Sumitomo Sitix Corp 接着ウエーハの剥離方法及び剥離装置
US5994207A (en) * 1997-05-12 1999-11-30 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
EP0926709A2 (de) * 1997-12-26 1999-06-30 Canon Kabushiki Kaisha Herstellungsmethode einer SOI Struktur
EP0951980A2 (de) * 1998-04-23 1999-10-27 Sela Semiconductor Engineering Laboratories Ltd. Kristallspaltvorrichtung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 01 31 January 1996 (1996-01-31) *

Also Published As

Publication number Publication date
WO2001043168A2 (de) 2001-06-14
DE19958803C1 (de) 2001-08-30

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