WO2001011667A1 - Method for transferring a thin layer comprising a step of excess fragilization - Google Patents
Method for transferring a thin layer comprising a step of excess fragilization Download PDFInfo
- Publication number
- WO2001011667A1 WO2001011667A1 PCT/FR2000/002239 FR0002239W WO0111667A1 WO 2001011667 A1 WO2001011667 A1 WO 2001011667A1 FR 0002239 W FR0002239 W FR 0002239W WO 0111667 A1 WO0111667 A1 WO 0111667A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- thin layer
- source substrate
- separation
- thickness
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Definitions
- the present invention relates to a method of transferring a thin layer from a substrate, called source substrate, to a support called target support.
- the invention finds applications in particular in the fields of microelectronics, micro-mechanics, integrated optics and integrated electronics.
- the thin layer which is made of a material selected for its physical properties
- a support in order to form a stack with several layers.
- the transfer of a layer makes it possible in particular to associate in the same structure parts which a priori exhibit incompatibilities such as a significant difference in coefficients of thermal expansion.
- the "Smart-cut” process is essentially based on the implantation of hydrogen or another gas in neutral or ionic form in a substrate so as to form there a weakened cleavage zone.
- the cleavage zone extends, substantially parallel to its surface and is located in the substrate at a depth fixed by the implantation energy.
- the cleavage zone thus delimits in the substrate a thin surface layer which extends in thickness from the cleavage zone to the surface of the substrate.
- a second step comprises the adhesion of the source substrate with a target support so that the thin layer is integral with the target support.
- the fixing of the thin layer on the target support can take place by means of an adhesive and / or by means of a bonding layer. I t may also take place by direct molecular bonding between the substrate surface and the surface o f the target medium.
- a final step in the process consists in fracturing the substrate according to the cleavage zone in order to separate the thin layer therefrom. This then remains solid with the target support.
- the fracture (or cleavage) of the substrate is caused by supplying energy in the form of a heat treatment.
- the implantation conditions define the cleavage zone and condition the separation of the thin layer from the substrate.
- document (2) which proposes a process derived from that of document (1).
- Document (2) provides a method for obtaining the separation of its original substrate from a thin film which is self-supporting. For this, it is necessary that the implanted gaseous species are at a sufficient depth and / or that a layer of a material is deposited, after the implantation step, making it possible to stiffen the structure to obtain separation at of the implanted area without having blisters.
- the document (4) which also describes a process based on the principle established by the document (1), shows that the thermal budget used to cause the fracture of the source substrate depends on the thermal budgets of all the heat treatments imposed on the source substrate from implantation to fracture.
- thermal budget is meant the couple of heat treatment time / heat treatment temperature.
- a solution to this problem then consists in modifying the implantation conditions by carrying out an overdose of the implanted species. Such an overdose in fact makes it possible to reduce the thermal budget of the separation fracture (cleavage).
- a dose of implanted hydrogen ions of 1.10 17 / cm 2 instead of 6.10 16 / cm 2 , allows for a heat treatment duration of a few hours to lower the temperature from 400 ° C to 280 ° C.
- the solution of overdosing the implantation is not always satisfactory because of the difference in coefficient of thermal expansion that may exist between the substrate and the support.
- the thermal budget necessary for the separation can be such that it causes the separation of the substrate and the support and / or the breaking of the substrate and / or the support in their volume.
- Disclosure of the invention aims to provide a method of transferring a thin layer, not presenting the difficulties and limitations of the methods indicated above.
- One goal is in particular to propose such a process which implements a reduced thermal budget see null to obtain a separation fracture of the thin layer.
- Another object is to propose a method suitable for the transfer of a thin layer onto a target support, in which the materials of the thin layer and of the target support have different coefficients of thermal expansion.
- Yet another object is to propose a transfer process in which an excellent surface condition of the source substrate (without blisters) can be preserved so as to allow good adhesion with the target support, with or without the addition of a binder (glue), and by allowing a very weakened cleavage zone.
- an object of the invention is to propose a transfer method making it possible to obtain, after transfer, a thin layer on the target support, which has a free surface with low roughness.
- the invention more specifically relates to a process for transferring a thin layer from a source substrate to a target support comprising, in order, the following steps: a) implantation of ions or gaseous species in the source substrate so as to form there a zone, called a cleavage zone, which delimits said thin layer in the source substrate, b) the transfer of the source substrate to the target support and the joining of the thin layer with the target support, c) separation of the thin layer from the source substrate according to the cleavage zone.
- the process comprises, before step b),
- the step of forming a film thickness consists in performing step a) of implantation so as to obtain the cleavage zone at said thickness, the film then being formed by the thin layer.
- the step of forming a film thickness consists in carrying out a step of forming a so-called thickener layer on the thin layer, the thin layer and the layer of thickness then forming the film.
- the limiting thickness of the film is the thickness making it possible to stiffen the structure in order to obtain the separation of the film at the level of the cleavage zone without the appearance of blisters on the surface. It is this limiting thickness which makes it possible to obtain self-supporting films. This thickness depends in particular on the mechanical properties of the materials, but also on the separation conditions of step c) such as for example the rise in temperature of the heat treatment.
- the invention also comprises the production, before step b), of all or part of microelectric and / or micromechanical and / or optoelectronic components.
- the separation of the thin layer from the source substrate, carried out in step c) can take place under the effect of a heat treatment, under the effect of mechanical forces or under the effect of these actions. combined.
- the thermal budget and / or the mechanical forces used during step c) for the separation fracture can be particularly reduced. This has the advantage of not causing a break in adhesion between the thin film and the target support, even in the event of a difference in the coefficients of thermal expansion of the materials brought into contact.
- Another advantage of the invention is to eliminate or reduce the mechanical forces exerted on the parts in contact and thus avoid damaging them. This facilitates separation.
- step of over-embrittlement is not limited by the effects of differential expansion constraints insofar as this step is carried out before the transfer of the source substrate to the target support (step b).
- the over-embrittlement comprises a heat treatment implemented with a thermal budget greater than or equal to 50%, and preferably greater than 60%, of an overall thermal budget allowing the separation.
- the overall thermal budget considered here takes into account not only the heat treatments carried out within the strict framework of the process of the invention, but also includes any heat treatments used, for example, for the production of components or for the deposition of materials on the thin layer between steps a) and b).
- steps c) and the over-embrittlement step may include an exercise of mechanical forces.
- thermal separation treatment can also be chosen sufficient to cause during step c) a separation of the thin layer, by simple separation of the source substrate and the target support or a total separation only by this thermal treatment.
- the implantation step a) makes it possible to form cavities located in the cleavage zone in the source substrate.
- the cavities can be in different forms. They can be spherical and / or flattened with a thickness of only a few inter-atomic distances. Furthermore, the cavities may contain a free gas phase and / or gas atoms from the implanted ions, fixed on the atoms of the material forming the walls of the cavities or contain little or even no gas.
- This phenomenon also makes it possible to obtain, after the transfer and the separation fracture, a free surface of the thin layer with low roughness.
- the thickener layer for example made of Si, Si0 2 , Si 3 N 4 or even Sic, covers the thin layer in whole or in part.
- the thickness of the thickener layer to obtain a film thickness is chosen for example from a range from 3 to 10 ⁇ m for a Si0 2 thickener.
- a layer used as a thickener layer may be a layer which is also used in whole or in part for producing electronic, optoelectronic, or mechanical components on the surface of the thin layer.
- the invention also relates to a method of transferring a thin layer from a source substrate comprising the following steps: a) implantation of ions or gaseous species in the source substrate so as to form a zone therein, known as cleavage, which delimits said thin layer in the source substrate, b) separation of the thin layer from the source substrate according to the cleavage zone, in accordance with the invention, the method further comprises, prior to step b):
- the invention makes it possible to obtain very significant overgreenings, which can range up to 80 to 90% of the complete separation thanks to the presence of a thickener.
- This thickener is deposited on the surface with the aim of increasing the overgreening.
- FIG. 1 is a schematic section of a source substrate and illustrates an ion implantation operation.
- - Figure 2 is a schematic section of the source substrate of Figure 1 and illustrates the formation of a thick layer.
- - Figure 3 is a schematic section of the source substrate of Figure 2 and illustrates a weakening step.
- FIG. 4 is a schematic section of a structure formed from the source substrate of Figure 3, transferred to a target support.
- Figure 5 is a schematic section of the structure of Figure 4 after separation fracture of the source substrate.
- the following description relates to a transfer of a thin layer of silicon onto a target support of molten silica (incorrectly called quartz).
- the invention can however be implemented for other solid materials, whether they are crystalline or not. These materials can be dielectric, conductive, semi-insulating or semi-conducting.
- the target support can be a final or intermediate support, such as a handle, a solid substrate or a multilayer substrate.
- the process can in particular be used for the transfer of layers of non-semiconductor, ferroelectric, piezoelectric materials such as for example LiNb0 3 or III-V semiconductors such as AsGa, InP on silicon or SiC.
- non-semiconductor, ferroelectric, piezoelectric materials such as for example LiNb0 3 or III-V semiconductors such as AsGa, InP on silicon or SiC.
- FIG. 1 shows an initial silicon substrate 10. This undergoes ion implantation hydrogen indicated with arrows 12. This layout corresponds to step a ⁇ ) of the process.
- the implantation carried out for example with a dose of 6.10 16 / cm 2 and an energy of 70 keV, makes it possible to form microcavities 14 in the substrate 10 at a depth of the order of 7000 A.
- This depth also corresponds to the thickness of a thin layer 18. This is delimited on the surface of the substrate by an area 16, called a cleavage area, comprising the microcavities 14.
- the thin surface layer 18 may be subjected to other treatments, known per se, for the formation in this layer of electronic, optical, or mechanical components. These components are not shown in the figure for reasons of clarity. In this case, these stages are taken into account for the overgreening.
- FIG. 2 which corresponds to the step of using a thickness of the process, shows the deposition of a layer of silicon oxide 20 with a thickness of the order of, or greater than 5 ⁇ m, on the thin layer 18.
- the silicon oxide layer is for example deposited by a chemical gas deposition process assisted by plasma at a temperature of 300 ° C. Thermal budgets are chosen in such a way so that they avoid the appearance of blisters during the thicknessing stage.
- the silicon oxide layer 20 acts as a thickener for the thin layer 18. In other words, its function is to prevent deformation of the thin layer under the effect of subsequent heat treatments.
- FIG. 3 corresponds to the process of over-embrittlement of the process. During this step, the substrate is subjected to treatments aimed at further weakening the cleavage zone 16.
- a heat treatment is carried out at a temperature of the order of 450 ° C for a period of the order of 12 minutes.
- This thermal budget is preferably greater than 60% of the thermal budget necessary to obtain separation only by annealing. Such over-embrittlement is possible with a sufficient thickness of film.
- the layer of thickness 20 which covers the thin layer 18, prevents its deformation and in particular prevents the formation of blisters.
- the heat treatment can be followed by a step of polishing the free face of the thickener layer 20 just to improve the surface roughness so as to prepare it for molecular bonding.
- Figure 4 shows the transfer of the source substrate 10 on a target support 30 which, in this case, is a quartz plate.
- the transfer is carried out so as to bring a flat face of the target support into contact with the free flat face of the thickener layer 20.
- the transfer can take place by means of a binder or an adhesive.
- the molecular adhesion forces can be reinforced for example by a heat treatment and / or by surface preparations.
- the heat treatment is carried out at a relatively low temperature, of the order of 200 ° C. for a period of 20 hours. This heat treatment can contribute to inducing stresses such that the fracture of the substrate can be obtained according to this zone.
- FIG. 5 illustrates step c) of the method which corresponds to a fracture of the source substrate.
- the fracture takes place according to the cleavage zone and separates the thin layer 18 from the remaining part of the substrate 10. This last part can then be reused for example for a new transfer of thin layer.
- the thin layer 18 remains integral with the support
- the thickener layer can be omitted.
- the thin layer is then directly in contact with the target support.
- the fracture of the source substrate can be caused by the exercise of mechanical force and / or by heat treatment.
- a razor blade In the example shown, a razor blade
- the invention applies particularly well to the production of a thin layer of silicon on molten silica, the main advantage of which is to have a transparent support with a semiconductor layer which may include components.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00956612A EP1203403A1 (en) | 1999-08-04 | 2000-08-03 | Method for transferring a thin layer comprising a step of excess fragilization |
JP2001516228A JP2003506892A (en) | 1999-08-04 | 2000-08-03 | Method for transferring thin layers with excessive weakening steps |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR99/10121 | 1999-08-04 | ||
FR9910121A FR2797347B1 (en) | 1999-08-04 | 1999-08-04 | METHOD FOR TRANSFERRING A THIN FILM HAVING A SURFRAGILILIZATION STEP |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001011667A1 true WO2001011667A1 (en) | 2001-02-15 |
Family
ID=9548879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2000/002239 WO2001011667A1 (en) | 1999-08-04 | 2000-08-03 | Method for transferring a thin layer comprising a step of excess fragilization |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1203403A1 (en) |
JP (1) | JP2003506892A (en) |
KR (1) | KR100742240B1 (en) |
FR (1) | FR2797347B1 (en) |
MY (1) | MY137329A (en) |
TW (1) | TW457565B (en) |
WO (1) | WO2001011667A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006505122A (en) * | 2002-10-30 | 2006-02-09 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | Method for manufacturing separable substrate |
JP2006505941A (en) * | 2002-11-07 | 2006-02-16 | コミサリヤ・ア・レネルジ・アトミク | Method for generating brittle regions in a substrate by co-implantation |
US7256103B2 (en) | 2004-06-10 | 2007-08-14 | S.O.I.Tec Silicon On Insulator Technologies | Method for manufacturing a compound material wafer |
WO2008132895A1 (en) * | 2007-04-20 | 2008-11-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate and semiconductor device |
WO2009147778A1 (en) * | 2008-06-03 | 2009-12-10 | 信越半導体株式会社 | Bonded wafer manufacturing method |
US7951689B2 (en) | 2007-09-14 | 2011-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate and method for manufacturing semiconductor device |
US8211780B2 (en) | 2007-12-03 | 2012-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
US20210305097A1 (en) * | 2020-03-31 | 2021-09-30 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Low-temperature method for transfer and healing of a semiconductor layer |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (en) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | METHOD FOR THE TRANSFER OF A THIN FILM COMPRISING A STEP OF CREATING INCLUSIONS |
FR2823599B1 (en) | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | DEMOMTABLE SUBSTRATE WITH CONTROLLED MECHANICAL HOLDING AND METHOD OF MAKING |
FR2830983B1 (en) * | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING THIN FILMS CONTAINING MICROCOMPONENTS |
JP4277481B2 (en) * | 2002-05-08 | 2009-06-10 | 日本電気株式会社 | Semiconductor substrate manufacturing method and semiconductor device manufacturing method |
FR2845518B1 (en) * | 2002-10-07 | 2005-10-14 | Commissariat Energie Atomique | IMPLEMENTING A DEMONDABLE SEMICONDUCTOR SUBSTRATE AND OBTAINING A SEMICONDUCTOR ELEMENT |
FR2845517B1 (en) * | 2002-10-07 | 2005-05-06 | Commissariat Energie Atomique | IMPLEMENTING A DEMONDABLE SEMICONDUCTOR SUBSTRATE AND OBTAINING A SEMICONDUCTOR ELEMENT |
US7176108B2 (en) | 2002-11-07 | 2007-02-13 | Soitec Silicon On Insulator | Method of detaching a thin film at moderate temperature after co-implantation |
FR2848336B1 (en) | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | METHOD FOR PRODUCING A STRESS STRUCTURE FOR DISSOCIATING |
FR2856844B1 (en) | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | HIGH PERFORMANCE CHIP INTEGRATED CIRCUIT |
FR2857953B1 (en) * | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | STACKED STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME |
FR2861497B1 (en) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION |
US7772087B2 (en) | 2003-12-19 | 2010-08-10 | Commissariat A L'energie Atomique | Method of catastrophic transfer of a thin film after co-implantation |
JP4879737B2 (en) * | 2004-01-29 | 2012-02-22 | ソワテク | Method for separating semiconductor layers |
FR2886051B1 (en) | 2005-05-20 | 2007-08-10 | Commissariat Energie Atomique | METHOD FOR DETACHING THIN FILM |
FR2889887B1 (en) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | METHOD FOR DEFERING A THIN LAYER ON A SUPPORT |
FR2891281B1 (en) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM ELEMENT |
FR2899378B1 (en) | 2006-03-29 | 2008-06-27 | Commissariat Energie Atomique | METHOD FOR DETACHING A THIN FILM BY FUSION OF PRECIPITS |
JP5284576B2 (en) * | 2006-11-10 | 2013-09-11 | 信越化学工業株式会社 | Manufacturing method of semiconductor substrate |
FR2910179B1 (en) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING THIN LAYERS OF GaN BY IMPLANTATION AND RECYCLING OF A STARTING SUBSTRATE |
KR101440930B1 (en) * | 2007-04-20 | 2014-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method of manufacturing soi substrate |
FR2925221B1 (en) | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | METHOD FOR TRANSFERRING A THIN LAYER |
FR2947098A1 (en) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | METHOD OF TRANSFERRING A THIN LAYER TO A TARGET SUBSTRATE HAVING A THERMAL EXPANSION COEFFICIENT DIFFERENT FROM THAT OF THE THIN LAYER |
US8524572B2 (en) * | 2011-10-06 | 2013-09-03 | Micron Technology, Inc. | Methods of processing units comprising crystalline materials, and methods of forming semiconductor-on-insulator constructions |
US9281233B2 (en) * | 2012-12-28 | 2016-03-08 | Sunedison Semiconductor Limited | Method for low temperature layer transfer in the preparation of multilayer semiconductor devices |
FR3055063B1 (en) * | 2016-08-11 | 2018-08-31 | Soitec | METHOD OF TRANSFERRING A USEFUL LAYER |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0763849A1 (en) * | 1995-09-13 | 1997-03-19 | Commissariat A L'energie Atomique | Process for preparing thin semiconductor films |
EP0807970A1 (en) * | 1996-05-15 | 1997-11-19 | Commissariat A L'energie Atomique | Method of manufacturing a thin semiconductor layer |
WO1998052216A1 (en) * | 1997-05-12 | 1998-11-19 | Silicon Genesis Corporation | A controlled cleavage process |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US5909627A (en) * | 1998-05-18 | 1999-06-01 | Philips Electronics North America Corporation | Process for production of thin layers of semiconductor material |
-
1999
- 1999-08-04 FR FR9910121A patent/FR2797347B1/en not_active Expired - Fee Related
-
2000
- 2000-08-03 WO PCT/FR2000/002239 patent/WO2001011667A1/en active Search and Examination
- 2000-08-03 JP JP2001516228A patent/JP2003506892A/en active Pending
- 2000-08-03 KR KR1020027001366A patent/KR100742240B1/en not_active IP Right Cessation
- 2000-08-03 EP EP00956612A patent/EP1203403A1/en not_active Withdrawn
- 2000-08-04 MY MYPI20003580A patent/MY137329A/en unknown
- 2000-09-05 TW TW089115613A patent/TW457565B/en not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0763849A1 (en) * | 1995-09-13 | 1997-03-19 | Commissariat A L'energie Atomique | Process for preparing thin semiconductor films |
EP0807970A1 (en) * | 1996-05-15 | 1997-11-19 | Commissariat A L'energie Atomique | Method of manufacturing a thin semiconductor layer |
WO1998052216A1 (en) * | 1997-05-12 | 1998-11-19 | Silicon Genesis Corporation | A controlled cleavage process |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US5909627A (en) * | 1998-05-18 | 1999-06-01 | Philips Electronics North America Corporation | Process for production of thin layers of semiconductor material |
Non-Patent Citations (1)
Title |
---|
EN W G ET AL: "THE GENESIS PROCESSTM: A NEW SOI WAFER FABRICATION METHOD", ANNUAL IEEE INTERNATIONAL SILICON-ON-INSULATOR CONFERENCE,US,NEW YORK, NY: IEEE, vol. CONF. 24, 1998, pages 163 - 164, XP000830696, ISBN: 0-7803-4501-0 * |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006505122A (en) * | 2002-10-30 | 2006-02-09 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | Method for manufacturing separable substrate |
JP2006505941A (en) * | 2002-11-07 | 2006-02-16 | コミサリヤ・ア・レネルジ・アトミク | Method for generating brittle regions in a substrate by co-implantation |
US7256103B2 (en) | 2004-06-10 | 2007-08-14 | S.O.I.Tec Silicon On Insulator Technologies | Method for manufacturing a compound material wafer |
WO2008132895A1 (en) * | 2007-04-20 | 2008-11-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate and semiconductor device |
US8399329B2 (en) | 2007-04-20 | 2013-03-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate and semiconductor device |
US8629031B2 (en) | 2007-04-20 | 2014-01-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate and semiconductor device |
US8951878B2 (en) | 2007-04-20 | 2015-02-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate and semiconductor device |
US7951689B2 (en) | 2007-09-14 | 2011-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate and method for manufacturing semiconductor device |
US8399337B2 (en) | 2007-09-14 | 2013-03-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate and method for manufacturing semiconductor device |
US8211780B2 (en) | 2007-12-03 | 2012-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
WO2009147778A1 (en) * | 2008-06-03 | 2009-12-10 | 信越半導体株式会社 | Bonded wafer manufacturing method |
US20210305097A1 (en) * | 2020-03-31 | 2021-09-30 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Low-temperature method for transfer and healing of a semiconductor layer |
Also Published As
Publication number | Publication date |
---|---|
JP2003506892A (en) | 2003-02-18 |
TW457565B (en) | 2001-10-01 |
MY137329A (en) | 2009-01-30 |
KR20020085868A (en) | 2002-11-16 |
KR100742240B1 (en) | 2007-07-24 |
FR2797347A1 (en) | 2001-02-09 |
FR2797347B1 (en) | 2001-11-23 |
EP1203403A1 (en) | 2002-05-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2001011667A1 (en) | Method for transferring a thin layer comprising a step of excess fragilization | |
EP1299905B1 (en) | Method for cutting a block of material and for forming a thin film | |
EP0950257B1 (en) | Method for making a thin film on a support | |
EP1155442B1 (en) | Method for fabricating a multilayer structure with controlled internal stresses | |
EP1285461B1 (en) | Method of manufacturing a thin film | |
EP1922752B1 (en) | Method of transferring a thin film onto a support | |
EP0898307B1 (en) | Method of treatment for molecular gluing and ungluing of two structures | |
EP1354346B1 (en) | Method for producing a thin film comprising implantation of gaseous species | |
EP3646374B1 (en) | Process for transferring a thin layer to a support substrate that have different thermal expansion coefficients | |
WO2004044976A1 (en) | Method for forming a brittle zone in a substrate by co-implantation | |
EP2342745B1 (en) | Method for producing a hybrid substrate with an embedded electrically insulating continuous layer | |
EP2195835A1 (en) | Method of fabricating a microelectronic structure involving molecular bonding | |
EP1923912A1 (en) | Method of manufacturing a mixed microtechnology structure and structure obtained using same | |
EP2842155B1 (en) | Process for bonding in an atmosphere of a gas having a negative joule-thomson coefficient | |
WO2008031980A1 (en) | Method of transferring a layer at high temperature | |
WO2011161122A1 (en) | Method for transferring a single-crystal silicon thin film | |
EP1631982B1 (en) | Method for production of a very thin layer with thinning by means of induced self-support | |
EP2065906B1 (en) | Process for moderating deformation | |
EP2263251B1 (en) | Method of transfer using a ferroelectric substrate | |
EP2023380A1 (en) | Method and installation for fracturing a composite substrate via an embrittlement plane | |
WO2020188169A1 (en) | Method for transferring a useful layer to a carrier substrate | |
WO2006100301A1 (en) | Method of producing a hetero-structure comprising at least one thick layer of semiconductor material | |
EP3939077A1 (en) | Method for transferring a useful layer onto a support substrate | |
FR3059149A1 (en) | PROCESS FOR PRODUCING A THIN FILM BASED ON INP OR GAAS |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR SG US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2000956612 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020027001366 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10048337 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 2000956612 Country of ref document: EP |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWP | Wipo information: published in national office |
Ref document number: 1020027001366 Country of ref document: KR |