WO2000065565A1

WO2000065565A1 - High resolution display controller with reduced working frequency requirement for the display data handling circuitry

Info

Publication number: WO2000065565A1
Application number: PCT/US2000/010587
Authority: WO
Inventors: Heather Bowers; Jiann-Tsuen Chen
Original assignee: Opti, Inc.
Priority date: 1999-04-23
Filing date: 2000-04-19
Publication date: 2000-11-02
Also published as: AU4473100A

Abstract

Display controllers for flat panel usually comprise an A/D converter, a pixel processor (e.g. for performing scaling and dithering of the image) and a display memory controller. When, as requested with high display resolutions, such controllers have to work at high frequencies, they become complex and power consuming. Such problem is solved here by splitting the controller in two similar arrangements that work in parallel, e.g. one for even pixels in the pixel data stream and the other for odd pixels. By virtue of parallel working, the operating frequency of each arrangement is halved. Pixel processors in each of the two arrangements receive data from the A/D converters of both arrangements, which is necessary for most pixel operations. Possibly, also the display memory is split in even and odd memories. Both odd and even pixel data streams output by the controllers are then recombined and provided synchronously to the display panel.

Description

HIGH RESOLUTION DISPLAY CONTROLLER WITH REDUCED WORKING FREQUENCY REQUIREMENT FOR THE DISPLAY DATA HANDLING CIRCUITRY

BACKGROUND OF THE INVENTION Field of the Invention

The present invention is directed towards image processing. More specifically, the present invention is directed towards a display controller for supporting high resolution graphics.

Description of Related Art

In general, display controllers process incoming analog video signals and provide digital video signals to a display. Once such display controller is a display controller for a liquid crystal display ("LCD"). A display controller for a LCD receives analog video signals, such as VGA and UXGA signals. These signals are then processed and provided to a liquid crystal display panel.

In providing signals to the LCD panel, the display controller performs pixel processing. Pixel processing is performed by a display controller to enhance the quality of the output video. Two types of pixel processing are scaling and dithering.

When scaling, the display controller either adds or removes pixels from an input image. For example, if an input image does not provide enough pixels to fill a display panel, then the display controller scales the input image to be larger by adding enough pixels to enable the output image to fill the display panel. When dithering, a display controller attempts to offset color degradation that occurs when pixels in true color input images are converted into display pixels with a reduced number of data bits. A reduction in the number of data bits when converting an incoming pixel into a display pixel is typically encountered with liquid crystal displays. A display controller also provides support for storing incoming pixels in a display memory buffer. Display memory buffers are often necessary, because the rate at which incoming pixels are received exceeds the rate at which pixels are provided to an output display panel.

As display technology improves, the resolution of both input and output images increases. As a result, the rate at which incoming video information is provided to a display controller increases. For example, in 1600 x 1200 resolution, incoming pixel data is provided to a display controller at a bit rate of 200 MHz. This is in sharp contrast with the bit rate of 108 MHz that occurs at a resolution of 1280 x 1024.

The increased frequency of incoming pixel data provides several challenges in the design of display controllers. Complex circuitry is required for capturing incoming pixel information without corruption from high frequency noise components. Increased input pixel data frequencies also create a need for the speed of the display memory interface to be increased. In addition to meeting each of these needs, it is beneficial for the display controller to continue performing pixel processing. Fig. 1 illustrates traditional display controller 100. Display controller 100 receives analog input pixel information from graphics controller 102 and converts this input information to display pixels that are provided to display panel 104. Display controller 100 receives pixels from graphics controller 102 that contain red, green, and blue components (IR, IG, and IB, respectively). Display controller 100 includes analog to digital converter 106 for receiving input pixel components IR, IG, and IB.

Analog to digital converter 106 actually includes three separate analog to digital converters, with each one being dedicated to one of the red, green, and blue input pixel components. Analog to digital converter 106 captures each of incoming pixel components IR, IG, and IB by using a reference clock received by analog to digital converter 106 with frequency Fin.

Accordingly, analog to digital converter 106 provides the dual function of synchronizing input pixel components IR, IG, and IB and converting them into digital pixel components. At its output, analog to digital converter 106 provides red digital pixel component PCR, green digital pixel component PCG, and a blue digital pixel component PCB.

Digital pixel components PCR, PCG, PCB are provided to pixel processor 108. Pixel processor 108 performs the above-described pixel processing, such as scaling and dithering. The output of pixel processor 108 provides a display pixel value representing a pixel which can be provided to display panel display 104. The output of pixel processor 108 is coupled to memory controller 1 10, which stores display pixels in display memory 1 14. As shown in Fig. 1 , display memory 1 14 typically resides outside of display controller 100. Display panel controller 1 12 is coupled to memory controller 1 10 for retrieving display pixels from display memory 1 14. After retrieving display pixels, display panel controller 1 12 provides them to display panel 104. In interfacing with display panel 104, display panel controller 1 12 provides pixel data and a clock signal, which is employed by display panel 104 to capture the pixel data.

When image resolutions are increased, as described above, analog to digital converter 106 receives very high frequency pixel inputs, which can exceed 200 MHz. Traditionally, the design of such a high speed analog to digital converter has required the use of very complex circuitry to prevent the introduction of disruptive noise in digital pixel components PCR, PCG, and PCB. Additionally, high transistor switching speeds will occur in transistors forming analog to digital converter 106, thereby increasing the power consumption of display controller 100. This is undesirable in certain computer systems where it is desirable to minimize power consumption.

In order to support increased rates of incoming pixel data, the bus interface between memory controller 1 10 and display memory 1 14 is typically required to increase significantly in either data bus size or speed. In either case, additional transistor switching will occur in memory controller 1 10, thereby increasing the power consumption of display controller 100. If the speed of the bus interface between memory controller 1 10 and display memory 1 14 is increased, then memory controller 1 10 will also have to be designed with complex circuitry to prevent the introduction of noise into display pixels being transferred to and from display memory 1 14. A partial solution has been attempted for addressing the design of a display controller for high frequency input data. One such solution is the use of analog to digital converters that are external to the display controller. For each of the red, green, and blue pixel components (IR, IG, and IB), two analog to digital converters are employed, instead of one. A first analog to digital converter captures even pixels, and a second analog to digital converter captures odd pixels. The outputs of the analog to digital converter pair for each pixel component are then combined to provide an even-odd pixel component pair to the display controller.

While the above-stated solution alleviates the need for developing a high frequency analog to digital converter, it has the shortcoming of not addressing the need for increased bandwidth in the interface between memory controller 1 10 and display memory 1 14. As a result, either complex high frequency circuitry or a higher performance data bus will have to be employed on memory controller 1 10.

Accordingly, it is desirable to provide a display controller capable of receiving input pixels at high frequencies without the need for employing complex high frequency circuitry, and without the need for increasing the operating speed of the display memory interface.

SUMMARY OF THE INVENTION In accordance with the present invention, a display controller is provided for processing high frequency pixel data inputs without the need for including complex high frequency circuitry or a high speed interface to display memory. Such a display controller includes a first analog to digital converter for receiving even pixels in a high frequency pixel data input stream and a second analog to digital converter for receiving odd pixels in the high frequency pixel data input stream. The display controller also includes an even pixel processor and an odd pixel processor. The even pixel processor receives the output of the even analog to digital converter and the odd analog to digital converter. The odd pixel processor receives the output of the even analog to digital converter and the odd analog to digital converter. Each pixel processor provides for processing digitized pixel data, so that operations such as scaling and dithering are performed. Each pixel processor receives both even and odd pixels, since processing operations often require the use of information from adjacent pixels.

The output of the even pixel processor is coupled to an even memory controller. The even memory controller has an interface to an even display memory, which is employed for storing even display pixels. The display controller also includes an odd memory controller, which is coupled to the odd pixel processor for receiving odd display pixels. The odd memory controller has an interface to an odd display memory, which is employed for storing odd display pixels.

The display controller includes both an even display panel controller and an odd display panel controller. The even display panel controller is coupled to the even memory controller for the purpose of retrieving even display pixels from the even display memory. The odd display panel controller is coupled to the odd memory controller for the purpose of retrieving odd display pixels from odd display memory. The even display panel controller provides both an even display pixel output and a display clock, which allows a display panel to synchronously receive the output even display pixels. The even display controller's display clock is also coupled to the odd display panel controller. This enables the odd display panel controller to provide output odd display pixels synchronous with the output even display pixels. The even and odd display pixels can then be provided simultaneously to a display panel.

These and other objects and advantages of the present invention will appear more clearly from the following description in which the preferred embodiment of the invention has been set forth in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described with reference to the following drawings, in which:

Fig. 1 illustrates a traditional display controller.

Fig. 2 illustrates a display controller in one embodiment of the present invention. Fig. 3 illustrates a display controller in an alternate embodiment of the present invention.

DETAILED DESCRIPTION In accordance with the present invention, a display controller is provided that does not need to employ complex high frequency circuitry to support high resolution images. The present invention's display controller also avoids the need to significantly increase transistor switching speeds in an analog to digital converter and display memory interface, so that a display controller does not consume excessive amounts of power.

In accordance with the present invention, a display controller includes an analog to digital converter to receive red, green, and blue pixel components. The analog to digital converter includes a pair of analog to digital converters for each input pixel component, so that pixel components can be captured at half the frequency of incoming pixels. Within each pair, one analog to digital converter is dedicated to even pixels, and another analog to digital converter is dedicated to odd pixels. A display controller in accordance to the present invention also includes two display memory interfaces. One display memory interface is included for supporting a display memory for even pixels, and another display memory interface is included for supporting a display memory for odd pixels. By dividing the display controller's operation into even and odd channels, the transistor switching speeds employed throughout the display controller can be kept significantly lower than in a single high frequency channel. Accordingly, a display controller in accordance with the present invention does not require the consumption of significantly high levels of power, nor does it require complex high frequency circuitry.

In one embodiment of the present invention, the display controller is implemented in a pair of integrated circuits. One integrated circuit is designed to support even pixels, and the other integrated circuit is designed to support the odd pixels. In order to support pixel processing, each integrated circuit provides its digital pixel components to the other integrated circuit. This is beneficial when supporting pixel processing, because pixel processing typically employs the use of adjacent pixels.

Fig. 2 illustrates a display controller 200 in accordance with the present invention. Display controller 200 includes even display controller 210 and odd display controller 230. Analog to digital converter 212 is included in even display controller 210, and analog to digital converter 232 is included in odd display controller 230. Analog to digital converter 212 receives red, green, and blue pixel components (IR, IG, and IB, respectively) for each input pixel. Within analog to digital converter 212, an analog to digital converter is included for each of red, green, and blue pixel component IR, IG, and IB. Each of the analog to digital converters within analog to digital converter 212 includes a clock input, which is coupled to a clock having input frequency Fin. The Fin frequency can be provided by either a clock source that is external to even display controller 210 or a phase lock loop that exists within even display controller 210.

Analog to digital converter 232 is included within odd display controller 230 to also receive incoming red, green, and blue pixel components (IR, IG, and IB, respectively). An analog to digital converter for each of pixel component inputs IR, IG, and IB is included within analog to digital converter 232. Each of the analog to digital converters within analog to digital converter 232 also includes a clock input.

These clock inputs are coupled to the clock input for analog to digital converter 21 2 through inverter 250 to receive the inverted Fin frequency clock signal.

In operation, analog to digital converter 212 captures IR, IG, and IB pixel components for even pixels, and analog to digital converter 232 captures IR, IG, and IB pixel components for odd pixels. Even and odd is a naming convention for adjacent pixels in a stream of pixel data provided to display controller 200. Each even pixel in the stream is adjacent to two odd pixels, and each odd pixel in the stream is adjacent to two even pixels. By requiring analog to digital converters 212 and 232 to only capture either even or odd pixel components, analog to digital converters 212 and 232 are able to operate at frequencies (Fin) that are half of the frequency required for capturing adjacent incoming pixel components.

Analog to digital converter 212 and analog to digital converter 232 capture and process even and odd input pixel components, respectively, to provide digital versions of those pixel components. The output of analog to digital converter 212 provides red, green, and blue even digital output pixel components (PCRE, PCGE, and

PCBE, respectively) for respective red, green, and blue input pixel component (IR, IG, and IB) . Analog to digital converter 232 provides red, green, and blue odd digital output pixel components (PCRO, PCGO, and PCBO, respectively) for respective red, green, and blue input pixel component (IR, IG, and IB). The PCRO, PCGO, and PCBO outputs of analog to digital converter 232 are coupled to the inputs of pixel processor 234 in display controller 230 and pixel processor 214 in display controller 210. The PCRE, PCGE, and PCBE outputs of analog to digital converter 212 are coupled to the inputs of pixel processor 214 and pixel processor 234. Pixel processors 214 and 234 receive the outputs of both analog to digital converter 212 and analog to digital converter 232, so that each pixel processor (214, 234) receives all pixels entering display controller 200. This is useful, since certain types of pixel processing, such as scaling and dithering, rely upon the use of adjacent pixels.

Pixel processor 214 processes pixel components PCRO, PCGO, PCBO, PCRE, PCGE, and PCBE and provides even display pixel DPE. Memory controller 216 in controller 210 is coupled to pixel processor 214 to receive even display pixel DPE. Pixel processor 234 processes pixel component PCRO, PCGO, PCBO, PCRE, PCGE, and PCBE and provides odd display pixel DPO. Memory controller 236 in controller 230 is coupled to pixel processor 232 to receive odd display pixel DPO. Memory controller 216 provides an interface to display memory 220, which stores even display pixels. Memory controller 236 provides an interface to odd display memory 240, which stores odd display pixels. As a result, memory controller 216 and memory controller 236 are both able to employ traditional data interfaces to transfer display pixels to and from display memory 220 and display memory 240, respectively. This avoids the need for high frequency memory interfaces. In one embodiment of the present invention, even display memory 220 and odd display memory 240 are external to display controller 200.

Display panel controller 21 8 in controller 210 is coupled to memory controller 216 for the purpose of retrieving even display pixels from even display memory 220. Display panel controller 238 in controller 230 is coupled to odd memory controller

236 for the purpose of retrieving odd display pixels from odd display memory 240. Display panel controller 218 provides even display pixels (DPE) to panel 204 synchronous with an output clock provided by display panel controller 218 having frequency FD. The clock provided by display panel controller 21 8 is coupled to clock inputs of display panel 204 and display panel controller 238. As a result, display panel controller 21 8 and display panel controller 238 synchronously provide even and odd display pixels, respectively, on their outputs. The outputs of display panel controller 218 and display panel controller 238 are coupled to display panel 204. Display panel 204 is representative of display panels that are well known in the art, which have the capability of simultaneously receiving both even and odd display pixels. In an alternate embodiment of the present invention, display panel controller 238 provides the FD output clock, which is then coupled to clock inputs of display panel 204 and display panel controller 218.

Even though memory controller 200 is supporting high resolution pixel input data, which has frequencies of over 200 MHz, it appears to even display controller

210 and odd display controller 230 that the input pixel data is only arriving at half of the actual input frequency. As a result, traditional circuitry can be employed to design analog to digital converters 212 and 232 and memory controllers 216 and 236. Further, the operating switching speeds of transistors in even display controller 210 and odd display controller 230 are significantly less than those in a display controller having a single high frequency analog to digital converter channel for receiving both even and odd pixels. As a result, the power consumption of display controller 200 is less than a display controller that would receive high resolution inputs through a single high frequency analog to digital converter channel. In one embodiment of the present invention, even display controller 210 is implemented on one integrated circuit, and odd display controller 230 is implemented on another integrated circuit. In an alternate embodiment of the present invention, both even display controller 210 and odd display controller 230 are implemented on the same integrated circuit. In yet another embodiment of the present invention, a plurality of integrated circuits exceeding two are used to implement both even display controller 210 and odd display controller 230.

Fig. 3 illustrates yet another embodiment of a display controller in accordance with the present invention, in which there is no pixel processing. Such an embodiment may be useful when it is not desirable to include pixel processing. In the embodiment shown in Fig. 3, the elements with the same reference numbers as those appearing in Fig. 2 operate the same, except for analog to digital converter 212 and analog to digital converter 232. The only difference with analog to digital converter 212 in Fig. 3 is that the output of analog to digital converter 212 is provided directly to the input of memory controller 216 to provide even display pixels DPE. In one embodiment of the present invention, analog to digital converter 212 combines even digital pixel component values PCRE, PCGE, and PCBE to form even display pixel DPE.

Analog to digital converter 232 in Fig. 3 is the same as in Fig. 2, except that its output is coupled directly to memory controller 236 to provide odd display pixels DPO. In one such embodiment, analog to digital converter 232 combines odd digital pixel component values PCRO, PCGO, and PCBO to provide odd display pixel DPO. As a result, even display controller 210 and odd display controller 230 in Fig. 3 operate to achieve the same result as described for Fig. 2, except that no pixel processing is performed. The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

CLAIMSWhat is claimed is:

1 . A display controller for receiving an input stream of pixels having a first frequency and providing an output stream of display pixels, said display controller comprising: a first analog to digital converter coupled to receive a first set of pixel components in said input stream of pixels at a frequency less than said first frequency, said first analog to digital converter having an output for providing a first set of digital pixel components; a second analog to digital converter coupled to receive a second set of pixel components in said input stream of pixels at a frequency less than said first frequency, said second analog to digital converter having an output for providing a second set of digital pixel components; a first memory controller coupled to said output of said first analog to digital converter and said output of said second analog to digital converter; and a second memory controller coupled to said output of said first analog to digital converter and said output of said second analog to digital converter.

2. The display controller called for in claim 1 , further including: a first pixel processor coupling said output of said first analog to digital converter and said output of said second analog to digital converter to said first memory controller; and a second pixel processor coupling said output of said first analog to digital converter and said output of said second analog to digital converter to said second memory controller.