CN101257588B - Image processing system and method for processing television divided pictures - Google Patents
Image processing system and method for processing television divided pictures Download PDFInfo
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- CN101257588B CN101257588B CN2008100857781A CN200810085778A CN101257588B CN 101257588 B CN101257588 B CN 101257588B CN 2008100857781 A CN2008100857781 A CN 2008100857781A CN 200810085778 A CN200810085778 A CN 200810085778A CN 101257588 B CN101257588 B CN 101257588B
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Abstract
The invention relates to an image processing system and method for processing television divided pictures. The system comprises a line buffer, a first multiplexor, a video processing engine, a zoom engine and a sequence signal generation device. The line buffer is used for receiving part pixel of a first and a second video. The first multiplexor selects the part pixel of the first and the second video as the output. The video processing engine executes video processing to the output pixel from the first multiplexor. The zoom engine executes zoom calculation to the pixel after video processing and generates a part zoom pixel of the first or the second video. The sequence signal generation device generates sequence signals for the video processing engine and the zoom engine and generates enable signals corresponding to the first and the second video. The video processing engine and the zoom engine process the part pixel of the first or the second video in a multitask mode.
Description
Technical field
The invention relates to the technical field of image processing, refer to a kind of image processing system and method for handling the divided frame of TV especially.
Background technology
The function of PIP often is provided, to increase the surcharge of TV on the TV of top grade.According to the form that PIP shows, be broadly divided into PIP/divided frame (Picture-in-Picture/Picture-out-Picture, PIP/POP).Figure 1A is the sketch map of PIP (PIP), and Figure 1B is the sketch map of divided frame (POP).Can know that by Figure 1B divided frame (POP) is big or small close because of two pictures, so its image quality usually requires unanimity, so its hardware structure is complicated than the hardware structure of PIP (PIP).
Known way is to carry out the decoding of two pictures in the divided frame (POP) respectively with two groups of hardware.Fig. 2 is a known sketch map of carrying out the hardware structure of divided frame (POP).Because the input of two pictures maybe be from different image source, and its raw frames size all maybe be inequality with form, for the quality that will reach two pictures outputs respectively with big or small consistent; Outside image processor 210,220 needs independences, because the scaling of two pictures maybe be inequality; So device for zooming 230,240 also needs two cover hardware units, a cover is handled the key frame image; Another set of processing sprite image so just can reach the function of divided frame (POP).
A known TV is carried out the sketch map of divided frame (POP) among Fig. 3.Image A is different input images with image B, and video frame (video frame) size of image A and image B is different with form, so need use image processor 210,220 to handle different input images respectively.Two different image A can obtain different image output A ' and image output B ' with image B respectively through different image processor 210,220 and device for zooming 230,240.Output to a panel after through image mixing apparatus 250 two image outputs being mixed at last, just can on panel, obtain the effect that two pictures are play simultaneously.Yet aforementioned means is occupied very large tracts of land in chip, that is in order to realize the divided frame function, the chip area demand is big relatively, and the cost of integrated circuit improves thereupon, and then influences competitiveness.Hence one can see that, and the TV of known divided frame still has many shortcomings and necessity of improving is arranged.
Summary of the invention
The objective of the invention is is providing a kind of image processing system and method for handling the divided frame of TV; It only needs a cover image processing hardware can reach the function of divided frame (POP); Not only can not have influence on the speed (frame rate) of video playback, can save great amount of cost simultaneously.
According to characteristics of the present invention, be to propose a kind of image processing system of handling the divided frame of TV, it comprises a line buffer, one first multiplexer, an image processing engine, a zooming engine, reaches a clock signal generation device.This line buffer is in order to the partial pixel that receives one first image and the partial pixel of one second image, and this line buffer also can be exported the partial pixel of this first image and the partial pixel of this second image respectively.This first multiplexer has two inputs and is connected to this line buffer, with the output as this multiplexer of the partial pixel of the partial pixel of selecting this first image or this second image.This image processing engine is connected to this first multiplexer; With multitask mode the partial pixel of this first image of this first multiplexer output or the partial pixel of this second image are carried out image processing, the partial image that makes the partial image that produces this first image handle back pixel or this second image is handled the back pixel.This zooming engine is connected to this image processing engine; With multitask mode the partial image processing back pixel of this first image or the partial image of this second image are handled the computing of back pixel execution convergent-divergent, make the part convergent-divergent pixel of this first image of generation or the part convergent-divergent pixel of this second image.This clock signal generation device is connected to this multiplexer, this image processing engine, and this zooming engine, in order to the clock signal that produces this image processing engine and this zooming engine, and corresponding to the enable signal of this first image and this second image.
According to another characteristics of the present invention, be to propose a kind of image treatment method that is used to handle television divided pictures, it comprises the following step: (A) partial pixel of the partial pixel of buffer memory one first image and one second image in a line buffer; (B) this line buffer is exported the n bar line image data of this first image when the very first time; (C) this line buffer is exported the n bar line image data of this second image when second time; (D) respectively the n bar line image data of this first image and second image is carried out the convergent-divergent computing, make the part convergent-divergent pixel of this first image of generation or the part convergent-divergent pixel of this second image; (E), has the picture of this first image and the combination of this second image with generation with the part convergent-divergent pixel of this first image or the mixed back of part convergent-divergent pixel and the output of this second image.
Description of drawings
Figure 1A is the sketch map of PIP (PIP).
Figure 1B is the sketch map of divided frame (POP).
Fig. 2 is a known sketch map of carrying out the hardware structure of divided frame.
Fig. 3 is the sketch map that a known TV is carried out divided frame.
Fig. 4 is the calcspar that is used to handle the image processing system of television divided pictures of the present invention.
Calcspar when Fig. 5 is the non-execution divided frame of the present invention function.
Fig. 6 is the sketch map that clock signal generation device of the present invention produces clock signal and enable signal.
Among the figure:
Image processor 210,220
Device for zooming 230,240
Image blender 250
Zooming engine 425
Clock signal generation device 435
Image blender 430
The 3rd multiplexer 405
Temporary storage location 411,412
Embodiment
See also Fig. 4; It is a calcspar of handling the image processing system of television divided pictures of the present invention, and it comprises a line buffer 410, one first multiplexer 415, an image processing engine 420, a zooming engine 425, a clock signal generation device 435, an image blender 430, one first register 440, one second register 445, one second multiplexer 450, and one the 3rd multiplexer 405.
The 3rd multiplexer 405 is connected to this line buffer 410; In order to the partial pixel that receives one first image Stream_A and the partial pixel of one second image Stream_B, and the partial pixel of this first image Stream_A and the partial pixel of this second image Stream_B are sent to this line buffer 410 to make task state more.
This line buffer 410 is connected to the 3rd multiplexer 405, in order to the partial pixel that receives this first image Stream_A and the partial pixel of this second image Stream_B.This line buffer 410 also has two outputs, with the partial pixel of exporting this first image Stream_A respectively and the partial pixel of this second image Stream_B.
Calcspar when Fig. 5 is the non-execution divided frame of the present invention function.At this moment, the 3rd multiplexer 405 only receives the partial pixel of the first image Stream_A.This line buffer 410 is configured to store fully the partial pixel of this first image Stream_A.Please with reference to shown in Figure 4, when utilizing the present invention to carry out the divided frame function, the 3rd multiplexer 405 is sent to this line buffer 410 with multitask mode with the partial pixel of this first image Stream_A and the partial pixel of this second image Stream_B again.This line buffer 410 is configured to two temporary storage location 411,412, to keep in the partial pixel of this first image Stream_A and the partial pixel of this second image Stream_B respectively.This line buffer 410 can be connected directly to this image processing engine 420; So that the partial pixel of this first image Stream_A or the partial pixel of this second image Stream_B are carried out image processing, the partial image that makes the partial image that produces this first image Stream_A handle back pixel or this second image Stream_B is handled the back pixel.Perhaps, between this line buffer 410 and this image processing engine 420 this first multiplexer 415 can be set, export this image processing engine 420 to the partial pixel of selecting this first image Stream_A or the partial pixel of this second image Stream_B.
This zooming engine 425 is connected to this image processing engine 420; In order to the partial image processing back pixel of this first image Stream_A or the partial image of this second image Stream_B are handled the computing of back pixel execution convergent-divergent, make the part convergent-divergent pixel of this first image of generation Stream_A or the part convergent-divergent pixel of this second image Stream_B.
This image blender 430 is connected to this zooming engine 425, so that the part convergent-divergent pixel of this first image Stream_A or the part convergent-divergent pixel of this second image Stream_B are mixed, has a signal of video signal of divided frame video effect with generation.
This clock signal generation device 435 is connected to this first multiplexer 415, this image processing engine 420, and this zooming engine 425, in order to the clock signal that produces this image processing engine 420 and this zooming engine 425, and corresponding to the enable signal of this first image Stream_A and this second image Stream_B.
This clock signal and enable signal that this image processing engine 420 and this zooming engine 425 are produced according to this clock signal generation device are handled the partial pixel of this first image Stream_A or the partial pixel of this second image Stream_B with multitask mode.
Setup parameter when this first register 440 is handled the computing of back pixel execution convergent-divergent in order to the partial image of temporary 425 pairs of these first images of this zooming engine Stream_A.
Setup parameter when this second register 445 is handled the computing of back pixel execution convergent-divergent in order to the partial image of temporary 425 pairs of these second images of this zooming engine Stream_B.
This second multiplexer 450 is connected to this first register 440, this second register 445, and this zooming engine 425, the parameter setting when providing this zooming engine to carry out convergent-divergent computing.
Fig. 6 is the sketch map that clock signal generation device 435 of the present invention produces clock signal and enable signal.It is to use sequential to share the sketch map of (timing sharing) processing mode.As shown in Figure 6, represent the output line of an image in two HSYNC waveforms.Each bar image output line is controlled the data input of this image processing engine 420 with enable signal EN_A and enable signal EN_B.When enable signal EN_A was enabled, this image processing engine 420 received the image data of the first image Stream_A, output again after the execution image processing.When enable signal EN_B was enabled, this image processing engine 420 received the image data of the second image Stream_B, output again after the execution image processing.
When the clock signal of the first image Stream_A and enable signal produced, this clock signal generation device 435 was read the image data of the first image Stream_A by the temporary storage location 411 of this line buffer 410.When the clock signal of the second image Stream_B and enable signal produced, this clock signal generation device 435 was read the image data of the second image Stream_B by the temporary storage location 412 of this line buffer 410.The image data of first image like this and second image just can be delivered to this image processing engine 420 at different time.That is enable signal EN_A and enable signal EN_B can't take place simultaneously.
When the time control signal of the first image Stream_A produced, this clock signal generation device 435 can be read the required parameter of this image processing engine 420 by this first register 440.When the time control signal of the second image Stream_B produced, this clock signal generation device 435 can be read the required parameter of this image processing engine 420 by this second register 445.Can deliver to this zooming engine 425 in regular turn through these image processing engine 420 data processed afterwards.
Likewise, when the time control signal of the first image Stream_A produced, this clock signal generation device 435 can be read the required parameter of this zooming engine 425 by this first register 440.When the time control signal of the second image Stream_B produced, this clock signal generation device 435 can be read the required parameter of this zooming engine 425 by this second register 445.At last, can deliver to this image blender 430 in regular turn through these zooming engine 425 data processed.
As shown in Figure 6; When time T 1, export the n bar line image data of the first image Stream_A; When time T 2, export the n bar line image data of the second image Stream_B; When time T 3, export the n+1 bar line image data of the first image Stream_A, when time T 4, export the n+1 bar line image data of the second image Stream_B.Can every image line be combined like this, just can be combined into the picture that left one side of something is the first image Stream_A, and right one side of something be the picture of the second image Stream_B, just as using the resulting picture of two cover hardware the same.
Can know that by above-mentioned explanation known technology need use two cover image processing hardware just can reach the function at divided frame (POP).And the present invention only needs a cover image processing hardware to add that sequential control circuit can reach the function of divided frame (POP), not only can not have influence on the speed (frame rate) of video playback.Simultaneously, only use a cover image processing hardware, can save great amount of cost.
From the above, no matter the present invention all shows it be different from the characteristic of known technology, have practical value with regard to purpose, means and effect.But it should be noted that above-mentioned many embodiment give an example for the ease of explanation, the right that the present invention advocated is as the criterion with claims, but not only limits to the foregoing description.
Claims (7)
1. image processing system that is used to handle television divided pictures comprises:
One line buffer in order to the partial pixel that receives one first image and the partial pixel of one second image, and is exported the line image data of partial pixel of line image data and this second image of the partial pixel of this first image;
One image processing engine; Be connected to this line buffer; To the line image data of this first image of this line buffer output or the line image data carries out image processing of this second image, the line image data that makes the line image data that produces this first image handle back pixel or this second image is handled the back pixel with multitask mode;
One zooming engine; Be connected to this image processing engine; With multitask mode the line image data processing back pixel of this first image or the line image data of this second image are handled the computing of back pixel execution convergent-divergent, make the line image data convergent-divergent pixel of this first image of generation or the line image data convergent-divergent pixel of this second image;
One image blender connects this zooming engine, makes up with the image line that the line image data convergent-divergent pixel of the line image data convergent-divergent pixel of first image and second image is formed, and has a signal of video signal of divided frame video effect with generation; And
One clock signal generation device is connected to this image processing engine, and this zooming engine, in order to the clock signal that produces this image processing engine and this zooming engine, and corresponding to the enable signal of this first image and this second image.
2. image processing system as claimed in claim 1 is characterized in that it also comprises:
One first register, the setup parameter when the line image data of this first image being handled the computing of back pixel execution convergent-divergent in order to temporary this zooming engine;
One second register, the setup parameter when the line image data of this second image being handled the computing of back pixel execution convergent-divergent in order to temporary this zooming engine;
One second multiplexer is connected to this first register, this second register, and this zooming engine, the parameter setting when providing this zooming engine to carry out convergent-divergent computing.
3. image processing system as claimed in claim 2 is characterized in that it also comprises:
One the 3rd multiplexer; Be connected to this line buffer; In order to the partial pixel that receives this first image and the partial pixel of this second image, and the partial pixel of this first image and the partial pixel of this second image are sent to this line buffer with multitask mode.
4. image processing system as claimed in claim 1 is characterized in that, wherein this line buffer is to have a plurality of temporary storage location to keep in the partial pixel of this first image and the partial pixel of this second image respectively.
5. image processing system as claimed in claim 1 is characterized in that, wherein this clock signal generation device is that the image data of controlling this first image and this second image is delivered to this image processing engine at different time.
6. image processing system as claimed in claim 1 is characterized in that, also comprises:
One first multiplexer has two inputs that are connected to this line buffer, with the output as this first multiplexer of the line image data of the line image data of selecting this first image or this second image.
7. image processing method that is used to handle television divided pictures, it comprises the following step:
(A) partial pixel of the partial pixel of buffer memory one first image and one second image in a line buffer;
(B) this line buffer is exported the n bar line image data of this first image when the very first time;
(C) this line buffer is exported the n bar line image data of this second image when second time;
(D) respectively the n bar line image data of this first image and second image is carried out the convergent-divergent computing, make the part convergent-divergent pixel of this first image of generation or the part convergent-divergent pixel of this second image; And
(E) the every image line of the part convergent-divergent pixel of the part convergent-divergent pixel of this first image and this second image being formed mix back and output, has the picture that this first image and this second image make up with generation.
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| CN101383951B (en) * | 2008-09-25 | 2010-06-02 | 杭州爱威芯科技有限公司 | Picture splitting device |
| US20120256957A1 (en) * | 2011-04-10 | 2012-10-11 | Sau-Kwo Chiu | Image processing method of performing scaling operations upon respective data portions for multi-channel transmission and image processing apparatus thereof |
| CN111770382B (en) * | 2019-04-02 | 2022-11-18 | 瑞昱半导体股份有限公司 | Video processing circuit and method for processing multiple videos using a single video processing path |
| CN110413822B (en) * | 2019-06-19 | 2021-11-19 | 北京旷视科技有限公司 | Offline image structured analysis method, device and system and storage medium |
| CN113905171B (en) * | 2020-07-06 | 2024-04-26 | 瑞昱半导体股份有限公司 | Multi-path image processing device and method |
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