WO1999016223A1

WO1999016223A1 - Modulator/demodulator and modulation/demodulation method

Info

Publication number: WO1999016223A1
Application number: PCT/JP1998/004147
Authority: WO
Inventors: Yoshikazu Hayashi; Ippei Kanno; Mikihiro Ouchi
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 1997-09-19
Filing date: 1998-09-16
Publication date: 1999-04-01
Also published as: CN100375475C; CN1239621A; KR100365982B1; KR20000068952A

Abstract

A modulator/demodulator and a method by which carrier synchronization of time division multiplex n-phase PSK modulated signals is performed stably at high speed by means of a demodulator when the C/N is low. The modulator performs time division multiplexing so as to insert BPSK-modulate carrier-synchronization auxiliary signals (or carrier-synchronization auxiliary signals upon which the differentially encoded number-of-phases information of the PSK-modulated wave of the next packet is superposed) into each packet in the cycle of the packets which are the minimum units where the modulating systems change. The demodulator performs carrier reproduction by extracting the BPSK-modulated carrier-synchronization auxiliary signals (and BPSK-modulated main signals).

Description

Description Modulation and demodulation device and method

The present invention relates to a modulation / demodulation device and method, and more particularly, to a modulation / demodulation device and method used in a digital satellite broadcasting system. Background art

Conventionally, as a modulator and a method used in a digital satellite broadcasting system, a paper by Kato and Hashimoto, “Study of Satellite I SDB Transmission Method,” ITE Technical Report, BCS'97-12 (Mar. l997) (hereinafter referred to as conventional literature) is known.

The modulation device and method described in this conventional document make it possible to transmit two data streams independently. That is, error correction is performed independently on the low-layer signal and the high-layer signal, and the low-layer signal and the high-layer signal are collected by an appropriate number of buckets to form a frame having a fixed total number of packets. I do. Here, the conventional modulation device performs BP SK (Binary Phase Shift Keying) or QP SK (Quaternary Phase Shift Keying) on the lower layer signal, and applies the higher layer signal to the lower layer signal. Is subjected to 8 P SK (8 phase shift keying) and transmitted by time division multiplexing. In addition, the conventional modulation device transmits the frame synchronization signal and a transmission multiplexing configuration control (TMCC) signal indicating a division of each layer in the frame and a modulation mode of each layer to the lowest C / N (carrier wave). Power / noise power) and transmit with BP SK, which enables stable reception.

The conventional modulation device and method will be briefly described below with reference to FIGS. I do. FIG. 77 is a block diagram showing a configuration of a conventional modulation device. FIG. 78 is a diagram showing the structure of a communication frame output from a conventional demodulation device. FIG. 79 is a diagram illustrating mapping of BPSK, QPSK, and 8PSK to a code arrangement. FIG. 80 is a diagram showing a data structure and a frame structure of an MPEG in a conventional modulation device and method.

In FIG. 77, the conventional modulation device includes a frame synchronization signal / TMCC signal generation unit 1001, a TS packet synthesis unit 1002, a TMCC error correction coding unit 1003, a first error correction coding unit 1004, A frame synchronization signal / TMCC signal including an error correction coding unit 1005, a BPSK mapping unit 1006, a BPSK / QP SK mapping unit 1007, an 8P SK mapping unit 1008, and a multiplexing / quadrature modulation unit 1009. The generation unit 1001 generates a frame synchronization signal / TMCC signal based on the input TMCC information. The frame synchronization signal / TMCC signal is subjected to error correction coding in TMCC error correction coding section 1003, and then input to BPSK mapping section 1006. BP SK mapping section 1006 maps the input frame synchronization signal and TMCC signal to the BP SK code arrangement shown in FIG. 79 (a), and outputs the result to multiplexing / quadrature modulation section 1009.

The TS packet combining unit 1002 combines a plurality of input MPEG-TS packets (FIG. 80 (a)), and is composed of a group of low-layer signal packets and a group of high-layer signal packets. A frame with a fixed number of packets (Fig. 80 (b)) is generated. In this frame, the packet group of the low-layer signal is subjected to error correction coding in the first error correction coding unit 1004, and is then input to the BP SK / QP SK mapping unit 1007. The BPSK / QPSK mapping section 1007 maps the input lower-layer signal to the BP SK code arrangement shown in FIG. 79 (a) or the QPSK code arrangement shown in FIG. 79 (b), and performs multiplexing / orthogonality. Output to modulation section 1009 . On the other hand, among the above-mentioned frames, the packet group of the high-layer signal is subjected to error correction coding in the second error correction coding section 1005, and then input to the 8PSK matching section 1008. The 8PSK mapping unit 1008 converts the input high-layer signal

9 is mapped to the 8 PSK code arrangement shown in (c) and output to the multiplexing / orthogonal modulation section 1009.

Then, multiplexing / quadrature modulation section 1009 time-division multiplexes the signals input from each mapping section in the arrangement shown in FIG. 78 to generate a communication frame, and then performs quadrature modulation and outputs the result to the demodulation device . Here, as can be seen from FIG. 78, the multiplexing / quadrature modulation section 1009 includes a frame synchronization signal and a TMCC signal to which BP SK has been applied, a packet group of a higher layer signal to which 8P SK has been applied, and a BPSK or QP SK Then, time-division multiplexing is performed in units of bucket groups of the low-layer signals subjected to, and a communication frame is generated.

Next, a demodulation device for inputting and demodulating a communication frame generated by the conventional modulation device will be described with reference to FIG. FIG. 81 is a block diagram showing a configuration of a conventional demodulation device.

In FIG. 81, a conventional demodulator includes a quadrature detector 1101 and a PSK demodulator 1

102, a BER (Bit Error Rate) detection unit 1103, a TMCC decoder 1104, an error correction unit 1105, and a video decoder 1106.

The communication frame transmitted from the modulation device is input to quadrature detection section 1101. The quadrature detection unit 1101 performs quadrature detection on each signal in the input communication frame by the internal local oscillator and digitizes the signals. 81 (Output to demodulation unit 1102 and TMC C decoder 1104.

First, the demodulation unit 1102 performs frequency correction and phase correction assuming that all signals of the input communication frame have been subjected to 8PSK, and performs demodulation into I and Q signals. Here, the TMC C decoder 1104 detects the frame synchronization signal to which BPSK has been applied in this state, recognizes the beginning of the communication frame, and simultaneously It detects at which phase of the phase the phase SK demodulation section 1102 is in phase synchronization. Further, the TMCC decoder 1104 detects the TMCC signal following the frame synchronization signal to identify the configuration of the phase modulation applied to each hierarchical signal, and detects the TMCC signal on the demodulator side in the phase error detection for phase correction. Switch the phase reference to the one corresponding to each phase modulation.

And? 31 <The demodulation unit 1102 remaps the demodulated I and Q signals based on the phase information indicating which phase of the eight phases was synchronized, and converts them into absolute phase I and Q signals. And outputs it to the error correction unit 1105 at the subsequent stage.

The error correction unit 1105 has two independent error correction circuits, and decodes the signal demodulated by the demodulation unit 1102 in packets. After sorting and error correction, the order of the packets rearranged on the time axis for time division multiplex transmission is restored, and this output is output to the video decoder 1106.

The 8 × 1 detection unit 1103 performs trellis encoding again on a signal obtained by performing trellis decoding on the demodulated 8 PSK signal to which trellis encoding, which is a type of error correction encoding, is performed. The BER of the higher layer signal is monitored by comparing with the demodulated 8 PSK signal. As a result, if it is determined that the quality of the decoded video of the higher hierarchy is lower than the allowable value, the BER detector 1103 outputs a video signal of the lower hierarchy that is highly resistant to the quality deterioration of the transmission path. The signal is controlled by the video decoder 1106 as described above.

With the above-described processing, the conventional modulation and demodulation apparatus and method allow the user to continue viewing the service even if the quality of the transmission path deteriorates due to rainfall during reception.

As described above, in the above-described conventional modulation device, error correction is performed independently on the low-layer signal and the high-layer signal, and BPSK or QPSK with low transmission efficiency but high transmission reliability is applied to the low-layer signal. Transmission efficiency is high but transmission reliability is high for high layer signals Are applied, and they are transmitted by time division multiplexing.

On the other hand, in the above-mentioned conventional demodulator, first, all the signals of the input communication frame are regarded as signals to which 8PSK has been applied, and the frequency correction and the phase correction are performed. After carrier synchronization, the TMCC signal is decoded, the phase modulation configuration applied to each hierarchical signal is identified, demodulated for each signal, and the BER is detected to reduce the quality of the transmission path. On the other hand, a low-hierarchy signal with high tolerance can be selected.

However, in the above-mentioned conventional demodulator, when power is turned on or channel selection is performed at low C / N where demodulation (frequency correction and phase correction) using 8PSK cannot be performed, carrier synchronization cannot be performed. There was a problem that they could not watch.

Therefore, an object of the present invention is to provide a modulation and demodulation apparatus and method capable of performing stable and high-speed carrier synchronization even when an operation such as turning on the power of the demodulation apparatus or selecting a channel is performed at a low C / N. It is to provide. Disclosure of the invention

A first aspect is a modulation device that generates a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiency for each layer of the data on a plurality of data to be communicated. ,

Phase modulation means for performing a phase modulation corresponding to the contents of each of the plurality of data to generate a modulation signal,

Signal generating means for generating a carrier synchronization auxiliary signal that has been subjected to phase modulation using phase modulation with the smallest number of phases (hereinafter referred to as minimum phase modulation) among a plurality of phase modulations applied to data;

Multiplexing means for time-division multiplexing the modulation signal and the carrier synchronization auxiliary signal so that the carrier synchronization auxiliary signal is dispersed at equal time intervals within the communication frame. As described above, according to the first aspect, the signal for assisting carrier synchronization in the demodulator is modulated by strong minimum phase modulation for a low C / N state, and dispersed and inserted into a packet. Output communication frame. As a result, in the demodulator, even in the low C / N state, high-speed and stable carrier synchronization can be performed using the carrier synchronization auxiliary signal dispersed in the bucket.

The second aspect is characterized in that, in the first aspect, the carrier synchronization auxiliary signal is time-division multiplexed continuously for two or more symbols.

As described above, the second aspect specifies a typical time-division multiplexing form of the carrier synchronization auxiliary signal in the first aspect.

In a third aspect, in the first and second aspects, the carrier synchronization auxiliary signal is a phase modulation signal applied to a modulation signal serving as a next packet with respect to a time division multiplexed position in a communication frame. Is characterized by superimposing information for identifying.

As described above, according to the third aspect, in the first and second aspects, a signal for assisting carrier synchronization in a demodulation device in which information defining the modulation scheme of the next packet is superimposed is reduced. The communication frame is modulated by the minimum phase modulation that is strong against the C / N state, and the communication frame that is dispersedly inserted in the packet is output. As a result, in the demodulator, even in the low C / N state, carrier synchronization can be performed at high speed and stably using the carrier synchronization auxiliary signal dispersed in the packet and the main signal subjected to the minimum phase modulation.

A fourth aspect is the third aspect, further comprising a differential encoding unit that performs differential encoding on an input signal and outputs the result.

The signal generation means generates a carrier synchronization auxiliary signal obtained by performing a minimum phase modulation among a plurality of phase modulations performed on the signal after the differential encoding in the differential encoding means. It is characterized by the following.

As described above, according to the fourth aspect, in the third aspect, a signal for assisting carrier synchronization in a demodulation device on which information defining a modulation scheme of a next packet is superimposed. Is generated after differential encoding is performed. As a result, the modulation method information can be decoded even in a state where the carrier is not synchronized in the demodulation device.

The fifth aspect is a modulation method for generating a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiency for each layer of the data on a plurality of data to be communicated. So,

A carrier synchronization auxiliary signal that has been subjected to phase modulation using the phase modulation with the smallest number of phases (hereinafter referred to as the minimum phase modulation) among the plurality of phase modulations performed overnight is generated. Are time-division multiplexed so that they are distributed at equal time intervals within a communication frame.

As described above, according to the fifth aspect, a signal that assists carrier synchronization during demodulation operation is modulated by strong minimum phase modulation for a low C / N state, and dispersed in a packet. Construct the inserted communication frame. As a result, at the time of demodulation operation, even in a low C / N state, high-speed and stable carrier synchronization can be performed using the carrier synchronization auxiliary signal dispersed in the bucket.

A sixth aspect is characterized in that in the fifth aspect, the carrier synchronization auxiliary signal is time-division multiplexed continuously for two or more symbols.

As described above, the sixth aspect specifies a typical time-division multiplexing form of the carrier synchronization auxiliary signal in the fifth aspect.

According to a seventh aspect, in the fifth and sixth aspects, the carrier synchronization auxiliary signal is a phase modulation signal applied to a modulation signal serving as a next packet with respect to a time division multiplexed position in a communication frame. Is characterized by superimposing information for identifying.

As described above, according to the seventh aspect, in the fifth and sixth aspects, at the time of demodulation operation, a signal for assisting carrier synchronization in which information defining a modulation scheme of the next bucket is superimposed, It modulates by the strong minimum phase modulation for the low C / N state, and outputs the communication frame dispersedly inserted in the packet. As a result, in the demodulation operation, the carrier synchronization auxiliary signal dispersed in the packet even in the low C / N state Carrier synchronization can be performed at high speed and stably using the main signal subjected to signal and minimum phase modulation.

In an eighth aspect, in the seventh aspect, the carrier synchronization auxiliary signal is obtained by performing a minimum phase modulation of a plurality of phase modulations performed on the signal after differential encoding on the signal after the differential encoding. It is characterized by being generated by

As described above, according to the eighth aspect, in the seventh aspect, in the demodulation operation, a signal for assisting carrier synchronization in which information defining a modulation scheme of the next bucket is superimposed is differentially encoded. Is generated after applying. As a result, the modulation method information can be decoded even when the carrier is not synchronized during the demodulation operation. The ninth aspect is that a carrier synchronization auxiliary signal that has been phase-modulated using the phase modulation having the smallest number of phases in a communication frame (hereinafter referred to as minimum phase modulation) together with a plurality of phase-modulated signals is transmitted at equal time intervals. A demodulator that receives the communication frame time-division multiplexed so as to be dispersed,

Frequency correction means for detecting a frequency error in a predetermined signal period in a communication frame and correcting a frequency deviation,

Phase correction means for detecting a phase error during a predetermined signal period in a communication frame and correcting a phase shift;

Frame synchronization detection means for receiving an output signal of either the frequency correction means or the phase correction means and detecting a synchronization signal of the communication frame using delay detection to detect a frame head position;

Timing for detecting at least the period of the carrier synchronization auxiliary signal (hereinafter referred to as a synchronization signal period) in the period in which the minimum phase modulation is performed based on the frame head position detected by the frame synchronization detection means, and providing the synchronization signal period And a evening generating means for generating a signal.

The frequency correction means and the phase correction means perform a correction operation according to the minimum phase modulation during a synchronization signal period given by the evening imaging signal. As described above, according to the ninth aspect, of the time-division multiplexed phase-modulated signals, the frequency correction and the phase correction are performed using the minimum phase-modulated signal including the carrier synchronization auxiliary signal dispersedly arranged in the bucket. Carrier recovery) enables fast and stable carrier synchronization even in the low C / N state.

In a tenth aspect, in the ninth aspect, the output signal of any one of the frequency correction means and the phase correction means is input, and a frequency pull-in state is detected to determine whether or not the frequency is a frequency at which the phase correction means is pseudo-synchronized. Frequency pull-in detection means for determining

As a result of the determination by the frequency pull-in detection means, when the frequency correction by the frequency correction means is completed to a frequency at which the phase correction means does not perform pseudo-synchronization, phase correction reset means for initializing the phase correction means is further provided. And

As described above, according to the tenth aspect, in the ninth aspect, the frequency pull-in detection means is provided, and the frequency correction is performed by the frequency correction means up to a frequency at which the phase correction means is not pseudo-synchronized. Initialize and restart the means. This makes it possible to avoid pseudo-synchronization in the phase correction unit in the frequency pull-in process by the frequency correction unit.

The eleventh aspect is the ninth aspect, wherein the output signal of the phase correction means is input, and a phase synchronization detection means for detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal;

Error correction detecting means for detecting a correction state of an error correction process of a transmission control signal (TMC C signal) included in the frame synchronization signal;

Pseudo-synchronization determining means for determining whether or not pseudo-synchronization is performed based on detection results of the phase synchronization detecting means and the error correction detecting means;

If the result of the determination by the pseudo-synchronization determining means is pseudo-synchronization, the apparatus further comprises phase correction reset means for initializing the phase correction means.

As described above, according to the eleventh aspect, in the ninth aspect, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of the possibility of error correction of the TMCC signal are performed. Is performed, and it is determined whether or not the synchronization is normal based on the detection result. Then, in the case of the pseudo synchronization, the phase correction means is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase correction means in the frequency pull-in process by the frequency correction means.

In a twelfth aspect, in the ninth aspect, a first phase synchronization detecting means for inputting an output signal of the phase correction means and detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal,

Second phase synchronization detection means for receiving an output signal of the phase correction means and detecting a state of phase synchronization during a transmission control signal (TMC C signal) included in the frame synchronization signal;

Pseudo-synchronization determining means for determining whether or not to perform pseudo-synchronization based on detection results of the first phase synchronization detecting means and the second phase synchronization detecting means,

As described above, according to the twelfth aspect, in the ninth aspect, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of phase synchronization during the period of the frame synchronization signal / TMCC signal are performed. Then, based on the detection result, it is determined whether the synchronization is normal. Then, in the case of the pseudo synchronization, the phase correction means is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase complementing means in the frequency pull-in process by the frequency correcting means.

According to a thirteenth aspect, in the ninth aspect, a phase synchronization detecting means for receiving an output signal of the phase correcting means and detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal,

Judgment of pseudo-synchronization based on detection results of phase synchronization detection means and error correction detection means Pseudo synchronization determination means,

If the result of the determination by the pseudo-synchronization determining means is pseudo-synchronization, the method further comprises frequency step means for stepwise changing the frequency input to the phase correction means.

As described above, according to the thirteenth aspect, in the ninth aspect, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of the possibility of error correction of the TMCC signal are performed. To determine whether or not the synchronization is normal. Then, in the case of the pseudo synchronization, the frequency of the frequency correcting means is controlled so that the phase correcting means can perform normal synchronization. This makes it possible to avoid pseudo-synchronization in the phase correction means in the frequency pull-in process by the frequency correction means.

In a fourteenth aspect, in the ninth aspect, the first phase synchronization detection means receives the output signal of the phase correction means and detects a state of phase synchronization during a period of the carrier synchronization auxiliary signal,

As described above, according to the fourteenth aspect, in the ninth aspect, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of phase synchronization during the period of the frame synchronization signal / TMCC signal are performed. Then, based on the detection result, it is determined whether the synchronization is normal. In the case of pseudo synchronization, the frequency of the frequency correction means is controlled so that the phase correction means can perform normal synchronization. As a result, the frequency correction means In the wave number pull-in process, etc., it becomes possible to avoid pseudo synchronization in the phase correction means.

According to a fifteenth aspect, in the thirteenth aspect, an output signal of either the frequency correction means or the phase correction means is input, and a frequency pull-in state is detected to determine whether or not the frequency is a frequency at which the phase correction means is pseudo-synchronous. Frequency pull-in detection means for determining whether

In a sixteenth aspect, in the fourteenth aspect, an output signal of either the frequency correction means or the phase correction means is input, and a frequency pull-in state is detected to determine whether or not the frequency is such that the phase correction means is in a pseudo-synchronous state. Frequency pull-in detection means for determining whether

As described above, according to the 15th and 16th aspects, the 13th and 14th stations are further provided with frequency pull-in detection means, and the phase correction means is not pseudo-synchronized in the frequency correction means After the frequency has been corrected to the frequency, initialize the phase correction means and restart the operation. This makes it possible to avoid pseudo-synchronization in the phase correction means in the frequency pull-in process by the frequency correction means.

In a seventeenth aspect, in the ninth aspect, the frame synchronization determination means for receiving an output signal of the phase correction means and detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal,

C / N detection means for receiving the output signal of the phase correction means and detecting the state of C / N (carrier power / noise power) of the received signal;

Based on the detection result of the frame synchronization determination means and C / N detection means, and the timing signal, there is phase synchronization, and the C / N is higher than a predetermined threshold. Further comprises a gate signal generating means for generating a gate signal for giving the entire period of the communication frame, and in other cases, a gate signal generating means for generating a gate signal for giving a synchronous signal period. During the synchronization signal period, the phase error due to the minimum phase modulation is detected. Outside the synchronization signal period, after detecting the phase error due to the phase modulation having the largest number of phases in the communication frame, correction is performed according to the period given by the gate signal. The operation is performed.

As described above, according to the seventeenth aspect, in the ninth aspect, the C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected, and the C / N is determined in advance. If the signal level is at a lower level, the phase error is corrected assuming that the maximum phase modulation is also performed for the main signal period of the communication frame. As a result, carrier synchronization can be performed quickly and stably even in a low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

In an eighteenth aspect, in the ninth aspect, a frame synchronization determining means for inputting an output signal of the phase correction f stage and detecting phase synchronization in the phase correcting means,

In the communication frame, a signal period giving means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period;

Demodulation mode switching means for outputting a demodulation mode signal for switching the demodulation method in the phase correction means in accordance with the phase modulation method based on the signal output from the signal period providing means and the timing signal;

Based on the detection results of the frame synchronization determining means, the C / N detecting means and the error correction detecting means, and the signal and the timing signal output by the signal period providing means,

If there is phase synchronization and error correction is completed, If the C / N is higher than the predetermined first threshold, the gate signal that gives the entire period of the communication frame is

If the C / N is lower than the second predetermined threshold, the gate signal giving the period of the signal subjected to the minimum phase modulation is

Otherwise, generate a gate signal that provides a minimum phase modulation period and a predetermined modulation signal period,

A gate signal generating means for generating a gate signal for providing a synchronization signal period except when the phase is synchronized and the error correction is completed;

The phase correction means detects a phase error by a phase modulation method according to a demodulation mode signal, and performs a correction operation in accordance with a period given by the gate signal.

As described above, according to the eighteenth aspect, in the ninth aspect, the C / N state when phase synchronization is performed during the minimum phase modulation signal period is detected, and the C / N state and the C / N state are detected. In the initial state, phase correction is performed using the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period that are minimum phase-modulated according to the reference phase corresponding to the phase modulation method according to the demodulation mode signal. After the phase synchronization, the phase correction is performed also in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed rapidly and stably even in a low C / N state, and the effect of the phase jitter of the demodulated signal during the main signal period can be reduced to improve the reception performance. it can. In a ninth aspect, in the ninth aspect, a frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

In the communication frame, a signal period giving means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period; Demodulation mode that switches the demodulation method in the phase correction means according to the phase modulation method based on the detection results of the frame synchronization determination means and the error correction detection means, and the signal and the timing signal output by the signal period providing means. Demodulation mode switching means for outputting a signal;

Based on the detection results of the frame synchronization determining means, the C7N detecting means and the error correction detecting means, and the signal and the timing signal output by the signal period providing means,

If there is phase synchronization and error correction is completed,

If the C / N is higher than the predetermined first threshold, the gate signal that gives the entire period of the communication frame is

If the C / N is lower than the second predetermined threshold value, the gate signal that gives the period of the signal subjected to the minimum phase modulation is

If there is phase synchronization and error correction has not been completed,

If C / N is lower than the second predetermined threshold, a gate signal giving a synchronization signal period is generated,

When there is no phase synchronization, further comprising a gate signal generation means for generating a gate signal for giving a synchronization signal period;

If the error correction is not completed, the phase correction means detects the phase difference due to the minimum phase modulation during the synchronization signal period given by the timing signal, and uses the phase modulation having the largest number of phases in the communication frame during periods other than the synchronization signal period. When the phase error is detected and the error correction is completed, the phase error is detected by the phase modulation method according to the demodulation mode signal, and then the correction operation is performed according to the period given by the gate signal. As described above, according to the nineteenth aspect, in the ninth aspect, the C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected, and the C / N is determined in advance. If the level is the highest level, the phase error is corrected assuming that the maximum phase modulation is performed in all periods other than the synchronization signal period in the communication frame, and the phase modulation method according to the demodulation mode signal is supported. According to the reference phase, phase correction is performed using the frame synchronization signal / TMCC signal period and carrier synchronization auxiliary signal period that are initially phase-modulated at the initial state, and phase correction is also performed during the main signal modulation period other than the period. . As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

In a twentieth aspect, in the ninth aspect, the frame synchronization determination means for receiving an output signal of the phase correction means and detecting phase synchronization in the phase correction means,

Measures the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detects the state of C / N (carrier power / noise power) based on the bit error rate. BER detection means,

If there is phase synchronization based on the detection result of the frame synchronization determination means and BER detection means and the timing signal, and the C / N is higher than a predetermined threshold, a gate that gives the entire period of the communication frame And a gate signal generating means for generating a gate signal for providing a synchronization signal period otherwise, wherein the phase correction means performs minimum phase modulation during a synchronization signal period provided by the timing signal. Then, after detecting the phase error, detecting the phase error due to the phase modulation having the largest number of phases in the communication frame during the period other than the synchronization signal period, the correction operation is performed according to the period given by the gate signal.

As described above, according to the 20th aspect, in the ninth aspect, the C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal However, if the C / N is at a predetermined level, The phase error is corrected assuming that the maximum phase modulation is also performed for the main signal period. As a result, carrier synchronization can be performed quickly and stably even in a low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

In a twelfth aspect, in the ninth aspect, a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means,

Measures the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detects the state of C / N (carrier power / noise power) based on the bit error rate BER detection means;

Based on the detection results of the frame synchronization determining means, the B ER detecting means and the error correction detecting means, and the signal and the timing signal output by the signal period providing means,

If there is phase synchronization and error correction is completed,

Unless phase synchronization is performed and error correction is completed, a synchronization signal period is added. And a gate signal generating means for generating a gate signal for detecting a phase error by a phase modulation method according to a demodulation mode signal, and performing a correcting operation according to a period given by the gate signal. I do.

As described above, according to the twenty-first aspect, in the ninth aspect, the C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal According to the C / N state and the reference phase corresponding to the phase modulation method according to the demodulation mode signal, the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period, which are minimum phase modulated in the initial state, are used. After the phase synchronization, the phase correction is performed also in the main signal modulation period other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

In a twelfth aspect, in the ninth aspect, a frame synchronization determining means for receiving an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means,

Demodulation mode for switching the demodulation method in the phase correction means according to the phase modulation method based on the detection results of the frame synchronization determination means and the error correction detection means, and the signal and the timing signal output by the signal period giving means. Demodulation mode switching means for outputting a signal;

Detection results of the frame synchronization determination means, the BER detection means and the error correction detection means, Based on the signal and the timing signal output by the signal period giving means,

If there is phase synchronization and error correction is completed,

If there is phase synchronization and error correction has not been completed,

If the error correction is not completed, the phase correction means detects the phase difference due to the minimum phase modulation during the synchronization signal period given by the timing signal, and uses the phase modulation having the largest number of phases in the communication frame during periods other than the synchronization signal period. Detecting the phase error and, if the error correction has been completed, detecting the phase error by the phase modulation method according to the demodulation mode signal, and then performing the correction operation according to the period given by the gate signal. As described above, according to the second aspect, in the ninth aspect, the C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal. However, if the C / N is at a predetermined level, it is assumed that the maximum phase modulation is performed in all periods other than the synchronization signal period in the communication frame, and the phase error is corrected. , The groups corresponding to the phase modulation method in accordance with the demodulation mode signal In accordance with the quasi-phase, the phase is corrected using the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period that are minimum phase modulated in the initial state, and after the phase synchronization, the phase is corrected even during the main signal modulation period other than the period. Make corrections. As a result, carrier synchronization can be performed quickly and stably even in a low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced to improve the reception performance. .

According to a twenty-third aspect, in the tenth to sixteenth aspects, an output signal of the phase correction means is input, a frame synchronization determination means for detecting phase synchronization in the phase correction means, and an output signal of the phase correction means. C / N detection means for inputting and detecting the state of C / N (carrier power / noise power) of the received signal;

Based on the detection result of the frame synchronization judgment means and CZN detection means, and based on the timing signal, if there is phase synchronization and the C / N is higher than a predetermined threshold, a gate that gives the entire period of the communication frame And a gate signal generating means for generating a gate signal for providing a synchronization signal period otherwise, wherein the phase correction means performs minimum phase modulation in a synchronization signal period provided by the timing signal. After detecting a phase error and detecting a phase error due to phase modulation having the largest number of phases in a communication frame during a period other than the synchronization signal period, a correction operation is performed according to a period given by the gate signal.

In a twenty-fourth aspect, in the tenth, the twenty-second, the fourteenth, and the sixteenth aspect, a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means When,

In the communication frame, a signal giving the period of each phase modulation signal other than the synchronization signal period Signal period giving means for outputting a signal,

If there is phase synchronization and error correction is completed,

The phase correction means detects a phase error by a phase modulation method according to a demodulation mode signal, and performs a correction operation according to a period given by a gate signal.

According to a twenty-fifth aspect, in the eleventh, thirteenth, and fifteenth aspects, a frame synchronization determination unit that inputs an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

A demodulation mode signal for switching the demodulation method in the phase correction means in accordance with the phase modulation method based on the signal output by the signal period providing means and the timing signal. A demodulation mode switching means,

If there is phase synchronization and error correction is completed,

A gate signal generating means for generating a gate signal for providing a synchronization signal period except when the phase synchronization is performed and the error correction is completed;

According to a twenty-sixth aspect, in the tenth, the twelve-fourth, the fourteenth and the sixteenth aspect, a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means When,

C / N detection means for inputting the output signal of the phase correction means and detecting the state of C / N (carrier power / noise power) of the received signal;

Demodulation mode that switches the demodulation method in the phase correction means according to the phase modulation method based on the detection results of the frame synchronization determination means and the error correction detection means, and the signal and the timing signal output by the signal period providing means. Demodulation module that outputs signals Mode switching means,

If there is phase synchronization and error correction is completed,

If there is phase synchronization and error correction has not been completed,

If the C / N is lower than the second predetermined threshold, a gate signal giving a synchronization signal period is generated,

A gate signal generating means for generating a gate signal for providing a synchronization signal period when there is no phase synchronization;

If the error correction is not completed, the phase correction means detects the phase difference due to the minimum phase modulation during the synchronization signal period given by the timing signal, and uses the phase modulation having the largest number of phases in the communication frame during periods other than the synchronization signal period. When the phase error is detected and the error correction is completed, the phase error is detected by the phase modulation method according to the demodulation mode signal, and then the correction operation is performed according to the period given by the gate signal. According to a seventh aspect, in the eleventh, the thirteenth, and the fifteenth aspect, an output signal of the phase correction means is input, and frame synchronization determination means for detecting phase synchronization in the phase correction means, C / N detection means for receiving the output signal of the phase correction means and detecting the state of C / N (carrier power / noise power) of the received signal;

If there is phase synchronization and error correction is completed,

If there is phase synchronization and error correction has not been completed,

If the error correction is not completed, the phase correction means detects a phase difference due to the minimum phase modulation during a synchronization signal period provided by the timing signal, and performs communication during periods other than the synchronization signal period. In the frame, the phase error due to phase modulation with the largest number of phases is detected, and if the error correction has been completed, the phase error due to the phase modulation method according to the demodulation mode signal is detected, and then, according to the period given by the gate signal In a twenty-eighth aspect, a correction operation is performed. In the tenth to sixteenth aspects, a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means And the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction is measured, and the state of C / N (carrier power / noise power) is determined based on the bit error rate. BER detection means for detecting,

If there is phase synchronization based on the detection result of the frame synchronization determination means and BER detection means and the timing signal, and the C / N is higher than a predetermined threshold, a gate that gives the entire period of the communication frame And a gate signal generating means for generating a gate signal for providing a synchronization signal period otherwise, wherein the phase correction means performs minimum phase modulation in a synchronization signal period provided by the timing signal. After detecting a phase error and detecting a phase error due to phase modulation having the largest number of phases in a communication frame during a period other than the synchronization signal period, a correction operation is performed according to a period given by a gate signal.

In a twentieth aspect, in the tenth, twenty-second, fourteenth, and sixteenth aspects, the frame synchronization determination means receives the output signal of the phase correction means and detects phase synchronization in the phase correction means. When,

If there is phase synchronization and error correction is completed,

In a thirtieth aspect, in the eleventh, thirteenth, and fifteenth aspects, an output signal of the phase correction means is input, and frame synchronization determination means for detecting phase synchronization in the phase correction means,

A phase correction method is performed based on the signal output from the signal period providing means and the timing signal. Demodulation mode switching means for outputting a demodulation mode signal for switching the demodulation method in the stage according to the phase modulation method;

If there is phase synchronization and error correction is completed,

According to a thirty-first aspect, in the tenth, the twelfth, the fourteenth and the sixteenth aspect, a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means When,

Detection result of frame synchronization judgment means and error correction detection means, and signal period Demodulation mode switching means for outputting a demodulation mode signal for switching the demodulation method in the phase correction means in accordance with the phase modulation method based on the signal output by the applying means and the timing signal;

If there is phase synchronization and error correction is completed,

If there is phase synchronization and error correction has not been completed,

If the error correction is not completed, the phase correction means detects the phase difference due to the minimum phase modulation during the synchronization signal period given by the timing signal, and uses the phase modulation having the largest number of phases in the communication frame during periods other than the synchronization signal period. When the phase error is detected and the error correction is completed, the phase error is detected by the phase modulation method according to the demodulation mode signal, and then the correction operation is performed according to the period given by the gate signal. The second aspect is the phase correction means according to the first, first, third, and fifteenth aspects. Frame synchronization determining means for inputting the output signal of

Measures the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detects the state of C / N (carrier power Z noise power) based on the bit error rate. BER detection means,

If there is phase synchronization and error correction is completed,

If there is phase synchronization and error correction has not been completed,

If there is no phase synchronization, a gate that generates a gate signal that gives the synchronization signal period Signal generation means,

If the error correction is not completed, the phase correction means detects the phase difference due to the minimum phase modulation during the synchronization signal period given by the timing signal, and uses the phase modulation having the largest number of phases in the communication frame during periods other than the synchronization signal period. When the phase error is detected and the error correction is completed, after detecting the phase error by the phase modulation method according to the demodulation mode signal, the correction operation is performed according to the period given by the gate signal. As described above, the 23rd to 32nd aspects are combinations of the 10th to 16th aspects and the 17th to 22nd aspects, respectively. Therefore, the 23rd to 32nd stations can carry out carrier synchronization stably at high speed even in the low C / N state, respectively, and in the frequency pull-in process by the frequency correction means, etc. Pseudo-synchronization can be avoided, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced to improve the reception performance.

According to a third aspect, in the ninth to thirty-second aspects, the frame synchronization detection means includes: a delay detection means for delay-detecting the signal;

One or more phase identification means for identifying the transmitted signal from the differentially detected phase modulated signal;

Matching means for performing pattern matching between the output of one or more phase identification means and the frame synchronization signal,

One or more of the phase discrimination means has a phase discrimination area corresponding to the phase modulation for transmitting the frame synchronization signal, and the two or more phase discrimination areas are provided in parallel with different phase rotations. ,

The matching means is characterized in that pattern matching is performed on each output of the phase identification means having different phase rotation amounts in the phase identification area.

In a thirty-fourth aspect, in the ninth to thirty-second aspects, the frame synchronization detection means includes: a delay detection means for delay-detecting the signal; A plurality of phase rotation means for applying a predetermined number of types of phase rotation to the differential detection signal; a phase identification means for performing phase identification for each output of the plurality of phase rotation means; an output of the phase identification means; and a frame synchronization signal. Matching means for performing pattern matching of

The phase discrimination means has a phase discrimination region corresponding to the phase modulation in which the frame synchronization signal is transmitted, and discriminates a signal transmitted with respect to each phase modulation signal to which a different phase rotation is given by delay detection. ,

The matching means performs pattern matching on each output of the phase identification means.

A thirty-fifth aspect is the ninth to thirty-second aspect, wherein the frame synchronization detection means includes: a delay detection means for delay-detecting the signal;

Phase identification means for identifying a signal transmitted from the differentially detected phase modulation signal, identification phase rotation means for rotating the identification phase of the phase identification means,

A matching means for comparing the output of the phase identification means and the pattern of the frame synchronization signal,

The phase identification means has a phase identification area corresponding to the phase modulation for transmitting the frame synchronization signal, and the phase rotation means determines the phase of the phase identification area in the phase identification means until the matching means detects the frame synchronization signal. It is characterized by rotating.

According to a sixth aspect, in the ninth to thirty-second aspects, the frame synchronization detection means includes: a delay detection means for delay-detecting the signal;

Phase rotation means for performing phase rotation on the differential detection signal,

Phase identification means for receiving an output of the phase rotation means and identifying a signal transmitted from the differentially detected phase modulation signal;

A matching means for comparing the output of the phase identification means and the pattern of the frame synchronization signal, The phase rotation unit rotates the phase until the frame synchronization signal is detected by the matching unit.

As described above, the 33rd to 36th aspects show typical configurations of the ninth to 32nd frame synchronization detecting means. Thus, even when the input frequency error is large, it is possible to eliminate the malfunction of frame synchronization detection by delay detection and perform carrier synchronization.

According to a thirty-seventh aspect, in the ninth to the thirty-sixth aspects, the output signal of the frequency correction means is input, the bandwidth of the output signal is limited, and then the bandwidth limitation filter output to the phase correction means is further performed. Prepared,

The frame synchronization detecting means is characterized by inputting an output signal of either the frequency correcting means or the band limiting filter or the phase correcting means, and detecting a frame head position.

As described above, the thirty-seventh aspect is the ninth to thirty-sixth aspects in which a band limiting filter for spectrally shaping the phase modulation signal output by the frequency correction means is further added to the configuration. is there. Therefore, the effects of the 37th phase are the same as the effects of the 9th to 36th phases, respectively.

In a thirty-eighth aspect, in the ninth to thirty-seventh aspects, the phase in which the carrier synchronization auxiliary signal is applied to the modulated signal serving as the next bucket with respect to the time-division multiplexed position in the communication frame. If the information identifying the modulation is superimposed,

Information detecting means for detecting a period of a signal subjected to minimum phase modulation based on the information, and outputting a signal giving the minimum phase modulation period to the timing generating means;

The timing generation means generates a timing signal that gives a minimum phase modulation period in addition to the synchronization signal period.

As described above, according to the thirty-eighth aspect, in the ninth to thirty-seventh aspects, of the phase-modulated signals to be time-division multiplexed, the carrier synchronization auxiliary distributed in a bucket is provided. Performs frequency correction and phase correction (regeneration of carrier wave) using the main signal that has been subjected to minimum phase modulation in addition to the minimum phase modulation signal including the signal. As a result, carrier synchronization can be performed quickly and stably even in a low C / N state.

In a ninth aspect, in the thirteenth to sixteenth aspects, when the frequency at which the pseudo-synchronization occurs is fg [Hz], the frequency step means obtains (— 1) ⁿ — ¹ nxfg [H z] (n = l, 2,...), and the frequency input to the phase correction means is shifted stepwise.

As described above, according to the thirty-ninth aspect, in the thirteenth to sixteenth aspects, the frequency step means sets the frequency fg at which the pseudo-synchronization occurs as a step unit, and alternates the frequency in the order of positive and negative. Shift to increase. As a result, even in the case of the pseudo synchronization, the normal synchronization can be finally performed by repeating the above step operation.

In the 40th aspect, a carrier synchronization auxiliary signal that has been phase-modulated using the phase modulation having the smallest number of phases in a communication frame (hereinafter referred to as minimum phase modulation) together with a plurality of phase-modulated signals is an equal time interval. A demodulation method of the communication frame time-division multiplexed so that

Detecting a synchronization signal of the communication frame to detect at least a period of the carrier synchronization auxiliary signal (hereinafter referred to as a synchronization signal period) in the period in which the minimum phase modulation is performed;

Performing a frequency and phase correction operation according to the minimum phase modulation during the synchronization signal period.

As described above, according to the 40th aspect, of the phase-modulated signals to be time-division multiplexed, the frequency correction and the phase correction are performed by using the minimum phase-modulated signal including the carrier synchronization auxiliary signal dispersedly arranged in the bucket. By performing correction (carrier recovery), carrier synchronization can be performed quickly and stably even in a low C / N state. In addition, even when the input frequency error is large, the malfunction of frame synchronization detection by delay detection is eliminated. Carrier synchronization can be performed.

In a forty-first aspect, in the forty-fourth aspect, a step of detecting a frequency pull-in state to determine whether or not the frequency is a frequency at which pseudo synchronization occurs,

If the result of the determination in the determining step is that the frequency does not cause pseudo-synchronization, the method further includes the step of initializing the phase correction operation.

As described above, according to the forty-first aspect, in the forty-fourth aspect, the frequency lock-in state is detected, and the frequency correction is performed up to the frequency at which the phase correction operation is not pseudo-synchronized in the frequency correction operation. After that, the phase correction operation is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase correction operation in the frequency pull-in process by the frequency correction operation.

In a forty-second aspect, in the forty-fourth aspect, a step of detecting a state of phase synchronization in a period of the carrier synchronization auxiliary signal,

Detecting a correction state of an error correction process of a transmission control signal (TMC C signal) included in the frame synchronization signal;

Determining whether or not pseudo synchronization is to be performed based on the phase synchronization state during the carrier synchronization auxiliary signal period and the error correction state during the TMCC signal period;

If the result of determination in the determining step is pseudo-synchronization, the method further includes the step of initializing the phase correction operation.

As described above, according to the forty-second aspect, in the forty-fourth aspect, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of the error correction of the TMCC signal are performed. It is determined from the result whether or not the synchronization is normal. Then, in the case of the pseudo synchronization, the phase correction operation is initialized and restarted. This makes it possible to avoid quasi-synchronization in the phase correction operation in the frequency pull-in process by the frequency correction operation.

In a forty-third aspect, in the forty-fifth aspect, a step of detecting a state of phase synchronization in a period of the carrier synchronization auxiliary signal, Detecting a phase synchronization state during a transmission control signal (TMCC signal) included in the frame synchronization signal;

Determining whether or not pseudo synchronization is to be performed based on the phase synchronization state during the carrier synchronization auxiliary signal period and the phase synchronization state during the T MCC signal period;

As described above, according to the forty-third aspect, in the forty-fourth aspect, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of phase synchronization during the period of the frame synchronization signal / TMCC signal are performed. Then, it is determined whether or not the synchronization is normal based on the detection result. Then, in the case of pseudo-synchronization, the phase correction operation is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase correction operation in the frequency pull-in process by the frequency correction operation.

In a forty-fourth aspect, in the forty-fourth aspect, a step of detecting a state of phase synchronization in a period of the carrier synchronization auxiliary signal,

If the result of determination in the determining step is pseudo-synchronization, the method further includes the step of stepwise changing the frequency at which the phase correction operation is performed.

As described above, according to the forty-fourth aspect, in the forty-fourth aspect, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of the possibility of error correction of the TMCC signal are performed. It is determined from the result whether or not the synchronization is normal. Then, in the case of the pseudo synchronization, the frequency of the frequency correction operation is controlled so that the normal synchronization can be performed by the phase correction operation. This makes it possible to avoid pseudo-synchronization in the phase correction operation in the frequency pull-in process by the frequency correction operation. In a forty-fifth aspect, in the forty-fourth aspect, a step of detecting a state of phase synchronization in a period of the carrier synchronization auxiliary signal,

Detecting a phase synchronization state during a transmission control signal (TMC C signal) included in the frame synchronization signal;

As described above, according to the forty-fifth aspect, in the forty-fourth aspect, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of phase synchronization during the period of the frame synchronization signal / TMCC signal are performed. Then, it is determined whether or not the synchronization is normal based on the detection result. In the case of pseudo synchronization, the frequency of the frequency correction operation is controlled so that normal synchronization can be performed by the phase correction operation. This makes it possible to avoid quasi-synchronization in the phase correction operation in the frequency pull-in process or the like by the frequency correction operation.

In a forty-sixth aspect, in the forty-fourth aspect, a step of detecting a frequency pull-in state to determine whether or not the frequency is a frequency at which pseudo synchronization occurs,

In a forty-seventh aspect, in the forty-fifth aspect, a step of detecting a frequency pull-in state to determine whether or not the frequency is a frequency at which pseudo synchronization occurs,

As described above, according to the forty-sixth and forty-seventh aspects, in the forty-fourth and forty-fifth stations, the frequency pull-in state is further detected, and the phase correction operation is not pseudo-synchronized in the frequency correction operation. Phase correction after frequency correction up to frequency Initialize T / JP operation and restart. This makes it possible to avoid quasi-synchronization in the phase correction operation in the frequency pull-in process by the frequency correction operation. In a forty-eighth aspect, in the forty-eighth aspect, a step of detecting a state of phase synchronization;

There is a step of detecting the C / N (carrier power / noise power) state of the received signal and phase synchronization, and if the C / N is higher than a predetermined threshold, the minimum phase in the synchronization signal period The phase error due to modulation is detected, and the number of phases is largest in the communication frame during periods other than the synchronization signal period of the communication frame.After detecting the phase error due to phase modulation, the phase correction operation is performed throughout the communication frame. And performing the following.

As described above, according to the forty-eighth aspect, in the forty-fourth aspect, the C / N state during phase synchronization during the minimum phase modulation signal period is detected, and the C / N is determined in advance. If the level is the same level, the phase error is corrected assuming that the maximum phase modulation is also performed for the main signal period of the communication frame. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

In a forty-ninth aspect, in the forty-ninth aspect, a step of detecting a state of phase synchronization,

Detecting a C / N (carrier power / noise power) state of the received signal; and detecting a correction state of an error correction process of a transmission control signal (TMC C signal) included in the frame synchronization signal.

If phase synchronization is achieved and error correction is completed, and if the C / N is higher than the first predetermined threshold value, the phase error due to the corresponding phase modulation is detected in the entire communication frame period. However, if the C / N is between the first threshold value and the predetermined second threshold value, the C / N is not used during the period other than the period during which phase modulation with the largest number of phases is performed in the communication frame. Detect the phase error due to the corresponding phase modulation, When the C / N is lower than the second threshold value, detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and then performing a phase correction operation. Further prepare.

As described above, according to the forty-ninth aspect, in the forty-ninth aspect, the C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected, and the C / N state and the C / N state are detected. According to the reference phase corresponding to the phase modulation method according to the demodulation mode signal, phase correction is performed using the frame synchronization signal / TMCC signal period and carrier synchronization auxiliary signal period that are minimum phase modulated in the initial state, and after phase synchronization. Performs phase correction in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced to improve the reception performance. In a fiftyth aspect, in the forty-fifth aspect, a step of detecting a state of phase synchronization;

If phase synchronization is achieved and error correction is completed, and if the C / N is higher than the first predetermined threshold value, the phase error due to the corresponding phase modulation is detected in the entire communication frame period. However, if the C / N is between the first threshold value and a predetermined second threshold value, the phase modulation having the largest number of phases in the communication frame (hereinafter referred to as the maximum phase modulation) is A phase error due to the corresponding phase modulation is detected in a period other than the period in which the modulation is performed, and when the C / N is lower than the second threshold, the minimum value is obtained in the synchronization signal period and the period in which the minimum phase modulation is performed. Performing a phase correction operation after detecting a phase error due to phase modulation;

If there is phase synchronization and error correction has not been completed, and C / N is higher than the first threshold, the phase error due to minimum phase modulation is reduced during the synchronization signal period. Detecting and detecting a phase error due to maximum phase modulation in the communication frame during a period other than the synchronization signal period of the communication frame, and then performing a phase correction operation.

As described above, according to the 50th aspect, in the 40th aspect, the C / N state when phase synchronization is performed during the minimum phase modulation signal period is detected, and the C / N is determined in advance. If the level is higher than that, the phase error is corrected assuming that the maximum phase modulation is performed in all periods other than the synchronization signal period in the communication frame, and the phase modulation method according to the demodulation mode signal is used. According to the corresponding reference phase, phase correction is performed using the frame synchronization signal / TMCC signal period and carrier synchronization auxiliary signal period that are minimum phase modulated in the initial state, and after the phase synchronization, the modulation period of the main signal other than the period Also, the phase correction is performed. This enables fast and stable carrier synchronization even in the low C / N state, and reduces the influence of the phase jitter of the demodulated signal during the main signal period, thereby improving the reception performance. .

In a fifty-first aspect, in the forty-fifth aspect, a step of detecting a state of phase synchronization;

Measures the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detects the state of C / N (carrier power / noise power) based on the bit error rate. Steps and

If there is phase synchronization and C / N is higher than a predetermined threshold, the phase error due to minimum phase modulation is detected during the synchronization signal period, and the phase error within the communication frame is not included during the period other than the communication frame synchronization signal period. Performing a phase correction operation after detecting a phase error due to the largest number of phase modulations.

As described above, according to the fifty-first aspect, in the forty-fifth aspect, the C / N state when the phase is synchronized in the minimum phase modulation signal period is based on the bit error rate of the TMCC signal. If the detected C / N is at a predetermined level, it is assumed that maximum phase modulation has been performed even for the main signal period of the communication frame, and the phase error is corrected. Do. As a result, carrier synchronization can be performed quickly and stably even in a low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

In a fifty-second aspect, in the forty-fifth aspect, a step of detecting a state of phase synchronization;

If phase synchronization is performed and error correction is completed, and C / N is higher than the first predetermined threshold, a phase error due to the corresponding phase modulation is detected in the entire communication frame period. However, if the C / N is between the first threshold value and the predetermined second threshold value, the C / N is not used during the period other than the period during which phase modulation with the largest number of phases is performed in the communication frame. The phase error due to the corresponding phase modulation is detected.If the C / N is lower than the second threshold value, the phase error due to the minimum phase modulation is detected during the synchronization signal period and the period where the minimum phase modulation is performed. Performing a phase correction operation after the above.

As described above, according to the 52nd aspect, in the 40th aspect, the C / N state when phase synchronization is performed during the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal According to the reference phase corresponding to the phase modulation method according to the C / N state and the demodulation mode signal, the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period that are minimum phase-modulated in the initial state are used. After the phase synchronization, the phase correction is performed also in the modulation period of the main signal other than the period. This allows fast and stable carrier synchronization even in the low C / N state, and reduces the effect of demodulated signal phase jitter during the main signal period. However, the reception performance can be improved.

In a fifty-third aspect, in the forty-fifth aspect, a step of detecting a state of phase synchronization;

If phase synchronization is performed and error correction is completed, and C / N is higher than the first predetermined threshold, a phase error due to the corresponding phase modulation is detected in the entire communication frame period. However, if the C / N is between the first threshold value and a predetermined second threshold value, the phase modulation having the largest number of phases in the communication frame (hereinafter referred to as the maximum phase modulation) is The phase error due to the corresponding phase modulation is detected in a period other than the period in which the modulation is performed, and when C / N is lower than the second threshold value, the minimum value is obtained in the synchronization signal period and the period in which the minimum phase modulation is performed. Performing a phase correction operation after detecting a phase error due to phase modulation;

If phase synchronization is performed and error correction is not completed, and C / N is higher than the first threshold, a phase error due to minimum phase modulation is detected during the synchronization signal period, and the communication frame And performing a phase correction operation after detecting a phase error due to maximum phase modulation in the communication frame during a period other than the synchronization signal period.

As described above, according to the 53rd aspect, in the 40th aspect, the C / N state when phase synchronization is performed during the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal However, if the C / N is at a predetermined level, the phase error is corrected assuming that the maximum phase modulation is performed in all periods other than the synchronization signal period in the communication frame, and the demodulation mode signal is Corresponding to the phase modulation method According to the reference phase, phase correction is performed using the frame synchronization signal / TMCC signal period and carrier synchronization auxiliary signal period that are minimum phase modulated in the initial state, and after the phase homogenization period, even during the main signal modulation period other than this period. Perform phase correction. As a result, the carrier synchronization can be performed quickly and stably even in a low C / N state, and the effect of the phase jitter of the demodulated signal in the main signal period can be reduced to improve the reception performance. it can.

In a fifty-fourth aspect, in the fourth to seventh aspects, a step of detecting a state of phase synchronization is provided,

There is a step of detecting the C / N (carrier power / noise power) state of the received signal, and there is phase synchronization, and if the C / N is higher than a predetermined threshold, it is the lowest in the synchronization signal period. Performing a phase correction operation after detecting a phase error due to the modulation and detecting a phase error due to the phase modulation having the largest number of phases in the communication frame other than the synchronization signal period of the communication frame.

In a fifty-fifth aspect, in the forty-first, fourth, fourth, and fifth aspects, a step of detecting a state of phase synchronization is provided;

If phase synchronization is achieved and error correction is completed, and if the C / N is higher than the first predetermined threshold value, the phase error due to the corresponding phase modulation is detected in the entire communication frame period. If the C / N is between the first threshold value and a predetermined second threshold value, the period during which phase modulation with the largest number of phases is performed in the communication frame is performed. The phase error due to the corresponding phase modulation is detected in periods other than the above, and if the C / N is lower than the second threshold value, the minimum phase modulation is applied during the synchronization signal period and the period in which the minimum phase modulation is performed. Performing a phase correction operation after detecting the phase error. In a fifty-sixth aspect, the steps of detecting the state of phase synchronization in the fourth, fourth, and fourth aspects;

Detecting the C / N (carrier power / noise power) state of the received signal; and performing phase synchronization and error correction, and the C / N (C / N) is determined based on a predetermined first threshold. If / N is high, the phase error due to the corresponding phase modulation is detected during the entire communication frame, and the C / N is between the first threshold and the second predetermined threshold. In the communication frame, the phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed, and if the C / N is lower than the second threshold value, the synchronization is detected. Performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the signal period and the period in which the minimum phase modulation is performed.

In a fifty-seventh aspect, in the forty-first, fourth, fourth, and fourth aspects, a step of detecting a state of phase synchronization;

If phase synchronization is performed and error correction is completed, and C / N is higher than the first predetermined threshold, a phase error due to the corresponding phase modulation is detected in the entire communication frame period. However, if the C / N is between the first threshold value and a predetermined second threshold value, the phase modulation having the largest number of phases in the communication frame (hereinafter referred to as the maximum phase modulation) is A phase error due to the corresponding phase modulation is detected in a period other than the period in which the modulation is performed, and when the C / N is lower than the second threshold, the minimum value is obtained in the synchronization signal period and the period in which the minimum phase modulation is performed. Performing a phase correction operation after detecting a phase error due to phase modulation;

If there is phase synchronization and error correction has not been completed and the C / N is higher than the first threshold, the phase error due to minimum phase modulation is reduced during the synchronization signal period. Detecting and detecting a phase error due to maximum phase modulation in the communication frame during a period other than the synchronization signal period of the communication frame, and then performing a phase correction operation.

In the fifty-eighth aspect, in the fourth, fourth and sixth aspects, a step of detecting a state of phase synchronization;

Detecting the C / N (carrier power / noise power) state of the received signal; and performing phase synchronization and error correction, and the C / N (C / N) is determined based on a predetermined first threshold. If / N is high, the phase error due to the corresponding phase modulation is detected during the entire communication frame, and if C / N is between the first threshold value and a predetermined second threshold value. In a communication frame, a phase error due to the corresponding phase modulation is detected in a period other than a period in which phase modulation having the largest number of phases is performed (hereinafter, referred to as a maximum phase modulation), and the second threshold is set to C. If / N is low, performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed;

If phase synchronization is performed and error correction is not completed and the C / N is higher than the first threshold, a phase error due to minimum phase modulation is detected during the synchronization signal period, and the communication frame And performing a phase correction operation after detecting a phase error due to maximum phase modulation in the communication frame during a period other than the synchronization signal period.

In a ninth aspect, in the fourth to fourth aspects, a step of detecting a state of phase synchronization is provided;

If there is phase synchronization and C / N is higher than a predetermined threshold, a phase error due to minimum phase modulation is detected during the synchronization signal period, and the synchronization signal period of the communication frame is detected. Otherwise, after detecting a phase error due to the phase modulation having the largest number of phases in the communication frame, performing a phase correction operation.

The 60th phase is a step of detecting the state of phase synchronization in the 41st, 43rd, 45th, and 47th aspects;

Measures the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detects the state of C / N (carrier power / noise power) based on the bit error rate Steps to

In a sixty-first aspect, in the forty-second, fourth and sixth aspects, a step of detecting a state of phase synchronization;

If phase synchronization is performed and error correction is completed, and C / N is higher than the first predetermined threshold, a phase error due to the corresponding phase modulation is detected in the entire communication frame period. If the C / N is between the first threshold value and a predetermined second threshold value, the phase modulation having the largest number of phases in the communication frame is performed. The phase error due to the corresponding phase modulation is detected in the period other than the period in which the signal is applied, and if the C / N is lower than the second threshold value, the synchronization signal period and the period in which the minimum phase modulation is performed Performing a phase correction operation after detecting a phase error due to the minimum phase modulation in.

In a 62nd aspect, in the 41st, 43rd, 45th, and 47th aspects, a step of detecting a state of phase synchronization;

In a sixth aspect, in the fourth, the fourth and the sixth aspects, a step of detecting a state of phase synchronization; Measures the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detects the state of C / N (carrier power / noise power) based on the bit error rate. Steps and

As described above, the 54th to 63rd aspects are combinations of the 41st to 47th aspects and the 48th to 53rd aspects, respectively. Therefore, the 54th to 63rd stations can carry out carrier synchronization stably at high speed even in the low C / N state, and in the frequency pull-in process by the frequency correction operation, etc. Pseudo-synchronization can be avoided, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced to improve the reception performance.

A sixty-fourth aspect is the phase in which, in the forty-fourth to sixty-third aspects, the carrier synchronization auxiliary signal is applied to a modulated signal that is the next bucket with respect to a position where time division multiplexing is performed in a communication frame. If the information identifying the modulation is superimposed,

Based on the information, the period of the signal subjected to the minimum phase modulation is detected, and A signal providing a phase modulation period is output to a step of generating a timing signal, and the step of generating a timing signal is characterized by generating a timing signal providing a minimum phase modulation period in addition to the synchronization signal period.

As described above, according to the sixty-fourth aspect, in the forty-fourth to sixty-third aspects, among the phase-modulated signals to be time-division multiplexed, the carrier synchronization auxiliary signal distributed and arranged in a bucket is used. Performs frequency correction and phase correction (carrier recovery) using the minimum phase modulated signal as well as the minimum phase modulated main signal. As a result, carrier synchronization can be performed quickly and stably even in a low C / N state.

In the sixty-fifth aspect, in the fourth to the forty-seventh aspects, the step of changing the frequency stepwise is as follows: when the frequency at which the pseudo-synchronization occurs is fg [Hz], (— 1) ^π _ 'xnxfg [H z] (n = 1, 2, · · · ·) The frequency at which the phase correction operation is performed is shifted stepwise.

As described above, according to the 65th aspect, in the 44th to 47th aspects, the step of changing the frequency stepwise includes the step of setting the frequency fg at which the pseudo-synchronization occurs to It is shifted so that it increases in the order of positive and negative. Thus, even in the case of the pseudo synchronization, the normal synchronization can be finally performed by repeating the above step operation. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a configuration of a modulation device according to one embodiment of the present invention. FIG. 2 is a diagram showing an example of a communication frame generated in the modulation device according to one embodiment of the present invention.

FIG. 3 is a block diagram showing an example of the configuration of the multiplexing / quadrature modulation section 19 of FIG. 1. FIG. 4 is a block diagram showing the configuration of the demodulation device according to the first embodiment of the present invention. ο FIG. 5 is a flowchart showing an operation performed by the demodulation device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a signal detected by the frame synchronization detection unit 35 and a timing signal generated by the timing generation unit 36.

FIG. 7 is a block diagram illustrating a configuration of the first embodiment of the frame synchronization detection unit 35. FIG. 8 is a block diagram illustrating a configuration of the second embodiment of the frame synchronization detection unit 35. FIG. 9 is a block diagram illustrating a configuration of the frame synchronization detection unit 35 according to the third embodiment. FIG. 10 is a block diagram illustrating a configuration of the fourth embodiment of the frame synchronization detection unit 35. FIG. 11 is a block diagram illustrating a configuration of the fifth embodiment of the frame synchronization detection unit 35. FIG. FIG. 7 is a diagram illustrating a phase relationship in frame synchronization detection.

FIG. 13 is a diagram illustrating a phase relationship in frame synchronization detection.

FIG. 14 is a diagram illustrating a frequency shift in frequency correction.

FIG. 15 is a diagram illustrating a phase relationship in frame synchronization detection.

FIG. 16 is a diagram illustrating a phase relationship in frame synchronization detection.

FIG. 17 is a block diagram illustrating a more detailed configuration of the frequency correction unit 32. FIG. 18 is a block diagram showing a more detailed configuration of the phase correction unit 34. FIG. 19 is a diagram for explaining a phase shift in the phase correction.

FIG. 20 is a diagram for explaining pseudo synchronization generated in the phase correction unit 34.

FIG. 21 is a diagram for explaining the pseudo synchronization that occurs in the phase correction unit 34.

FIG. 22 is a block diagram illustrating a configuration of a demodulation device according to the second embodiment of the present invention.

FIG. 23 is a flowchart showing the operation performed by the demodulation device according to the second embodiment of the present invention.

FIG. 24 is a block diagram showing a more detailed configuration of the frequency pull-in determination unit 42. is there.

FIG. 25 is a block diagram illustrating an example of a more detailed configuration of the phase correction unit 34A.

FIG. 26 is a block diagram illustrating an example of a more detailed configuration of the phase correction unit 34A.

FIG. 27 is a block diagram illustrating a configuration of a demodulation device according to the third embodiment of the present invention.

FIG. 28 is a flowchart showing the operation performed by the demodulation device according to the third embodiment of the present invention.

FIG. 29 is a block diagram illustrating a configuration of the phase synchronization detection unit 43 according to the first embodiment. FIG. 30 is a block diagram illustrating a configuration of the phase synchronization detection unit 43 according to the second embodiment. FIG. 31 is a diagram illustrating an example of a threshold value set in the phase synchronization determination section 437 of the phase synchronization detection section 43.

FIG. 32 is a diagram for explaining the operation principle of the pseudo synchronization determination performed by the pseudo synchronization determination unit 45 in FIG.

FIG. 33 is a block diagram illustrating a configuration of a demodulation device according to the fourth embodiment of the present invention.

FIG. 34 is a diagram illustrating another timing signal generated by the timing generation unit 36.

FIG. 35 is a diagram for explaining the operation principle of the pseudo-synchronization determination performed by the pseudo-synchronization determination unit 45 in FIG.

FIG. 36 is a block diagram illustrating a configuration of a demodulation device according to the fifth embodiment of the present invention.

FIG. 37 is a flowchart showing the operation performed by the demodulation device according to the fifth embodiment of the present invention.

FIG. 38 is a block diagram illustrating an example of a configuration of the pseudo-synchronization determination unit 45 in FIG. FIG. 39 is a block diagram showing the configuration of the frequency step section 46.

FIG. 40 is a diagram showing each signal waveform in the frequency step section 46.

FIG. 41 is a diagram for explaining the operation principle of the frequency step.

FIG. 42 is a block diagram showing a configuration of the demodulation device according to the sixth embodiment of the present invention.

FIG. 43 is a block diagram showing a configuration of the demodulation device according to the seventh embodiment of the present invention.

FIG. 44 is a flowchart showing the operation performed by the demodulation device according to the seventh embodiment of the present invention.

FIG. 45 is a block diagram showing a configuration of the demodulation device according to the eighth embodiment of the present invention.

FIG. 46 is a diagram for explaining the phase jitter.

FIG. 47 is a diagram illustrating the relationship between the phase jitter and C / N.

FIG. 48 is a block diagram showing the configuration of the demodulation device according to the ninth embodiment of the present invention.

FIG. 49 is a flowchart showing the operation performed by the demodulation device according to the ninth embodiment of the present invention.

FIG. 50 is a block diagram showing a configuration of frame synchronization determination section 47.

FIG. 51 is a block diagram illustrating a configuration of the C / N detection unit 48.

FIG. 52 is a block diagram showing a configuration of the gate signal selection unit 49.

FIG. 53 is a block diagram illustrating a configuration of the phase error detection unit 341 of the phase correction unit 34B.

FIG. 54 is a diagram for explaining the phase error detection operation performed by the phase error detection unit 341 of the phase correction unit 34B.

FIG. 55 is a block diagram showing a configuration of a demodulation device according to the tenth embodiment of the present invention. It is.

FIG. 56 is a flowchart showing the operation performed by the demodulation device according to the tenth embodiment of the present invention.

FIG. 57 is a block diagram illustrating a configuration of the C / N detection unit 48A.

FIG. 58 is a block diagram illustrating a configuration of the gate signal selection unit 49A.

FIG. 59 is a diagram illustrating each timing signal input to the demodulation mode switching unit 50 and the demodulation mode signal output.

FIG. 60 is a block diagram illustrating a configuration of the phase error detection unit 341 of the phase correction unit 34C.

FIG. 61 is a diagram illustrating a phase error detection operation performed by the phase error detection unit 341 of the phase correction unit 34C.

FIG. 62 is a block diagram illustrating a configuration of the demodulation device according to the first embodiment of the present invention.

FIG. 63 is a flowchart showing the operation performed by the demodulation device according to the first embodiment of the present invention.

FIG. 64 is a block diagram illustrating a configuration of the gate signal selection unit 49B.

FIG. 65 is a block diagram illustrating a configuration of the demodulation mode switching unit 5OA.

FIG. 66 is a block diagram showing a configuration of the demodulation device according to the 12th embodiment of the present invention.

FIG. 67 is a block diagram illustrating the configuration of the BER detection unit 51.

FIG. 68 is a diagram illustrating the relationship between C / N and the bit error rate.

FIG. 69 is a block diagram showing a configuration of the demodulation device according to the thirteenth embodiment of the present invention.

FIG. 70 is a block diagram showing a configuration of the BER detection unit 51A.

FIG. 71 is a block diagram showing a configuration of the demodulation device according to the fourteenth embodiment of the present invention. FIG. 72 is a block diagram illustrating a configuration of another modulation device according to an embodiment of the present invention.

FIG. 73 is a diagram illustrating an example of a communication frame generated in another modulation device according to an embodiment of the present invention.

FIG. 74 is a block diagram illustrating a configuration of another demodulation device according to an embodiment of the present invention.

FIG. 75 is a block diagram showing a configuration of the carrier synchronization auxiliary signal decoder 52. FIG. 76 is a diagram showing a timing signal generated by the evening generating unit 36A. FIG. FIG. 2 is a block diagram illustrating a configuration of the device.

FIG. 78 is a diagram illustrating an example of a communication frame generated in a conventional modulation device.

FIG. 79 is a diagram illustrating mapping of BPSK, QPSK, and 8PSK to a code arrangement.

FIG. 80 is a diagram showing a data structure and a frame structure of MPEG in the conventional modulation device and method.

FIG. 81 is a block diagram showing a configuration of a conventional demodulation device. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention enables high-speed and stable carrier synchronization even in a low C / N state by using a BPSK including a carrier synchronization auxiliary signal dispersedly arranged in a packet among time-division multiplexed phase modulated signals. Modulation and demodulation apparatus and method.

Hereinafter, a modulation device and method (transmission system) and a demodulation device and method (reception system) will be described in order for each embodiment of the present invention. (1) Transmission system

FIG. 1 is a block diagram showing a configuration of a modulation device according to an embodiment of the present invention, corresponding to claims 1 to 3 and 6 to 8. In FIG. 1, a modulation device according to one embodiment of the present invention includes a frame synchronization signal / TMCC signal generation unit 11, a TS packet synthesis unit 12, a TMCC error correction encoding unit 13, a first error correction code Synchronization section 14, second error correction coding section 15, first BPSK mapping section 16, BPSK / QPSK mapping section 17, 8PSK mapping section 18, multiplexing / quadrature modulation section 19, and synchronization. An auxiliary signal generation unit 20 and a second BPSK mapping unit 21 are provided.

FIG. 2 is a diagram showing an example of a communication frame generated in the modulation device according to one embodiment of the present invention. FIG. 3 is a block diagram showing an example of the configuration of the multiplexing / quadrature modulation unit 19 in FIG.

Hereinafter, an operation performed by the modulation device according to the embodiment of the present invention will be described.

The frame synchronization signal / TMCC signal generation unit 11 generates a frame synchronization signal / TMCC signal based on the input TMCC information. The frame synchronization signal / TMCC signal is subjected to error correction coding in the TMCC error correction coding unit 13, and then input to the BPSK mapping unit 16. The BP SK mapping section 16 maps the input frame synchronization signal and TMCC signal to the BP SK code arrangement (see FIG. 79 (a)), and outputs it to the multiplexing / quadrature modulation section 19.

The TS bucket synthesizing unit 12 synthesizes a plurality of input MPEG-TS packets (see FIG. 80 (a)), and is composed of a packet group of a lower layer signal and a packet group of a higher layer signal. Generate a frame with a fixed number of packets (see Fig. 80 (b)). In this frame, the packet group of the low-layer signal is subjected to error correction coding in the first error correction coding unit 14 and then input to the BP SK / QP SK mapping unit 17. The BPSK / QPSK mapping unit 17 converts the input low-layer signal into a BPSK code arrangement (see FIG. 79 (a)) or a QPSK code. This is mapped to the constellation (see Fig. 79 (b)) and output to the multiplexing quadrature modulation unit 19. On the other hand, among the above-mentioned frames, the packet group of the high-layer signal is input to the 8PSK mapping section 18 after being subjected to error correction coding in the second error correction coding section 15. The 8PSK mapping section 18 maps the input high-layer signal to a code arrangement of 8PSK (see FIG. 79 (c)), and outputs it to the multiplexing / quadrature modulation section 19.

The synchronization auxiliary signal generation unit 20 generates a signal (hereinafter, abbreviated as a carrier synchronization auxiliary signal) for assisting carrier synchronization in a demodulation device described later. The second BPSK mapping section 21 receives the carrier synchronization auxiliary signal generated by the synchronization auxiliary signal generation section 20 and maps it into the BP SK code arrangement (see FIG. 79 (a)). / Output to quadrature modulator 19.

The reason why the BPSK is mapped to the carrier synchronization auxiliary signal in this way is to enable the demodulation device to reproduce the carrier by using the BPSK portion of the plurality of time-division multiplexed phase modulations.

Then, the multiplexing / orthogonal modulation unit 19 generates a communication frame by time-division multiplexing each signal input from each mapping unit in the arrangement shown in FIG. 2, and then performs quadrature modulation to output. Here, as can be seen in FIG. 2, the multiplexing / quadrature modulation unit 19 includes a frame synchronization signal and a TMCC signal to which BPS has been applied, a bucket group of higher-layer signals to which 8PSK has been applied, and a BPSK or Time-division multiplexing is performed in units of packet groups of low-layer signals to which QPSK has been applied, and the carrier synchronization auxiliary signal subjected to BPSK modulation is dispersed in a packet that is the minimum unit at which the modulation method is switched. The communication frame is generated by performing time division multiplexing (insertion).

In this time division multiplexing, for example, using a circuit as shown in FIG. 3, a gate signal for controlling insertion timing of each signal is generated from an output signal of a frame counter for counting the number of symbols of one frame. It can be done by switching each switch. As will be described in the demodulation device described later, the carrier synchronization auxiliary signal is inserted continuously for two or more symbols so as to enable delay detection. Also, in order to improve the demodulation characteristics, it is preferable that the insertion period of the carrier synchronization auxiliary signal be as short as possible, specifically, about 200 symbols or less.

As described above, according to the modulation device of one embodiment of the present invention, the signal that assists the carrier synchronization in the demodulation device is modulated by the BPSK that is strong against the low C / N state, and dispersed in the packet. And output the communication frame inserted.

As a result, in the demodulator, even in the low C / N state, carrier synchronization can be performed at high speed and stably using the BPSK carrier synchronization auxiliary signal dispersed in the packet.

(2) Reception system

Next, a demodulation device and method for demodulating a communication frame generated by the modulation device according to the embodiment of the present invention described above will be sequentially described below.

In the following description, the first embodiment is a basic demodulator, and the second to eighth embodiments are demodulators that avoid pseudo-synchronization with respect to the first embodiment. The 14th to 14th embodiments are demodulation devices in which the phase noise is further reduced as compared with the first embodiment.

(First Embodiment)

FIG. 4 is a block diagram showing a configuration of a demodulation device according to a first embodiment of the present invention, which corresponds to claims 9, 37, and 40. In FIG. 4, the demodulator according to the first embodiment includes a quadrature detector 31, a frequency corrector 32, a band limiting filter 33, a phase corrector 34, and a frame synchronization detector 3. 5, a timing generation section 36, a first error correction section 37, a second error correction section 38, a video decoder 39, a TMCC decoder 40, and a BER measurement section 41. .

In addition, the frequency correction unit 3 2 includes a frequency error detection unit 3 2 1 and a frequency error holding unit 3 2, a numerically controlled oscillator 3 2 3, and a complex multiplier 3 2 4. The phase correction section 34 includes a phase error detection section 341, a phase error holding section 342, a numerical control oscillation section 3443, and a complex multiplication section 3444.

In FIG. 4, signal lines indicated by bold lines and “/ 2” indicate signal lines of signals expressed in a complex manner (hereinafter, the same applies to each drawing).

First, an outline of the demodulation device according to the first embodiment will be described.

The quadrature detector 31 demodulates each PSK modulated signal in the input communication frame by quadrature detection using a local oscillation signal of a fixed frequency, and equalizes the in-phase component (I) and the quadrature component (Q) of the low-frequency signal. Is output. The frequency correction unit 32 receives the signal output from the quadrature detection unit 31 and receives a frequency shift due to a frequency shift of a frequency converter (not shown) in the satellite antenna from the timing generation unit 36. Correct based on the timing signal.

Each configuration of the frequency correction unit 32 will be briefly described. The frequency error detector 3221 receives the signal output from the band limiting filter 33, detects the frequency error by performing delay detection. The frequency error holding unit 3222 averages the frequency errors in the BPSK period among the frequency errors detected by the frequency error detection unit 321, according to the output signal from the timing generation unit 36. The numerical control oscillator 322 performs a numerical operation on the averaged signal output from the frequency error holding unit 322 and outputs an oscillation signal. The complex multiplication unit 3 2 4 performs complex multiplication of the signal output from the quadrature detection unit 3 1 and the signal output from the numerical control oscillation unit 3 2 3 to cancel the frequency error.

The band limiting filter 33 inputs the signal output from the frequency correction unit 32 and performs spectrum shaping of each PSK signal. The frame synchronization detector 35

33 The signal output by 3 is input, and the BPSK-modulated frame synchronization signal, that is, the head of the communication frame, is detected by differential detection. The timing generation unit 36 determines the period of the frame synchronization signal / TMCC signal within one communication frame and the carrier synchronization auxiliary signal based on the information at the head of the frame detected by the frame synchronization detection unit 35. A period is detected, and a timing signal (gate signal) corresponding to the period is generated. The phase corrector 34 receives the signal output from the band-limiting filter 33 and corrects the phase shift based on the evening timing signal received from the evening timing generator 36.

Each configuration of the phase correction unit 34 will be briefly described. The phase error detector 341 receives the signal output from the band limiting filter 33 via the complex multiplier 344, and detects a phase difference from a predetermined reference phase. The phase error holding unit 342 averages the phase error in the BPSK period among the phase errors detected by the phase error detection unit 341 according to the output signal from the timing generation unit 36. The numerically controlled oscillator 343 performs a numerical operation on the averaged signal output from the phase error holder 342 and outputs an oscillated signal. The complex multiplication unit 344 performs a complex multiplication of the signal output from the band limiting filter 33 and the signal output from the numerical control oscillation unit 343 to cancel the phase error. The first error correction section 37 receives the signal output from the phase correction section 34 and converts the main signal, which has been individually error-correction-coded into a high-layer packet group and a low-layer packet group in the modulation device, into a packet. Performs error correction in units and restores the order of packets rearranged on the time axis for time division multiplex transmission. This output is output to the video decoder 40. Second error correction section 38 receives the signal output from phase correction section 34 and performs error correction on the TMCC signal that has been error-correction-coded in the modulation device. This output is output to the TMCC decoder 40. The TMCC decoder 40 detects TMCC information indicating the division of each layer in the frame and the modulation mode of each layer. The BER measurement unit 41 re-trellis the signal obtained by performing trellis decoding on the demodulated 8 PSK signal that has been subjected to trellis coding, which is a type of error correction coding, and demodulates the signal. 8 Monitor BER of higher layer signal by comparing with PSK signal. As a result, if it is determined that the quality of the decoded video of the higher layer is lower than the allowable value, the BER measurement unit 41 outputs a lower-layer video signal having high resistance to the quality deterioration of the transmission path. To control the video decoder 40 Next, the operation performed by the demodulation device according to the first embodiment will be described in detail along the processing flow with reference to FIGS. 5 to 19 further.

FIG. 5 is a flowchart illustrating an operation performed by the demodulation device according to the first embodiment. FIG. 6 is a diagram showing a signal detected by the frame synchronization detection unit 35 and a timing signal generated by the timing generation unit 36. FIGS. 7 to 11 are block diagrams showing the configuration of each embodiment of the frame synchronization detection unit 35. FIG. FIGS. 12 to 16 are diagrams illustrating the phase relationship in each embodiment of the frame synchronization detection unit 35. FIG. FIG. 17 is a block diagram showing a more detailed configuration of the frequency correction unit 32. As shown in FIG. FIG. 18 is a block diagram showing a more detailed configuration of the phase correction unit 34. As shown in FIG.

Referring to FIG. 5, the demodulation device first detects a frame synchronization signal in frame synchronization detection section 35 for a signal input to quadrature detection section 31 via a tuner (not shown) ( Step S101). By this detection, as shown in FIG. 6 (b), the head of the communication frame, that is, the head of the frame synchronization signal / TMC C signal can be detected.

Here, as the frame synchronization detection unit 35 that realizes such detection of the head of the frame, five embodiments having a specific configuration can be considered. Hereinafter, these five embodiments will be described in order.

(Example 1 of frame synchronization detection section 35)

FIG. 7 is a block diagram illustrating a configuration of the first embodiment of the frame synchronization detection unit 35 according to claim 33. In FIG. 7, the first embodiment includes a delay detection unit 351, a phase identification unit 352, and a collation unit 3553.

The delay detection unit 351 receives the signal from the band-limiting filter 33, and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The phase identification unit 352 identifies the phase of the signal output from the delay detection unit 351 and decodes the data. Here, since the frame synchronization signal to be detected is a BPSK modulation signal, the phase discrimination section 352 outputs the output signal of the delay detection section 351, as shown in FIG. If the phase is between -90 degrees and 90 degrees or less (A region), "0" is output, and 90 degrees or more and 180 degrees or less or -180 degrees or more -90 degrees or less (B It operates to output “1” when it is in the area. The matching section 353 compares the signal output from the phase identifying section 352 with a predetermined frame synchronization signal, and detects the start position of the frame. Here, the reference signal referred to in the matching section 353 is obtained by differentially decoding the frame synchronization signal.

(Embodiment 2 of the frame synchronization detector 35)

In the first embodiment, when there is a frequency shift in the phase modulation signal input to the delay detector 351, the output of the delay detector 351 must have a phase shift as shown in FIG. (X in the figure). In addition, when the C / N is low, the result is as shown in FIG. 15. In the phase identification method of the first embodiment, a phase error occurs.

Therefore, the second embodiment corresponds to this.

FIG. 8 is a block diagram illustrating a configuration of the second embodiment of the frame synchronization detecting unit 35 according to claim 33. In FIG. 8, the second embodiment includes a delay detection unit 351, first to third phase identification units 352a to 352c, and a matching unit 353.

The delay detection unit 351 receives the signal from the band-limiting filter 33, and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The first to third phase discriminating sections 3552a to 3552c discriminate the phases of the signals output from the delay detecting section 3551, respectively. Here, each of the first to third phase discriminating sections 352 a to 352 c has a phase discriminating area of 180 degrees as shown in FIG. Each has a different phase rotation. For example, as shown in FIG. 13 (a), the first phase discriminating section 35 2 a sets the phase of the output signal of the delay detecting section 35 1 to 90 degrees or more and 90 degrees or less (A region). It operates to output “0” in some cases, and to output “1” when it is in the range of 90 ° to 180 ° or 180 ° to 90 ° or less (B region). Further, as shown in FIG. 13 (b), the second phase discriminating section 352b changes the phase of the output signal of the delay detecting section 351 to ( If it is above (90 + a) degrees and below (90 +) degrees (area A), "0" is output, and above (90 + a) degrees and below 180 degrees or above-180 degrees It operates to output “1” when it is below (−9 0 + a) degrees (area B). Further, as shown in FIG. 13 (c), the third phase discriminating section 352c determines that the phase of the output signal of the delay detecting section 351 is more than (—90—H) degrees (90— “0” is output if the angle is below (H) degrees (A area), and (90 ° -H) degrees or more and 180 ° or less or 180 ° degrees or more and (−90—H) degrees or less (B It operates to output “1” when it is in the area. The matching section 353 performs matching between each signal output by the first to third phase identifying sections 352 a to 352 c and a predetermined frame synchronization signal. The start position of the frame is detected for any one of the matched signals. Here, the reference signal referred to in the matching section 353 is obtained by differentially decoding the frame synchronization signal.

(Embodiment 3 of the frame synchronization detector 35)

In the second embodiment, the phase identification is performed by applying a phase rotation to the coordinate axes in the phase identification unit, that is, by applying different phase rotations to the phase identification regions. However, a method is also conceivable in which the phase discrimination unit does not perform phase rotation, and performs phase rotation on the output of the delay detection unit 351, to discriminate phases.

Therefore, the third embodiment corresponds to this.

FIG. 9 is a block diagram showing a configuration of a third embodiment of the frame synchronization detecting section 35, corresponding to claim 34. In FIG. 9, the third embodiment is different from the delay detection section 351, the first to third phase rotation sections 354a to 354c, the three phase identification sections 352, and the matching section 353. Is provided.

The delay detection unit 351 receives the signal from the band-limiting filter 33, and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The first to third phase rotation units 354a to 354c receive the signals output from the delay detection unit 351 and apply different phase rotations to the signals to output the signals. 3 phase identification sections 3 5 2 Inputs the signals output by the first to third phase rotation units 354a to 354c, identifies the signals by the reference phase in the same phase identification area, and decodes the data. The matching section 353 compares each signal output from the three phase identification sections 352 with a predetermined frame synchronization signal, and determines a frame for any one signal that matches the frame synchronization signal. Detects the start position of.

As described above, the phase detection of the output of the delay detection 35 1 is equivalently the same as that shown in FIG. 13, and the same effect as that of the second embodiment can be obtained.

In the description of the second and third embodiments, the signals subjected to the three types of phase rotation are collated. However, if the collation can be performed using the signals subjected to the more types of phase rotation, the delay may be reduced. The accuracy of frame synchronization by detection can be improved.

(Embodiment 4 of frame synchronization detection section 35)

FIG. 10 is a block diagram illustrating a configuration of a fourth embodiment of the frame synchronization detecting unit 35 according to claim 35. In FIG. 10, the fourth embodiment includes a delay detection unit 351, a phase identification unit 352, a phase rotation unit 365, and a collation unit 353.

The delay detection unit 351 receives the signal from the band-limiting filter 33, and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The phase identification unit 352 identifies the phase of the signal output from the delay detection unit 351, and decodes the data. Here, since the frame synchronization signal to be detected is a BPSK modulation signal, phase identification section 352 has a phase identification area of 180 degrees (see FIG. 12). The matching section 353 compares the signal output from the phase identifying section 352 with a predetermined frame synchronization signal, and detects the start position of the frame. Here, the reference signal referred to in matching section 353 is a signal obtained by differentially decoding the frame synchronization signal. As shown in FIG. 16, the discrimination phase rotation unit 3555 performs phase rotation on the phase discrimination unit 352, and changes the rotation phase until the frame synchronization detection is obtained in the matching unit 353.

(Embodiment 5 of the frame synchronization detector 35) In the fourth embodiment, the phase identification is performed by applying a phase rotation to the coordinate axes in the phase identification unit, that is, by applying different phase rotations to the phase identification regions. However, a method is also conceivable in which the phase discrimination unit does not perform phase rotation, and performs phase rotation on the output of the delay detection unit 351, thereby discriminating the phase.

Therefore, the fifth embodiment corresponds to this.

FIG. 11 is a block diagram showing a configuration of a fifth embodiment of the frame synchronization detecting unit 35 according to claim 36. In FIG. 11, the fifth embodiment includes a delay detection unit 351, a phase rotation unit 354, a phase identification unit 352, and a collation unit 3553.

The delay detection unit 351 receives the signal from the band-limiting filter 33, and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The phase rotation unit 354 receives the signal output from the delay detection unit 351 and performs phase rotation to output the signal. Here, the phase rotation section 354 changes its rotation phase until the collation section 353 obtains frame synchronization detection. The phase identification unit 352 identifies the phase of the signal output from the phase rotation unit 354 and decodes the data. The collation unit 353 compares the signal output from the phase identification unit 352 with a predetermined frame synchronization signal, and detects the head position of the frame.

As described above, the phase detection of the output of the delay detection 35 1 is equivalently the same as that shown in FIG. 16, and the same effect as that of the fourth embodiment can be obtained.

Since the frame synchronization detection unit 35 of the first to fifth embodiments uses delay detection, if the frequency correction unit 32 or later is used, the installation position is the same as the frequency correction unit 32. There is no particular limitation as long as the output is the output of the band limiting filter 33 or the output of the phase correction unit 34. As will be described later, since the delay detection is also used in the frequency correction unit 32, the delay detection unit 35 1 of the frame synchronization detection unit 35 is shared with the delay detection unit of the frequency correction unit 32. This makes it possible to reduce the circuit scale.

Referring again to FIG. 5, the frame start signal detected by frame synchronization detecting section 35 is Are input to the timing generation unit 36. The timing generation unit 36 detects the period of the frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in one communication frame based on the frame head signal detected by the frame synchronization detection unit 35. A BPSK timing signal corresponding to the period as shown in (c) is generated (step S102).

It should be noted that the BP SK timing signal according to only the period of the carrier synchronization auxiliary signal as shown in FIG. 6D can obviously provide the useful effects of the present invention.

Here, in the demodulation device according to the first embodiment, the insertion interval and the insertion width (the number of symbols) of the BPSK-modulated carrier synchronization auxiliary signal are important to reproduce the carrier in the BPSK period. Regarding the insertion interval, the longer the interval is, the longer the holding state of the frequency correction unit 32 and the phase correction unit 34 is, and if any frequency error remains, the phase rotation of the modulation signal occurs between them. Depending on the period, the pull-in phase may differ by 180 degrees, or even out of synchronization. Regarding the number of inserted symbols, at least two symbols are required because frequency error detection in the frequency correction unit 32 uses delay detection, detects the phase shift between one symbol and uses it as the frequency error. .

Therefore, as described above, in the modulation device, it is preferable that the carrier synchronization auxiliary signal is continuously inserted for two or more symbols and the insertion interval is set to about 200 symbols or less.

Then, the timing generation section 36 sends the generated BPSK timing signal (FIG. 6 (c) or FIG. 6 (d)) to the frequency error holding section 322 of the frequency correction section 32 and the phase error holding section 342 of the phase correction section 34. Output each (see Figure 4). Next, the operation of the frequency correction unit 32 will be described with reference to FIG.

In FIG. 17, a frequency correction unit 32 includes a frequency error detection unit 321 including a delay detection unit 321a and a phase error detection unit 321b, a switching unit 322a, and a constant generation unit. Frequency error holding section 322 including section 322b, adder 322c, and delay section 322d; adder 323a, delay section 323b, cosine wave generation section 323c, and sign wave generation section 323d. And a complex multiplying unit 324.

The signal output from the quadrature detector 31 is output to the complex multiplier 324 and the band-limited filter.

The signal 33 is input to the delay detection section 321 a of the frequency error detection section 321 via 33. Delay detection unit 321 a, the current n-phase PSK modulation signal ^{(η = 2 ', 2 2} , 2 3 ···, following the same) and the complex conjugate of the one-symbol preceding eta phase P SK-modulated signal Performs complex multiplication with the signal to calculate differential detection output.

The equation for calculating the delay detection output is shown in the following equation (1).

Delay detection output 2 ex p (j (2 ττ / η · (D 1) + 2 ττ · Δf · t 1))-exp (-j (2 ττ / η-(D 0) + 27T-Af-t O))

= e x p ((2 π / τι '(D l— D 0) + 2TT' mm f 'T s))

.... (i)

D 1: Phase state of current symbol of n-phase PSK modulation signal (0 to (! L-l))

D O: Phase status of one symbol before the n-phase PSK modulation signal (0 to (! 1-1))

Δΐ: Frequency shift of equivalent low-frequency signal [Hz]

t 1: current time [t]

t 0: time before one symbol [t]

T s: Symbol period [t]

In the case of BPSK, if there is no frequency shift according to the above equation (1), the phase state of the differential detection output is 7Γ · η (η = 0 to 1) as indicated by the symbol in FIG. However, if there is a frequency shift △: £ ", the phase is shifted from the mark by ² · · Δί ¹ · T s (= 6>) as shown by the X mark.

Therefore, the phase error detection unit 32 lb detects the phase difference from the X mark when there is a frequency shift as the frequency error with the Hata mark when there is no frequency shift as the reference on the receiving side. I do. Since the processing is performed in the rectangular coordinate system, the phase difference is originally calculated by arct an (y / x) .However, in a simplified manner, the amount proportional to the frequency error is Alternatively, the error Ay of the orthogonal component of the differential detection signal may be output as a frequency error.

The frequency error detected by the phase error detection unit 321b is input to a loop filter composed of the adder 322c and the delay unit 322d via the switching unit 322a, and the frequency error is averaged. Here, the frequency error holding unit 322 averages the frequency errors obtained only during the period of the frame synchronization signal / TMC C signal and the period of the carrier synchronization auxiliary signal in which BP SK modulation is performed within one communication frame. In order to perform the conversion, the switching unit 322a is switched using the timing signal output from the evening generation unit 36. The switching section 322a inputs the frequency error output from the phase error detection section 321b during the period of the BP SK modulation signal of the timing signal (Hi level period in FIG. 6 (c) or (d)) to the loop filter. During other periods, switching is performed so that “constant 0” generated by the constant generator 322b is input to the loop filter.

Then, the output signal of the frequency error holding unit 322 controls the numerical operation oscillating unit (NCO) 323, and the complex multiplication unit 324 cancels the frequency error by the oscillating signal obtained therefrom. As a result, the frequency error is corrected (step S103). In the above description, the input signal of the frequency error detection unit 321 is the output signal of the band limiting filter 33, but since the frequency error detection unit 321 uses delay detection, the signal after the complex multiplication unit 324 In other words, there is no particular limitation as long as it is an output signal of the complex multiplication unit 324, an output signal of the band limiting filter 33, or an output signal of the phase correction unit 34.

Next, the operation of the phase correction unit 34 will be described with reference to FIG.

In FIG. 18, the phase correction unit 34 includes a phase error detection unit 341, a switching unit 342a, a constant generation unit 342b, adders 342c and 342e, a delay unit 342d, and a holding unit. Phase error holding section 3 4 2 composed of 3 4 2 f and amplifier 3 4 2 g, and adder 3 4

Numerically controlled oscillator 3 4 3 consisting of 3 a, delay section 3 4 3 b, cosine wave generator 3 4 3 c and sine wave generator 3 4 3 d, and complex multiplier 3 4 4 .

At the initial stage of the operation of the phase corrector 34, the output signal of the band-limiting filter 33 is in phase with the output signal of the numerically controlled oscillator 3443, although the frequency error has been canceled by the frequency corrector 32. Therefore, the output of the complex multiplier 344 contains a phase error. The output of the complex multiplier 344 including the phase error is input to the phase error detector 341. As shown in Fig. 19, the phase error detection by the phase error detector 341 detects the phase difference between the received signal X with a phase shift ΔΦ and the reference phase on the receiving side indicated by 〇. I do. In addition, since processing is performed in the rectangular coordinate system (I, Q planes), the phase error is originally calculated by arctan (Q / I), but is simplified to an amount proportional to the phase error. , BPSK, the error ΔQ of the orthogonal component may be output as the phase error.

The phase error detected by the phase error detection unit 3 41

The signal is input to the loop filter composed of the adders 3 4 2 c and 3 4 2 e, the delay section 3 4 2 d and the amplifier 3 4 2 g via the 4 2 f, and the phase error signal is averaged. The loop filter in the phase error holding unit 342 is divided into a direct system that enters the adder 342 e via the amplifier 342 g, and a direct system that enters the adder 342 c and the delay unit 342 d. The direct system is used to correct phase errors, and the integral system is used to correct small frequency shifts that could not be removed by the frequency correction unit 32. The amplifier 342g determines the direct system and the integral system gain distribution.

Here, the phase error holding section 3 4 2 is used to average the phase error obtained only during the period of the frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in which BPSK modulation is performed in one communication frame. Using the timing signal output from the timing generation unit 36, the switching of the switching unit 342a and the control of the holding unit 342 are performed. This switching and control is performed during the period of the BPSK modulation signal of the timing signal. During this period (the Hi level period in FIG. 6 (c) or (d)), the phase error output from the phase error detector 341 is input to the loop filter.

In the loop-fill integration system, during the BPSK modulation signal period, the output signal of the phase error detector 341 is input to the adder 342c, and during the other periods, the constant generator 342b The switching section 3 4 2a is switched so that “constant 0” is input. In the direct system of the loop filter, during the BPSK modulation signal period, the output signal of the phase error detector 341 is output to the adder 342 e via the amplifier 342 g. During the period, the holding unit 342 f is controlled so as to hold the output signal of the phase error detection unit 341 in the previous BPSK modulation signal period and output the signal to the adder 342 e. Then, the output signal of the phase error holding unit 342 controls the numerical operation oscillating unit (NCO) 343, and the complex signal 344 cancels the phase error by the oscillating signal obtained therefrom. As a result, the phase error is corrected (Step S104). After that, the processing shifts to the steady demodulation processing (step S105).

The steady demodulation processing here is a demodulation operation after the phase correction unit 34 is phase-synchronized. The numerical control oscillation means 3 2 That is, the oscillation frequency of 3 is not changed, and the phase synchronization in the phase correction unit 34 is not lost. For example, once the phase is synchronized, until the phase synchronization is lost for some reason, the updating of the coefficient of the frequency error holding unit 322 of the frequency correction unit 32, the reduction of the loop gain (lowering the sensitivity), etc. In the flowchart of FIG. 5, the operation of the frequency correction unit 32 (step S103) and the operation of the phase correction unit 34 (step S104) are described in separate steps. However, there is no problem even if the phase correction unit 34 operates in step S103 (hereinafter, the same applies to the processing in step S103 in each embodiment).

As described above, according to the demodulation device according to the first embodiment of the present invention, time-division multiplexing Carrier recovery is performed using the BP SK that includes the carrier synchronization auxiliary signal dispersedly arranged in the bucket among the phase modulated signals, so that carrier synchronization can be performed quickly and stably even in a low C / N state. it can.

In addition, even when the input frequency error is large, carrier synchronization can be performed without erroneous operation of frame synchronization detection by delay detection.

(Second embodiment)

The demodulation device according to the second embodiment of the present invention avoids a malfunction due to pseudo synchronization in the phase correction unit 34 in the demodulation device according to the first embodiment. Therefore, pseudo-synchronization in the case where the phase is corrected using the carrier synchronization auxiliary signal modulated by BPSK will be described first.

Pseudo synchronization means that the insertion period of the carrier synchronization auxiliary signal in the modulator is constant (see Fig. 2), and the input frequency error to the phase correction unit 34 is 180 degrees xm (phase of the insertion period of the carrier synchronization auxiliary signal). (m is an arbitrary integer other than 0.) If the rotation frequency is used, the phase correction unit 34 cannot identify the original phase error in the carrier synchronization auxiliary signal cycle, and synchronizes with a different phase. is there.

For example, as shown in FIG. 20, when the phase is rotated by 180 degrees in the carrier synchronization auxiliary signal insertion period (① in the figure) due to a frequency shift (A in the figure), the phase error detection in the phase correction unit 34 It is not possible to detect a phase change in the carrier synchronization auxiliary signal insertion cycle ((2) in the figure). In this case, only a phase error of angle? Is detected at each time ((2) and (2) in the figure). (B in the figure).

By performing phase correction based on the phase error signal detected in this way, the phase correction unit 34 simulates carrier synchronization despite the presence of a frequency error, and shifts to a steady demodulation operation. Will be stable. The frequency of the pseudo synchronization is as shown in the following equation (2).

△ f = (mx l 80 degrees) / 360 degrees xf sym / S (2)

fs ym: Symbol frequency (modulation speed) [Hz] s: Carrier synchronization auxiliary signal insertion cycle [symbol]

m: Arbitrary integer (± 1, ± 2, ± 3, ...)

For example, when the symbol frequency is 20 Mbaud and the period is 207 symbols, pseudo-synchronization can be performed at each frequency as shown in FIG.

Hereinafter, a demodulation device according to the second embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

FIG. 22 is a block diagram showing a configuration of the demodulation device according to the second embodiment of the present invention, which corresponds to claims 10, 37, and 41. In FIG. 22, the demodulation device according to the second embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34 A, a frame synchronization detection unit 35, a timing generation section 36, a frequency pull-in detection section 42, a first error correction section 37, a second error correction section 38, a video decoder 39, and a TMCC decoder 40. , BER measuring unit 41.

FIG. 23 is a flowchart showing the operation performed by the demodulation device according to the second embodiment.

As shown in FIG. 22, the demodulation device according to the second embodiment is different from the demodulation device according to the first embodiment in that a frequency pull-in detection unit 42 that detects a frequency pull-in state in the frequency correction unit 32 In this configuration, the phase correction unit 34 is replaced with the phase correction unit 34A.

The rest of the configuration of the demodulation device according to the second embodiment is the same as the configuration of the demodulation device according to the above-described first embodiment. Omitted.

Steps in FIG. 23 that perform the same processing as in FIG. 5 are assigned the same step numbers, and descriptions thereof are omitted.

First, the operation of the frequency pull-in detection unit 42 will be described with reference to FIG. FIG. 24 is a diagram showing a more detailed configuration of the frequency pull-in detector 42 of FIG. FIG. In FIG. 24, the frequency pull-in detection unit 42 includes a frequency error detection unit 4 21 composed of a delay detection unit 4 21 a and a phase error detection unit 4 21 b, a switching unit 4 22, Integrator 4 2 4 consisting of constant generator 4 2 3, adder 4 2 4 a, delay 4 2 4 b, switch 4 2 4 c, constant generator 4 2 4 d, and evening It comprises a generator 425, an absolute value generator 427, and a frequency pull-in determiner 426.

The signal output from the band-limiting filter 33 is input to the delay detection unit 421a. The delay detection unit 4 2 1a performs complex multiplication of the current n-phase PSK modulation signal and the complex conjugate signal of the n-phase PSK modulation signal one symbol before, as in the other delay detection units, and performs delay detection. Calculate the output. The equation for calculating the delay detection output is as shown in the above equation (1).

Then, as described above, the phase error detection unit 4221b detects the phase difference from the X mark when there is a frequency shift as a frequency error with the mark when there is no frequency shift as a reference on the receiving side. (See Figure 14).

The frequency error detected by the phase error detection section 421b is input to the adder 424a via the switching section 422, and the frequency error is averaged every predetermined period. Here, in order to perform frequency pull-in detection by the frequency correction unit 32 during the period of the frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in which BPSK modulation is performed in one communication frame, the timing generation unit 36 The switching section 422 is switched using the output timing signal (FIG. 6 (c) or (d)). The switching section 422 integrates the frequency error output from the phase error detection section 421 b during the period of the BPSK modulation signal of the timing signal (the Hi level period in FIG. 6C or 6D). Input to 4 2 4, and in other periods, switch so that “constant 0” generated by constant generating section 4 2 3 is input to integrating section 4 2 4. The timing generation section 425 generates a timing pulse having a constant period, and controls the switching section 424c. The integrator 4 2 4 connects the input of the power calculator 4 2 a to the feedback output of the delay 4 2 4 b or the constant generator 4 in accordance with the timing pulse generated by the timing generator 4 2 5. By switching to one of the “constants 0” that generates 24d, an averaged frequency error for each fixed period is output. The averaged frequency error output from the integration unit 424 is converted to a positive value by the absolute value conversion unit 427, and then output to the frequency pull-in determination unit 426. The frequency pull-in determination unit 426 inputs the positive value averaged frequency error output from the absolute value averaging unit 427, and when the timing generation unit 425 generates a timing pulse, the averaged frequency error is determined in advance. The frequency pull-in is determined based on whether it is below the threshold (step S201).

When the averaged frequency error falls below a predetermined threshold value as a result of this determination, the frequency pull-in determination unit 426 performs frequency pull-in, that is, the frequency correction unit 32 performs pseudo-synchronization in the phase correction unit 34. Judgment is made that the frequency has been corrected to a frequency that does not occur, and a signal for resetting the phase correction unit 34 is output so that the phase correction unit 34 is operated again.

Here, the threshold value in the frequency pull-in determination unit 426 may be set in advance so that the phase correction unit 34 can determine whether or not the frequency correction unit 32 has corrected the frequency up to a frequency at which the pseudo-sync is not performed. The frequency of the pseudo-synchronization is as shown in the above equation (2).

For example, if the symbol frequency is 2 OMbaud and the period is 207 symbols, there are pseudo-synchronous frequencies as shown in FIG. 21, and the pull-in frequency range of the phase correction unit 34 around each pseudo-synchronous frequency exists. as the threshold value in the frequency pull-in determining unit 426, it is desirable to set the following frequency Di ¹ represented by the following formula (3).

△ f = 1/2 X 180 ° / 360 ° X f s ym / S (3)

fsym: Symbol frequency (modulation rate) [Hz]

S: Carrier synchronization auxiliary signal insertion cycle [symbol]

Next, the operation of the phase correction unit 34A will be described with reference to FIG.

FIG. 25 is a block diagram showing an example of a more detailed configuration of the phase correction unit 34A. You. As shown in FIG. 25, the phase correction unit 34 A further includes a switching unit 34 2 h and a constant generation unit 34 2 i in the phase error holding unit 34 2 in the configuration of the phase correction unit 34. This is an additional configuration.

In FIG. 25, components denoted by the same reference numerals as in FIG. 18 are components that perform the same operations, and thus description thereof will be omitted.

The reset signal output from the frequency pull-in determination unit 4 26 is input to the holding unit 3 42 f of the phase error holding unit 3 42 and the switching unit 3 42 h. The holding unit 342 initializes the phase error signal in the direct system based on the reset signal. The switching section 342 h switches the phase signal in the integration system by switching the feedback signal to the adder 342 c to “constant 0” output from the constant generation section 342 i based on the reset signal. Initialize the error signal.

As a result, in the phase correction unit 34 A, the frequency error corrected to the frequency at which the pseudo-synchronization does not occur for the phase error signal input to the phase error holding unit 342 after the reset operation. New phase correction is performed on the output signal of the correction unit 32 (step S202). After that, the processing shifts to the steady demodulation processing (step S105).

As shown in FIG. 26, also in the numerically controlled oscillation section 343, a switching section 343e and a constant generation section 344f are provided, and the switching section 324h and the constant generation section 344 are provided. Operations similar to 2 i may be performed in parallel. Performing the reset operation in parallel in this manner enables more reliable initialization.

As described above, the demodulation device according to the second embodiment of the present invention includes the frequency pull-in detection unit 42, and the frequency correction unit 32 performs frequency correction up to a frequency at which the phase correction unit 34A is not pseudo-synchronized. After that, reset the phase corrector 34A and restart it.

This makes it possible to avoid pseudo-synchronization in the complementary unit 34A during the frequency pull-in process by the frequency correction unit 32, and the like. In the demodulation device according to the second embodiment, since the frequency pull-in detection unit 42 uses delay detection, if the frequency correction unit 32 or later is used, the installation position is the frequency correction unit There is no particular limitation as long as it is the output of 32, the output of the band limiting filter 33, or the output of the complementary portion 34A.

Further, the frequency error detection section 4 21 of the frequency pull-in detection section 4 2 has the same function as the frequency error detection section 3 2 1 of the frequency correction section 3 2. It is also possible to share. If shared, the circuit scale can be reduced.

(Third embodiment)

The demodulation device according to the third embodiment of the present invention, like the second embodiment described above, has the same function as the second embodiment described above, except that the demodulation device according to the first embodiment malfunctions due to pseudo synchronization in the phase correction unit 34. Avoid it.

Hereinafter, a demodulation device according to a third embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

FIG. 27 is a block diagram showing the configuration of the demodulation device according to the third embodiment of the present invention, corresponding to claims 11, 37, and 42. In FIG. 27, the demodulation device according to the third embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34 A, a frame synchronization detection unit 35, evening timing generation section 36, phase synchronization detection section 43, error correction detection section 44, pseudo synchronization determination section 45, first error correction section 37, and second error It includes a correction unit 38, a video decoder 39, a TMCC decoder 40, and a BER measurement unit 41.

FIG. 28 is a flowchart illustrating an operation performed by the demodulation device according to the third embodiment.

As shown in FIG. 27, the demodulation device according to the third embodiment is different from the demodulation device according to the first embodiment in that the phase synchronization detection unit 43, the error correction detection unit 44, and the pseudo synchronization determination unit 4 5 is further added, and the phase correction unit 34 is replaced with a phase correction unit 34A. The other configuration of the demodulation device according to the third embodiment is the same as the configuration of the demodulation device according to the first and second embodiments, and the components are denoted by the same reference numerals. The description is omitted.

Also, steps in FIG. 28 that perform the same processing as in FIG. 5 are assigned the same step numbers, and descriptions thereof are omitted.

First, the operation of the phase synchronization detector 43 will be described.

The signal input via the tuner (not shown) is subjected to frequency correction and phase correction as described in the first embodiment (step S301), and then sent to the phase synchronization detector 43. Is entered. The phase synchronization detecting section 43 detects the phase synchronization / phase asynchronism only for the period of the BPSK modulated carrier synchronization auxiliary signal with respect to the input corrected signal.

As the phase synchronization detecting section 43, two embodiments having specific configurations can be considered. Hereinafter, these two embodiments will be described in order.

(Embodiment 1 of phase synchronization detector 43)

FIG. 29 is a block diagram illustrating a configuration of the phase synchronization detection unit 43 according to the first embodiment. Figure

29, the phase synchronization detection unit 43 includes the phase error detection unit 431, and the absolute value generation unit 431.

3 2, switching section 4 3 3, constant generating section 4 3 4, adder 4 35 a, delay section 4 35 b, switching section 4 35 c, and constant generating section 4 35 d An integrating section 435, a timing generating section 436, and a phase synchronization judging section 347 are provided.

The signal output from the phase correction unit 34 A is input to the phase error detection unit 43 1. As described above, the phase error detection unit 431 uses the symbol 〇 when there is no phase shift as a reference on the receiving side, and uses the phase difference from the X mark when there is a phase shift as the phase error ΔΦ [degree]. (See Figure 19). The phase error ΔΦ detected by the phase error detecting section 431 is converted into a positive value IΔΦI by the absolute value converting section 432. Then, the phase error I ΔΦ I output from the absolute value conversion unit 4 32 is input to the adder 4 35 a via the switching unit 4 33, and the phase error I Δ Φ I Are averaged. Where 1 In order to perform phase synchronization detection only during the period of the carrier synchronization auxiliary signal subjected to BPSK modulation in the transmission frame, the switching unit 4 uses the timing signal (Fig. 6 (d)) output by the timing generation unit 36. 3 Perform switching of 3. The switching unit 433 converts the phase error IΔΦI output from the absolute value conversion unit 432 during the period of the BPSK modulated signal of the evening signal (Hi level period in FIG. 6D) into the integration unit 4. In the other period, switching is performed so that “constant 0” generated by the constant generator 4 3 4 is input to the integrator 4 3 5. The timing generator 436 generates a timing pulse having a constant period, and controls the switch 435 c. The integrator 435 generates the input of the adder 435 a from the feedback output of the delay 435 b or the constant generator 435 d according to the timing pulse generated by the timing generator 435. By switching to any one of the constants “0”, the averaged phase error I ΔΦ I for each fixed period is output. The phase synchronization determination section 437 inputs the averaged phase error output from the integration section 435, and when the timing generation section 436 generates a timing pulse, the averaged phase error is a predetermined threshold. The phase synchronization is determined based on whether the value is below the value (step S302). Then, as a result of this determination, if the averaged phase error falls below a predetermined threshold, the phase synchronization determination section 437 determines that phase synchronization has been achieved, and compares the result with the pseudo synchronization determination section 45. Output to

Here, the threshold value in the phase synchronization determination section 437 can be set arbitrarily according to the purpose of use or characteristics of the demodulation device. For example, when the phase synchronization is completely out of sync (pseudo- When synchronization is not performed), the phase rotation remains as shown in Fig. 31 (a) and the symbols exist with the same probability over the entire 360 degrees. After conversion to a positive value (first quadrant) in 32, the phase error may be set to 45 degrees, which is the average value of the phase error, or lower (Fig. 31 (b)).

(Embodiment 2 of the phase synchronization detector 43)

FIG. 30 is a block diagram illustrating a configuration of the phase synchronization detection unit 43 according to the second embodiment. Figure In 30, the phase synchronization detecting section 43 adds the absolute value converting sections 4 32 A and 43 2 B, the comparing section 4 38, the switching section 4 33, and the constant generating section 4 3 4 to the addition. Integrator 4 3 5 consisting of the unit 4 3 5 a, delay 4 3 5 b, switching 4 3 5 c, constant generator 4 3 5 d, evening timing generator 4 3 6, and phase synchronization And a judgment unit 437.

As for the signal output from the phase correction section 34 A, the I (in-phase) component signal is input to the absolute value conversion section 4 32 A, and the Q (quadrature) component signal is input to the 4 32 B. The absolute value conversion unit 432A converts the input I component signal into a positive value I I I. The absolute value conversion section 4 3 2 B converts the input Q component signal into a positive value I Q I. The comparison unit 438 inputs the value III converted by the absolute value conversion unit 432A and the value | Q | converted by the absolute value conversion unit 432B, and compares both values. Outputs comparison value “1” for IQI and comparison value “0” for III≤i QI. The comparison value output by the comparison section 4 3 8

The signal is input to the adder 4 3 5 a via 3 3, and is averaged every certain period. Here, in order to perform phase synchronization detection only during the period of the carrier synchronization auxiliary signal in which BPSK modulation is performed in one communication frame, the evening timing signal (FIG. 6 (d)) output from the timing generation unit 36 is used. Switching unit 4 3 3 is switched. This switching unit

433 inputs the comparison value output by the comparison section 438 to the integration section 435 during the period of the BPSK modulation signal of the timing signal (the Hi level period in FIG. 6 (d)). During the period, switching is performed so that the “constant 0” generated by the constant generation section 434 is input to the integration section 435. The timing generator 436 generates a timing pulse having a constant period, and controls the switching unit 435c. The integrator 4 35 sends the input of the adder 4 35 a to the delay 4 3 5 according to the timing pulse generated by the timing generator 4 36.

By switching to either “constant 0”, which is the feedback output of 5 b or the constant generator 4 3 5 d, an averaged comparison value for each fixed period is output. The phase synchronization determination section 437 inputs the averaged comparison value output from the integration section 435, and when the timing generation section 436 generates a timing pulse, the averaged comparison value is determined in advance. The phase synchronization is determined based on whether the value falls below the threshold value (step S302). So Then, as a result of this determination, if the averaged comparison value falls below a predetermined threshold, the phase synchronization determination section 437 determines that phase synchronization has been achieved, and compares the result with the pseudo synchronization determination section 4. Output for 5

Here, the threshold value in the phase synchronization determination section 437 can be set arbitrarily according to the purpose of use or characteristics of the demodulation device. For example, when the phase synchronization is completely out of sync (pseudo- (When not synchronized), the phase rotation remains as shown in Fig. 31 (a), and the symbols exist with the same probability over the entire 360 degrees, so that iII> IQI Since the probability of entering the region is 1/2, it is sufficient to set it to a majority or less than the number of integrations performed by the integration unit 435 (Fig. 31 (b)).

Next, the operation of the error correction detection unit 44 will be described.

The error correction detection unit 44 inputs a signal indicating that error correction cannot be performed and a signal indicating that the error remains, which are output by the second error correction unit 38 in the process of error correction. Then, the error correction detection unit 44 detects whether or not correct error correction has been performed on the TMCC signal (step S303), and sends the result of this detection to the pseudo synchronization determination unit 45. Output.

Next, with reference to FIG. 32, the operation of the pseudo-synchronization determination unit 45 will be described.

The detection result of the phase synchronization detection unit 43 and the detection result of the error correction detection unit 44 are input to the pseudo synchronization determination unit 45. The pseudo-synchronization determination section 45 first determines whether or not phase synchronization has been achieved based on the determination result of the phase-lock detection section 43. If the phase synchronization is established in this determination, the pseudo-synchronization determination section 45 next determines whether the phase synchronization is normal synchronization or pseudo-synchronization from the determination result of the error correction section 44.

The reasons for making such a judgment are as follows.

The phase synchronization detector 43 can reliably determine the phase asynchronism.However, since the phase synchronization is determined only during the period of the carrier synchronization auxiliary signal, whether the synchronization is normal even if the phase synchronization is achieved. It cannot be determined whether it is pseudo-synchronous. For example, If the received signal has a frequency shift of 180 degrees in phase at the insertion interval of the carrier synchronization auxiliary signal, the phase synchronization judgment only during the period of the carrier synchronization auxiliary signal is as shown in FIG.

As shown in (a), it is determined that synchronization is apparent (ie, pseudo-synchronization). On the other hand, in the case of the pseudo-synchronization, the output signal of the phase corrector 34A during the TMCC signal period has a large phase rotation as shown in FIG. 32 (b) (arrow in the figure). Bit errors that cannot be corrected by the error correction unit 38 (shaded portions in the figure) are included. Therefore, pseudo-synchronization can be determined by detecting whether or not the second error correction unit 38 has been able to correct the error with respect to the TMC C signal normally.

As described above, the pseudo-synchronization determination unit 45 determines phase synchronization / asynchronization based on the detection result of the phase synchronization detection unit 43, and determines normal synchronization / pseudo-synchronization based on the detection result of the error correction detection unit 44. I have. This determination method is shown in Table 1 below.

【table 1】

Then, as a result of performing the above-described determination, if the pseudo-synchronization determination unit 45 determines that the synchronization is normal, the pseudo-synchronization determination unit 45 proceeds to the steady demodulation processing as it is (step S105) and determines that the synchronization is pseudo-synchronization. In this case, a signal for resetting the phase correction operation is output to the phase correction section 34A (step S304). This reset signal can be arbitrarily set, for example, a pulse signal sufficient to operate the phase correction unit 34A. Based on the reset signal output from the pseudo-synchronization determination section 45, the phase correction section 34 The reset operation performed by A is the same as that described in the second embodiment, and the description here is omitted, but the purpose of instructing the reset operation is different from each other. That is, in the second embodiment, the reset operation is performed as an initialization operation for starting the phase correction operation after the frequency correction is normally performed, and the reset operation is performed in the third embodiment. Is an instruction for a reset operation to re-perform the complementation when the normal synchronization is not performed as a final result.

As described above, the demodulation device according to the third embodiment of the present invention detects the phase synchronization during the period of the carrier synchronization auxiliary signal, and detects whether the TMCC signal is error-correctable. It is determined whether or not it is synchronous. Then, in the case of the pseudo synchronization, the phase correction unit 34A is reset and restarted.

This makes it possible to avoid pseudo-synchronization in the complementary unit 34A during the frequency pull-in process by the frequency correction unit 32, and the like.

When the first embodiment is used in the phase synchronization detecting section 43, the phase error detecting section 431 included therein is different from the phase error detecting section 341 included in the phase correcting section 34A. Since they have similar functions, it is possible to share both phase error detectors. If shared, the circuit scale can be reduced.

(Fourth embodiment)

The demodulation device according to the fourth embodiment of the present invention is the same as the second and third embodiments described above, except that in the demodulation device according to the first embodiment, the pseudo synchronization in the phase correction unit 34 is used. This avoids a malfunction caused by the above.

Hereinafter, a demodulation device according to a fourth embodiment of the present invention which avoids the above-described malfunction due to pseudo synchronization will be described.

FIG. 33 is a block diagram showing a configuration of a demodulation device according to a fourth embodiment of the present invention, corresponding to claims 12, 37, and 43. In FIG. 33, the demodulation device according to the fourth embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34 A, a frame synchronization detection unit 3 5 and timing generator 3 6 A first phase synchronization detection unit 43A, a second phase synchronization detection unit 43B, a pseudo synchronization determination unit 45, a first error correction unit 37, a second error correction unit 38, and a video decoding unit. BER 39, a TMCC decoder 40, and a BER measurement unit 41.

As shown in FIG. 33, the demodulation device according to the fourth embodiment is different from the demodulation device according to the first embodiment in that a first phase synchronization detection unit 43A and a second phase synchronization detection unit 43B are provided. This is a configuration in which a pseudo-synchronization determination unit 45 is further added, and the phase correction unit 34 is replaced with a phase correction unit 34A. Also, in the demodulation device according to the third embodiment, the phase synchronization detection unit 43 is The configuration is such that the error correction detection unit 44 is replaced by the second phase synchronization detection unit 43B in the first phase synchronization detection unit 43A.

The rest of the configuration of the demodulator according to the fourth embodiment is the same as the configuration of the demodulator according to the first to third embodiments, and the same reference numerals are given to the components. The description is omitted.

In addition, the processing steps performed by the demodulation device according to the fourth embodiment are the same as the processing steps shown in FIG. 28 in the third embodiment, and thus description thereof will be omitted.

Hereinafter, a portion in which the demodulation device according to the fourth embodiment performs an operation different from that of the demodulation device according to the third embodiment will be described.

First, based on the frame start signal detected by the frame synchronization detector 35, the timing generator 36 generates a timing signal for the period of the frame synchronization signal / TMC signal and the period of the carrier synchronization auxiliary signal (FIG. 6 (c) ) And a timing signal only during the period of the carrier synchronization auxiliary signal (see Fig. 6 (d)), and a timing signal only during the period of the frame synchronization signal / TMCC signal (Fig. 34). . The timing signal only during the period of the frame synchronization signal / TMCC signal is output to the second phase synchronization detection unit 43B.

The first phase synchronization detecting section 43A and the second phase synchronization detecting section 43B have the same configuration as that described in the third embodiment (FIG. 29 or 30). First phase synchronization In the detection unit 43A, a timing signal only during the period of the carrier synchronization auxiliary signal is used to control the switching unit 433, and the synchronization / asynchronization of the phase during the period is performed on the signal after the frequency correction and the phase correction. Detection is performed (FIG. 28, step S302). In the second phase synchronization detection section 43B, a timing signal only during the period of the frame synchronization signal / TMCC signal is used to control the switching section 433, and the signal after frequency correction and phase correction is used. Detection of phase synchronization / asynchronization in the period is performed (FIG. 28, step S303).

Then, the first phase synchronization detecting section 43A and the second phase synchronization detecting section 43B output a detection result indicating whether or not phase synchronization has been achieved to the pseudo synchronization determining section 45, respectively. The pseudo-synchronization determination unit 45 makes a determination shown in Table 2 below based on the detection results of the first phase-lock detection unit 43A and the second phase-lock detection unit 43B, and it is normal synchronization. If it is determined that the phase is correct, the process proceeds to the normal demodulation process (FIG. 28, step S105). Is output (FIG. 28, step S304).

[Table 2]

The reason for the above determination is the same as that in the above-described second error correction section 38, that is, in the first phase synchronization detection section 43A, the period of the carrier synchronization auxiliary signal is Since phase synchronization is detected, apparent synchronization is achieved as shown in Fig. 35 (a) even during pseudo synchronization, while the second phase synchronization detector 43B has Since the phase synchronization is detected during the period of the frame synchronization signal / TMCC signal, the phase is largely rotated during pseudo-synchronization as shown in Fig. 35 (b) (arrow in the figure), and the phase homology is established. It is because it can be judged that there is not. Therefore, by detecting this phase asynchronism, it is possible to determine that it is pseudo-synchronous.

As described above, the demodulation device according to the fourth embodiment of the present invention performs detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of phase synchronization during the period of the frame synchronization signal / TMCC signal. Judge from the detection result whether or not the synchronization is normal. Then, in the case of the pseudo synchronization, the phase correction unit 34A is reset and restarted.

In the case where the first embodiment is used in the first phase synchronization detecting section 43A and the second phase synchronization detecting section 43B, the phase error detecting section 431, included in the first and second phase synchronization detecting sections 43A and 43B, performs phase correction. Since it has the same function as the phase error detection section 341 included in the section 34A, both phase error detection sections can be shared. If shared, the circuit scale can be reduced.

(Fifth embodiment)

The demodulation device according to the fifth embodiment of the present invention is similar to the second to fourth embodiments described above, except that the demodulation device according to the first embodiment employs a pseudo-synchronization in the phase correction unit 34. This is to avoid malfunction. However, while the demodulation devices according to the second to fourth embodiments control the phase correction unit, the demodulation device according to the fifth embodiment can detect the pseudo-synchronous frequency. (As described above, which is uniquely determined by the symbol frequency and the insertion period of the carrier synchronization auxiliary signal), and controls the frequency correction unit.

Hereinafter, a demodulation device according to a fifth embodiment of the present invention that avoids the malfunction due to the pseudo synchronization described above will be described. FIG. 36 is a block diagram showing a configuration of a demodulation device according to a fifth embodiment of the present invention, corresponding to claims 13, 37, 39, 44, and 65. In FIG. 36, the demodulator according to the fifth embodiment includes a quadrature detection unit 31, a frequency correction unit 32 A, a band limiting filter 33, a phase correction unit 34, and a frame synchronization detection unit. 35, a timing generation unit 36, a phase synchronization detection unit 43, an error correction detection unit 44, a pseudo synchronization determination unit 45, a frequency step unit 46, and a first error correction unit 3 7, a second error correction section 38, a video decoder 39, a TMCC decoder 40, and a BER measurement section 41.

FIG. 37 is a flowchart showing the operation performed by the demodulation device according to the fifth embodiment.

As shown in FIG. 36, the demodulation device according to the fifth embodiment is different from the demodulation device according to the first embodiment in that the phase synchronization detection unit 43, the error correction detection unit 44, and the pseudo synchronization determination unit 4 5 and a frequency step unit 46 are further added, and the frequency correction unit 32 is replaced with a frequency correction unit 32 A. Further, the frequency correction unit 32 is different from the demodulation device according to the third embodiment. The configuration is such that 32 is replaced with a frequency correction section 32 A, the phase correction section 34 A is returned to the phase correction section 34, and a frequency step section 46 is further added.

The rest of the configuration of the demodulation device according to the fifth embodiment is the same as the configuration of the demodulation device according to the first and third embodiments, and the components are denoted by the same reference numerals. The description is omitted.

Also, in FIG. 37, steps for performing the same processing as in FIGS. 5 and 28 are denoted by the same step numbers, and description thereof will be omitted.

Hereinafter, a portion in which the demodulation device according to the fifth embodiment performs an operation different from that of the demodulation device according to the third embodiment will be described.

First, the operation of the pseudo synchronization determination section 45 will be described.

As described above, the pseudo synchronization determination unit 45 determines whether the phase synchronization is normal synchronization or pseudo synchronization based on the detection result of the phase synchronization detection unit 43 and the detection result of the error correction detection unit 44. to decide. Then, as a result of performing the above-described determination, the pseudo-synchronization determination unit 45 directly proceeds to the normal demodulation processing when it is determined that the synchronization is normal (step S105), and when the pseudo-synchronization is determined. Outputs a signal that causes the frequency step section 46 to perform a step operation (the signal form is the same as the above-described reset signal) (step S401).

Here, a method of generating a signal for performing a step operation in the pseudo synchronization determination section 45 will be described with reference to FIG. FIG. 38 is a block diagram illustrating an example of the configuration of the pseudo-synchronization determination section 45. In FIG. 38, the pseudo-synchronization determination unit 45 includes a logical sum (0 R) circuit 451, a counter 452, and a pulse output unit 453.

The pseudo synchronization determination unit 45 inputs the detection result of the phase synchronization detection unit 43 to the input terminal of the counter 45, and inputs the detection result of the error correction detection unit 44 to one terminal of the OR circuit 45 1. I do. The counter 452 counts the period during which the detection result of the phase synchronization detector 43 is Hi, and clears the counted value when the output of the OR circuit 451 becomes Hi. The pulse output section 453 determines whether or not the count value output from the counter 452 has reached a predetermined value, and outputs a pulse signal indicating a step operation when the count value has reached a predetermined value. The pulse signal is fed back to the other terminal of the R circuit 451, and the count value of the counter 452 is cleared simultaneously with the output of the pulse signal. As a result, when normal synchronization is detected (that is, when phase synchronization is detected, the counter 452 starts counting, but it is detected that error correction has been completed before the count value reaches a predetermined value). In this case, no pulse signal is output, and the phase is synchronized but pseudo-synchronous (that is, the phase synchronization is detected and the counter 452 starts counting, but the error correction is not completed and the count value is increased). If the value reaches a predetermined value), a pulse signal is output.

Next, the operation of the frequency step unit 46 will be described with reference to FIGS. FIG. 39 is a block diagram showing an example of the configuration of the frequency step section 46. As shown in FIG. FIG. 40 is a diagram showing signal waveforms generated by the frequency step unit 46. Figure 41 shows the FIG. 7 is a diagram showing the operation principle of a wave number step unit 46.

In FIG. 39, the frequency step unit 46 includes a control signal generation unit 461 composed of an exclusive OR (X〇R) circuit 46 1 a, a delay unit 46 lb, and a logical product (AND) circuit 461 c. It includes a constant generation unit 462, a second constant generation unit 463, a switching unit 464, an integration unit 465, a negative encoding unit 466, and a switching unit 467. The pulse signal (FIG. 40 (a)) output from the pseudo-synchronization determination unit 45 is input to the XOR circuit 461a and the AND circuit 461c, respectively. The XOR circuit 461a performs an exclusive OR operation on the pulse signal and a signal that is fed back via the delay unit 461b, and generates and outputs a control signal B (FIG. 40 (c)). The AND circuit 461c calculates the logical product of the pulse signal and the control signal B, generates and outputs the control signal A (FIG. 40 (b)). The switching unit 464 generates a constant Fg generated by the first constant generation unit 462 when the control signal A is at the Hi level (a numerical value in which the oscillation frequency of the numerical control oscillation unit 323 changes by the pseudo-synchronous frequency interval (fg)). Is switched to output the “constant 0” generated by the second constant generation unit 463 when the control signal A is at the Lo level to the integration unit 465. Integrator 465 performs cumulative addition of the input numerical values and outputs the result. The switching unit 467 outputs the signal output from the integrating unit 465 as it is when the control signal B is at the Hi level, and the negative encoding unit 466 outputs the signal output from the integrating unit 465 when the control signal B is at the L0 level. And then switch to output.

Therefore, every time the pulse signal (FIG. 40 (a)) becomes Hi level, the frequency step section 46 sets the frequency signal shown in FIG. 40 (d), that is, + Fg, -Fg, + 2Fg, -2Fg,. Are output in order.

The reason for outputting the frequencies in this order (step) will be described with reference to FIG. FIG. 41 shows the case where the frequency f _g is 48.3 kHz and the frequency is 96.6 kHz and the pseudo synchronization is performed.

As described in the second embodiment, the frequency interval fg at which pseudo synchronization occurs is determined from the symbol frequency and the insertion period of the carrier synchronization auxiliary signal. Can be. In other words, it can be said that the pseudo synchronization occurs at the frequency of the normal synchronization frequency ± πι · fg (m is an integer other than 0). Therefore, based on the frequency fg, + F g, -F g, +2 F g, -2 F g,... Are calculated by the frequency step unit 46, and the frequency correction unit 32A is calculated based on the calculated value. Is controlled to change to + fg, -fg, +2 fg, one 2 fg, ..., and forcedly shifted to a frequency that can be phase-synchronized by the phase correction unit 34, so that the normal phase This leads to synchronization (Fig. 41).

In the demodulation device according to the fifth embodiment, the frequency of the phase synchronization in the phase correction unit 34 is forcibly shifted in the frequency correction unit 32A. Hereinafter, the operation of the frequency correction unit 32A will be described with reference to FIG.

In FIG. 36, the frequency correction unit 32A includes a frequency error detection unit 321, a frequency error holding unit 322, an adder 325, a numerically controlled oscillation unit 323, and a complex multiplication unit 324.

As shown in FIG. 36, the frequency correction unit 32A has a configuration in which an adder 325 is further added to the frequency correction unit 32 of FIG. The output signal of frequency error holding section 322 and the frequency step control signal output from frequency step section 46 are input to adder 325. The adder 325 forcibly shifts the oscillation frequency of the numerical operation oscillator (NCO) 323 by adding both the input signals. Thereafter, phase correction is performed again at the shifted frequency (steps S401 and S104). As described above, the demodulation device according to the fifth embodiment of the present invention performs detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of the presence or absence of a bit error during the period of the frame synchronization signal / TMCC signal. Then, it is determined from the detection result whether or not the synchronization is normal. In the case of pseudo synchronization, the frequency of the frequency correction unit 32A is controlled so that the phase correction unit 34 can perform normal synchronization.

This makes it possible to avoid quasi-synchronization in the phase correction unit 34 during the frequency pull-in process and the like by the frequency correction unit 32A. (Sixth embodiment)

The demodulation device according to the sixth embodiment of the present invention is similar to the second to fifth embodiments described above, except that the demodulation device according to the first embodiment employs a pseudo-synchronization in the phase correction unit 34. This is to avoid malfunction. However, while the demodulation devices according to the second to fourth embodiments control the phase correction unit, the demodulation device according to the sixth embodiment has the same configuration as the fifth embodiment. The frequency correction unit is controlled by using the fact that the frequency of the pseudo synchronization is known (as described above, it is uniquely determined by the symbol frequency and the insertion period of the carrier synchronization auxiliary signal).

Hereinafter, a demodulation device according to a sixth embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

FIG. 42 is a block diagram showing a configuration of a demodulation device according to a sixth embodiment of the present invention, corresponding to claims 14, 37, 39, 45, and 65. In FIG. 42, the demodulation device according to the sixth embodiment includes a quadrature detection unit 31, a frequency correction unit 32 A, a band limiting filter 33, a phase correction unit 34, and a frame synchronization detection unit. 35, a timing generation unit 36, a first phase synchronization detection unit 43A, a second phase synchronization detection unit 43B, a pseudo synchronization determination unit 45, and a frequency step unit 46. , A first error correction unit 37, a second error correction unit 38, a video decoder 39, a TMCC decoder 40, and a BER measurement unit 41.

As shown in FIG. 42, the demodulation device according to the sixth embodiment is different from the demodulation device according to the first embodiment in that a first phase synchronization detection unit 43 A and a second phase synchronization detection unit 4 3B, a pseudo-synchronization determination unit 45 and a frequency step unit 46 are further added, and the frequency correction unit 32 is replaced by a frequency correction unit 32A. Also, the demodulation according to the fourth embodiment is performed. In the device, the frequency correction unit 32 is replaced with the frequency correction unit 32A, the phase correction unit 34A is returned to the phase correction unit 34, and the frequency step unit 46 is added.

Note that other configurations of the demodulation device according to the sixth embodiment are the same as those of the first and fourth demodulation devices. The configuration is the same as that of the demodulation device according to this embodiment, and the same components are denoted by the same reference numerals and description thereof will be omitted.

The processing steps performed by the demodulation device according to the sixth embodiment are the same as the processing steps shown in FIG. 37 in the fifth embodiment, and a description thereof will be omitted. A portion in which the demodulation device performs an operation different from that of the demodulation device according to the fourth embodiment will be described.

As described above, based on the detection result of the first phase synchronization detection unit 43A and the detection result of the second phase synchronization detection unit 43B, the pseudo synchronization determination unit 45 determines whether the phase synchronization is normal synchronization or not. Determine if they are synchronized. Then, as a result of performing the above-described determination, the pseudo-synchronization determination unit 45 proceeds to the normal demodulation processing if it is determined that the synchronization is normal (step S105). A signal for causing the frequency step section 46 to perform the step operation (the signal form is the same as the reset signal described above) is output (step S401).

Note that the method of generating a signal for performing a step operation in the pseudo-synchronous determination unit 45 and the configuration of the pseudo-synchronous determination unit 45 have been described in the fifth embodiment, and a description thereof will be omitted.

As described in the fifth embodiment, each time the pulse signal (FIG. 40 (a)) goes to the Hi level, the frequency step unit 46 performs the frequency signal shown in FIG. Fg, -F g, +2 F g, -2 F g, ... are output in order. Then, the frequency step unit 46 inputs the output frequency step control signal to the adder 325 of the frequency correction unit 32A. The adder 325 adds the input frequency step control signal to the output signal of the frequency error holding unit 322 to forcibly shift the oscillation frequency of the numerical calculation oscillator (NCO) 323. Thereafter, phase correction is performed again at the shifted frequency (steps S401 and S104).

As described above, the demodulation device according to the sixth embodiment of the present invention provides a carrier synchronization assist Detection of phase synchronization in the signal period and detection of phase synchronization in the frame synchronization signal / TMCC signal period are performed, and it is determined from the detection result whether or not the synchronization is normal. Then, in the case of the pseudo synchronization, the frequency of the frequency correction unit 32A is controlled so that the phase correction unit 34 can perform normal synchronization.

This makes it possible to avoid pseudo synchronization in the phase correction unit 34 during the frequency pull-in process by the frequency correction unit 32A.

(Seventh embodiment)

The demodulation device according to the seventh embodiment of the present invention is the same as the second to sixth embodiments described above, except that the demodulation device according to the first embodiment employs a pseudo synchronization in the phase correction unit 34. This is to avoid malfunction. The demodulation device according to the seventh embodiment controls the phase correction unit performed in the second embodiment and controls the frequency correction unit performed in the fifth embodiment.

Hereinafter, a description will be given of a demodulation device according to a seventh embodiment of the present invention which avoids the malfunction caused by the pseudo synchronization described above.

FIG. 43 is a block diagram showing a configuration of a demodulation device according to a seventh embodiment of the present invention, which corresponds to claims 15, 37, 39, 46, and 65. In FIG. 43, the demodulation device according to the seventh embodiment includes a quadrature detection unit 31, a frequency correction unit 32A, a band limiting filter 33, a phase correction unit 34A, a frame synchronization detection Unit 35, evening-imaging generation unit 36, frequency lock-in detection unit 42, phase synchronization detection unit 43, error correction detection unit 44, pseudo-synchronization determination unit 45, and frequency step unit 4 6, a first error correction section 37, a second error correction section 38, a video decoder 39, a TMCC decoder 40, and a BER measurement section 41.

As shown in FIG. 43, the demodulation device according to the seventh embodiment has a configuration in which the demodulation device according to the second embodiment and the demodulation device according to the fifth embodiment are combined. Accordingly, the configuration of the demodulation device according to the seventh embodiment is the same as the configuration of the demodulation devices according to the second and fifth embodiments, and the same reference numerals are given and the description thereof will be omitted. Abbreviate.

However, since the order of the processing steps is slightly different, the processing steps performed by the demodulation device according to the seventh embodiment will be described below with reference to FIG.

The demodulator first detects a frame synchronization signal in the frame synchronization detection unit 35 for a signal input to the quadrature detection unit 31 via a tuner (not shown) (step S101). The frame head signal detected by the frame synchronization detection unit 35 is input to the timing generation unit 36. In the demodulation device, based on the frame head signal detected by the frame synchronization detection unit 35 in the timing generation unit 36, the period of the frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in one communication frame Is detected, and a BP SK evening timing signal corresponding to the period as shown in FIG. 6 (c) is generated (step S102). Note that a BPSK timing signal corresponding only to the period of the carrier synchronization auxiliary signal as shown in FIG. 6D may be used. The BPSK timing signal (FIG. 6 (c)) is output to the frequency correction unit 32A, the phase correction unit 34A, and the frequency pull-in detection unit 42. Further, a signal giving the period of the carrier synchronization auxiliary signal shown in FIG. 6 (d) is output to the phase synchronization detection unit 43. Next, the demodulation device sets the period of the BP SK timing signal in the frequency correction unit 32A. The frequency error is corrected for (step S103). Then, in the demodulation device, the frequency pull-in detection unit 42 calculates an average frequency error for the frequency-corrected signal, and determines the frequency pull-in state (step S201). If the demodulation device determines in step S201 that the frequency has not been pulled, the process returns to step S103 to perform the frequency error correction process again, while determining that the frequency has been pulled. In this case, after resetting the phase correction operation for the phase correction unit 34A (step S304), a new phase error correction process is performed (step S104).

When the above series of frequency error and phase error correction processing is completed, the demodulation device The pseudo-synchronization determination unit 45 detects the phase synchronization state during the carrier synchronization auxiliary signal period detected by the phase synchronization detection unit 43 and the detection result of whether the TMCC signal can correct the error detected by the error correction detection unit 44. Then, it is determined whether the current state is normal synchronization, pseudo synchronization, or asynchronous (steps S302, S303). If the demodulation device determines that the state is asynchronous in steps S302 and S303, the demodulator returns to step S104 to perform the phase error correction process again, and the state becomes pseudo. If synchronization is determined, the oscillation frequency in the frequency correction unit 34A is stepped by the frequency step unit 46 (step S401), and then the process returns to step S104 to return to the phase error. Perform correction processing. On the other hand, if the demodulation device determines that the state is normal synchronization in the above-mentioned steps S302 and S303, it shifts to a steady demodulation process as it is (step S105).

As described above, the demodulation device according to the seventh embodiment of the present invention is provided with the frequency pull-in detection unit 42, and the frequency correction unit 32A includes a frequency correction unit 34A up to a frequency at which the phase correction unit 34A does not simulate. After the frequency correction is performed, reset the phase corrector 34 A and restart it. Further, phase synchronization is detected during the period of the carrier synchronization auxiliary signal, and the presence / absence of a bit error is detected during the period of the frame synchronization signal / TMCC signal. From the detection result, it is determined whether or not normal synchronization is performed. In the case of pseudo synchronization, the frequency of the frequency correction unit 32A is controlled so that the phase correction unit 34A can perform normal synchronization.

This makes it possible to avoid false synchronization in the phase corrector 34A during the frequency pull-in process by the frequency corrector 32A.

(Eighth embodiment)

The demodulation device according to the eighth embodiment of the present invention is the same as the second to seventh embodiments described above, except that the demodulation device according to the first embodiment employs pseudo-synchronization in the phase correction unit 34. This is to avoid malfunction. The demodulation device according to the eighth embodiment includes the control of the phase correction unit performed in the second embodiment and the control of the frequency correction performed in the sixth embodiment. It controls the number correction unit.

Hereinafter, a demodulation device according to an eighth embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

FIG. 45 is a block diagram showing a configuration of a demodulation device according to an eighth embodiment of the present invention, corresponding to claims 16, 37, 39, 47, and 65. In FIG. 45, the demodulation device according to the eighth embodiment includes a quadrature detection unit 31, a frequency correction unit 32A, a band limiting filter 33, a phase correction unit 34A, a frame synchronization detection Section 35, evening-imaging section 36, frequency pull-in detecting section 42, first phase-locking detecting section 43A, second phase-locking detecting section 43B, and pseudo-sync determining section 45, a frequency step section 46, a first error correction section 37, a second error correction section 38, a video decoder 39, a TMCC decoder 40, and a BER measurement section 41. Prepare.

As shown in FIG. 45, the demodulation device according to the eighth embodiment has a configuration in which the demodulation device according to the second embodiment and the demodulation device according to the sixth embodiment are combined. Therefore, the configuration of the demodulation device according to the eighth embodiment is the same as the configuration of the demodulation devices according to the second and sixth embodiments, and the same reference numerals are given and the description is omitted.

The processing steps performed by the demodulation device according to the eighth embodiment are basically the same as those of the demodulation device according to the seventh embodiment, and the flowchart is omitted. explain.

The demodulation device first detects a frame synchronization signal in a frame synchronization detection unit 35 for a signal input to the quadrature detection unit 31 via a tuner (not shown) (step S101). The frame head signal detected by the frame synchronization detection unit 35 is input to the timing generation unit 36. The demodulation device, in the timing generation section 36, based on the frame head signal detected by the frame synchronization detection section 35, detects the period of the frame synchronization signal / TMCC signal in one communication frame and the carrier synchronization auxiliary signal. The period is detected, and the BPSK evening image corresponding to the period is detected as shown in Fig. 6 (c). A signaling signal is generated (step S102). It should be noted that the BP SK timing signal according to only the period of the carrier synchronization auxiliary signal as shown in FIG. 6 (d) may be used. The BPSK timing signal (FIG. 6 (c)) is output to the frequency correction unit 32A, the phase correction unit 34A, and the frequency pull-in detection unit 42. A signal giving the period of the carrier synchronization auxiliary signal shown in FIG. 6 (d) is sent to the first phase synchronization detection unit 43A, and the frame synchronization shown in FIG. 34 is sent to the second phase synchronization detection unit 43B. A signal giving a signal / TMCC signal period is output.

Next, in the demodulation device, the frequency correction unit 32A corrects the frequency error for the period of the BP SK timing signal (step S103). Then, in the demodulation device, the frequency pull-in detection unit 42 calculates an average frequency error for the frequency-corrected signal, and determines the frequency pull-in state (step S201). If the demodulation device determines in step S201 that the frequency has not been locked, the process returns to step S103 to perform the frequency error correction process again. If it is determined, the phase correction operation is reset for the phase correction unit 34A (step S304), and then a new phase error correction process is performed (step S104).

When the above-described series of frequency error and phase error correction processing is completed, the demodulation device determines, in the pseudo synchronization determination unit 45, the phase synchronization state of the carrier synchronization auxiliary signal period detected by the first phase synchronization detection unit 43A, Based on the phase synchronization state of the T MCC signal period detected by the second phase synchronization detection unit 43B, it is determined whether the current state is normal synchronization, pseudo synchronization, or asynchronous (step S302, S 303). If the demodulator determines in step S302 or S303 that the state is asynchronous, the demodulator returns to step S104 and corrects the phase error again, and the state becomes pseudo-synchronous. If it is determined that there is, the oscillation frequency in the frequency correction unit 34A is stepped by the frequency step unit 46 (step S401), and the process returns to the step S104 to correct the phase error again. On the other hand, the demodulator If it is determined in steps S302 and S303 that the state is normal synchronization, the process directly proceeds to a steady demodulation process (step S105).

As described above, the demodulation device according to the eighth embodiment of the present invention includes the frequency pull-in detection unit 42, and the frequency correction unit 32A up to the frequency at which the phase correction unit 34A is not pseudo-synchronized. After the frequency correction is performed, reset the phase corrector 34 A and restart it. Further, phase synchronization is detected during the period of the carrier synchronization auxiliary signal, and phase synchronization is detected during the period of the frame synchronization signal / TMCC signal. From the detection result, it is determined whether the synchronization is normal or not. In the case of the pseudo synchronization, the frequency of the frequency correction unit 32A is controlled so that the phase correction unit 34A can perform normal synchronization. This makes it possible to avoid false synchronization in the phase corrector 34A during the frequency pull-in process by the frequency corrector 32A.

(Ninth embodiment)

The demodulation device according to the ninth embodiment of the present invention improves the reception performance by reducing the effect of phase jitter caused by phase noise in the demodulation device according to the first embodiment. .

Therefore, the phase jitter of the demodulated signal in the case where the phase is corrected using the frame synchronization signal / TMCC signal and the carrier synchronization auxiliary signal which are BPSK modulated will be described first.

As shown in Fig. 46, the communication frame input to the demodulator, that is, the phase modulation signal, has a subtle phase as shown in Fig. 46 mainly due to the phase noise of the local oscillation frequency signal used for frequency conversion of the satellite broadcast antenna and tuner. Fluctuating. This phase change is called phase jitter.

As shown in FIG. 2, the communication frame transmitted from the modulation device includes a frame synchronization signal / TMCC signal and a carrier synchronization auxiliary signal which are subjected to BPSK modulation in a dispersed manner. Therefore, in order to perform carrier synchronization during the period of this signal in the demodulation device, as described in the first embodiment, the frequency correction unit 32 and the frequency correction unit 32 are used. The phase corrector 34 operates only during the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period.

As a result, the phase jitter is corrected during the period in which the phase correction unit 34 operates, but is not corrected during other periods. In other words, phase jitter is corrected during the period of the main signal (high-layer signal and low-layer signal) modulated by BPSK, QPSK, and 8ΡSK other than the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period. Instead, the phase jitter remains in the demodulated signal.

Therefore, for example, in the case of an 8PSK modulated signal, the C / N is low as shown in FIG. 47 (in the figure, the shaded circles correspond, and the smaller the circle, the higher the C / N and the higher the C / N If the phase error remains, the output signal of the phase correction unit 34 exceeds the phase boundary (shown by a dotted line in the figure) for identifying each code point, that is, if a code error occurs. It will happen.

Hereinafter, a demodulation apparatus according to a ninth embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter will be described.

FIG. 48 is a block diagram showing a configuration of a demodulation device according to a ninth embodiment of the present invention, corresponding to claims 17, 37, and 48. In FIG. 48, the demodulation device according to the ninth embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34B, a frame synchronization detection unit 35, and a timing generation unit. Unit 36, frame synchronization determination unit 47, C / N detection unit 48, gate signal selection unit 49, first error correction unit 37, second error correction unit 38, video decoder 39, TMCC It includes a decoder 40 and a BER measurement unit 41.

FIG. 49 is a flowchart showing an operation performed by the demodulation device according to the ninth embodiment.

As shown in FIG. 48, the demodulation device according to the ninth embodiment is different from the demodulation device according to the first embodiment in that a frame synchronization determination unit 47, a C / N detection unit 48, a gate signal selection unit 49 And the phase correction unit 34 is replaced with a phase correction unit 34B. You.

The rest of the configuration of the demodulation device according to the ninth embodiment is the same as the configuration of the demodulation device according to the above-described first embodiment. Omitted.

Also, the steps in FIG. 49 that perform the same processing as in FIG. 5 are assigned the same step numbers, and descriptions thereof are omitted.

First, the operation of the frame synchronization determination section 47 will be described with reference to FIG.

FIG. 50 is a block diagram showing a configuration of the frame synchronization determination section 47. In FIG. 50, the frame synchronization determination section 47 includes a phase identification section 471, and a collation section 472.

The signal input through the tuner (not shown) is subjected to the frequency correction and the phase correction as described in the first embodiment (steps S103, S104), and then the phase correction is performed. Input from the section 34B to the phase identification section 471. The phase identification unit 471 identifies the phase of the input signal. The collating unit 353 compares the signal identified by the phase identifying unit 471 with a predetermined frame synchronization signal, detects whether or not frame synchronization has been achieved, and uses the result as a gate signal. Output to the selection section 49 (Step S501).

Next, the operation of the C / N detector 48 will be described with reference to FIG.

FIG. 51 is a block diagram showing the configuration of the C / N detection unit 48, which detects C / N equivalently based on a phase error. In FIG. 51, the C / N detection unit 48 includes a phase error detection unit 481, an absolute value conversion unit 482, a switching unit 483, a constant generation unit 4884, and an adder 4 8 5 a, delay section 4 8 5 b, switching section 4 8 5 c, constant generating section 4 85 d, integrating section 4 85, timing generating section 4 86, C / N high level And a judgment unit 487.

A signal input via a tuner (not shown) is subjected to frequency correction and phase correction as described in the first embodiment (steps S103, S104). The signal is input from the phase correction unit 34 B to the phase error detection unit 48 1. As described above, the phase error detector 481 uses the symbol 〇 when there is no phase shift as a reference on the receiving side, and uses the phase difference from the X when there is a frequency shift as the phase error ΔΦ [degree]. (See Figure 19). The phase error ΔΦ detected by the phase error detector 481 is converted to a positive value IΔΦI by the absolute value converter 482. Then, the phase error I ΔΦ I output from the absolute value conversion unit 482 is input to the adder 485 a via the switching unit 483, and the phase error I Δ Φ I Are averaged. Here, in order to perform C / N detection only during the period of the carrier synchronization auxiliary signal in which BPSK modulation is performed in one communication frame, the timing signal (FIG. 6 (d)) output by the timing generation unit 36 is used. To switch the switching section 4 8 3. The switching unit 483 integrates the phase error I ΔΦ I output by the absolute value conversion unit 482 during the period of the BPSK modulation signal of the timing signal (the Hi level period in FIG. 6D). 5, and in other periods, switching is performed such that “constant 0” generated by the constant generation section 484 is input to the integration section 485. The timing generating section 486 generates a timing pulse having a constant period, and controls the switching section 485c. The integrator 485 generates the input of the adder 485a according to the timing pulse generated by the timing generator 486, and generates the feedback output of the delay 485b or the constant generator 485d. By switching to any one of “constant 0”, the averaged phase error I ΔΦ I for each fixed period is output. The C / N high level judgment unit 487 inputs the averaged phase error output from the integrator 485, and when the timing generator 486 generates a timing pulse, the averaged phase error is It is determined whether the C / N is high or low depending on whether the value falls below a predetermined threshold value (step S502). Then, as a result of this determination, if the averaged phase error falls below a predetermined threshold, the C / N high level determination unit 487 determines that C / N is high, and uses the result to select the gate signal. Output to part 49.

Here, the threshold value in the C / N high level determination section 487 is used for the phase correction section 34 B by using a modulation method having a large number of phases for the phase correction when the C / N is low. It must be determined so that the phase error detection unit 341 does not output incorrect phase error information.

For example, the distance D between n-phase PSK codes is represented by the following equation (4), where A is the amplitude of the n-phase PSK signal.

D = 2A.s i η (ττ / η) (4)

Based on this equation (4), the η-phase PSK inter-symbol distance D is D = 2 A for BPSK modulation, D = ^ 2 A for QP SK modulation, D = 2 As i η for 8 PSK modulation, κ / 8). Generally, as shown in FIG. 47, if the effective amplitude value of the noise is equal to or less than 1/2 of the intersymbol distance D, the phase error detection unit 341 is considered not to output erroneous phase error information. C / N at this time is expressed by the following equation (5).

C / N = 20-l og (A / (D / 2)) [dB]

The C / N high level threshold determines whether or not to perform phase correction during the 8PSK period. Therefore, in the above equation (5), 8.3 dB obtained by substituting the inter-symbol distance of 8PSK into the n-phase PSK intersymbol distance D is a measure of the C / N high level threshold.

The C / N detection unit 48 in FIG. 51 obtains the C / N equivalently by converting the phase error into an absolute value, and the C / N high level determination unit 487 corresponding to 8.3 dB is used. At the code point of 8PSK is 1/2 of the angle difference between adjacent phase discrimination boundaries (dotted lines in Fig. 47), that is, 11.25 [degrees].

Next, an operation of the gate signal selection unit 49 will be described with reference to FIG.

FIG. 52 is a block diagram showing a configuration of gate signal selecting section 49. In FIG. 52, the gate signal selection unit 49 includes an AND circuit 491, a constant generation unit 492, and a switching unit 493.

One input terminal of the AND circuit 491 receives the determination result output by the frame synchronization determination unit 47, and the other input terminal receives the detection result output by the C / N detection unit 48. Each is entered. The switching unit 493 includes a timing signal (FIG. 6 (c) or (d)) in the BPSK modulation signal period, which is an output signal of the timing generation unit 36, and “constant 1 (Hi level)” generated by the constant generation unit 492. And switches the output based on the signal indicated by the AND circuit 491. Here, switching section 493 determines that the determination result output from frame synchronization determination section 47 is “with synchronization” and the detection result output from C / N detection section 48 is “C / N is high”. In step S503, a constant 1 is output, ie, a gate signal instructing the execution of the phase correction operation during the entire communication frame period. If the result is other than that, the output signal of the timing generation unit 36 is output. That is, switching is performed so as to output a gate signal (FIG. 6 (c) or (d)) for instructing execution of the phase correction operation only in the BP SK period (step S504). This gate signal is output to the phase error holding unit 342 of the phase correction unit 34B. Next, the operation of the phase correction unit 34B will be described.

This phase corrector 34B differs from the phase corrector 34 of the demodulator according to the first embodiment only in the configuration of the phase error detector 341. Therefore, the operation of the phase error detection unit 341 will be described below with reference to FIGS. 53 and 54.

FIG. 53 is a block diagram showing a configuration of the phase error detection unit 341. In FIG. 53, the phase error detection section 341 includes a BPSK phase error detection section 341a, an 8PSK phase error detection section 341b, and a switching section 341d. FIG. 54 is a diagram for explaining phase error detection performed by the BPSK phase error detection section 341a and the 8PSK phase error detection section 341b.

The output of the complex multiplier 344 including the phase error is input to both the BPSK phase error detector 341a and the 8PSK phase error detector 341b. The BPSK phase error detector 34la detects the phase error with respect to the BPSK modulation axis (0 degree, 180 degrees) (Fig. 54 (a)). 34 lb 8PSK phase error detector, 8PSK modulation axis

(0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, 315 °) are detected (Fig. 54 (b)). Switching unit 341 d The timing signal period (BPSK modulation period) is output from the BPSK phase error detector 341a using the timing signal output from the analog signal generator 36. The phase error detected by the BPSK phase error detector 34a is used. Error detection unit 341 b Switches to output the detected phase error to phase error holding unit 342.

The operation after the phase error holding unit 342 is the same as that described in the first embodiment, except that the timing generation unit 36 outputs a signal for controlling the switching unit 342a and the holding unit 342f. The gate signal output by the gate signal selector 49 is used instead of the timing signal (gate signal) to be output (see FIG. 48).

Accordingly, the phase correction unit 34B can perform the phase correction based on the C / N state according to the timing signal and the gate signal (Step S505). The contents are shown in Table 3 below.

In Table 3 below, “BPSK synchronization signal period” refers to both the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period (when the timing signal in FIG. 6 (c) is used), or the carrier. The figure shows only the synchronization auxiliary signal period (when the timing signal in Fig. 6 (d) above is used).

[Table 3]

As described above, the demodulation device according to the ninth embodiment of the present invention determines the C / N state when phase synchronization is performed in the BP SK modulation signal period based on the phase error in the carrier synchronization auxiliary signal period. If the detected C / N is at a predetermined level, The phase error is corrected assuming that 8 PSK modulation is also performed for the main signal period of the system.

As a result, carrier synchronization can be performed quickly and stably even in a low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

Since the phase error detecting section 48 1 in the C / N detecting section 48 has the same function as the phase error detecting section 3 41 of the phase correcting section 34 B, both phase error detecting sections are used. It is possible to share. If they are shared, the circuit scale can be reduced. Since the frame synchronization determination section 47 is an example of a method of determining phase synchronization, the phase synchronization detection section 43 described in the third embodiment is used instead of the frame synchronization determination section 47. The same effect can be obtained.

(10th embodiment)

The demodulation device according to the tenth embodiment of the present invention, similar to the ninth embodiment described above, reduces the influence of phase jitter caused by phase noise in the demodulation device according to the first embodiment. This improves the reception performance.

Hereinafter, a demodulation device according to the tenth embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter will be described.

FIG. 55 is a block diagram showing a configuration of the demodulation device according to the tenth embodiment of the present invention, corresponding to claims 18, 37, and 49. In FIG. 55, the demodulator according to the tenth embodiment includes a quadrature detector 31, a frequency corrector 32, a band limit filter 33, a phase corrector 34 C, and a frame synchronization. Detection unit 35, Timing generation unit 36, Error correction detection unit 44, Frame synchronization judgment unit 47, C / N detection unit 48A, Gate signal selection unit 49A, Demodulation mode It includes a switching unit 50, a first error correction unit 37, a second error correction unit 38, a video decoder 39, a TMCC decoder 40, and a BER measurement unit 41.

FIG. 56 is a flowchart showing the operation performed by the demodulation device according to the tenth embodiment. It is.

As shown in FIG. 55, the demodulation device according to the tenth embodiment is different from the demodulation device according to the first embodiment in that an error correction detection unit 44, a frame synchronization determination unit 47, and a C / N A detection unit 48 A, a gate signal selection unit 49 A, and a demodulation mode switching unit 50 are further added, and the phase correction unit 34 is replaced with a phase correction unit 34 C. An error correction detector 44 and a demodulation mode switching unit 50 are further added to the demodulator according to the embodiment, and the C / N detector 48 is replaced with a C / N detector 48 A, and a gate signal selector. 49 is replaced by a gate signal selection unit 49 A.

The rest of the configuration of the demodulation device according to the tenth embodiment is the same as the configuration of the demodulation devices according to the first and ninth embodiments, and the same reference numerals are given to the components. The description is omitted.

Steps in FIG. 56 that perform the same processing as in FIG. 5 and FIG. 49 are assigned the same step numbers, and descriptions thereof are omitted.

First, the operation of the error correction detector 44 will be described.

The error correction detection unit 44 inputs a signal indicating that error correction cannot be performed and a signal indicating that the error remains, which are output by the second error correction unit 38 in the process of error correction. Then, the error correction detection unit 44 detects whether or not correct error correction has been performed on the TMCC signal, and outputs the result of this detection to the gate signal selection unit 49A (step S6). 0 1) ο

Next, the operation of the C / N detector 48A will be described with reference to FIG.

FIG. 57 is a block diagram showing the configuration of the C / N detection unit 48A, which detects C / N equivalently based on a phase error. In FIG. 57, the C / N detection unit 48 A is composed of a phase error detection unit 481, an absolute value conversion unit 482, a switching unit 483, a constant generation unit 4884, and an adder. 48.5a, delay section 48.5b, switching section 48.5c, constant generation section 48.5d, integration section 485, timing generation section 486, and high C / N ratio It has a level judgment section 487 and a C / N low level judgment section 488. As shown in FIG. 57, the C / N detection unit 48A has a configuration obtained by further adding a C / N low level determination unit 488 to the configuration of the C / N detection unit 48 of the ninth embodiment.

The C / N high-level determination unit 487 inputs the averaged phase error output from the integration unit 485, and when the timing generation unit 486 generates a timing pulse, the averaged phase error is the first predetermined value. It is determined whether the C / N is high depending on whether the value is below the threshold (step S502). Then, as a result of this determination, if the averaged phase error falls below a predetermined first threshold, C / N high level determination section 487 determines that C / N is high and gates the result. Outputs to signal selector 49A. On the other hand, the C / N low-level determination unit 488 inputs the averaged phase error output from the integration unit 485, and when the timing generation unit 486 generates a timing pulse, the averaged phase error is set to a second predetermined value. It is determined whether the C / N is low based on whether or not the threshold is exceeded (step S602). Then, as a result of this determination, if the averaged phase error exceeds a predetermined second threshold value, C / N high level determination section 488 determines that C / N is low, and gates the result. Outputs to signal selector 49A. Here, for example, the first threshold value in the C / N high level determination unit 487 may be determined using 11.25 [degrees] as a guide as described above.

The C / N low level threshold value determines whether or not to perform the phase correction only in the BP SK period. Therefore, in the above equation (5), 3 dB obtained by substituting the inter-symbol distance of QP SK into the inter-symbol distance D of n-phase P SK is a measure of the C / N low level threshold. The threshold in the C / N low-level decision unit 488 corresponding to this 3 dB is 1/2 of the angle difference between adjacent phase identification boundaries at the code point of QPSK, that is, 22.5 [degrees]. Become.

Therefore, in this case, the output of the C / N detector 48A is as shown in Table 4 below. [Table 4] C / N high level C / N low level

Phase error C / N judgment

Judgment output

1 1.25 deg or less H i L o 问

1 1.25 deg ~

22.5 deg L o L o Medium

22.5 deg or more Low Hi Low

Next, the operation of gate signal selecting section 49 # will be described with reference to FIG.

FIG. 58 is a block diagram showing a configuration of gate signal selecting section 49A. In FIG. 58, the gate signal selection unit 49A includes AND circuits 491 and 495, a constant generation unit 492, switching units 493 and 494, and OR circuits 496 and 497. The switching unit 493 includes a timing signal that provides both the BPSK modulation period and the QPSK modulation period of the main signal input from the TMCC decoder 40 via the OR circuit 497, and a “constant 1” generated by the constant generation unit 492. Is input, and the output is switched based on the determination result output from the C / N high level determination unit 487. The switching section 494 receives the timing signal of the main signal input from the TMCC decoder 40 during the BP SK modulation period and the signal output by the switching section 493, and determines whether the C / N low level determination section 488 outputs the signal. Switch output based on results. Here, switching sections 493 and 494 output “constant 1” when the C / N determination is “high”, that is, a gate signal instructing execution of the phase correction operation during the entire communication frame period (step If the C / N judgment is “medium”, the timing signal of the QPSK and BP SK modulation period of the main signal is set (step S603), and if the C / N judgment is “low”, the main signal is set. Switch to output the timing signal (step S504) of the BPSK modulation period.

On the other hand, the determination result output from the frame synchronization determination unit 47 and the detection result output from the error correction detection unit 44 are input to the AND circuit 491. The output of the AND circuit 49 1 is output to the AND circuit 49 together with the signal output from the switching unit 494. Entered in 5. The OR circuit 496 receives the output of the AND circuit 495 and the BPSK timing signal output by the timing generator 36. Therefore, the output signal of the switching unit 494 is output as a gate signal only when the phase is synchronized by the AND circuits 495 and 495 and the OR circuit 496 and the TMCC is correctly corrected. As before, the BPSK timing signal (Fig. 6 (c) or (d)) is output as a gate signal.

This gate signal is output to the phase error holding unit 342 of the phase correction unit 34C. Next, the operation of the demodulation mode switching section 50 will be described with reference to FIG.

FIG. 59 is a diagram showing each timing signal input to the demodulation mode switching unit 50 and the demodulation mode signal output.

The demodulation mode switching unit 50 receives the timing signal (FIG. 59 (b)) of the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period from the timing generation unit 36, and the main signal QPSK timing signal (FIG. 59) from the TMCC decoder 40. (c)), and the main signal BPSK timing signal (Fig. 59 (d)). Based on these timing signals, the demodulation mode switching unit 50 performs a first demodulation mode signal (FIG. 59 (e)) indicating the period of the BPSK modulation signal and a second demodulation mode signal indicating the period of the QPSK modulation signal. A demodulation mode signal (FIG. 59 (f)) is generated and output to the phase error detector 341.

The first and second demodulation mode signals are used to switch the demodulation mode of the phase error detection section 341.

Next, the operation of the phase correction unit 34C will be described.

The phase correction unit 34C differs from the phase correction unit 34 of the demodulation device according to the first embodiment only in the configuration of the phase error detection unit 341. Therefore, the operation of the phase error detection unit 341 will be described below with reference to FIGS. 60 and 61.

FIG. 60 is a block diagram illustrating a configuration of the phase error detection unit 341. In FIG. 60, the phase error detection section 341 includes a BP SK phase error detection section 341 a and a QP SK It includes a phase error detection section 341b, an 8 PSK phase error detection section 341c, and switching sections 341d and 341e. FIG. 61 is a diagram for explaining the phase error detection performed by the BPSK phase error detection unit 341a, the QPSK phase error detection unit 34lb, and the 8PSK phase error detection unit 341c.

The output of the complex multiplication unit 344 including the phase error is input to each of the BPSK phase error detection unit 341a, the QPSK phase error detection unit 341b, and the 8PSK phase error detection unit 341c. The BPSK phase error detector 341a detects a phase error with respect to the BPSK modulation axis (0 degree, 180 degrees) (FIG. 61 (a)). The QPSK phase error detection section 341b detects a phase error with respect to the QPSK modulation axis (45 degrees, 135 degrees, 225 degrees, 315 degrees) (FIG. 61 (b)). The 8PSK phase error detection unit 341c detects the phase error with respect to the 8PSK modulation axis (0, 45, 90, 135, 180, 225, 270, 315 degrees) (Fig. 61 (c)). . The switching unit 341 d uses the second demodulation mode signal (see FIG. 59 (d)) output from the demodulation mode switching unit 50 to determine the phase detected by the QPSK phase error detection unit 341 b during the Hi signal period. The error is switched to output the phase error detected by the 8PSK phase error detection unit 341c to the switching unit 341e during the other periods. The switching unit 341 e uses the first demodulation mode signal (see FIG. 59 (e)) output from the demodulation mode switching unit 50 to determine the phase detected by the BP SK phase error detection unit 341 a during the Hi signal period. The error is switched so that the phase error output from the switching unit 341 d is output to the phase error holding unit 342 during the other periods.

That is, the demodulation mode of the phase error detector 341 is switched in the order of priority of BPSK> QPSK> 8PSK.

The operation after the phase error holding unit 342 is the same as that described in the first embodiment, except that the timing generation unit 36 outputs a signal for controlling the switching unit 342a and the holding unit 342f. The gate signal output by the gate signal selector 49A is used instead of the output timing signal (gate signal) (see FIG. 55). This allows the phase correction unit 34C to perform phase correction based on the C / N state in accordance with the first and second demodulation mode signals and the gate signal (step S505).

The contents are shown in Table 5 below.

In Table 5 below, “BPSK synchronization signal period” refers to both the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period (when the timing signal in FIG. 6 (c) is used), or the carrier. The figure shows only the synchronization auxiliary signal period (when the timing signal in Fig. 6 (d) above is used).

[Table 5]

As described above, the demodulation device according to the tenth embodiment of the present invention determines the C / N state when the phase is synchronized in the BP SK modulation signal period based on the phase error in the carrier synchronization auxiliary signal period. According to the C / N state and the reference phase corresponding to a plurality of phase modulation schemes provided in the phase error detection section 341, the BPSK-modulated frame synchronization signal / TMCC signal period and carrier in the initial carrier recovery. The phase is corrected using the synchronization auxiliary signal period, and after the phase synchronization, the phase correction is also performed during the modulation period of the main signal other than the period.

This enables stable and fast carrier synchronization even in low C / N conditions. In addition to this, it is possible to reduce the influence of the phase jitter of the demodulated signal during the period of the main signal on which the BP SK, QP SK, and 8 P SK modulation is performed, thereby improving the reception performance.

The phase error detector 481 of the C / N detector 48A has the same function as the phase error detector 341 of the phase corrector 34C, so that both phase error detectors must be shared. Is possible. If they are shared, the circuit scale can be reduced. Further, since the frame synchronization determination unit 47 is an example of a method of determining phase synchronization, the same effect can be obtained even if the phase synchronization detection unit 43 described in the third embodiment is used instead of the frame synchronization determination unit 47. Is obtained.

(Eleventh Embodiment)

The demodulation device according to the eleventh embodiment of the present invention is the same as the ninth and tenth embodiments described above, except that the demodulation device according to the first embodiment has a phase jitter caused by phase noise. Is reduced to improve the reception performance.

Hereinafter, the demodulation device according to the eleventh embodiment of the present invention for reducing the influence of the above-described phase jitter and improving the reception performance will be described.

FIG. 62 is a block diagram corresponding to Claims 19, 37, and 50, showing the configuration of the demodulation device according to the eleventh embodiment of the present invention. In FIG. 62, the demodulation device according to the first embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34C, a frame synchronization detection unit 35, Timing generator

36, an error correction detection unit 44, a frame synchronization determination unit 47, a (/? ^ Detection unit 48A, a gate signal selection unit 49B, a demodulation mode switching unit 5OA, and a first error correction unit 37 , A second error correction unit 38, a video decoder 39, and a TMCC decoder

40 and a BER measurement unit 41.

FIG. 63 is a flowchart showing the operation performed by the demodulation device according to the first embodiment.

As shown in FIG. 62, the demodulation device according to the eleventh embodiment The demodulator according to the embodiment further includes an error correction detection unit 44, a frame synchronization determination unit 47, a C / N detection unit 48A, a gate signal selection unit 49B, and a demodulation mode switching unit 5OA, and a phase correction unit 34 is added. In the demodulation device according to the tenth embodiment, the gate signal selection unit 49A is replaced with the gate signal selection unit 49B, and the demodulation mode switching unit 50 is replaced with the demodulation mode. The configuration of the demodulation device according to the first embodiment is the same as that of the demodulation devices according to the first and ninth to tenth embodiments. The same reference numerals are given to the components and the description is omitted.

Also, in FIG. 63, steps for performing the same processing as in FIGS. 5, 49 and 56 are denoted by the same step numbers, and description thereof is omitted.

First, the operation of the gate signal selection unit 49B will be described with reference to FIG.

FIG. 64 is a block diagram showing a configuration of gate signal selecting section 49B. In FIG. 64, the gate signal selection section 49 B includes AND circuits 491, 491 a, 495, constant generation sections 492, 492 a, switching sections 493, 494, 499, and an OR circuit 496, 497 and a NOT circuit 498.

In the gate signal selection section 49B, the operation up to the output of the OR circuit 496 is as described in the tenth embodiment. The AND circuits 491, 495 and the OR circuit 496 achieve the phase synchronization and the TMCC The output signal of the switching section 494 is output as a gate signal only when is correctly corrected, otherwise, the BPSK timing signal (FIG. 6 (c) or (d)) is output as a gate signal as before. Is done.

On the other hand, the AND circuit 49 la includes a signal (inverse logic) of the determination result output from the C / N high-level determination unit 487, the determination result output from the frame synchronization determination unit 47, and the detection result output from the error correction detection unit 44. (The logical value is inverted by the NOT circuit 498). The switching unit 499 controls the period of the frame synchronization signal / TMCC signal and the carrier. The timing signal of the period auxiliary signal period and the “constant 1” generated by the constant generator 492a are input, and the output is switched based on the output of the AND circuit 491a. Here, the switching unit 499 outputs the “constant 1” generated by the constant generation unit 492a when the phase synchronization is obtained, the TMCC is not correctly corrected, and the C / N state is high. Otherwise, switching is performed so that the signal output from the OR circuit 496 is output as a gate signal (step S701). As a result, even when the TMCC is not correctly corrected, that is, when the signal representing the timing of the main signal generated from the TMCC decoder 40 is not reliable, the phase synchronization can be achieved and the high C / N state can be achieved. If, “constant 1” instructing execution of the phase correction operation is output as a gate signal during the entire period of the communication frame (step S702). In the case of the low C / N state, a signal in the BP SK period is output as a gate signal (step S703).

This gate signal is output to the phase error holding unit 342 of the phase correction unit 34C. Next, the operation of the demodulation mode switching unit 5OA will be described with reference to FIG.

FIG. 65 is a block diagram showing a configuration of the demodulation mode switching unit 5OA. In FIG. 65, the demodulation mode switching unit 5 OA includes AND circuits 501 to 503 and an OR circuit 504.

The AND circuit 501 inputs the determination result output from the frame synchronization determination unit 47 and the detection result output from the error correction detection unit 44. The AND circuit 502 inputs the main signal BP SK timing signal (see FIG. 59 (d)) and the output of the AND circuit 501. The AND circuit 503 receives the main signal QPSK timing signal (see FIG. 59 (c)) and the output of the AND circuit 501, and outputs the logic result as a second demodulation mode signal. 〇 The R circuit 504 inputs the timing signal (see Fig. 59 (b)) of the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period and the output of the AND circuit 502, and performs the first demodulation on the logical result. Output as a mode signal. Thus, the gate signal selection unit 49B and the demodulation mode switching unit 50A allow the If the TMCC signal is correctly corrected by controlling the phase corrector 34C, and before the phase correction corresponding to each modulation method of the main signal, synchronization is achieved and the C / N state is high. Then, as described in the ninth embodiment, the period of the main signal is regarded as 8 PSK, and the phase is corrected (steps S704 and S601). After that, in the same manner as described in the tenth embodiment, phase correction is performed corresponding to each modulation method (steps S502 to S505, S602 to S603).

The contents are shown in Table 6 below.

In Table 6 below, “: BPSK synchronization signal period” means the period of both the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period (when the timing signal in FIG. 6 (c) is used). Alternatively, it shows only the carrier synchronization auxiliary signal period (when the timing signal in Fig. 6 (d) above is used).

[Table 6]

As described above, the demodulation device according to the first embodiment of the present invention uses the C / N state when the phase is synchronized in the BPSK modulation signal period based on the phase error in the carrier synchronization auxiliary signal period. If the detected C / N is at a predetermined level, The phase error is corrected by assuming that 8 PSK modulation is performed during the entire frame period, and the BPSK is recovered in the initial carrier wave recovery according to the reference phases corresponding to the multiple phase modulation methods provided in the phase error detection unit 341. The phase correction is performed using the modulated frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period, and after the phase synchronization, the phase correction is also performed in the modulation period of the main signal other than the period. This enables fast and stable carrier synchronization even in the low C / N state, and reduces the effect of demodulated signal phase jitter during the main signal that is BPSK, QPSK and 8PSK modulated. As a result, the reception performance can be improved.

(Twelfth embodiment)

The demodulator according to the twelfth embodiment of the present invention is the same as the ninth to eleventh embodiments, except that the demodulator according to the first embodiment has a phase jitter caused by phase noise. Is reduced to improve the reception performance.

Hereinafter, a demodulation device according to a twelfth embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter will be described.

FIG. 66 is a block diagram showing a configuration of a demodulation device according to a twelfth embodiment of the present invention, corresponding to claims 20, 37, and 51. In FIG. 66, the demodulation device according to the twelfth embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34C, a frame synchronization detection unit 35, Generating section 36, frame synchronization determining section 47, BER detecting section 51, gate signal selecting section 49, first error correcting section 37, second error correcting section 38, video decoder 39, TMCC It includes a decoder 40 and a BER measurement unit 41.

As shown in FIG. 66, the demodulation device according to the twelfth embodiment is different from the demodulation device according to the first embodiment in that a frame synchronization determination unit 47, a BER detection unit 51, and a gate signal selection unit 49 are provided. In addition, the configuration is such that the phase correction unit 34 is replaced with a phase correction unit 34C. Further, in the demodulation device according to the ninth embodiment, a 〇? ^ Detection unit 48 is provided. This is a configuration in which the BER detector 51 is replaced.

The other configuration of the demodulation device according to the twelfth embodiment is the same as the configuration of the demodulation device according to the first and ninth embodiments, and the same reference numerals are assigned to the components. The description is omitted.

The processing steps performed by the demodulation device according to the twelfth embodiment are the same as the processing steps shown in FIG. 49 in the ninth embodiment, and a description thereof will not be repeated.

Hereinafter, the BER detection unit 51 having a different configuration will be described with reference to FIG. FIG. 67 is a block diagram illustrating a configuration of the BER detection unit 51. In FIG. 67, the BER detection unit 51 includes an error correction re-encoding unit 511, a comparison unit 512, and a C / N high level determination unit 513.

The error correction re-encoding unit 511 receives the error-corrected TMCC signal output from the second error correction unit 38. Then, the error correction re-encoding unit 511 re-encodes the input error-corrected TMCC signal based on the frame synchronization signal / TMCC signal period timing signal. Comparing section 512 receives the re-encoded TMCC signal output from error-correcting re-encoding section 511 and the uncorrected signal output from phase correcting section 34C. Then, the comparing section 512 extracts the period of the TMCC signal from the signal output by the phase correction section 34C based on the timing signal of the frame synchronization signal / TMCC signal period, The bit error rate is calculated by comparing the signal and the re-encoded TMCC signal. C / N high level determination section 513 receives the bit error rate output from comparison section 512, and determines whether the C / N is high or low depending on whether the bit error rate falls below a predetermined threshold. Judge (see FIG. 49, step S502). If the bit error rate falls below a predetermined threshold as a result of this determination, C / N high level determination section 513 determines that C / N is high, and determines the result as a gate signal selection section. Output to 49. Here, as for the threshold value in the C / N high level determination section 5 13, as described in the ninth embodiment, a modulation method having a large number of phases when the C / N is low is used for phase correction. Therefore, the determination must be made so that the phase error detection section 341 of the phase correction section 34 C does not output erroneous phase error information.

For example, a threshold value will be calculated for the value 11.25 deg used in the ninth embodiment. As described above, the C / N at 11.25 deg is 8.3 dB from the above equation (5).

On the other hand, the relationship between the C / N and the bit error rate in BPSK modulation is generally known to be as shown in FIG. 68, so the bit error rate at 8.3 dB from FIG. When reading a, 1 X 1 0- ⁴ is obtained. Therefore, the threshold may be set to measure the 1 X 1 0- ^4.

As described above, the demodulation device according to the 12th embodiment of the present invention detects the C / N state when phase synchronization is performed during the BPSK modulation signal period based on the bit error rate of the TMCC signal. If the C / N is at a predetermined level, the phase error is corrected on the assumption that the 8 PSK modulation is also performed for the main signal period of the communication frame.

(Third Embodiment)

The demodulation device according to the thirteenth embodiment of the present invention is the same as the ninth to twelfth embodiments, except that the demodulation device according to the first embodiment has a phase jitter caused by phase noise. The effect of the evening is reduced to improve the reception performance.

Hereinafter, a demodulation device according to a thirteenth embodiment of the present invention, which improves the reception performance by reducing the influence of the above-described phase jitter, will be described.

FIG. 69 shows a thirteenth embodiment of the present invention corresponding to claims 21, 37, 52. FIG. 3 is a block diagram illustrating a configuration of the demodulation device. In FIG. 69, the demodulation device according to the thirteenth embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34C, a frame synchronization detection unit 35, A generation unit 36, an error correction detection unit 44, a frame synchronization determination unit 47, a BER detection unit 51A, a gate signal selection unit 49A, a demodulation mode switching unit 50, a first error correction unit 37, It includes a second error correction section 38, a video decoder 39, a TMCC decoder 40, and a BER measurement section 41.

As shown in FIG. 69, the demodulation device according to the thirteenth embodiment is different from the demodulation device according to the first embodiment in that an error correction detection unit 44, a frame synchronization determination unit 47, and a BER detection unit 51A And a gate signal selection unit 49A and a demodulation mode switching unit 50, and the phase correction unit 34 is replaced with a phase correction unit 34C. In addition, the demodulation device according to the tenth embodiment Thus, the configuration is such that the C / N detection unit 48A is replaced by the BER detection unit 51A.

The rest of the configuration of the demodulation device according to the thirteenth embodiment is the same as that of the demodulation devices according to the first and tenth embodiments, and the same reference numerals are given to the components. The description is omitted.

Further, the processing steps performed by the demodulation device according to the thirteenth embodiment are the same as the processing steps shown in FIG. 56 in the tenth embodiment, and thus description thereof will be omitted.

Hereinafter, a BER detection unit 51A having a different configuration will be described with reference to FIG. FIG. 70 is a block diagram illustrating a configuration of the BER detection unit 51A. In FIG. 70, BER detection section 51A includes error correction and re-encoding section 5 11, comparison section 512, C / N high level determination section 513, and C / N low level determination section 514. .

The error correction re-encoding unit 511 receives the error-corrected TMCC signal output from the second error correction unit 38. Then, the error correction re-encoding unit 5111 receives the input error correction based on the timing signal in the frame synchronization signal / TMCC signal period. Re-encoding is performed on the TMCC signal after the correction. Comparing section 512 receives the re-encoded TMCC signal output from error-correcting re-encoding section 511 and the uncorrected signal output from phase correcting section 34C. Then, comparing section 512 extracts the period of the TMCC signal from the signal output from phase correcting section 34C based on the timing signal of the frame synchronization signal / TMCC signal period, and extracts the error-corrected TMCC signal. The bit error rate is calculated by comparing the signal and the re-encoded TMCC signal. C / N high level determination section 513 receives the bit error rate output from comparison section 512, and has a high C / N depending on whether or not the bit error rate falls below a predetermined first threshold value. (See FIG. 56, step S502). On the other hand, C / N low-level determining section 514 receives the bit error rate output from comparing section 512, and determines whether the bit error rate exceeds a predetermined second threshold value. Is determined (see FIG. 56, step S602). If the bit error rate falls below a predetermined first threshold value as a result of this determination, the C / N high-level determination unit 513 determines that C / N is high, and determines the result as a gate signal. Output to selection section 49A, and if the bit error rate exceeds a second predetermined threshold, C / N low level determination section 514 determines that C / N is low and determines the result. Output to gate signal selector 49A.

Here, for example, it is about the first threshold value in C / N and high-level determination unit 513 may be the 1 X 10- ⁴ as described above.

Further, the second threshold value in C / N low level determination section 514 is determined according to C / N = 3 dB at value 22.5 [deg] used in the tenth embodiment, as shown in FIG. When reading from, 2. 3 x 10- ² is obtained. Therefore, the first threshold value, a 1 X 10- ^4, the second threshold may be set to a guide 2. 3 X 10. As described above, the demodulation device according to the thirteenth embodiment of the present invention detects the C / N state when phase synchronization is performed during the BP SK modulation signal period based on the bit error rate of the TMC C signal. Provided in the C / N state and phase error detection section 341 According to the reference phase corresponding to a plurality of phase modulation methods, the phase is corrected using the BP SK modulated frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period in the initial carrier recovery, and the corresponding period after the phase synchronization The phase correction is also performed during the modulation period of the main signal other than.

As a result, carrier synchronization can be performed quickly and stably even in a low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal subjected to BPSK, QP SK and 8P SK modulation is reduced. As a result, the reception performance can be improved.

(14th embodiment)

The demodulation device according to the fourteenth embodiment of the present invention is similar to the ninth to thirteenth embodiments described above, except that in the demodulation device according to the first embodiment, phase demodulation caused by phase noise is reduced. The effect is reduced to improve the reception performance.

Hereinafter, a demodulation device according to a fourteenth embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter will be described.

FIG. 71 is a block diagram showing a configuration of a demodulation device according to a fourteenth embodiment of the present invention, which corresponds to claims 22, 37, and 53. In FIG. 71, the demodulation device according to the fourteenth embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34C, a frame synchronization detection unit 35, Evening generator

36, an error correction detection unit 44, a frame synchronization determination unit 47, a BER detection unit 51A, a gate signal selection unit 49B, a demodulation mode switching unit 5OA, a first error correction unit 37, 2 error correction unit 38, video decoder 39, TMCC decoder

40 and a BER measurement unit 41.

As shown in FIG. 71, the demodulator according to the fourteenth embodiment is different from the demodulator according to the first embodiment in that an error correction detector 44, a frame synchronization determiner 47, and a BER detector 51A are provided. The configuration is such that a gate signal selection unit 49B and a demodulation mode switching unit 5OA are further added, and the phase correction unit 34 is replaced with a phase correction unit 34C. The demodulation device according to the embodiment has a configuration in which the C / N detection unit 48A is replaced with a BER detection unit 51A.

The rest of the configuration of the demodulation device according to the fourteenth embodiment is the same as the configuration of the demodulation device according to the first and eleventh embodiments, and the same reference numerals are used for the components. The description is omitted here.

Also, the processing steps performed by the demodulation device according to the fourteenth embodiment are the same as the processing steps shown in FIG. 63 in the above-described first embodiment, and thus description thereof will be omitted.

As described above, the demodulation device according to the fourteenth embodiment of the present invention detects the C / N state when the phase is synchronized during the BPSK modulation signal period based on the bit error rate of the TMCC signal. However, when the C / N is at a predetermined level, it is assumed that 8 PSK modulation is performed during the entire period of the communication frame, and the phase error is corrected. According to the reference phase corresponding to the multiple phase modulation methods, the phase is corrected using the BPSK-modulated frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period in the initial carrier recovery, and after the phase homology period, the phase correction is performed. The phase correction is also performed during the modulation period of the main signal other than the period.

This enables fast and stable carrier synchronization even in the low C / N state, and reduces the effect of the phase jitter of the demodulated signal during the period of the main signal subjected to BPSK, QPSK and 8PSK modulation. Therefore, the reception performance can be improved.

In the demodulators according to the ninth to fourteenth embodiments, even after steady demodulation, the state of C / N is monitored, and the target of phase correction is determined based on the C / N detection result. It is needless to say that by changing the value, the effect of the phase jitter of the demodulated signal can be reduced and the receiving performance can be improved.

Note that the demodulation devices according to the second to eighth embodiments have the purpose of avoiding pseudo-synchronization with respect to the demodulation device according to the first embodiment. The demodulation devices according to the ninth to fourteenth embodiments have been individually described for the purpose of reducing the influence of the phase jitter on the basic demodulation device according to the first embodiment. However, by combining the configurations of the demodulation devices according to the second to eighth embodiments and the configurations of the demodulation devices according to the ninth to fourteenth embodiments, respectively, it is possible to avoid pseudo synchronization and reduce phase jitter. The effect can be reduced at the same time (claims 23-32, 54-63).

Further, in the first to fourteenth embodiments, BP SK, QP SK, and 8 P SK are described as the modulation schemes for performing time division multiplexing. However, the modulation scheme of the carrier synchronization auxiliary signal is time division multiplexed. If the phase modulation having the smallest number of phases n among the n-phase phase modulations, the same effect as described above can be obtained in other modulation methods. Further, when the installation position of the frame synchronization signal in each communication frame is somewhat close to the position corresponding to the insertion period of the carrier synchronization auxiliary signal, the frame synchronization determination unit 47 described in the ninth embodiment (FIG. 50) Is applied to the phase synchronization detection unit 43 in the third, fifth, and seventh embodiments, and to the first phase synchronization detection unit 43A in the fourth, sixth, and eighth embodiments, respectively. It is possible to simplify the circuit.

(3) Other transmission and reception systems

In the above description of (1) the transmission system and (2) the reception system, the modulation / demodulation device which dispersively inserts the BPSK modulated carrier synchronization auxiliary signal into the communication frame and corrects the frequency and phase using this carrier synchronization auxiliary signal. And the method was explained.

Here, as described above, the main signal includes a low-layer signal, that is, a signal subjected to BPSK modulation (see FIG. 2). Therefore, if the lower hierarchical signal, which is the main signal of the BPSK modulation, is also used for the initial carrier recovery, synchronization can be performed at higher speed and more stably.

Therefore, in the following, the BP SK modulated low-layer signal is also used to carry A modulation and demodulation device and method capable of transmitting and reproducing waves will be described.

(Other Embodiments of Modulator and Method)

FIG. 72 is a block diagram showing a configuration of another modulation device according to an embodiment of the present invention, which corresponds to claims 3, 4, 7, and 8. In FIG. 72, another modulation device according to an embodiment of the present invention includes a frame synchronization signal / TMCC signal generation unit 11, a TS packet synthesis unit 12, a TMCC error correction encoding unit 13, A first error correction coding unit 14, a second error correction coding unit 15, a first BPSK mapping unit 16, a BPSK / QPSK mapping unit 17, and a 8 PSK mapping unit 18; A multiplexing / quadrature modulation unit 19, a synchronization auxiliary signal generation unit 22, a differential encoding unit 23, and a second BPSK mapping unit 21.

As shown in FIG. 72, the other modulation apparatus further includes a differential encoding section 23 in addition to the above-mentioned modulation apparatus (see FIG. 1), and a synchronization auxiliary signal generation section 20 is added to the synchronization auxiliary signal generation section 2. The configuration is replaced with 2.

The other configurations of the other modulation devices are the same as those of the above-described modulation device, and the corresponding components are denoted by the same reference numerals and description thereof will be omitted.

Hereinafter, operations of the synchronization auxiliary signal generation unit 22 and the differential encoding unit 23, in which another modulation device has a different configuration from the above-described modulation device, will be described.

The synchronization auxiliary signal generator 22 generates the carrier synchronization auxiliary signal as described above. At this time, based on the input TMCC information, the synchronization auxiliary signal generation unit 22 transmits information defining the modulation scheme to be applied to the packet next to the position where the carrier synchronization auxiliary signal is inserted, as shown in FIG. Superimpose. The differential encoding unit 23 receives the carrier synchronization auxiliary signal on which the modulation scheme information is superimposed, and performs differential encoding on the modulation scheme information so that the demodulation apparatus can decode the modulation scheme information even when the carrier is not synchronized. Is applied. Then, a carrier synchronization complement in which the differentially encoded modulation scheme information is superimposed. The auxiliary signal is input to the second BP SK matting unit 21.

The subsequent operation is as described above.

The operations performed by the synchronization auxiliary signal generation unit 22 and the differential encoding unit 23 will be described using specific values as an example.

Now, consider a case where a communication frame is generated in which four carrier synchronization auxiliary signals of four symbols (= 4 bits) are inserted in one packet. At this time, the carrier synchronization auxiliary signal (4 × 4 = 16 bits) of each modulation scheme generated by the synchronization auxiliary signal generation unit 22 is set as follows.

8PSK: 0111111111 111111

QP SK: 0010101010101010

BP SK: 0101010101010101

When differential encoding is performed on the carrier synchronization auxiliary signal by the differential encoding unit 23, respectively, the following is obtained.

8PSK: 0101010101010101

QP SK: 0011001100110011

BPSK: 0110011001 100110

When the carrier synchronization auxiliary signal after differential encoding is decoded by a demodulation device described later, the result is as follows.

8PSK: X 111111111 111111

QP SK: X010101010101010

BP SK: X101010101010101

In this way, the carrier synchronization auxiliary signal after differential encoding has no consecutive 1's or 0's, so that the carrier does not rise in the modulated wave, and the same pattern every 2 bits after differential decoding. Since the signal appears seven times, reliability can be improved by using a majority decision in the demodulator.

As described above, according to another modulation device according to an embodiment of the present invention, a demodulation device A signal that assists carrier synchronization, superimposed with information that defines the modulation scheme for the next packet, is modulated by BPSK, which is strong against low C / N conditions, and is distributed and inserted into the packet. Is output.

As a result, in the demodulation device, even in the low C / N state, high-speed and stable carrier synchronization can be performed using the BPSK carrier synchronization auxiliary signal dispersed in the packet and the BPSK modulated main signal.

(Other Embodiments of Demodulator and Method)

Next, a demodulation device and a method for demodulating a communication frame generated in another modulation device according to an embodiment of the present invention will be described below.

FIG. 74 is a block diagram showing a configuration of another demodulation device according to an embodiment of the present invention, which corresponds to claims 38 and 64. In FIG. 74, another demodulation device according to an embodiment of the present invention includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34, and a frame. A synchronization detection unit 35, a timing generation unit 36A, a carrier synchronization auxiliary signal decoder 52, a first error correction unit 37, a second error correction unit 38, a video decoder 39, It includes a TMCC decoder 40 and a BER measurement unit 41.

As shown in FIG. 74, another demodulation device according to one embodiment further includes a carrier synchronization auxiliary signal decoder 52 added to the demodulation device according to the first embodiment, and a timing generation unit 36 This is a configuration in which the generator 36A is replaced.

The other configuration of the other demodulator according to the embodiment is the same as the configuration of the demodulator according to the first embodiment, and the components are denoted by the same reference numerals and the description thereof will be omitted. Omitted.

Hereinafter, the operations of the carrier synchronization auxiliary signal decoder 52 and the timing generator 36A, in which another demodulation device according to one embodiment has a different configuration from the demodulation device according to the first embodiment, will be described in order.

FIG. 75 is a block diagram showing a configuration of the carrier synchronization auxiliary signal decoder 52. . In FIG. 75, the carrier synchronization auxiliary signal decoder 52 includes a delay detection section 521, a phase identification section 522, a BPSK synchronization auxiliary signal pattern matching section 523, and a main signal BP SK gate generation section 524.

The delay detection unit 521 receives the signal from the band limiting filter 33, and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The phase identification section 522 identifies the phase of the signal output from the delay detection section 521 and decodes the data. The BP SK synchronization auxiliary signal pattern matching unit 523 detects the position of the carrier synchronization auxiliary signal from the signal output from the phase identification unit 522, extracts the modulation method information superimposed on the carrier synchronization auxiliary signal, and extracts the main signal BP SK Output to the gate generation unit 524. The main signal BP SK gate generation section 524 generates a timing signal (gate signal) for giving a period of the main signal whose modulation scheme is BP SK, based on the input modulation scheme information (FIG. 76 (c)).

This timing signal is output to the timing generator 36A.

The timing generation unit 36A first detects the period of the frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in one communication frame based on the frame head signal detected by the frame synchronization detection unit 35. An auxiliary signal BPSK timing signal corresponding to the period as shown in FIG. 76 (b) is generated. Next, the timing generation section 36A generates the generated BP SK timing signal (FIG. 76 (b)) and the main signal BP SK timing signal output by the carrier synchronization auxiliary signal decoder 52 (FIG. 76 (c)). Based on the above, all BPSK timing signals (FIG. 76 (d)) giving the period during which the BPSK modulation is performed in the communication frame are generated.

This all BP SK timing signal is output to the frequency correction unit 32 and the phase correction unit 34, and correction is performed according to the signal.

As described above, according to another demodulation device according to an embodiment of the present invention, among the phase-modulated signals that are time-division multiplexed, in addition to the BP SK including the carrier synchronization auxiliary signal dispersedly arranged in the bucket, The carrier signal is also re-used using the main signal that has been subjected to BP SK modulation. Do raw.

As a result, even in the low C / N state, high-speed and stable carrier synchronization can be performed using the BPSK carrier synchronization auxiliary signal dispersed in the packet and the BPSK modulated main signal.

In the above embodiment, the case where the configurations of the carrier synchronization auxiliary signal decoder 52 and the timing generator 36A are used in the demodulation device according to the first embodiment has been described. However, the configurations of the carrier synchronization auxiliary signal decoder 52 and the timing generation unit 36A can be used in the demodulation devices according to the second to fourteenth embodiments. The effect can be achieved. Here, when the configurations of the carrier synchronization auxiliary signal decoder 52 and the timing generator 36 A are used in the demodulators according to the tenth, eleventh, thirteenth, and fourteenth embodiments, the TMCC decoder 4 Of course, it is also possible to obtain the information on the modulation method of the main signal obtained from 0 from the carrier synchronization auxiliary signal decoder 52.

Further, in each embodiment relating to the demodulation device described above, the frequency of the local oscillation signal in the quadrature detection unit 31 can be changed by the output of the frequency error holding unit 3 22 of the frequency correction unit 32, It goes without saying that the same effect can be obtained even if the frequency error is corrected by the quadrature detection unit 31 instead of the complex multiplication unit 3 2 4 of the frequency correction unit 32 of FIG. Industrial applicability

The present invention relates to a modulation / demodulation device capable of performing stable and high-speed carrier synchronization even in a digital satellite broadcasting system, even when the demodulation device is turned on or a channel is selected at a low C / N. It can be used as a method.

Claims

The scope of the claims

1. A modulation device that generates a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiency for each layer of the data for a plurality of data to be communicated,

Phase modulation means for performing, on each of the plurality of data, phase modulation corresponding to the content of the data to generate a modulation signal;

A signal generation unit that generates a carrier synchronization auxiliary signal that has been subjected to phase modulation using the phase modulation with the smallest number of phases (hereinafter, referred to as minimum phase modulation) among the plurality of phase modulations performed in the night;

A multiplexing means for time-division multiplexing the modulated signal and the carrier synchronization auxiliary signal so that the carrier synchronization auxiliary signal is dispersed at equal time intervals in the communication frame.

2. The modulation device according to claim 1, wherein the carrier synchronization auxiliary signal is time-division multiplexed continuously for two or more symbols.

3. The carrier synchronization auxiliary signal is characterized by superimposing information for identifying the phase modulation applied to the modulation signal serving as the next bucket at a position to be time-division multiplexed in the communication frame. The modulation device according to claim 1.

4. It is further equipped with differential encoding means for performing differential encoding on the input signal and outputting it.

The signal generation means includes: for a signal after differential encoding by the differential encoding means, a carrier synchronization auxiliary signal that has been subjected to the minimum phase modulation among a plurality of phase modulations performed to the data. The modulation device according to claim 3, wherein the modulation device is generated.

5. A modulation method for generating a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiencies for each layer of the data over a plurality of data to be communicated. , Generating a carrier synchronization auxiliary signal that has been subjected to phase modulation using the phase modulation having the smallest number of phases among the plurality of phase modulations performed on the data (hereinafter, referred to as minimum phase modulation); A modulation method characterized by performing time division multiplexing so as to be distributed at equal time intervals within a communication frame.

6. The modulation method according to claim 5, wherein the carrier synchronization auxiliary signal is time-division multiplexed continuously for two or more symbols.

7. The carrier synchronization auxiliary signal is characterized by superimposing information for identifying a phase modulation applied to a modulation signal serving as a next bucket at a position to be time-division multiplexed in the communication frame. The modulation method according to claim 5.

8. The carrier synchronization auxiliary signal is generated by subjecting the signal after differential encoding to the minimum phase modulation among a plurality of phase modulations applied to the data, The modulation method according to claim 7.

9. Along with a plurality of phase-modulated signals, the carrier synchronization auxiliary signal that has been phase-modulated using the phase modulation with the smallest number of phases in the communication frame (hereinafter referred to as minimum phase modulation) is distributed at equal time intervals A demodulator for receiving the time-division multiplexed communication frame,

Frequency correction means for detecting a frequency error in a predetermined signal period in the communication frame and correcting a frequency deviation,

Phase correction means for detecting a phase error of a predetermined signal period in the communication frame and correcting a phase shift;

A frame synchronization detection unit that receives an output signal of the frequency correction unit or the phase correction unit, detects a synchronization signal of the communication frame using delay detection, and detects a frame start position,

Based on the frame head position detected by the frame synchronization detecting means, at least a period of the carrier synchronization auxiliary signal in a period in which the minimum phase modulation is performed.

(Hereinafter referred to as “synchronization signal period”), and the timing of providing the synchronization signal period Timing generation means for generating a signal,

The demodulator, wherein the frequency correction unit and the phase correction unit perform a correction operation according to the minimum phase modulation during the synchronization signal period provided by the timing signal.

10. Frequency pull-in detection means for receiving an output signal of either the frequency correction means or the phase correction means, detecting a frequency pull-in state, and determining whether or not the frequency of the phase correction means is a pseudo-synchronous frequency. When,

As a result of the determination by the frequency pull-in detecting means, when the frequency correction by the frequency correcting means is completed to a frequency at which the phase correcting means is not pseudo-synchronized, a phase correction resetting means for initializing the phase correcting means is provided. The demodulation device according to claim 9, further comprising:

11. An output signal of the phase correction means, a phase synchronization detection means for detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal,

Error correction detecting means for detecting a correction state of error correction processing of a transmission control signal (TMC C signal) included in the frame synchronization signal;

Pseudo-synchronization determining means for determining whether or not to perform pseudo-synchronization from the detection results of the phase synchronization detecting means and the error correction detecting means,

The demodulation device according to claim 9, further comprising: a phase correction reset unit that initializes the phase correction unit when the result of the determination by the pseudo synchronization determination unit is a pseudo synchronization.

12. A first phase synchronization detecting means for receiving an output signal of the phase correcting means and detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal;

A second phase synchronization detection unit that receives an output signal of the phase correction unit and detects a state of phase synchronization during a transmission control signal (TMCC signal) included in the frame synchronization signal;

From the detection results of the first phase synchronization detection means and the second phase synchronization detection means Pseudo-synchronization determining means for determining whether or not pseudo-synchronization is performed;

13. An output signal of the phase correction means, and a phase synchronization detection means for detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal;

10. The method according to claim 9, further comprising: frequency step means for changing a frequency input to the phase correction means in a stepwise manner when the result of the judgment by the pseudo synchronization judgment means is pseudo synchronization. Demodulator.

14. A first phase synchronization detection unit that receives an output signal of the phase correction unit and detects a state of phase synchronization during a period of the carrier synchronization auxiliary signal,

Pseudo-synchronization determining means for determining whether or not pseudo-synchronization is performed based on detection results of the first phase synchronization detecting means and the second phase synchronization detecting means;

15. An input signal of either the frequency correction means or the phase correction means, a frequency pull-in detection means for detecting a frequency pull-in state and determining whether or not the frequency of the phase correction means is a pseudo-synchronous frequency. When, As a result of the determination by the frequency pull-in detecting means, when the frequency correction by the frequency correcting means is completed to a frequency at which the phase correcting means is not pseudo-synchronized, a phase correction resetting means for initializing the phase correcting means is provided. 14. The demodulation device according to claim 13, further comprising:

16. Frequency pull-in detecting means for receiving an output signal of either the frequency correcting means or the phase correcting means, detecting a frequency pull-in state, and determining whether or not the frequency of the phase correcting means is a pseudo-synchronous frequency. When,

As a result of the determination by the frequency pull-in detecting means, when the frequency correction by the frequency correcting means is completed to a frequency at which the phase correcting means is not pseudo-synchronized, a phase correction resetting means for initializing the phase correcting means is provided. The demodulation device according to claim 14, further comprising:

17. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects a state of phase synchronization during a period of the carrier synchronization auxiliary signal,

C / N detection means for receiving an output signal of the phase correction means and detecting a state of C / N (carrier power / noise power) of a received signal;

Based on the detection result of the frame synchronization determination unit and the C / N detection unit and the evening signal, if there is phase synchronization and C / N is higher than a predetermined threshold, the communication A gate signal generating unit that generates a gate signal that provides the entire period of the frame; otherwise, generates a gate signal that provides the synchronous signal period.

The phase correction unit detects a phase error due to minimum phase modulation during the synchronization signal period provided by the timing signal, and detects a phase error due to phase modulation having the largest number of phases in the communication frame outside the synchronization signal period. The correcting operation according to claim 9, wherein the correcting operation is performed in accordance with a period given by the gate signal.

18. The output signal of the phase correction means is input, and the phase in the phase correction means Frame synchronization determining means for detecting synchronization,

In the communication frame, a signal period giving unit that outputs a signal giving a period of each phase modulation signal other than the synchronization signal period,

Demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means according to a phase modulation method based on a signal output by the signal period providing means and the timing signal;

Based on the frame synchronization determination means, the detection results of the C / N detection means and the error correction detection means, and a signal output by the signal period giving means and the timing signal,

If there is phase synchronization and error correction is completed,

If the C / N is higher than a predetermined first threshold, a gate signal giving the entire period of the communication frame is

When the C / N is lower than a predetermined second threshold value, a gate signal giving a period of the signal subjected to the minimum phase modulation is given by:

Otherwise, generate a gate signal that gives the minimum phase modulation period and a predetermined modulation signal period,

There is a gate signal generation means for generating a gate signal for providing the synchronization signal period, except when the phase synchronization is performed and the error correction is completed,

10. The demodulation device according to claim 9, wherein the phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal, and performs a correction operation according to a period given by the gate signal.

1 9. The output signal of the phase correction means is input, and the phase in the phase correction means is Frame synchronization determining means for detecting synchronization,

Based on the detection results of the frame synchronization determining means and the error correction detecting means, and the signal output by the signal period providing means and the timing signal, the demodulation method in the phase correcting means corresponds to the phase modulation method. Demodulation mode switching means for outputting a demodulation mode signal;

If there is phase synchronization and error correction is completed,

If the C / N is higher than the predetermined first threshold, a gate signal that gives the entire period of the communication frame is

When C / N is lower than a predetermined second threshold value, a gate signal giving a period of the signal subjected to the minimum phase modulation is given by:

If there is phase synchronization and error correction has not been completed,

If the C / N is lower than the second predetermined threshold, a gate signal giving the synchronization signal period is generated, When there is no phase synchronization, further comprising a gate signal generating means for generating a gate signal for providing the synchronization signal period;

When the error correction is not completed, the phase correction unit detects a phase difference due to the minimum phase modulation during the synchronization signal period provided by the timing signal, and when the number of phases in the communication frame is outside of the synchronization signal period, When the phase error due to the most phase modulation is detected and the error correction is completed, after the phase error according to the phase modulation method according to the demodulation mode signal is detected, the correction operation is performed according to the period given by the gate signal. The demodulator according to claim 9, wherein the demodulation is performed.

20. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit;

A BER that measures a bit error rate of a transmission control signal (TMCC signal) included in the frame synchronization signal before error correction and detects a state of C / N (carrier power / noise power) based on the bit error rate. Detecting means;

Based on the detection result of the frame synchronization determination unit and the BER detection unit, and based on the evening signal, if phase synchronization is performed and C / N is higher than a predetermined threshold, A gate signal generating unit that generates a gate signal that provides the entire period, and otherwise generates a gate signal that provides the synchronous signal period.

21. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

Before error correction of the transmission control signal (TMCC signal) included in the frame synchronization signal BER detection means for measuring the bit error rate of the BER and detecting the state of C / N (carrier power / noise power) based on the bit error rate;

In the communication frame, a signal period providing unit that outputs a signal that gives a period of each phase modulation signal other than the synchronization signal period,

Demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with a phase modulation method based on the signal output by the signal period providing means and the timing signal. When,

The frame synchronization determination means, based on the detection results of the B ER detection means and the error correction detection means, and a signal output by the signal period giving means and the timing signal,

If there is phase synchronization and error correction is completed,

When C / N is higher than a predetermined first threshold value, a gate signal giving the entire period of the communication frame is

22. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit, A BER that measures the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction and detects the state of C / N (carrier power / noise power) based on the bit error rate. Detecting means;

If there is phase synchronization and error correction is completed,

When C / N is lower than a predetermined second threshold value, a gate signal that gives a period of the signal subjected to the minimum phase modulation is

If there is phase synchronization and error correction has not been completed,

If the C / N is lower than the second predetermined threshold, a gate signal giving the synchronization signal period is generated, When there is no phase synchronization, further comprising a gate signal generation means for generating a gate signal for providing the synchronization signal period;

23. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

Based on the detection result of the frame synchronization determination unit and the C / N detection unit, and the evening timing signal, if there is phase synchronization and C / N is higher than a predetermined threshold, A gate signal generating unit that generates a gate signal that provides the entire period of the communication frame; otherwise, a gate signal generating unit that generates a gate signal that provides the synchronization signal period.

The phase correction unit detects a phase error due to minimum phase modulation during the synchronization signal period provided by the timing signal, and detects a phase error due to phase modulation having the largest number of phases in the communication frame outside the synchronization signal period. The demodulator according to any one of claims 10 to 16, wherein a correction operation is performed in accordance with a period given by the gate signal.

24. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

C / N detection means for receiving an output signal of the phase correction means and detecting a state of C / N (carrier power / noise power) of a received signal; Error correction detection means for detecting a correction state of error correction processing of a transmission control signal (TMCC signal) included in the frame synchronization signal;

If there is phase synchronization and error correction is completed,

10. The method according to claim 10, wherein the phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal, and performs a correction operation according to a period given by the gate signal. The demodulation device according to any one of 12, 14, and 16.

25. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

C / N detection means for receiving an output signal of the phase correction means and detecting a state of C / N (carrier power / noise power) of a received signal; In the communication frame, a signal period providing unit that outputs a signal that gives a period of each phase modulation signal other than the synchronization signal period,

Demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means according to a phase modulation method based on the signal output by the signal period giving means and the timing signal;

Based on the detection results of the frame synchronization determination unit, the C / N detection unit and the error correction detection unit, and the signal output by the signal period assignment unit and the timing signal,

If there is phase synchronization and error correction is completed,

If the C / N is higher than the predetermined first threshold, a gate signal giving the entire period of the communication frame is

The phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal, and performs a correction operation according to a period given by the gate signal. 6. The demodulation device according to any one of 5.

26. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

Error correction detection means for detecting a correction state of error correction processing of a transmission control signal (TMCC signal) included in the frame synchronization signal; In the communication frame, a signal period providing unit that outputs a signal that gives a period of each phase modulation signal other than the synchronization signal period,

Based on the detection results of the frame synchronization determining means and the error correction detecting means, and the signal output by the signal period providing means and the timing signal, the demodulation method in the phase correcting means corresponds to the phase modulation method. Demodulation mode switching means for outputting a demodulation mode signal to be switched

If there is phase synchronization and error correction is completed,

If there is phase synchronization and error correction has not been completed,

If the C / N is lower than the second predetermined threshold, a gate signal giving the synchronization signal period is generated,

If there is no phase synchronization, further comprising a gate signal generating means for generating a gate signal for providing the synchronization signal period,

When the error correction is not completed, the phase correction unit detects a phase difference due to the minimum phase modulation during the synchronization signal period provided by the timing signal, and when the number of phases in the communication frame is outside of the synchronization signal period, By the most phase modulation When a phase error is detected and the error correction is completed, a phase error by a phase modulation method according to the demodulation mode signal is detected, and then a correction operation is performed according to a period given by the gate signal. The demodulation device according to any one of claims 10, 12, 14, and 16.

27. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

If there is phase synchronization and error correction is completed,

If there is phase synchronization and error correction has not been completed,

If C / N is higher than the predetermined first threshold, the communication frame Gate signal that gives the entire period of

When the error correction is not completed, the phase correction unit detects a phase difference due to the minimum phase modulation during the synchronization signal period provided by the timing signal, and when the number of phases in the communication frame is outside of the synchronization signal period, When the phase error due to the most phase modulation is detected and the error correction is completed, after the phase error according to the phase modulation method according to the demodulation mode signal is detected, the correction operation is performed according to the period given by the gate signal. The demodulation device according to any one of claims 11, 13, and 15, wherein the demodulation is performed.

28. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

A BER that measures the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction and detects the state of C / N (carrier power / noise power) based on the bit error rate. Detecting means;

The phase correction unit detects a phase error due to minimum phase modulation during the synchronization signal period provided by the timing signal, and detects a phase error due to phase modulation having the largest number of phases in the communication frame outside the synchronization signal period. The correction operation is performed according to a period given by the gate signal thereafter. The demodulator according to any one of the above.

29. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

If there is phase synchronization and error correction is completed,

The phase correction means may include a phase error caused by a phase modulation method according to the demodulation mode signal. The demodulation device according to claim 10, wherein a difference is detected, and a correction operation is performed in accordance with a period given by the gate signal.

30. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit;

If there is phase synchronization and error correction is completed,

The phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal, and performs a correction operation according to a period given by the gate signal. The demodulation device according to any one of claims 11, 13, and 15.

31. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

If there is phase synchronization and error correction is completed,

If there is phase synchronization and error correction has not been completed,

When there is no phase synchronization, further comprising gate signal generation means for generating a gate signal for providing the synchronization signal period;

When the error correction is not completed, the phase correction unit detects a phase difference due to the minimum phase modulation during the synchronization signal period provided by the timing signal, and when the number of phases in the communication frame is outside of the synchronization signal period, When the phase error due to the most phase modulation is detected and the error correction is completed, after the phase error according to the phase modulation method according to the demodulation mode signal is detected, the correction operation is performed according to the period given by the gate signal. The demodulator according to claim 10, wherein the demodulation is performed.

32. A frame synchronization determination unit that receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit,

Based on the detection results of the frame synchronization determination unit, the BER detection unit and the error correction detection unit, and a signal output by the signal period assignment unit and the timing signal, If there is phase synchronization and error correction is completed and C / N is higher than a predetermined first threshold, a gate signal giving the entire period of the communication frame is

If there is phase synchronization and error correction has not been completed,

When there is no phase synchronization, further comprising a gate signal generation means for generating a gate signal for providing the synchronization signal period;

3 3. The frame synchronization detecting means includes:

Delay detection means for delay-detecting the signal,

A pattern of the output of the one or more phase identification means and the frame synchronization signal. Verification means for performing verification,

The one or more phase discriminating means has a phase discriminating region corresponding to the phase modulation for transmitting the frame synchronization signal, and the two or more phase discriminating regions perform different phase rotations in parallel to perform the phase rotation. Install,

The demodulator according to any one of claims 9 to 32, wherein the matching unit performs pattern matching on each output of the phase identification unit having a different phase rotation amount of the phase identification region. .

3 4. The frame synchronization detecting means includes:

Delay detection means for delay-detecting the signal,

A plurality of phase rotation means for applying a predetermined number of types of phase rotation to the differential detection signal; a phase identification means for performing phase identification on the output of each of the plurality of phase rotation means;

A matching unit that performs pattern matching between the output of the phase identification unit and the frame synchronization signal,

The phase discriminating means has a phase discriminating region corresponding to the phase modulation in which the frame synchronization signal is transmitted, and converts a signal transmitted for each phase modulated signal that has been subjected to differential detection and given a different phase rotation. Identify,

33. The demodulation device according to claim 9, wherein the matching unit performs pattern matching on each output of the phase identification unit.

3 5. The frame synchronization detecting means includes:

Delay detection means for delay-detecting the signal,

Phase identification means for identifying a signal transmitted from the differentially detected phase modulated signal, identification phase rotation means for rotating the identification phase of the phase identification means,

A collation means for comparing the output of the phase identification means and the pattern of the frame synchronization signal,

The phase identification means may include a phase corresponding to a phase modulation for transmitting the frame synchronization signal. 10. A phase identification area, wherein the phase rotation means rotates the phase of the phase identification area in the phase identification means until the frame synchronization signal is detected by the matching means. 33. The demodulation device according to any one of to 32.

36. The frame synchronization detecting means includes:

Delay detection means for delay-detecting the signal,

The phase of the phase rotation means is rotated until the frame synchronization signal is detected by the matching means, wherein the demodulation according to any one of claims 9 to 32.

37. An output signal of the frequency correction unit is input, and after a band of the output signal is limited, a band limit filter output to the phase correction unit is further provided.

The frame synchronization detection unit receives an output signal of one of a frequency correction unit, a band limiting filter, and the phase correction unit, and detects the frame start position. 36 Demodulator according to any of 6

38. In the case where the carrier synchronization auxiliary signal superimposes information for identifying the phase modulation applied to the modulation signal to be the next packet with respect to the time division multiplexed position in the communication frame,

Information detecting means for detecting a period of the signal on which the minimum phase modulation is performed based on the information, and outputting a signal giving the minimum phase modulation period to the timing generation means,

The timing generation means may include, in addition to the synchronization signal period, the minimum phase modulation period The demodulation device according to any one of claims 9 to 37, which generates a timing signal that gives:

39. If the frequency at which the pseudo-synchronization occurs is fg [Hz], the frequency step means calculates the frequency based on (1-1) ⁿ — ¹ nxf g [Hz] (n = l, 2,. 17. The demodulation device according to claim 13, wherein the frequency input to the phase correction means is shifted stepwise.

40. A carrier synchronization auxiliary signal that has been phase-modulated using the phase modulation with the smallest number of phases (hereinafter referred to as minimum phase modulation) in a communication frame along with a plurality of phase-modulated signals is distributed at equal time intervals. A method for demodulating the time-division multiplexed communication frame,

Detecting a synchronization signal of the communication frame to detect at least a period of the carrier synchronization auxiliary signal (hereinafter, referred to as a synchronization signal period) in the period in which the minimum phase modulation is performed;

41. detecting a frequency pull-in state to determine whether the frequency is a frequency at which pseudo-synchronization occurs;

41. The demodulation method according to claim 40, further comprising, if the result of the determination in the determining step is a frequency at which pseudo synchronization does not occur, initializing a phase correction operation.

42. a step of detecting a state of phase synchronization during the period of the carrier synchronization auxiliary signal;

Detecting a correction state of error correction processing of a transmission control signal (TMCC signal) included in the frame synchronization signal;

Determining whether or not pseudo synchronization is to be performed based on a phase synchronization state of the carrier synchronization auxiliary signal period and an error correction state of the TMCC signal period; 41. The demodulation method according to claim 40, further comprising: if the result of the determination in the determining step is pseudo synchronization, the step of initializing a phase correction operation.

43. detecting a phase synchronization state during the period of the carrier synchronization auxiliary signal;

Detecting a phase synchronization state during a transmission control signal (TMCC signal) included in the frame synchronization signal;

Determining whether or not pseudo synchronization is to be performed based on the phase synchronization state during the carrier synchronization auxiliary signal period and the phase synchronization state during the TMCC signal period;

41. The demodulation method according to claim 40, further comprising: if the result of the determination in the determining step is pseudo synchronization, the step of initializing a phase correction operation.

44. a step of detecting a state of phase synchronization during the period of the carrier synchronization auxiliary signal;

Determining whether or not pseudo synchronization is to be performed based on a phase synchronization state of the carrier synchronization auxiliary signal period and an error correction state of the TMCC signal period;

41. The demodulation method according to claim 40, further comprising, if the result of the determination in the determining step is pseudo-synchronization, changing the frequency at which the phase correction operation is performed in a stepwise manner.

45. a step of detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal;

If the result of the judgment in the judging step is quasi-synchronous, phase correction Changing the frequency at which the operation is performed in a stepwise manner.

40. The demodulation method according to 40.

4 6. Detecting a frequency pull-in state and determining whether or not the frequency is a frequency at which pseudo synchronization occurs;

The demodulation method according to claim 44, further comprising, if the result of the determination in the determining step is a frequency at which pseudo synchronization does not occur, the step of initializing a phase correction operation.

4 7. Detecting a frequency pull-in state and determining whether or not the frequency is a frequency at which pseudo synchronization occurs;

46. The demodulation method according to claim 45, further comprising: if the result of the determination in the determining step is a frequency at which pseudo synchronization does not occur, the step of initializing a phase correction operation.

4 8. Detecting the state of phase synchronization;

Detecting the C / N (carrier power / noise power) state of the received signal; and if there is phase synchronization and the C / N is higher than a predetermined threshold, After detecting a phase error due to the minimum phase modulation, and detecting a phase error due to a phase modulation having the largest number of phases in the communication frame other than the synchronization signal period of the communication frame, correcting the phase during the entire period of the communication frame. The demodulation method according to claim 40, further comprising a step of performing an operation.

4 9. detecting the state of phase synchronization;

If there is phase synchronization and error correction is completed, and C / N is higher than a predetermined first threshold value, the phase error due to the corresponding phase modulation in the entire period of the communication frame is calculated. Detected, the first threshold value and a predetermined second threshold value If the C / N is between the maximum and minimum values, a phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase number is largest in the communication frame and the second operation is performed. Performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, when the C / N is lower than the threshold value. 41. The demodulation method according to claim 40, comprising:

50. detecting a state of phase synchronization;

If there is phase synchronization and error correction is completed, and if C / N is higher than a predetermined first threshold, the phase error due to the corresponding phase modulation in the entire communication frame period is calculated. If the detected value is C / N between the first threshold value and a predetermined second threshold value, phase modulation having the largest number of phases in the communication frame (hereinafter referred to as maximum phase modulation) ), A phase error due to the corresponding phase modulation is detected in a period other than the period in which C / N is lower than the second threshold value, and the synchronization signal period and the minimum phase modulation are performed. Performing a phase correction operation after detecting the phase error due to the minimum phase modulation during a period of time when the phase is synchronized and error correction is not completed, and the first threshold value is satisfied. High C / N In this case, a phase error due to the minimum phase modulation is detected during the synchronization signal period, and a phase error due to the maximum phase modulation within the communication frame is detected during a period other than the synchronization signal period of the communication frame, and then phase correction is performed. 41. The demodulation method according to claim 40, further comprising: performing an operation.

5 1. detecting the state of phase synchronization;

The bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction is measured, and the C / N (carrier power noise) is determined based on the bit error rate. Detecting the state of sound power);

If there is phase synchronization and C / N is higher than a predetermined threshold, a phase error due to the minimum phase modulation is detected in the synchronization signal period, and the phase error is detected in periods other than the synchronization signal period of the communication frame. The demodulation method according to claim 40, further comprising: performing a phase correction operation after detecting a phase error due to a phase modulation having the largest number of phases in the communication frame.

5 2. Detecting phase synchronization status;

Measuring a bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detecting a state of C / N (carrier power / noise power) based on the bit error rate; When,

A step of detecting a correction state of an error correction process of a transmission control signal (TMC C signal) included in the frame synchronization signal;

If there is phase synchronization and error correction is completed, and if C / N is higher than a predetermined first threshold, the phase error due to the corresponding phase modulation in the entire communication frame period is calculated. If the detected value is C / N between the first threshold value and a predetermined second threshold value, the C / N is a period other than the period in which the phase modulation with the largest number of phases is performed in the communication frame. The phase error due to the corresponding phase modulation is detected during the period, and if the C / N is lower than the second threshold value, the minimum phase is detected during the synchronization signal period and the period when the minimum phase modulation is performed. The demodulation method according to claim 40, further comprising: performing a phase correction operation after detecting a phase error due to modulation.

5 3. detecting the state of phase synchronization;

Error correction processing of a transmission control signal (TMCC signal) included in the frame synchronization signal Detecting a correction state of the

If there is phase synchronization and error correction is completed, and if C / N is higher than a predetermined first threshold, the phase error due to the corresponding phase modulation in the entire communication frame period is calculated. If the detected value is C / N between the first threshold value and a predetermined second threshold value, phase modulation having the largest number of phases in the communication frame (hereinafter referred to as maximum phase modulation) ), A phase error due to the corresponding phase modulation is detected in a period other than the period in which C / N is lower than the second threshold value, and the synchronization signal period and the minimum phase modulation are performed. Performing a phase correction operation after detecting the phase error due to the minimum phase modulation during a period of time when the phase is synchronized and error correction is not completed, and the first threshold value is satisfied. High C / N In this case, a phase error due to the minimum phase modulation is detected during the synchronization signal period, and a phase error due to the maximum phase modulation within the communication frame is detected during a period other than the synchronization signal period of the communication frame. 41. The demodulation method according to claim 40, further comprising: performing an operation.

5 4. detecting the state of phase synchronization;

Detecting the C / N (carrier power / noise power) state of the received signal; and if there is phase synchronization and the C / N is higher than a predetermined threshold, Detecting a phase error due to minimum phase modulation, detecting a phase error due to phase modulation having the largest number of phases in the communication frame other than the synchronization signal period of the communication frame, and then performing a phase correction operation. The demodulation method according to any one of claims 41 to 47, comprising:

5 5. detecting the state of phase synchronization;

In the case where phase synchronization is performed and error correction is completed, the first When C / N is higher than the threshold value, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and a phase error between the first threshold value and a predetermined second threshold value is detected. If the C / N is equal to, the phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation having the largest number of phases is performed in the communication frame. If / N is low, the method further comprises: performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed. The demodulation method according to any one of 1, 43, 45 and 47.

5 6. detecting the state of phase synchronization;

Detecting the C / N (carrier power / noise power) state of the received signal; and performing phase synchronization and error correction, and the C / N (C / N) is determined based on a predetermined first threshold. If / N is high, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and is C / N between the first threshold value and a predetermined second threshold value. In the communication frame, the phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation having the largest number of phases is performed in the communication frame, and when the C / N is lower than the second threshold, Performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed. Demodulation according to any of 6 Law.

5 7. detecting the state of phase synchronization;

If there is phase synchronization and error correction is completed, and C / N is higher than a predetermined first threshold value, the phase error due to the corresponding phase modulation in the entire period of the communication frame is calculated. Detected, the first threshold value and a predetermined second threshold value If the C / N is between the maximum value and the maximum value, the phase error due to the corresponding phase modulation in a period other than the period in which the number of phases is the largest in the communication frame (hereinafter referred to as the maximum phase modulation) is calculated. If the C / N is lower than the second threshold value, the phase correction operation is performed after detecting the phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed. Performing phase synchronization, and when error correction is not completed, and when C / N is higher than the first threshold value, the minimum phase modulation is performed in the synchronization signal period. Detecting a phase error due to the maximum phase modulation within the communication frame during a period other than the synchronization signal period of the communication frame, and then performing a phase correction operation. Comprising the al, claim 4 1, 4 3, 4 5 or 4 7 demodulating method of any crab described.

5 8. Detecting phase synchronization status;

Detecting the C / N (carrier power / noise power) state of the received signal; and performing phase synchronization and error correction, and the C / N (C / N) is determined based on a predetermined first threshold. If / N is high, a phase error due to the corresponding phase modulation is detected during the entire period of the communication frame, and is C / N between the first threshold value and a predetermined second threshold value. In this case, a phase error due to the corresponding phase modulation is detected in a period other than the period in which phase modulation having the largest number of phases (hereinafter, referred to as maximum phase modulation) is performed in the communication frame, and the second threshold value is set. On the other hand, when C / N is low, there is a step of performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed; and , Wrong If the positive is not completed and C / N is higher than the first threshold value, a phase error due to the minimum phase modulation is detected during the synchronization signal period, and the phase error of the communication frame is detected. And performing a phase correction operation after detecting a phase error due to the maximum phase modulation in the communication frame during a period other than the synchronization signal period. Demodulation method described above.

5 9. detecting the state of phase synchronization;

Measuring the bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detecting the state of C / N (carrier power / noise power) based on the bit error rate; When,

If there is phase synchronization and C / N is higher than a predetermined threshold, a phase error due to the minimum phase modulation is detected in the synchronization signal period, and the phase error is detected in periods other than the synchronization signal period of the communication frame. 48. The demodulation method according to claim 41, further comprising: performing a phase correction operation after detecting a phase error due to a phase modulation having the largest number of phases in the communication frame.

6 0. Detecting a state of phase synchronization;

If there is phase synchronization and error correction is completed, and if C / N is higher than a predetermined first threshold value, the phase error due to the corresponding phase modulation in the entire period of the communication frame is calculated. If the detected value is C / N between the first threshold value and a predetermined second threshold value, the C / N is a period other than the period in which the phase modulation with the largest number of phases is performed in the communication frame. The phase error due to the corresponding phase modulation is detected during the period, and when the C / N is lower than the second threshold value, the minimum phase is detected during the synchronization signal period and the period when the minimum phase modulation is performed. 48. The demodulation method according to claim 41, further comprising: performing a phase correction operation after detecting a phase error due to modulation.

6 1. detecting the state of phase synchronization; Measuring a bit error rate of the transmission control signal (TMCC signal) included in the frame synchronization signal before error correction, and detecting a state of C / N (carrier power / noise power) based on the bit error rate; When,

If there is phase synchronization and error correction is completed, and if C / N is higher than a predetermined first threshold, the phase error due to the corresponding phase modulation in the entire communication frame period is calculated. If the detected value is C / N between the first threshold value and a predetermined second threshold value, the C / N is a period other than the period in which the phase modulation with the largest number of phases is performed in the communication frame. The phase error due to the corresponding phase modulation is detected during the period, and if the C / N is lower than the second threshold value, the minimum phase is detected during the synchronization signal period and the period when the minimum phase modulation is performed. 47. The demodulation method according to claim 42, further comprising: performing a phase correction operation after detecting a phase error due to modulation.

6 2. Detecting phase synchronization status;

If there is phase synchronization and error correction is completed, and if C / N is higher than a predetermined first threshold, the phase error due to the corresponding phase modulation in the entire communication frame period is calculated. If the detected value is C / N between the first threshold value and a predetermined second threshold value, phase modulation having the largest number of phases in the communication frame (hereinafter referred to as maximum phase modulation) ), A phase error due to the corresponding phase modulation is detected in a period other than the period in which C / N is lower than the second threshold value, and the synchronization signal period and the minimum phase modulation are performed. Performing a phase correction operation after detecting a phase error due to the minimum phase modulation during a period of time, In the case where there is phase synchronization and error correction has not been completed and C / N is higher than the first threshold value, the phase error due to the minimum phase modulation is reduced in the synchronization signal period. Detecting and detecting a phase error due to the maximum phase modulation in the communication frame other than the synchronization signal period of the communication frame, and then performing a phase correction operation. The demodulation method according to any one of 45 or 47.

6 3. detecting the state of phase synchronization;

If there is phase synchronization and error correction is completed, and C / N is higher than a predetermined first threshold value, the phase error due to the corresponding phase modulation in the entire period of the communication frame is calculated. If the detected value is C / N between the first threshold value and a predetermined second threshold value, phase modulation having the largest number of phases in the communication frame (hereinafter referred to as maximum phase modulation) ), A phase error due to the corresponding phase modulation is detected in a period other than the period in which C / N is lower than the second threshold value, and the synchronization signal period and the minimum phase modulation are performed. Performing a phase correction operation after detecting the phase error due to the minimum phase modulation during a period of time when the phase is synchronized and error correction is not completed, and the first threshold value is satisfied. High C / N In this case, a phase error due to the minimum phase modulation is detected during the synchronization signal period, and a phase error due to the maximum phase modulation within the communication frame is detected during periods other than the synchronization signal period of the communication frame. 47. The demodulation method according to claim 42, further comprising a step of performing a correction operation.

6 4. Information for identifying the phase modulation applied to the modulation signal serving as the next bucket at the position where the carrier synchronization auxiliary signal is time-division multiplexed in the communication frame Information is superimposed,

Detecting a period of the signal subjected to the minimum phase modulation based on the information, outputting a signal providing the minimum phase modulation period to a step of generating the evening signal, and generating the timing signal; 64. The demodulation method according to claim 40, wherein the step generates a timing signal that gives the minimum phase modulation period in addition to the synchronization signal period.

65. In the step of changing the frequency stepwise, ^assuming that the frequency at which the pseudo-synchronization occurs is fg [Hz], (1-1) ^n- 'xnxf g [Hz] (n = l, 2, ... 48. The demodulation method according to any one of claims 44 to 47, wherein the frequency at which the phase correction operation is performed is shifted stepwise based on ().