JP3153188B2 - Modulation / demodulation device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a modulation / demodulation apparatus and method, and more particularly, to a modulation / demodulation apparatus and method used for a digital satellite broadcasting system.

[0002]

2. Description of the Related Art Conventionally, as a modulation device and a method used in a digital satellite broadcasting system, a paper by Kato and Hashimoto, "Study of Satellite ISDB Transmission System", ITE Technical Report, BCS'97-12 (Mar. (1997) (hereinafter referred to as conventional literature).

[0003] The modulation apparatus and method described in this conventional document make it possible to transmit two data streams independently. That is, error correction is independently performed on the low-layer signal and the high-layer signal, and the low-layer signal and the high-layer signal are collected by an appropriate number of packets to form a frame having a fixed total number of packets. Here, the conventional modulation apparatus uses BPSK (Binary Phase Shift Keying) or QPSK for the lower layer signal.
(Quaternary Phase Shift Keying) and 8PSK (8 phase shift keying; 8 Phase)
Shift Keying) and transmit by time division multiplexing. In addition, the conventional modulation apparatus uses a transmission multiplexing control (TMCC) indicating a frame synchronization signal, a division of each layer in a frame, and a modulation mode of each layer.
BPS that can receive signals stably even at the lowest C / N (carrier power / noise power)
Apply K and transmit.

Hereinafter, this conventional modulation apparatus and method will be described.
This will be briefly described with reference to FIGS. FIG. 77 is a block diagram showing a configuration of a conventional modulation device. Fig. 78
FIG. 3 is a diagram showing a structure of a communication frame output from a conventional demodulation device. FIG. 79 is a diagram illustrating mapping of BPSK, QPSK, and 8PSK to code constellations. FIG. 80 is a diagram showing an MPEG data structure and a frame structure in a conventional modulation device and method.

In FIG. 77, a conventional modulation device includes a frame synchronization signal / TMCC signal generation unit 1001, a TS packet synthesis unit 1002, and a TMCC error correction encoding unit 1
003, a first error correction coding unit 1004, a second error correction coding unit 1005, and a BPSK mapping unit 1
006 and BPSK / QPSK mapping section 1007
, An 8PSK mapping unit 1008, and a multiplexing / quadrature modulation unit 1009.

Frame synchronization signal / TMCC signal generator 1
001 generates a frame synchronization signal / TMCC signal based on the input TMCC information. This frame synchronization signal / TMCC signal is transmitted to TMCC error correction encoding section 100.
3 is input to the BPSK mapping unit 1006 after error correction coding. BPSK mapping unit 1
006 maps the input frame synchronization signal and TMCC signal to the BPSK code arrangement shown in FIG. 79 (a), and outputs the result to multiplexing / quadrature modulation section 1009.

A TS packet synthesizer 1002 synthesizes a plurality of input MPEG-TS packets (FIG. 80 (a)), and is composed of a group of low-layer signal packets and a group of high-layer signal packets. Is generated (FIG. 80 (b)). In this frame, the packet group of the lower layer signal is transmitted to the first error correction encoding unit 100.
4, after the error correction coding, the BPSK / QP
It is input to SK mapping section 1007. BPSK / Q
The PSK mapping section 1007 maps the input low-layer signal to the BPSK code arrangement shown in FIG. 79A or the QPSK code arrangement shown in FIG. I do. On the other hand, among the above-mentioned frames, the packet group of the high-layer signal is subjected to error correction encoding in the second error correction encoding section 1005, and then input to the 8PSK mapping section 1008. 8
The PSK mapping section 1008 maps the input high-layer signal to the code arrangement of 8PSK shown in FIG. 79 (c), and outputs it to the multiplexing / quadrature modulation section 1009.

[0008] Then, the multiplexing / quadrature modulation section 1009
Each signal input from each mapping unit is time-division multiplexed in the order shown in FIG. 78 to generate a communication frame, and then orthogonally modulated and output to a demodulation device. Here, as can be seen from FIG. 78, the multiplexing / quadrature modulation section 1009 outputs the frame synchronization signal and TMCC signal,
A packet group of a high-level signal to which K has been applied, and BPSK
Alternatively, a communication frame is generated by performing time-division multiplexing on a packet group of a low-layer signal subjected to QPSK.

Next, a demodulator for inputting and demodulating a communication frame generated by the conventional modulator is shown in FIG.
1 will be described. FIG. 81 is a block diagram showing a configuration of a conventional demodulation device. In FIG. 81, a conventional demodulation device includes a quadrature detection unit 1101 and a PSK demodulation unit 1102
BER (Bit Error Rate) detecting section 1103, T
An MCC decoder 1104, an error correction unit 1105, and a video decoder 1106 are provided.

[0010] The communication frame transmitted from the modulation device is:
Input to quadrature detector 1101. Quadrature detector 1101
Is used to quadrature-detect and digitize each signal in the input communication frame by an internal local oscillator,
102 and the TMCC decoder 1104.

First, the PSK demodulation unit 1102 performs frequency correction and phase correction, assuming that all signals of the input communication frame have been subjected to 8PSK, and demodulates them into I and Q signals. Here, the TMCC decoder 1104
Detects the frame synchronization signal subjected to BPSK in this state, recognizes the head of the communication frame, and detects at which phase of the eight phases the PSK demodulation unit 1102 is phase-synchronized. Also, the TMCC decoder 11
Reference numeral 04 identifies a phase modulation configuration applied to each hierarchical signal by detecting a TMCC signal subsequent to the frame synchronization signal, and determines a phase reference on the demodulation device side in phase error detection for phase correction. Switch to one that supports phase modulation. Then, the PSK demodulation unit 1102 remaps the demodulated I and Q signals based on the phase information indicating which phase of the eight phases was synchronized, and converts the I and Q signals into absolute phase I and Q signals. Error correction unit 110
Output to 5

The error correction section 1105 has two independent error correction circuits, and performs error correction by distributing the signal demodulated by the PSK demodulation section 1102 in packet units based on the decoded TMCC signal. Thereafter, an operation of restoring the order of the packets rearranged on the time axis for time division multiplex transmission is performed. This output is output to video decoder 1106.

The BER detection unit 1103 performs demodulation of a demodulated 8 P
The signal obtained by performing trellis decoding on the SK signal is subjected to trellis encoding again, and the BER of the higher layer signal is monitored by comparing the SK signal with the demodulated 8PSK signal. As a result, if it is determined that the quality of the high-layer decoded video is lower than the allowable value, the BER detection unit 1103 outputs a low-layer video signal that is highly resistant to quality deterioration of the transmission path. The signal is controlled by the video decoder 1106.

With the above-described processing, the conventional modulation / demodulation apparatus and method allow the user to continue viewing the service even if the quality of the transmission path is deteriorated due to rainfall during reception.

[0015]

As described above, in the above-mentioned conventional modulation apparatus, error correction is performed independently on the low-layer signal and the high-layer signal, and the transmission efficiency is low for the low-layer signal. BPSK or QPSK with high transmission reliability
And 8PSK, which has high transmission efficiency but low transmission reliability, are applied to high-layer signals, and are transmitted by time division multiplexing. On the other hand, in the above-mentioned conventional demodulator, first, each signal of the communication frame to be input is all 8P.
Frequency correction and phase correction are performed assuming that the signal has undergone SK. Then, after carrier synchronization, TMCC
The signal is decoded to identify the configuration of the phase modulation applied to each layer signal, and demodulated for each signal. By detecting the BER, a low-layer signal that is highly resistant to deterioration in the quality of the transmission path is obtained. You can choose.

However, in the above-mentioned conventional demodulator,
When an operation such as power-on or channel selection is performed during low C / N where demodulation (frequency correction and phase correction) by 8PSK is not possible, carrier synchronization cannot be performed, that is, there is a problem that services cannot be viewed.

Therefore, an object of the present invention is to provide a modulation / demodulation device capable of performing stable and high-speed carrier synchronization even when an operation such as turning on the power of a demodulation device or selecting a channel is performed at a low C / N. Is to provide a way.

[0018]

According to a first aspect of the present invention, a plurality of data to be communicated are subjected to phase modulation with different transmission efficiencies for each layer of the data and a predetermined fixed level is determined. A modulation device that generates a communication frame having a long length, a phase modulation unit that performs a phase modulation corresponding to the data content on each of a plurality of data to generate a modulation signal, and a plurality of phase modulations performed on the data. A signal generation means for generating a carrier synchronization auxiliary signal that has been subjected to phase modulation using the phase modulation having the smallest number of phases in the communication frame (hereinafter referred to as minimum phase modulation); Multiplexing means for time-division multiplexing the modulated signal and the carrier synchronization auxiliary signal so that
The carrier synchronization auxiliary signal is characterized in that information for identifying the phase modulation applied to the modulation signal to be the next packet is superimposed on the time division multiplexed position in the communication frame.

A second aspect of the present invention is a modulator for generating a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiencies for each layer of the data on a plurality of data to be communicated. there, for each of the multiple data,
A phase modulation means for performing phase modulation to produce a modulated signal corresponding to the data content, the number of phases of the plurality of phase modulation applied to the data is the smallest phase modulation (hereinafter, the minimum that phase modulation) was used and signal generating means for generating a carrier synchronization auxiliary signal subjected to phase modulation Te, career auxiliary synchronizing signal so as to disperse the equal time intervals in a succession communication frame than 2 symbols, Oyo modulation signal and multiplexing means for time-division multiplexing fine career auxiliary synchronizing signals, career auxiliary synchronizing signal is applied to the modulated signal as a next packet relative positions are time division multiplexed in the communication frame It is characterized in that information for identifying a phase modulation is superimposed.

As described above, according to the first and second aspects of the present invention, a signal for assisting carrier synchronization in a demodulator on which information defining the modulation scheme of the next packet is superimposed is output for a low C / N state. The communication frame is modulated by strong minimum phase modulation, and the communication frame dispersedly inserted in the packet is output.
Thus, in the demodulator, even in the low C / N state, carrier synchronization can be performed at high speed and stably using the carrier synchronization auxiliary signal dispersed in the packet and the main signal subjected to the minimum phase modulation.

According to a third aspect, in the first and second aspects, the apparatus further comprises a differential encoding means for performing differential encoding on an input signal and outputting the signal, and the signal generating means comprises a differential encoding means. A carrier synchronization auxiliary signal is generated by performing minimum phase modulation among a plurality of phase modulations performed on data on the signal that has been differentially encoded by the means.

As described above, according to the third aspect, the first aspect
In the second invention, a signal for assisting carrier synchronization in a demodulation device on which information defining a modulation scheme of a next packet is superimposed is generated after differential encoding.
As a result, the modulation method information can be decoded even in a state where the carrier is not synchronized in the demodulation device.

The fourth invention is a modulation method for generating a predetermined fixed-length communication frame by performing phase modulation of a plurality of data to be communicated with different transmission efficiency for each layer of the data. And generating a carrier synchronization auxiliary signal that has been subjected to phase modulation by using phase modulation having the smallest number of phases among a plurality of phase modulations applied to data (hereinafter, referred to as minimum phase modulation). Are time-division multiplexed so as to be distributed at equal time intervals in the communication frame, and the carrier synchronization auxiliary signal It is characterized in that information for identifying modulation is superimposed.

The fifth invention is a modulation method for generating a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiency for each layer of the data on a plurality of data to be communicated. And generating a carrier synchronization auxiliary signal that has been subjected to phase modulation by using phase modulation having the smallest number of phases among a plurality of phase modulations applied to data (hereinafter, referred to as minimum phase modulation). Is time-division multiplexed so that two or more symbols are continuously distributed at equal time intervals in the communication frame, and the carrier synchronization auxiliary signal is a modulated signal that becomes the next packet with respect to the time-division multiplexed position in the communication frame. Is superimposed with information for identifying the phase modulation applied to.

As described above, according to the fourth and fifth aspects of the present invention, the signal for assisting the carrier synchronization in which the information defining the modulation scheme of the next packet is superimposed during the demodulation operation is changed to the low C / N state. , And outputs a communication frame dispersedly inserted in the packet. Thereby, at the time of demodulation operation, even in the low C / N state, high-speed and stable carrier synchronization can be performed using the carrier synchronization auxiliary signal dispersed in the packet and the main signal subjected to the minimum phase modulation. .

According to a sixth aspect of the present invention, in the fourth and fifth aspects, the carrier synchronization auxiliary signal is the minimum phase modulation of a plurality of phase modulations applied to data with respect to the signal after differential encoding. Is generated by applying

As described above, according to the sixth aspect, the fourth aspect
In the fifth invention, a signal for assisting carrier synchronization in which information defining a modulation scheme of a next packet is superimposed upon demodulation is generated after differential encoding. As a result, the modulation scheme information can be decoded even when the carrier is not synchronized during the demodulation operation.

According to a seventh aspect of the present invention, a plurality of phase modulation signals are shared.
The phase change with the smallest number of phases in the communication frame
Key (hereinafter referred to as minimum phase modulation).
Carrier synchronization auxiliary signal distributed at equal time intervals
Receive the time-division multiplexed communication frame
A demodulator for detecting a synchronization signal of a communication frame
Frame synchronization detection to detect the frame start position
Means and a minimum phase modulation based on the frame start position.
Of the carrier synchronization auxiliary signal during at least the
Timing for giving a period (hereinafter referred to as a synchronization signal period)
Timing generating means for generating a signal, and a timing signal
By using the period given by
To perform frequency correction operation and phase correction operation according to
Means.

According to an eighth aspect of the present invention, a carrier synchronization auxiliary signal that has been phase-modulated using a phase modulation having the smallest number of phases in a communication frame (hereinafter referred to as a minimum phase modulation) together with a plurality of phase-modulated signals is the same. What is claimed is: 1. A demodulation device for receiving a communication frame time-division multiplexed so as to be dispersed in a time interval, comprising: a frequency correction unit configured to detect a frequency error of a predetermined signal period in the communication frame and correct a frequency shift. And a phase correction means for detecting a phase error of a predetermined signal period in a communication frame to correct a phase shift, and an output signal of one of a frequency correction means and a phase correction means, and performs delay detection. Frame synchronization detecting means for detecting a frame starting position by detecting a synchronizing signal of a communication frame using the communication frame, and a frame starting position detected by the frame synchronization detecting means Timing generation means for detecting at least a period of the carrier synchronization auxiliary signal (hereinafter referred to as a synchronization signal period) in the period in which the minimum phase modulation is performed, and generating a timing signal for giving the synchronization signal period. Frequency correction means and phase correction means,
In the synchronization signal period given by the timing signal, a correction operation according to the minimum phase modulation is performed.

As described above, according to the eighth aspect , of the phase modulation signals to be time-division multiplexed, the frequency correction and the frequency correction are performed by using the minimum phase modulation signal including the carrier synchronization auxiliary signal dispersedly arranged in the packet. By performing the phase correction (regeneration of carrier wave), carrier synchronization can be performed at high speed and stably even in the low C / N state.

In a ninth aspect based on the eighth aspect, an output signal of either the frequency correction means or the phase correction means is input, and a frequency pull-in state is detected to determine whether or not the frequency is a frequency at which the phase correction means is pseudo-synchronous. Frequency pull-in detecting means for determining whether the frequency pull-in detecting means,
When the frequency correction by the frequency correction means is completed to a frequency at which the phase correction means does not perform pseudo-synchronization, the phase correction means is further provided with a phase correction reset means for initializing the phase correction means.

As described above, according to the ninth aspect , the eighth aspect
In the invention, the frequency lock-in detection means is provided, and after the frequency correction is performed to a frequency at which the phase correction means is not pseudo-synchronized, the phase correction means is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase corrector in the frequency pull-in process by the frequency corrector.

In a tenth aspect based on the eighth aspect , a phase synchronization detecting means for inputting an output signal of the phase correcting means and detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal is included in the frame synchronization signal. Transmission control signal (T
Error correction detection means for detecting the correction state of the error correction processing of the MCC signal), pseudo-synchronization determination means for determining whether or not pseudo-synchronization is to be performed based on detection results of the phase synchronization detection means and error correction detection means, and pseudo-synchronization determination If the result of the determination by the means is that the synchronization is pseudo-synchronous, the apparatus further comprises phase correction reset means for initializing the phase correction means.

As described above, according to the tenth aspect , the
In the invention of the eighth aspect, the phase synchronization during the period of the carrier synchronization auxiliary signal and the detection of the error correction of the TMCC signal are performed, and it is determined whether or not the normal synchronization is obtained from the detection result. Then, in the case of the pseudo synchronization, the phase correction means is initialized and operated again. This makes it possible to avoid pseudo-synchronization in the phase corrector in the frequency pull-in process by the frequency corrector.

According to an eleventh aspect based on the eighth aspect , the first phase synchronization detecting means for receiving an output signal of the phase correcting means and detecting a state of phase synchronization during the period of the carrier synchronization auxiliary signal, Input the output signal of the means and transmit control signal (TMCC signal) included in the frame synchronization signal
Pseudo-synchronization determination for judging whether or not the pseudo-synchronization is performed based on the detection results of the second phase-synchronization detection means for detecting the state of the phase synchronization during the period, and the first and second phase-synchronization detection means Means and the result of the determination by the pseudo-synchronous determination means,
In the case of the pseudo-synchronization, a phase correction reset unit for initializing the phase correction unit is further provided.

As described above, according to the eleventh aspect , the
In the invention of the eighth aspect, the phase synchronization is detected during the period of the carrier synchronization auxiliary signal and the phase synchronization is detected during the period of the frame synchronization signal / TMCC signal, and it is determined whether or not the synchronization is normal based on the detection result. Then, in the case of the pseudo synchronization, the phase correction means is initialized and operated again. This makes it possible to avoid pseudo-synchronization in the phase corrector in the frequency pull-in process by the frequency corrector.

In a twelfth aspect based on the eighth aspect , a phase synchronization detecting means for inputting an output signal of the phase correcting means and detecting a state of phase synchronization during a carrier synchronization auxiliary signal period, the phase synchronization detecting means being included in the frame synchronization signal. Transmission control signal (T
Error correction detection means for detecting the correction state of the error correction processing of the MCC signal), pseudo-synchronization determination means for determining whether or not pseudo-synchronization is performed based on detection results of the phase synchronization detection means and error correction detection means, and pseudo-synchronization determination If the result of the determination by the means is that the synchronization is pseudo-synchronous, the apparatus further comprises frequency step means for stepwise changing the frequency input to the phase correction means.

As described above, according to the twelfth aspect ,
In the invention of the eighth aspect, the phase synchronization during the period of the carrier synchronization auxiliary signal and the detection of the error correction of the TMCC signal are performed, and it is determined whether or not the normal synchronization is obtained from the detection result. Then, in the case of the pseudo synchronization, the frequency of the frequency correcting means is controlled so that the phase correcting means can perform normal synchronization. This makes it possible to avoid pseudo-synchronization in the phase corrector in the frequency pull-in process by the frequency corrector.

According to a thirteenth aspect , in the eighth aspect , a first phase synchronization detecting means for receiving an output signal of the phase correcting means and detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal; Input the output signal of the means and transmit control signal (TMCC signal) included in the frame synchronization signal
Pseudo-synchronization determination for judging whether or not the pseudo-synchronization is performed based on the detection results of the second phase-synchronization detection means for detecting the state of the phase synchronization during the period, and the first and second phase-synchronization detection means Means and the result of the determination by the pseudo-synchronous determination means,
In the case of the pseudo-synchronization, a frequency step means for changing a frequency inputted to the phase correction means in a stepwise manner is further provided.

As described above, according to the thirteenth aspect , the thirteenth aspect
In the invention of the eighth aspect, the phase synchronization is detected during the period of the carrier synchronization auxiliary signal and the phase synchronization is detected during the period of the frame synchronization signal / TMCC signal, and it is determined whether or not the synchronization is normal based on the detection result. Then, in the case of the pseudo synchronization, the frequency of the frequency correcting means is controlled so that the phase correcting means can perform normal synchronization. This makes it possible to avoid pseudo-synchronization in the phase corrector in the frequency pull-in process by the frequency corrector.

According to a fourteenth aspect , in the twelfth aspect ,
A frequency correction means, or an output signal of any one of the phase correction means, and a frequency pull-in detection means for detecting a frequency pull-in state and determining whether or not the phase correction means is a pseudo-synchronous frequency; and If the result of the determination is that the frequency correction by the frequency correction means has been completed to a frequency at which the phase correction means does not perform pseudo-synchronization, phase correction reset means for initializing the phase correction means is further provided.

According to a fifteenth aspect , in the thirteenth aspect ,
A frequency correction means, or an output signal of any one of the phase correction means, and a frequency pull-in detection means for detecting a frequency pull-in state and determining whether or not the phase correction means is a pseudo-synchronous frequency; and If the result of the determination is that the frequency correction by the frequency correction means has been completed to a frequency at which the phase correction means does not perform pseudo-synchronization, phase correction reset means for initializing the phase correction means is further provided.

As described above, according to the fourteenth and fifteenth aspects, in the twelfth and thirteenth aspects, a frequency pull-in detecting means is further provided, and the frequency correcting means adjusts the frequency to a frequency at which the phase correcting means does not quasi-synchronize. After the correction is performed, the phase correction unit is initialized and operated again. This makes it possible to avoid pseudo-synchronization in the phase corrector in the frequency pull-in process by the frequency corrector.

In a sixteenth aspect based on the eighth aspect , a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting a state of phase synchronization during a carrier synchronization auxiliary signal period, and an output of the phase correcting means. C / N detection means for receiving a signal and detecting the state of C / N (carrier power / noise power) of a received signal; detection results of frame synchronization determination means and C / N detection means; and a timing signal. , Phase synchronization, and C / N with respect to a predetermined threshold
And a gate signal generating means for generating a gate signal for giving the entire period of the communication frame when the signal is high, and a gate signal generating means for generating a gate signal for giving the synchronous signal period otherwise. , A phase error due to the minimum phase modulation is detected during the synchronization signal period, and a phase error due to the phase modulation having the largest number of phases in the communication frame is detected during a period other than the synchronization signal period, and then a correction operation is performed according to the period given by the gate signal. It is characterized by the following.

As described above, according to the sixteenth aspect , the
In the invention of the eighth aspect , the C / N state when the phase synchronization is performed in the minimum phase modulation signal period is detected, and when the C / N is at a predetermined level, the C / N state is also detected for the main signal period of the communication frame. The phase error is corrected assuming that the maximum phase modulation has been performed. As a result, carrier synchronization can be performed stably at high speed even in the low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

In a seventeenth aspect based on the eighth aspect , the output signal of the phase correction means is input, the frame synchronization determination means for detecting phase synchronization in the phase correction means, and the output signal of the phase correction means are input, C / N detection means for detecting the C / N (carrier power / noise power) state of the received signal, and error correction for detecting the correction state of the error correction processing of the transmission control signal (TMCC signal) included in the frame synchronization signal Detecting means, a signal period providing means for outputting a signal giving a period of each phase modulation signal other than a synchronization signal period in a communication frame, and a phase correcting means based on a signal output by the signal period providing means and a timing signal. A demodulation mode switching means for outputting a demodulation mode signal for switching the demodulation method according to the phase modulation method, a frame synchronization determination means, a C / N detection means, and the like. Based on the detection result of the error correction detecting means and the signal and the timing signal output by the signal period providing means, when the phase synchronization is performed and the error correction is completed, and a predetermined first threshold value is set. When the C / N is high, the gate signal giving the entire period of the communication frame is provided. When the C / N is low with respect to the second predetermined threshold value, the gate signal of the signal subjected to the minimum phase modulation is provided. Generates a gate signal that provides a period, otherwise generates a gate signal that provides a minimum phase modulation period and a predetermined modulation signal period, and, unless there is phase synchronization and error correction is completed, a synchronization signal And a gate signal generation means for generating a gate signal for giving a period, wherein the phase correction means detects a phase error by a phase modulation method according to the demodulation mode signal, and follows the period given by the gate signal. And performing a correction operation.

As described above, according to the seventeenth aspect ,
In the invention of the eighth aspect , the C / N state when the phase is synchronized in the minimum phase modulation signal period is detected, and the initial state is determined according to the C / N state and the reference phase corresponding to the phase modulation method according to the demodulation mode signal. In the state (1), the phase correction is performed using the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period that are subjected to the minimum phase modulation. After the phase synchronization, the phase correction is performed also in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in a low C / N state, and the influence of the phase jitter of the demodulated signal during the period of the main signal can be reduced.
Reception performance can be improved.

In an eighteenth aspect based on the eighth aspect , the output signal of the phase correction means is input, the frame synchronization determination means for detecting phase synchronization in the phase correction means, and the output signal of the phase correction means are input, C / N detection means for detecting the C / N (carrier power / noise power) state of the received signal, and error correction for detecting the correction state of the error correction processing of the transmission control signal (TMCC signal) included in the frame synchronization signal Detecting means, a signal period providing means for outputting a signal giving a period of each phase modulation signal other than a synchronization signal period in a communication frame, detection results of the frame synchronization determining means and error correction detecting means, and signal period providing means. A demodulation mode signal is output based on the output signal and the timing signal, and switches the demodulation method in the phase correction means in accordance with the phase modulation method. Phase synchronization based on the detection results of the keying mode switching means, the frame synchronization determination means, the C / N detection means, and the error correction detection means, and the signal and the timing signal output by the signal period providing means. If the C / N is higher than the predetermined first threshold value and the C / N is higher than the predetermined first threshold value, the gate signal giving the entire period of the communication frame is set to the predetermined second threshold value.
/ N is low, a gate signal giving the period of the signal subjected to the minimum phase modulation is generated; otherwise, a gate signal giving the minimum phase modulation period and a predetermined modulation signal period is generated, In the case where there is synchronization and the error correction has not been completed and the C / N is higher than a predetermined first threshold value, a gate signal giving the entire period of the communication frame is determined in advance. C for the second threshold
And a gate signal generating means for generating a gate signal for providing a synchronization signal period when / N is low, and a gate signal for generating a gate signal for providing a synchronization signal period when there is no phase synchronization. If the correction has not been completed,
In the synchronization signal period given by the timing signal, the phase difference due to the minimum phase modulation is detected, and in the period other than the synchronization signal period, the phase error due to the phase modulation having the largest number of phases in the communication frame is detected. After detecting a phase error by a phase modulation method according to a demodulation mode signal, a correction operation is performed according to a period given by a gate signal.

As described above, according to the eighteenth aspect , the
In the invention of the eighth aspect , the C / N state when the phase synchronization is performed in the minimum phase modulation signal period is detected, and when the C / N is at a predetermined level, the communication frame other than the synchronization signal period in the communication frame is detected. While correcting the phase error assuming that the maximum phase modulation has been performed in the entire period, according to the reference phase corresponding to the phase modulation method according to the demodulation mode signal,
In the initial state, the frame synchronization signal /
The phase correction is performed using the TMCC signal period and the carrier synchronization auxiliary signal period, and the phase correction is performed also in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

In a nineteenth aspect based on the eighth aspect , a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means, and a transmission control signal ( BER detecting means for measuring a bit error rate before error correction of a TMCC signal) and detecting a state of C / N (carrier power / noise power) based on the bit error rate; frame synchronization determining means;
Based on the detection result with the detection means and the timing signal, if there is phase synchronization and the C / N is higher than a predetermined threshold, a gate signal for giving the entire period of the communication frame is generated. In other cases, further comprising a gate signal generating means for generating a gate signal providing a synchronization signal period, the phase correction means detects a phase error due to minimum phase modulation in the synchronization signal period provided by the timing signal,
In a period other than the synchronization signal period, after detecting a phase error due to phase modulation having the largest number of phases in a communication frame, a correction operation is performed according to a period given by a gate signal.

As described above, according to the nineteenth aspect , the
In the invention of the eighth aspect , the C / N state when the phase is synchronized in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal, and when the C / N is at a predetermined level, The phase error is corrected assuming that the maximum phase modulation is also performed for the main signal period of the frame. As a result, carrier synchronization can be performed stably at high speed even in the low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

In a twentieth aspect based on the eighth aspect , a frame synchronization determining means for receiving an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means, and a transmission control signal ( BER detecting means for measuring a bit error rate before error correction of a TMCC signal, and detecting a state of C / N (carrier power / noise power) based on the bit error rate, and transmission control included in a frame synchronization signal. Error correction detection means for detecting a correction state of error correction processing of a signal (TMCC signal); signal period providing means for outputting a signal for giving a period of each phase modulation signal other than a synchronization signal period in a communication frame; Demodulation mode for switching the demodulation method in the phase correction means in accordance with the phase modulation method based on the signal output by the applying means and the timing signal. Mode switching means for outputting a signal, frame synchronization determination means, BER detection means and error correction detection means detection results, and a signal and a timing signal output from the signal period giving means provide phase synchronization and error detection. When the correction is completed and the C / N is higher than the predetermined first threshold value, the gate signal for giving the entire period of the communication frame is changed to the predetermined second threshold value. If the C / N is low, a gate signal giving the period of the signal subjected to the minimum phase modulation is generated. Otherwise, a gate signal giving the minimum phase modulation period and a predetermined modulation signal period is generated. And a gate signal generation unit for generating a gate signal for providing a synchronization signal period except when the phase synchronization is performed and the error correction is completed, and the phase correction unit includes a demodulation mode signal. Detecting a phase error based on the phase modulation method in accordance with, and performs the correction operation in accordance with the period in which the gate signal on.

As described above, according to the twentieth aspect , the
In the invention of the eighth aspect , the C / N state when the phase is synchronized in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal, and the phase modulation according to the C / N state and the demodulation mode signal is performed. According to the reference phase corresponding to the system, phase correction is performed using a frame synchronization signal / TMCC signal period and a carrier synchronization auxiliary signal period that are minimum phase modulated in an initial state, and after phase synchronization, modulation of a main signal other than the period is performed. Phase correction is also performed during the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

In a twenty- first aspect based on the eighth aspect , a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means, and a transmission control signal ( BER detecting means for measuring a bit error rate before error correction of a TMCC signal, and detecting a state of C / N (carrier power / noise power) based on the bit error rate, and transmission control included in a frame synchronization signal. Error correction detection means for detecting a correction state of error correction processing of a signal (TMCC signal), signal period providing means for outputting a signal for giving a period of each phase modulation signal other than a synchronization signal period in a communication frame, and frame synchronization Based on the detection results of the determination means and the error correction detection means, and the signal and the timing signal output by the signal period providing means, the phase correction means Mode switching means for outputting a demodulation mode signal for switching the demodulation method according to the phase modulation method, detection results of the frame synchronization determination means, BER detection means and error correction detection means, and signal period output means. Based on the signal and the timing signal, when there is phase synchronization and error correction is completed,
If C / N is higher than a predetermined first threshold,
When the C / N is lower than a predetermined second threshold value, the gate signal that gives the entire period of the communication frame is a gate signal that gives the period of the signal subjected to the minimum phase modulation.
In other cases, a gate signal that gives a minimum phase modulation period and a predetermined modulation signal period is generated, and there is phase synchronization, and when error correction is not completed,
If C / N is higher than a predetermined first threshold,
When the C / N is lower than a predetermined second threshold value, a gate signal for providing the entire period of the communication frame is generated. A gate signal generation unit for generating a gate signal for giving a period, wherein the phase correction unit detects a phase difference due to minimum phase modulation in a synchronization signal period given by the timing signal when the error correction is not completed, and During a period other than the signal period, a phase error due to the phase modulation having the largest number of phases in the communication frame is detected. The correction operation is performed according to the period given by.

As described above, according to the twenty-first aspect , the twenty- first aspect
In the invention of the eighth aspect , the C / N state when the phase is synchronized in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal, and when the C / N is at a predetermined level, the communication is performed. In the frame, the phase error is corrected assuming that the maximum phase modulation is performed in all periods other than the synchronization signal period, and in the initial state according to the reference phase corresponding to the phase modulation method according to the demodulation mode signal, The phase correction is performed using the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period that are subjected to the minimum phase modulation, and after the phase synchronization, the phase correction is also performed in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

According to a twenty-second invention, in the ninth to fifteenth inventions, a frame synchronization determination means for inputting an output signal of the phase correction means and detecting phase synchronization in the phase correction means,
The output signal of the phase correction means is input and the C / N
Based on the C / N detection means for detecting the state of (carrier power / noise power), the detection results of the frame synchronization determination means and the C / N detection means, and the timing signal, there is phase synchronization and a predetermined A gate signal generating means for generating a gate signal for providing the entire period of the communication frame when the C / N is higher than the threshold value; otherwise, generating a gate signal for providing a synchronous signal period. The phase correction means detects a phase error due to the minimum phase modulation during the synchronization signal period given by the timing signal, and detects a phase error due to the phase modulation having the largest number of phases in the communication frame during a period other than the synchronization signal period. The correction operation is performed in accordance with the period given by.

According to a twenty- third aspect, in the ninth , eleventh , thirteenth, and fifteenth aspects, an output signal of the phase correcting means is input, and a frame synchronization determining means for detecting phase synchronization in the phase correcting means; C / N detection means for receiving the output signal of the correction means and detecting the C / N (carrier power / noise power) state of the received signal, and error correction of the transmission control signal (TMCC signal) included in the frame synchronization signal Error correction detection means for detecting a correction state of processing, signal period addition means for outputting a signal for giving a period of each phase modulation signal other than a synchronization signal period in a communication frame, and signal and timing output by the signal period addition means A demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with the phase modulation method based on the signal, Based on the detection results of the period determination means, the C / N detection means and the error correction detection means, and the signal and the timing signal output by the signal period giving means, when there is phase synchronization and error correction is completed, When the C / N is higher than the predetermined first threshold value, the gate signal for giving the entire period of the communication frame is set to the predetermined second threshold value.
If the C / N is low with respect to the threshold value, a gate signal giving the period of the signal subjected to the minimum phase modulation is given. Otherwise, the minimum phase modulation period and a predetermined modulation signal period are given. Generates a gate signal, has phase synchronization,
And a gate signal generating means for generating a gate signal for providing a synchronization signal period except when the error correction is completed, wherein the phase correction means detects a phase error by a phase modulation method according to a demodulation mode signal. The correction operation is performed according to the period given by the gate signal.

The twenty-fourth invention is directed to the tenth , twelfth and twelfth aspects.
In the fourteenth aspect , the output signal of the phase correction means is input, the frame synchronization determination means for detecting phase synchronization in the phase correction means, and the output signal of the phase correction means are input, and the C / N (carrier power / C / N detection means for detecting the state of noise power), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than a synchronization signal period in a communication frame, and a signal outputted by the signal period providing means Demodulation mode switching means for outputting a demodulation mode signal for switching the demodulation method in the phase correction means in accordance with the phase modulation method based on the phase signal and the timing signal, frame synchronization determination means, C / N detection means, and error correction detection Based on the detection result of the means and the signal and the timing signal output by the signal period providing means, if there is phase synchronization and error correction is completed. When the C / N is higher than the predetermined first threshold value, the gate signal for giving the entire period of the communication frame is set to have the C / N lower than the predetermined second threshold value. In the case, a gate signal giving the period of the signal subjected to the minimum phase modulation is generated, otherwise, a gate signal giving the minimum phase modulation period and a predetermined modulation signal period is generated, and there is phase synchronization, And a gate signal generating means for generating a gate signal for providing a synchronization signal period except when the error correction is completed, wherein the phase correction means detects a phase error by a phase modulation method according to a demodulation mode signal. The correction operation is performed according to the period given by the gate signal.

According to a twenty- fifth aspect, in the ninth , eleventh , thirteenth, and fifteenth aspects, a frame synchronization judging means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means, C / N detection means for receiving the output signal of the correction means and detecting the state of C / N (carrier power / noise power) of the received signal, and error correction of the transmission control signal (TMCC signal) included in the frame synchronization signal Error correction detection means for detecting a correction state of processing, signal period addition means for outputting a signal for giving a period of each phase modulation signal other than a synchronization signal period in a communication frame, and frame synchronization determination means and error correction detection means. Based on the detection result and the signal output from the signal period providing means and the timing signal, the demodulation method in the phase correction means is switched in accordance with the phase modulation method. A demodulation mode switching means for outputting a demodulation mode signal to obtain, on the basis of the frame synchronization determining means, the detection result of the C / N detection means and error correction detection means, and signal and timing signal whose period providing means for outputting,
In the case where the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value, a gate signal for giving the entire period of the communication frame is determined in advance. When C / N is lower than the second threshold value, a gate signal giving the period of the signal subjected to the minimum phase modulation is applied. Otherwise, the minimum phase modulation period and the predetermined modulation signal period are applied. In the case where phase synchronization is performed and error correction is not completed, and C / N is higher than a predetermined first threshold, a gate signal is generated. When the C / N is lower than a predetermined second threshold value, a gate signal that gives a synchronization signal period is generated. When there is no phase synchronization, a gate signal that gives a synchronization signal period is generated. Gate signal generating means for generating a signal Further comprising a phase correction means, if not completed error correction, it detects the phase difference by the minimum phase modulation by the synchronization signal period in which the timing signals provide,
During the period other than the synchronization signal period, the phase error due to the phase modulation having the largest number of phases in the communication frame is detected, and when the error correction is completed, the phase error is detected by the phase modulation method according to the demodulation mode signal, and then the gate is detected. The correction operation is performed according to the period given by the signal.

The twenty-sixth invention is directed to the tenth , twelfth, and twelfth aspects.
In the fourteenth aspect of the invention, the output signal of the phase correction means is input, the frame synchronization determination means for detecting phase synchronization in the phase correction means, and the output signal of the phase correction means are input, and the C / N (carrier power / C / N detection means for detecting a state of noise power, a signal period providing means for outputting a signal for giving a period of each phase modulation signal other than a synchronization signal period in a communication frame, frame synchronization determining means, and error correction detection. A demodulation mode switching unit that outputs a demodulation mode signal that switches a demodulation system in the phase correction unit in accordance with the phase modulation system, based on the detection result of the unit, and the signal and the timing signal output by the signal period providing unit; The detection results of the frame synchronization determining means, the C / N detecting means and the error correction detecting means, and the signals output by the signal period providing means and the timing A gate signal for giving the entire period of the communication frame when phase synchronization is performed based on the first signal and error correction is completed and C / N is higher than a predetermined first threshold value. When the C / N is lower than a predetermined second threshold value, a gate signal giving the period of the signal subjected to the minimum phase modulation is applied. When a gate signal that gives a predetermined modulation signal period is generated, phase synchronization is performed, and error correction is not completed, and C / N is higher than a predetermined first threshold value, When the C / N is lower than a predetermined second threshold value, a gate signal that provides a synchronization signal period is generated, and when there is no phase synchronization, a synchronization signal is generated. Generate a gate signal that gives a signal period A phase signal generation unit, wherein the phase correction unit detects a phase difference due to the minimum phase modulation in a synchronization signal period given by the timing signal when the error correction is not completed, and in a communication frame in a period other than the synchronization signal period. If the phase error due to the phase modulation with the largest number of phases is detected and the error correction is completed, the phase error based on the phase modulation method according to the demodulation mode signal is detected, and then the correction operation is performed according to the period given by the gate signal. It is characterized by performing.

In a twenty- seventh aspect based on the ninth to fifteenth aspects, a frame synchronization determining means for inputting an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means,
BER detection means for measuring a bit error rate of a transmission control signal (TMCC signal) included in a frame synchronization signal before error correction and detecting a state of C / N (carrier power / noise power) based on the bit error rate Based on the detection result of the frame synchronization determination means and the BER detection means, and based on the timing signal, if there is phase synchronization and C / N is higher than a predetermined threshold, the entire period of the communication frame is Gate signal generating means for generating a gate signal to be applied, and otherwise generating a gate signal for providing a synchronization signal period, wherein the phase correction means performs phase control by minimum phase modulation in the synchronization signal period provided by the timing signal. After detecting the error and detecting the phase error due to phase modulation with the largest number of phases in the communication frame other than the synchronization signal period,
The correction operation is performed according to the period given by the gate signal.

According to a twenty- eighth aspect based on the ninth , eleventh , thirteenth, and fifteenth aspects, a frame synchronization determination means for inputting an output signal of the phase correction means and detecting phase synchronization in the phase correction means, BER detection means for measuring a bit error rate before error correction of a transmission control signal (TMCC signal) included in the synchronization signal and detecting a state of C / N (carrier power / noise power) based on the bit error rate; ,
Error correction detecting means for detecting a correction state of an error correction process of a transmission control signal (TMCC signal) included in the frame synchronization signal, and a signal which gives a period of each phase modulation signal other than a synchronization signal period in a communication frame. A signal period providing unit, and a demodulation mode switching unit that outputs a demodulation mode signal that switches a demodulation system in the phase correction unit in accordance with the phase modulation system based on the signal and the timing signal output by the signal period providing unit; Based on the detection results of the frame synchronization determining means, the BER detecting means and the error correction detecting means, and the signal and the timing signal output by the signal period giving means, the phase synchronization is performed and the error correction is completed. If the C / N is higher than the predetermined first threshold, a gate signal for giving the entire period of the communication frame is determined in advance. When C / N is lower than the second threshold value, a gate signal giving the period of the signal subjected to the minimum phase modulation is applied. Otherwise, the minimum phase modulation period and the predetermined modulation signal period And a gate signal generating means for generating a gate signal for providing a synchronization signal period except when the phase correction is performed and error correction is completed. A phase error is detected by a phase modulation method according to a signal, and a correction operation is performed according to a period given by a gate signal.

A twenty- ninth aspect of the present invention is directed to the tenth , twelfth and
In the invention of the fourteenth aspect , a frame synchronization determining means for receiving an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means, and a bit error before error correction of a transmission control signal (TMCC signal) included in the frame synchronizing signal. BER detecting means for measuring a rate and detecting a state of C / N (carrier power / noise power) based on the bit error rate, and a signal which gives a period of each phase modulation signal other than a synchronization signal period in a communication frame. And a demodulation mode switch that outputs a demodulation mode signal that switches the demodulation method in the phase correction means in accordance with the phase modulation method based on the signal output from the signal period applying means and the timing signal. Means, frame synchronization determining means, BER detecting means and error correction detecting means, and signal period providing means. Based on the signal and the timing signal,
If phase synchronization is performed and error correction is completed, and C / N is higher than a predetermined first threshold, a gate signal that provides the entire period of the communication frame is determined in advance. When C / N is lower than the second threshold value, a gate signal giving the period of the signal subjected to the minimum phase modulation is applied. Otherwise, the minimum phase modulation period and the predetermined modulation signal period are applied. And a gate signal generating means for generating a gate signal for providing a synchronization signal period except when the phase correction is performed and error correction is completed. A phase error is detected by a phase modulation method according to a signal, and a correction operation is performed according to a period given by a gate signal.

According to a thirtieth aspect , in the ninth , eleventh , thirteenth, and fifteenth aspects, a frame synchronization determining means for receiving an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means, BER detection means for measuring a bit error rate before error correction of a transmission control signal (TMCC signal) included in the synchronization signal and detecting a state of C / N (carrier power / noise power) based on the bit error rate; ,
Error correction detecting means for detecting a correction state of an error correction process of a transmission control signal (TMCC signal) included in the frame synchronization signal, and a signal which gives a period of each phase modulation signal other than a synchronization signal period in a communication frame. Based on the detection results of the signal period providing means, the frame synchronization determining means and the error correction detecting means, and the signal and the timing signal output by the signal period providing means, the demodulation method in the phase correcting means corresponds to the phase modulation method. Mode switching means for outputting a demodulation mode signal to be switched over, and phase synchronization based on the detection results of the frame synchronization determination means, BER detection means and error correction detection means, and the signal and timing signal output by the signal period addition means. And when error correction is completed and C / N is higher than a predetermined first threshold value. If the gate signal applied to the entire period of the communication frame, C relative to the second threshold a predetermined
/ N is low, a gate signal giving the period of the signal subjected to the minimum phase modulation is generated; otherwise, a gate signal giving the minimum phase modulation period and a predetermined modulation signal period is generated, In the case where there is synchronization and the error correction has not been completed and the C / N is higher than a predetermined first threshold value, a gate signal giving the entire period of the communication frame is determined in advance. C for the second threshold
And a gate signal generating means for generating a gate signal for providing a synchronization signal period when / N is low, and a gate signal for generating a gate signal for providing a synchronization signal period when there is no phase synchronization. If the correction has not been completed,
In the synchronization signal period given by the timing signal, the phase difference due to the minimum phase modulation is detected, and in the period other than the synchronization signal period, the phase error due to the phase modulation having the largest number of phases in the communication frame is detected. After detecting a phase error by a phase modulation method according to a demodulation mode signal, a correction operation is performed according to a period given by a gate signal.

A thirty-first invention is directed to the tenth , twelfth, and twelfth aspects.
In the invention of the fourteenth aspect , a frame synchronization determining means for receiving an output signal of the phase correcting means and detecting phase synchronization in the phase correcting means, and a bit error before error correction of a transmission control signal (TMCC signal) included in the frame synchronizing signal. BER detecting means for measuring a rate and detecting a state of C / N (carrier power / noise power) based on the bit error rate, and a signal which gives a period of each phase modulation signal other than a synchronization signal period in a communication frame. The signal demodulation method in the phase correction means is performed based on the detection results of the frame synchronization determination means and the error correction detection means, and the signal and the timing signal output by the signal period addition means. Demodulation mode switching means for outputting a demodulation mode signal to be switched in accordance with Based on the detection result of the error correction detecting means, and the signal and the timing signal output by the signal period providing means, when there is phase synchronization and error correction has been completed, the predetermined first threshold value is set. On the other hand, when the C / N is high, the gate signal for giving the entire period of the communication frame is provided, and when the C / N is low with respect to the second predetermined threshold, the period of the signal subjected to the minimum phase modulation is provided. A gate signal that gives a minimum phase modulation period and a gate signal that gives a predetermined modulation signal period, otherwise, when there is phase synchronization, and error correction has not been completed, When the C / N is higher than the predetermined first threshold value, the gate signal for giving the entire period of the communication frame is synchronized. When the C / N is lower than the predetermined second threshold value, the gate signal is synchronized. Gate signal giving signal period Generate, if there is no phase synchronization further comprises a gate signal generating means for generating a gate signal to provide a synchronizing signal period,
When the error correction is not completed, the phase correction means detects a phase difference due to the minimum phase modulation during the synchronization signal period given by the timing signal, and detects a phase difference due to the largest number of phases in the communication frame during a period other than the synchronization signal period. When an error is detected and error correction is completed, a phase error is detected by a phase modulation method according to a demodulation mode signal, and then a correction operation is performed according to a period given by a gate signal.

As described above, the twenty -second to thirty-first inventions
This is a combination of the ninth to fifteenth inventions and the sixteenth to twenty-first inventions. Therefore, according to the twenty -second to thirty-first inventions, carrier synchronization can be performed at high speed and stably even in the low C / N state. And the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, and the receiving performance can be improved.

In a thirty- second aspect based on the eighth to thirty-first aspects, the frame synchronization detecting means discriminates the transmitted signal from the delay detecting means for delay-detecting the signal and the phase-modulated signal subjected to the delay detection. One or more phase discriminating means, and a matching means for performing pattern matching between an output of one or more phase discriminating means and a frame synchronization signal, wherein the one or more phase discriminating means converts the frame synchronization signal into one or more. Having a phase identification area corresponding to the phase modulation to be transmitted,
The two or more phase identification areas are provided in parallel by applying different phase rotations, and the matching means performs pattern matching on each output of the phase identification means having different phase rotation amounts of the phase identification areas. Features.

In a thirty- third aspect based on the eighth to thirty-first aspects, the frame synchronization detecting means comprises: a delay detecting means for delay-detecting the signal; Rotation means, for each output of the plurality of phase rotation means, a phase identification means for performing phase identification, and a matching means for performing pattern matching between the output of the phase identification means and the frame synchronization signal, the phase identification means Has a phase identification region corresponding to the phase modulation in which the frame synchronization signal is transmitted, identifies the signal transmitted for each phase modulation signal that is differentially detected and given a different phase rotation, And pattern matching is performed on the output of each of the phase identification means.

In a thirty- fourth aspect based on the eighth to thirty-first aspects, the frame synchronization detecting means includes: a delay detecting means for delay-detecting the signal; Identification means, identification phase rotation means for rotating the identification phase of the phase identification means, and collation means for pattern collating the output of the phase identification means with the frame synchronization signal, wherein the phase identification means transmits the frame synchronization signal It has a phase identification area corresponding to the phase modulation, and the phase rotation means until a frame synchronization signal is detected by the matching means.
It is characterized in that the phase of the phase identification area in the phase identification means is rotated.

In a thirty- fifth aspect based on the eighth to thirty-first aspects, the frame synchronization detecting means comprises: a delay detecting means for delay-detecting the signal; a phase rotating means for applying a phase rotation to the delayed detected signal; Phase identification means for identifying the signal transmitted from the phase-modulated signal that has been input and delayed detection, and matching means for comparing the output of the phase identification means with the pattern of the frame synchronization signal. Until a synchronization signal is detected, the phase of the phase rotation means is rotated.

As described above, the thirty- second to thirty -fifth aspects of the invention
It shows a typical configuration of the eighth to thirty-first frame synchronization detecting means. As a result, even when the input frequency error is large, it is possible to eliminate the malfunction of frame synchronization detection by delay detection and perform carrier synchronization.

In a thirty- sixth aspect based on the eighth to thirty-fifth aspects, there is further provided a band limiting filter for inputting an output signal of the frequency correcting means, performing band limiting on the output signal, and then outputting to the phase correcting means. The frame synchronization detecting means comprises:
An output signal of any one of the frequency correction means, the band limiting filter, and the phase correction means is input, and a frame head position is detected.

As described above, the thirty- sixth aspect of the present invention relates to the eighth to eighth aspects.
In the thirty-fifth aspect , a band-limiting filter for spectrum-shaping the phase-modulated signal output from the frequency correction means is further added to the configuration. Therefore, the effects of the thirty-seventh aspect are the same as those of the ninth to thirty-sixth aspects, respectively.

According to a thirty-seventh aspect based on the eighth to thirty- sixth aspects, the carrier synchronization auxiliary signal is applied to the modulated signal to be the next packet with respect to the time division multiplexed position in the communication frame. When information for identifying modulation is superimposed, information detecting means for detecting a period of a signal subjected to minimum phase modulation based on the information and outputting a signal giving the minimum phase modulation period to timing generation means In a further aspect, the timing generation means generates a timing signal that gives a minimum phase modulation period in addition to the synchronization signal period.

As described above, according to the thirty-seventh aspect , the thirty- seventh aspect
In the eighth to thirty- sixth aspects, among the time-division multiplexed phase modulated signals, in addition to the minimum phase modulated signal including the carrier synchronization auxiliary signal dispersedly arranged in the packet, a main signal subjected to the minimum phase modulation is also included. To perform frequency correction and phase correction (carrier wave reproduction). As a result, carrier synchronization can be performed quickly and stably even in the low C / N state.

In a thirty- eighth aspect based on the twelfth to fifteenth aspects, when the frequency at which the pseudo-synchronization occurs is fg [Hz], the frequency step means includes (-1) ^n-1 × n × f
The frequency input to the phase correction means is shifted stepwise based on g [Hz] (n = 1, 2,...).

As described above, according to the thirty- eighth aspect, the thirty- eighth aspect
In the twelfth to fifteenth aspects, the frequency step means includes:
The frequency fg at which pseudo-synchronization occurs is defined as a step unit,
The frequency is shifted so as to increase in order of positive and negative. Thereby, even in the case of the pseudo synchronization, the normal synchronization can be finally performed by repeating the above step operation.

According to a thirty-ninth aspect , a carrier synchronization auxiliary signal which has been phase-modulated using a phase modulation having the smallest number of phases in a communication frame (hereinafter, referred to as a minimum phase modulation) together with a plurality of phase-modulated signals. in so that dispersed in the time interval, when a division multiplexed demodulation method of the communication frame, by detecting the synchronizing signal of the communication frame,
Detecting a frame start position, the frame head
A step of generating a timing signal that provides at least a period of the carrier synchronization auxiliary signal (hereinafter, referred to as a synchronization signal period) in the period in which the minimum phase modulation is performed based on the position, and a timing signal. Use period multiple times
The frequency correction operation and position according to the minimum phase modulation
Performing a phase correction operation.

As described above, according to the thirty-ninth aspect , of the time-division multiplexed phase-modulated signals, the frequency correction and the frequency-correction are performed by using the minimum phase-modulated signal including the carrier synchronization auxiliary signal dispersedly arranged in the packet. By performing the phase correction (regeneration of carrier wave), carrier synchronization can be performed at high speed and stably even in the low C / N state. Further, even when the input frequency error is large, it is possible to eliminate the malfunction of the frame synchronization detection by the delay detection and perform the carrier synchronization.

[0080] A fortieth aspect of the present invention is based on the thirty-ninth aspect , wherein:
A step of detecting a frequency pull-in state and determining whether or not the frequency is a frequency at which pseudo-synchronization occurs; And further provided.

According to the fortieth aspect , as described above,
In the invention of the thirty-ninth aspect , the frequency lock-in state is detected, and after the frequency correction is performed to a frequency at which the phase correction operation is not pseudo-synchronized in the frequency correction operation, the phase correction operation is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase correction operation in a frequency pull-in process or the like by the frequency correction operation.

[0082] A forty-first aspect is a method according to the thirty-ninth aspect , wherein
Detecting a state of phase synchronization during the period of the carrier synchronization auxiliary signal; detecting a correction state of an error correction process of a transmission control signal (TMCC signal) included in the frame synchronization signal; The method further includes a step of determining whether or not a pseudo synchronization is performed based on the synchronization state and the error correction state of the TMCC signal period. .

As described above, according to the forty-first aspect , the forty- first aspect
According to the thirty-ninth aspect , detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of the possibility of error correction of the TMCC signal are performed, and whether or not normal synchronization is determined based on the detection result. Then, in the case of the pseudo synchronization, the phase correction operation is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase correction operation in a frequency pull-in process or the like by the frequency correction operation.

The forty-second invention is based on the thirty-ninth invention, wherein
Detecting a phase synchronization state during the period of the carrier synchronization auxiliary signal, detecting a phase synchronization state during the period of the transmission control signal (TMCC signal) included in the frame synchronization signal, The method further includes a step of determining whether or not a pseudo-synchronization is performed based on the synchronization state and the phase-synchronization state of the TMCC signal period. .

As described above, according to the forty- second aspect, the
In the invention of the thirty-ninth aspect, the phase synchronization is detected during the period of the carrier synchronization auxiliary signal and the phase synchronization is detected during the period of the frame synchronization signal / TMCC signal, and it is determined whether or not the synchronization is normal based on the detection result. Then, in the case of the pseudo synchronization, the phase correction operation is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase correction operation in a frequency pull-in process or the like by the frequency correction operation.

[0086] invention of a 43 Aspect 39,
Detecting a state of phase synchronization during the period of the carrier synchronization auxiliary signal; detecting a correction state of an error correction process of a transmission control signal (TMCC signal) included in the frame synchronization signal; A step of judging whether or not a pseudo-synchronization is performed based on the synchronization state and the error correction state of the TMCC signal period. Further comprising the step of:

As described above, according to the forty- third aspect,
According to the thirty-ninth aspect , detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of the possibility of error correction of the TMCC signal are performed, and whether or not normal synchronization is determined based on the detection result. In the case of pseudo synchronization, the frequency of the frequency correction operation is controlled so that normal synchronization can be performed by the phase correction operation. This makes it possible to avoid pseudo-synchronization in the phase correction operation in a frequency pull-in process or the like by the frequency correction operation.

A forty- fourth aspect of the present invention is the thirty-ninth aspect , wherein:
Detecting a phase synchronization state during the period of the carrier synchronization auxiliary signal, detecting a phase synchronization state during the period of the transmission control signal (TMCC signal) included in the frame synchronization signal, A step of determining whether or not a pseudo-synchronization is performed based on the synchronization state and a phase-synchronization state of the TMCC signal period; Further comprising the step of:

As described above, according to the forty- fourth aspect, the forty- fourth aspect
In the invention of the thirty-ninth aspect, the phase synchronization is detected during the period of the carrier synchronization auxiliary signal and the phase synchronization is detected during the period of the frame synchronization signal / TMCC signal, and it is determined whether or not the synchronization is normal based on the detection result. In the case of pseudo synchronization, the frequency of the frequency correction operation is controlled so that normal synchronization can be performed by the phase correction operation. This allows
In the frequency pull-in process by the frequency correction operation,
It is possible to avoid pseudo synchronization in the phase correction operation.

A forty- fifth aspect of the present invention is based on the forty- third aspect,
A step of detecting a frequency pull-in state and determining whether or not the frequency is a frequency at which pseudo-synchronization occurs; And further provided.

[0091] invention of a 46 Aspect 44,
A step of detecting a frequency pull-in state and determining whether or not the frequency is a frequency at which pseudo-synchronization occurs; And further provided.

[0092] As described above, according to the invention of a 45 and 46, in the invention of a 43 and 44, further performs detection of frequency locking state, the frequency until the phase correction operation is not pseudo sync in the frequency correction operation After the frequency correction is performed, the phase correction operation is initialized and restarted. This makes it possible to avoid pseudo-synchronization in the phase correction operation in a frequency pull-in process or the like by the frequency correction operation.

The forty- seventh invention is based on the thirty-ninth invention, wherein
Detecting the phase synchronization state;
Detecting a state of N (carrier power / noise power); and phase synchronization, and if C / N is higher than a predetermined threshold, detects a phase error due to minimum phase modulation in a synchronization signal period. And detecting a phase error due to phase modulation having the largest number of phases in the communication frame during a period other than the synchronization signal period of the communication frame, and then performing a phase correction operation in the entire period of the communication frame.

According to the forty- seventh aspect, as described above,
In the invention of the thirty-ninth aspect , the C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected, and when the C / N is at a predetermined level, the C / N state is also determined for the main signal period of the communication frame. The phase error is corrected assuming that the maximum phase modulation has been performed. As a result, carrier synchronization can be performed stably at high speed even in the low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

[0095] A forty-eighth invention provides the thirty-ninth invention, wherein
Detecting the phase synchronization state;
N (carrier power / noise power) state, and a transmission control signal (TMC) included in the frame synchronization signal.
A step of detecting the correction state of the error correction processing of the C signal) and a case where the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting the phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and the second predetermined threshold value, A phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed, and if the C / N is lower than the second threshold value, the synchronization signal period and the minimum phase Performing a phase correction operation after detecting a phase error due to the minimum phase modulation during the modulation period.

As described above, according to the forty- eighth aspect,
In the invention of the thirty-ninth aspect , the C / N state when the phase is synchronized during the minimum phase modulation signal period is detected, and the C / N state and the reference phase corresponding to the phase modulation method according to the demodulation mode signal are initially determined. In the state (1), the phase correction is performed using the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period that are subjected to the minimum phase modulation. After the phase synchronization, the phase correction is performed also in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

[0097] A forty- ninth aspect is the thirty-ninth aspect , wherein
Detecting the phase synchronization state;
N (carrier power / noise power) state, and a transmission control signal (TMC) included in the frame synchronization signal.
A step of detecting the correction state of the error correction processing of the C signal), a case where phase synchronization is performed and error correction is completed, and a case where C / N is higher than a predetermined first threshold value. Detecting the phase error due to the corresponding phase modulation during the entire period of the communication frame, and if the C / N is between the first threshold value and the predetermined second threshold value, When the phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation having the largest number of phases (hereinafter referred to as the maximum phase modulation) is performed, and the C / N is lower than the second threshold value Is a step of performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and a period in which the minimum phase modulation is performed, and a case where there is phase synchronization and error correction is not completed. So, When the C / N is high with respect to the threshold value of 1, after detecting the phase error due to the minimum phase modulation during the synchronization signal period, and after detecting the phase error due to the maximum phase modulation within the communication frame during the period other than the synchronization signal period of the communication frame. And performing a phase correction operation.

As described above, according to the forty- ninth aspect, the forty- ninth aspect
In the invention of the thirty-ninth aspect , a C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected, and when the C / N is at a predetermined level, a portion of the communication frame other than the synchronization signal period is included. The phase error is corrected by assuming that the maximum phase modulation is performed in the entire period, and the frame synchronization signal / minimum phase modulated in the initial state according to the reference phase corresponding to the phase modulation method according to the demodulation mode signal. The phase correction is performed using the TMCC signal period and the carrier synchronization auxiliary signal period, and after the phase synchronization, the phase correction is also performed in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

[0099] In a fiftieth aspect , in the thirty-ninth aspect ,
Detecting the state of phase synchronization, measuring the bit error rate before error correction of a transmission control signal (TMCC signal) included in the frame synchronization signal, and performing C / N (carrier power / noise) based on the bit error rate. Power detection) and phase synchronization, and if the C / N is higher than a predetermined threshold, a phase error due to minimum phase modulation is detected during the synchronization signal period to synchronize the communication frame. Performing a phase correction operation after detecting a phase error due to phase modulation having the largest number of phases in the communication frame during periods other than the signal period.

As described above, according to the fiftieth aspect , the tenth aspect
In the invention of the thirty-ninth aspect , the C / N state when phase synchronization is performed in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal. The phase error is corrected assuming that the maximum phase modulation is performed also for the main signal period of the frame. As a result, carrier synchronization can be performed stably at high speed even in the low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

The fifty-first invention is based on the thirty-ninth invention, wherein
Detecting the state of phase synchronization, measuring the bit error rate before error correction of a transmission control signal (TMCC signal) included in the frame synchronization signal, and performing C / N (carrier power / noise) based on the bit error rate. Power detection), a step of detecting a correction state of an error correction process of a transmission control signal (TMCC signal) included in the frame synchronization signal, and a step of performing phase synchronization and completing error correction. Therefore, C /
When N is high, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and when C / N is between the first threshold value and a predetermined second threshold value, A phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed in the communication frame, and C / C is determined for the second threshold value.
If N is low, the method further includes the step of detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and then performing a phase correction operation.

As described above, according to the fifty- first aspect, the fifth aspect
In the invention of the thirty-ninth aspect , the C / N state when the phase is synchronized in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal, and the phase modulation according to the C / N state and the demodulation mode signal is performed. According to the reference phase corresponding to the system, phase correction is performed using a frame synchronization signal / TMCC signal period and a carrier synchronization auxiliary signal period that are minimum phase modulated in an initial state, and after phase synchronization, modulation of a main signal other than the period is performed. Phase correction is also performed during the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

A fifty-second invention is based on the thirty-ninth invention, wherein
Detecting the state of phase synchronization, measuring the bit error rate before error correction of a transmission control signal (TMCC signal) included in the frame synchronization signal, and performing C / N (carrier power / noise) based on the bit error rate. Power detection), a step of detecting a correction state of an error correction process of a transmission control signal (TMCC signal) included in the frame synchronization signal, and a step of performing phase synchronization and completing error correction. Therefore, C /
When N is high, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and when C / N is between the first threshold value and a predetermined second threshold value, In a communication frame, a phase error due to the corresponding phase modulation is detected in a period other than a period in which phase modulation having the largest number of phases (hereinafter, referred to as maximum phase modulation) is performed,
When the C / N is lower than the second threshold value, detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and then performing a phase correction operation; In the case where there is synchronization and error correction is not completed, C / C
If N is high, detecting a phase error due to minimum phase modulation during the synchronization signal period, detecting a phase error due to maximum phase modulation within the communication frame during periods other than the synchronization signal period of the communication frame, and then performing a phase correction operation. Further prepare.

According to the fifty-second invention, as described above,
In the invention of the thirty-ninth aspect , the C / N state when the phase is synchronized in the minimum phase modulation signal period is detected based on the bit error rate of the TMCC signal, and when the C / N is at a predetermined level, In the frame, the phase error is corrected assuming that the maximum phase modulation is performed in all periods other than the synchronization signal period, and in the initial state according to the reference phase corresponding to the phase modulation method according to the demodulation mode signal, The phase correction is performed using the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period that are subjected to the minimum phase modulation, and after the phase synchronization, the phase correction is also performed in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, thereby improving the reception performance.

[0105] invention of a 53 Aspect 40 to 46, and detecting and detecting a phase synchronization state, the state of the received signal C / N (carrier power / noise power), the phase If there is synchronization and the C / N is higher than a predetermined threshold value, a phase error due to minimum phase modulation is detected in the synchronization signal period, and the number of phases in the communication frame is not within the synchronization signal period of the communication frame. Performing a phase correction operation after detecting the most phase error due to phase modulation.

The fifty- fourth invention is directed to the forty- fourth, forty- second and forty- fourth aspects.
In the forty- sixth aspect, a step of detecting a phase synchronization state, a step of detecting a C / N (carrier power / noise power) state of a received signal, and a transmission control signal (TMCC signal) included in a frame synchronization signal A) detecting the correction state of the error correction processing, and performing phase synchronization and completing error correction.
If the C / N is high with respect to the threshold value, the phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the phase error between the first threshold value and the predetermined second threshold value , The phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed in the communication frame, and the second error is detected.
If the C / N is lower than the threshold value, the phase correction operation is performed after detecting the phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed.

The fifty- fifth invention is directed to the forty-first , forty- third and forty- third embodiments.
In the forty- fifth aspect, the step of detecting the state of phase synchronization, the step of detecting the state of C / N (carrier power / noise power) of the received signal, and the step of performing phase synchronization and completing error correction If the C / N is higher than a predetermined first threshold, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the first threshold and the predetermined second threshold are detected. C / between a threshold of 2
If N, the phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed in the communication frame, and the C / N is lower than the second threshold value. In the case, the method further includes the step of performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed.

The fifty-sixth invention is directed to the forty- fourth, forty- second and forty- fourth aspects.
In the forty- sixth aspect, a step of detecting a phase synchronization state, a step of detecting a C / N (carrier power / noise power) state of a received signal, and a transmission control signal (TMCC signal) included in a frame synchronization signal A) detecting the correction state of the error correction processing, and performing phase synchronization and completing error correction.
If the C / N is high with respect to the threshold value, the phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the phase error between the first threshold value and the predetermined second threshold value is detected. , The phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation having the largest number of phases (hereinafter, referred to as the maximum phase modulation) is performed in the communication frame, and the second error is detected. C / N for the threshold of
Is low, a phase correction operation is performed after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and there is a phase synchronization operation and error correction is completed. If there is no C / N with respect to the first threshold value, the phase error due to the minimum phase modulation is detected during the synchronization signal period, and the maximum phase modulation within the communication frame is detected during periods other than the synchronization signal period of the communication frame. Performing a phase correction operation after detecting the phase error due to the above.

The fifty-seventh invention is directed to the forty-first , forty- third, and forty- third.
In the forty- fifth aspect, the step of detecting the state of phase synchronization, the step of detecting the state of C / N (carrier power / noise power) of the received signal, and the step of performing phase synchronization and completing error correction If the C / N is higher than a predetermined first threshold, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the first threshold and the predetermined second threshold are detected. C / between a threshold of 2
If N, a phase error due to the corresponding phase modulation is detected in a period other than the period in which phase modulation having the largest number of phases (hereinafter referred to as maximum phase modulation) is performed in the communication frame, and the second threshold is detected. If the C / N is lower than the value, a phase correction operation is performed after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and there is a phase synchronization; If error correction is not completed and C / N is higher than the first threshold, a phase error due to minimum phase modulation is detected in the synchronization signal period, and communication is performed in periods other than the synchronization signal period of the communication frame. Performing a phase correction operation after detecting a phase error due to maximum phase modulation in the frame.

[0110] invention of a 58 Aspect 40 to 46, and detecting a phase synchronization state, the bit error rate before error correction of the transmission control signal (TMCC signal) included in the frame synchronization signal Measuring and detecting the state of C / N (carrier power / noise power) based on the bit error rate; and if there is phase synchronization and C / N is higher than a predetermined threshold, Detecting a phase error due to the minimum phase modulation in the synchronization signal period, detecting a phase error due to the phase modulation having the largest number of phases in the communication frame in a period other than the synchronization signal period of the communication frame, and then performing a phase correction operation. Prepare.

[0111] invention of a 59 second 40, third 42, 44
In the forty- sixth aspect, a step of detecting a state of phase synchronization, a step of measuring a bit error rate before error correction of a transmission control signal (TMCC signal) included in the frame synchronization signal, and calculating C based on the bit error rate / N (carrier power /
Noise detection), a step of detecting a correction state of an error correction process of a transmission control signal (TMCC signal) included in the frame synchronization signal, and a step in which phase synchronization is performed and error correction is completed. When the C / N is higher than a predetermined first threshold value, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the first threshold value and the predetermined threshold value are detected. If the C / N is between the second threshold and the second threshold, the phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed in the communication frame, and If the C / N is lower than the threshold value of 2, the phase correction operation is performed after detecting the phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed. Provided.

The sixtieth invention is directed to the forty-first , forty- third and forty- third embodiments.
45. The method according to claim 45 , wherein the step of detecting a state of the phase synchronization and the transmission control signal (TM) included in the frame synchronization signal are performed.
Measuring the bit error rate of the CC signal before error correction, detecting the state of C / N (carrier power / noise power) based on the bit error rate, and performing phase synchronization and performing error correction. Completion is complete and the first
If the C / N is high with respect to the threshold value, the phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the phase error between the first threshold value and the predetermined second threshold value , The phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed in the communication frame, and the second error is detected.
If the C / N is lower than the threshold value, the phase correction operation is performed after detecting the phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed.

The sixty-first invention is based on the forty- fourth, forty- second, and forty- fourth aspects.
In the forty- sixth aspect, a step of detecting a state of phase synchronization, a step of measuring a bit error rate before error correction of a transmission control signal (TMCC signal) included in the frame synchronization signal, and calculating C based on the bit error rate / N (carrier power /
Noise detection), a step of detecting a correction state of an error correction process of a transmission control signal (TMCC signal) included in the frame synchronization signal, and a step in which phase synchronization is performed and error correction is completed. When the C / N is higher than a predetermined first threshold value, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the first threshold value and the predetermined threshold value are detected. When the C / N is between the second threshold value and the second threshold value, the corresponding phase modulation is performed in a period other than the period in which phase modulation having the largest number of phases (hereinafter, referred to as maximum phase modulation) is performed in the communication frame. When the phase error is detected and the C / N is lower than the second threshold value, after detecting the phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, the phase complement is detected. The step of performing the operation, the case where there is phase synchronization and the error correction is not completed, and if the C / N is higher than the first threshold value, the phase error due to the minimum phase modulation in the synchronization signal period And performing a phase correction operation after detecting a phase error due to the maximum phase modulation in the communication frame during a period other than the synchronization signal period of the communication frame.

The 62nd invention is the 41st , 43rd and 43rd inventions
45. The method according to claim 45 , wherein the step of detecting a state of the phase synchronization and the transmission control signal (TM) included in the frame synchronization signal are performed.
Measuring the bit error rate of the CC signal before error correction, detecting the state of C / N (carrier power / noise power) based on the bit error rate, and performing phase synchronization and performing error correction. Completion is complete and the first
If the C / N is high with respect to the threshold value, the phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the phase error between the first threshold value and the predetermined second threshold value is detected. , The phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation having the largest number of phases (hereinafter, referred to as the maximum phase modulation) is performed in the communication frame, and the second error is detected. C / N for the threshold of
Is low, a phase correction operation is performed after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and there is a phase synchronization operation and error correction is completed. If there is no C / N with respect to the first threshold value, the phase error due to the minimum phase modulation is detected during the synchronization signal period, and the maximum phase modulation within the communication frame is detected during periods other than the synchronization signal period of the communication frame. Performing a phase correction operation after detecting the phase error due to the above.

As described above, the 53rd to 62nd inventions
This is a combination of each of the fortieth to forty -sixth aspects and the forty -seventh to fifty- second aspects . Therefore, the 53rd to 62nd
According to the invention, carrier synchronization can be performed stably at high speed even in the low C / N state, and pseudo-synchronization in the phase correction operation can be avoided in the frequency pull-in process by the frequency correction operation, and The effect of the phase jitter of the demodulated signal during the period of the main signal can be reduced, and the reception performance can be improved.

[0116] invention of a 63 Aspect 39, second 62, phase carrier synchronization auxiliary signal, are applied to the modulation signal as a next packet relative positions are time division multiplexed within a communication frame When the information for identifying the modulation is superimposed, detects the period of the signal on which the minimum phase modulation is performed based on the information, and outputs a signal providing the minimum phase modulation period to a step of generating a timing signal, The step of generating the timing signal includes, in addition to the synchronization signal period,
A timing signal for providing a minimum phase modulation period is generated.

As described above, according to the 63rd aspect , the
In 39 to 62nd invention, among the phase-modulated signal is time-division multiplexed, in addition to the minimum phase-modulated signal containing a dispersion arranged carrier synchronization auxiliary signal in packets, also the main signal minimum phase modulation is made To perform frequency correction and phase correction (carrier wave reproduction). As a result, carrier synchronization can be performed quickly and stably even in the low C / N state.

[0118] invention of a 64 Aspect 43 to 46, the step of varying the frequency stepwise, when the frequency of the pseudo synchronization occurs was fg [Hz], (-
^{1) n-1 × n ×} fg [Hz] (n = 1,2, ...) , characterized in that the shifting stepwise the frequency of performing the phase correction operation based on.

As described above, according to the sixty- fourth aspect, the fourteenth aspect
In the thirty -sixth to forty- sixth aspects, the step of changing the frequency stepwise shifts the frequency in such a manner that the frequency fg at which the pseudo-synchronization occurs is incremented in the order of positive and negative alternately. Thereby, even in the case of the pseudo synchronization, the normal synchronization can be finally performed by repeating the above step operation.

[0120]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention uses a BPSK including a carrier synchronization auxiliary signal dispersedly arranged in a packet among phase-modulated signals that are time-division multiplexed, and is fast and stable even in a low C / N state. And a modulation / demodulation device and method that enable efficient carrier synchronization. Hereinafter, a modulation device and method (transmission system) and a demodulation device and method (reception system) will be described in order for each embodiment of the present invention.

(1) Transmission System FIG. 1 is a block diagram showing a configuration of a modulation device according to an embodiment of the present invention, corresponding to claims 1, 2, 4, and 5. In FIG. 1, a modulation device according to one embodiment of the present invention includes a frame synchronization signal / TMCC signal
S packet synthesizer 12 and TMCC error correction encoder 1
3, a first error correction encoding unit 14, a second error correction encoding unit 15, a first BPSK mapping unit 16,
A BPSK / QPSK mapping unit 17, an 8PSK mapping unit 18, a multiplexing / quadrature modulation unit 19, a synchronization auxiliary signal generation unit 20, and a second BPSK mapping unit 21 are provided. FIG. 2 is a diagram illustrating an example of a communication frame generated in the modulation device according to the embodiment of the present invention. FIG. 3 is a block diagram showing an example of the configuration of the multiplexing / quadrature modulation unit 19 in FIG. Hereinafter, an operation performed by the modulation device according to the embodiment of the present invention will be described.

Frame synchronization signal / TMCC signal generator 1
1 generates a frame synchronization signal / TMCC signal based on the input TMCC information. This frame sync signal /
After the TMCC signal is subjected to error correction coding in the TMCC error correction coding unit 13, the BPSK mapping unit 1
6 is input. The BPSK mapping section 16 maps the input frame synchronization signal and TMCC signal to a BPSK code arrangement (see FIG. 79A), and outputs the result to the multiplexing / quadrature modulation section 19.

The TS packet synthesizing unit 12 synthesizes a plurality of input MPEG-TS packets (see FIG. 80 (a)) and is composed of a packet group of a low-layer signal and a packet group of a high-layer signal. A frame in which the total number of packets has a constant value (see FIG. 80B) is generated. In this frame, the packet group of the low-layer signal is subjected to error correction coding in the first error correction coding unit 14 and then BPSK.
/ QPSK mapping section 17. BPSK /
The QPSK mapping unit 17 converts the input low-layer signal into
It is mapped to a BPSK code arrangement (see FIG. 79A) or a QPSK code arrangement (see FIG. 79B), and is output to the multiplexing / orthogonal modulation unit 19. On the other hand, among the above-mentioned frames, the packet group of the high-layer signal is subjected to error correction encoding in the second error correction encoding unit 15,
It is input to the 8PSK mapping unit 18. The 8PSK mapping section 18 maps the input high-layer signal to a code arrangement of 8PSK (see FIG. 79 (c)), and outputs it to the multiplexing / quadrature modulation section 19.

The synchronization auxiliary signal generation section 20 generates a signal (hereinafter, abbreviated as a carrier synchronization auxiliary signal) for assisting carrier synchronization in a demodulation device described later. The second BPSK mapping unit 21 includes a synchronization auxiliary signal generation unit 20
After inputting the carrier synchronization auxiliary signal generated by, and mapping it to the BPSK code arrangement (see FIG. 79 (a)),
Output to the multiplexing / quadrature modulator 19. As described above, the mapping of the BPSK to the carrier synchronization auxiliary signal is performed as follows.
BP out of a plurality of time-division multiplexed phase modulations
This is to enable carrier wave reproduction by the SK portion.

The multiplexing / orthogonal modulator 19 time-division multiplexes the signals input from the respective mapping units in the order shown in FIG. 2 to generate a communication frame, and then performs orthogonal modulation to output. Here, as can be seen from FIG. 2, the multiplexing / quadrature modulation unit 19 receives the BPSK-applied frame synchronization signal and the TMCC signal, the 8PSK-applied higher-layer signal packet group, and BPSK or QPSK. And time-division multiplexing (insertion) such that the BPSK-modulated carrier synchronization auxiliary signal is dispersed in the packet which is the minimum unit for switching the modulation method. To generate a communication frame.

In this time division multiplexing, for example, using a circuit as shown in FIG. 3, a gate signal for controlling the insertion timing of each signal is generated from an output signal of a frame counter for counting the number of symbols in one frame, What is necessary is just to perform each switch by switching. As will be described in the demodulation device described later, the carrier synchronization auxiliary signal is inserted continuously for two or more symbols so as to enable delay detection. Further, in order to improve the demodulation characteristics, the insertion period of the carrier synchronization auxiliary signal is set as short as possible.
It is preferable that the number is about 0 symbol or less.

As described above, according to the modulation device of one embodiment of the present invention, the signal for assisting carrier synchronization in the demodulation device is modulated by BPSK which is strong against the low C / N state, and is included in the packet. It outputs the communication frame that has been dispersed and inserted. Thereby, in the demodulation device, low C / N
Even in this state, carrier synchronization can be performed at high speed and stably using the carrier synchronization auxiliary signal of BPSK dispersed in the packet.

(2) Reception system Next, a demodulation device and a method for demodulating a communication frame generated by the modulation device according to one embodiment of the present invention will be described below in order. In the following description, the demodulation device based on the first embodiment is the
The eighth to eighth embodiments are demodulation devices that further avoid pseudo synchronization with respect to the first embodiment, and the ninth to fourteenth embodiments are
This is a demodulation device in which the phase noise is further reduced from the first embodiment.

(First Embodiment) FIG. 4 is a block diagram showing a configuration of a demodulation device according to a first embodiment of the present invention, corresponding to claims 7, 8 , 36, and 39 . 4, the demodulation device according to the first embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, a phase correction unit 34, a frame synchronization detection unit 35, and a timing generation unit 36. , A first error correction unit 37, a second error correction unit 38, and the video decoder 3.
9, a TMCC decoder 40, and a BER measuring unit 41. The frequency correction unit 32 includes a frequency error detection unit 321, a frequency error holding unit 322, a numerical control oscillation unit 323, and a complex multiplication unit 324. Phase correction unit 3
4 is a phase error detection unit 341 and a phase error holding unit 342
, A numerical control oscillator 343, and a complex multiplier 344. In FIG. 4, signal lines indicated by bold lines and “/ 2” indicate signal lines of signals expressed in a complex manner (hereinafter, the same applies to each drawing).

First, an outline of the demodulation device according to the first embodiment will be described. The quadrature detection unit 31 demodulates each PSK modulation signal in the input communication frame by quadrature detection using a local oscillation signal of a fixed frequency, and outputs an equalized low band signal of the in-phase component (I) and the quadrature component (Q). Output. Frequency correction unit 32
Receives a signal output from the quadrature detector 31 and corrects a frequency shift caused by a frequency shift of a frequency converter (not shown) or the like in the satellite antenna based on a timing signal received from the timing generator 36.

Each component of the frequency correction unit 32 will be briefly described. The frequency error detection unit 321 receives the signal output from the band-limiting filter 33, performs delay detection, and detects a frequency error. The frequency error holding unit 322 averages the frequency errors in the BPSK period among the frequency errors detected by the frequency error detection unit 321 according to the output signal from the timing generation unit 36. The numerical control oscillator 323 performs a numerical operation on the averaged signal output from the frequency error holding unit 322 and outputs an oscillation signal. The complex multiplication unit 324 performs a complex multiplication of the signal output from the quadrature detection unit 31 and the signal output from the numerical control oscillation unit 323 to cancel the frequency error.

The band limiting filter 33 is used to
2 is input and the spectrum of each PSK signal is shaped. The frame synchronization detecting section 35 receives the signal output from the band limiting filter 33, and performs B detection by delay detection.
The PSK-modulated frame synchronization signal, that is, the head of the communication frame is detected. The timing generator 36 determines the frame synchronization signal / TM in one communication frame based on the information on the top of the frame detected by the frame synchronization detector 35.
A period of the CC signal and a period of the carrier synchronization auxiliary signal are detected, and a timing signal (gate signal) corresponding to the period is detected.
Generate The phase correction unit 34 includes a band limiting filter 33
, And corrects the phase shift based on a timing signal received from the timing generator 36.

The components of the phase correction section 34 will be briefly described. The phase error detection unit 341 receives the signal output from the band-limiting filter 33 via the complex multiplication unit 344, and detects a phase difference from a predetermined reference phase. The phase error holding unit 342 averages the phase errors in the BPSK period among the phase errors detected by the phase error detection unit 341 according to the output signal from the timing generation unit 36. The numerical control oscillator 343 performs a numerical operation on the averaged signal output from the phase error holding unit 342 and outputs an oscillation signal. The complex multiplying unit 344 includes:
And the signal output by the numerical control oscillator 343 are subjected to complex multiplication to cancel the phase error.

The first error correction section 37 includes a phase correction section 34.
The signal output from is input, the main signal individually error-correction-encoded in the high-layer packet group and the low-layer packet group in the modulator, subjected to error correction in packet units,
In addition, the order of the packets rearranged on the time axis for time division multiplex transmission is restored. This output is output to the video decoder 39. The second error correction unit 38
The signal output from the phase correction unit 34 is input, and the modulation device performs error correction on the error-correction-coded TMCC signal. This output is output to TMCC decoder 40. The TMCC decoder 40 detects TMCC information indicating a break of each layer in the frame and a modulation mode of each layer. The BER measuring unit 41 performs trellis encoding again on a signal obtained by performing trellis decoding on a demodulated 8PSK signal on which trellis encoding, which is a type of error correction encoding, is performed, and generates a demodulated 8PSK signal. The BER of the higher hierarchical signal is monitored by comparison. As a result, when it is determined that the quality of the high-layer decoded video is lower than the allowable value, the BER measurement unit 41 outputs a low-layer video signal that is highly resistant to quality deterioration of the transmission path. The video decoder 39 is controlled.

Next, the operation performed by the demodulation device according to the first embodiment will be described in detail along the processing flow with reference to FIGS. 5 to 19. FIG. 5 is a flowchart illustrating an operation performed by the demodulation device according to the first embodiment. FIG.
5 is a diagram showing a signal detected by the frame synchronization detection unit 35 and a timing signal generated by the timing generation unit 36. FIG. 7 to 11 are block diagrams illustrating the configuration of each embodiment of the frame synchronization detection unit 35. 12 to 16
FIG. 7 is a diagram illustrating a phase relationship in each embodiment of the frame synchronization detection unit 35. FIG. 17 is a block diagram illustrating a more detailed configuration of the frequency correction unit 32. FIG.
FIG. 3 is a block diagram showing a more detailed configuration of a phase correction unit 34.

Referring to FIG. 5, the demodulation apparatus first detects a frame synchronization signal in frame synchronization detection section 35 for a signal input to quadrature detection section 31 via a tuner (not shown) ( Step S101). By this detection, as shown in FIG. 6A, the head of the communication frame, that is, the head of the frame synchronization signal / TMCC signal can be detected. Here, as the frame synchronization detection unit 35 that realizes such detection of the head of the frame,
Five embodiments of a specific configuration are conceivable. Hereinafter, these five embodiments will be described in order.

[0137] Figure 7 (Example 1 of the frame synchronization detector 35) corresponds to claim 32, the frame synchronization detector 3
FIG. 13 is a block diagram illustrating a configuration of Example 1 of Embodiment 5. In FIG. 7, the first embodiment is different from the delay detection unit 351 and the phase identification unit 3 in the first embodiment.
52 and a collating unit 353. Delay detection section 351
Receives the signal from the band limiting filter 33 and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The phase identification section 352 identifies the phase of the signal output from the delay detection section 351 and decodes the data. Here, since the frame synchronization signal to be detected is a BPSK modulation signal,
As shown in FIG. 2, when the phase of the output signal of the delay detection unit 351 is in the range from −90 degrees to 90 degrees (A region), “0” is set.
Is output, and when it is in the range from 90 degrees to 180 degrees or from -180 degrees to -90 degrees (B region), "1" is output. The collation unit 353 includes the phase identification unit 35
2 is compared with a predetermined frame synchronization signal to detect the head position of the frame. Here, the reference signal referred to by the matching unit 353 is obtained by differentially decoding the frame synchronization signal.

(Second Embodiment of Frame Synchronization Detector 35) In the first embodiment, when there is a frequency shift in the phase modulation signal input to the delay detector 351, the output of the delay detector 351 is as shown in FIG. As shown, there is a phase shift (x in the figure). In addition, low C / N
At this time, the result is as shown in FIG. 15, and a phase error occurs in the phase identification method of the first embodiment. Therefore, Example 2
It corresponds to this.

[0139] Figure 8 corresponds to claim 32 is a block diagram showing a configuration of a second embodiment of the frame synchronization detection unit 35. In FIG. 8, the second embodiment includes a delay detection unit 351 and
It includes first to third phase identification units 352 a to 352 c and a matching unit 353. The delay detection unit 351 receives the signal from the band limiting filter 33, and
The complex multiplication of the phase modulated signal before the symbol and the complex conjugate signal is performed. First to third phase identification units 352a to 352c
Decodes data by identifying the phase of the signal output from the delay detection unit 351. Here, as shown in FIG. 13, each of the first to third phase identification sections 352a to 352c has a phase identification area of 180 degrees, and different phase rotations are applied to the phase identification areas. I have.

For example, as shown in FIG. 13A, the first phase discriminating section 352a sets “0” when the phase of the output signal of the delay detecting section 351 is in the range from −90 degrees to 90 degrees (A region). And outputs 90 degrees or more and 180 degrees or less, or -1.
"1" when it is between 80 degrees and -90 degrees (region B)
It operates to output. Also, the second phase identification unit 3
52b is a delay detection unit 351 as shown in FIG.
Is more than (-90 + α) degrees (90 + α)
Degrees (A region), "0" is output and (90
+ Α) degrees or more and 180 degrees or less or −180 degrees or more (−
If it is less than (90 + α) degrees (area B), it operates to output “1”. Also, the third phase identification unit 352c
Outputs “0” when the phase of the output signal of the delay detection unit 351 is not less than (−90−α) degrees and not more than (90−α) degrees (A region) as shown in FIG. 13C. , (90-α)
Degrees or more and 180 degrees or less or -180 degrees or more (-90-
.alpha.) degrees or less (B region), it operates to output "1". The matching unit 353 compares each of the signals output from the first to third phase identification units 352a to 352c with a predetermined frame synchronization signal, and performs frame matching on any one of the signals that match the frame synchronization signal. Detects the start position of. Here, the reference signal referred to by the matching unit 353 is obtained by differentially decoding the frame synchronization signal.

(Third Embodiment of Frame Synchronization Detector 35) In the second embodiment, the phase discrimination unit performs phase rotation on the coordinate axes, that is, performs different phase rotation on the phase discrimination regions to perform phase discrimination. . However, a method is also conceivable in which the phase discrimination unit does not perform phase rotation, and performs phase rotation on the output of the delay detection unit 351 to discriminate the phase. Therefore, the third embodiment corresponds to this.

[0142] Figure 9 corresponds to claim 33 is a block diagram showing a configuration of a third embodiment of the frame synchronization detection unit 35. In FIG. 9, the third embodiment includes a delay detection unit 351 and
It includes first to third phase rotation units 354a to 354c, three phase identification units 352, and a comparison unit 353. The delay detection unit 351 receives the signal from the band limiting filter 33, and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The first to third phase rotation units 354a to 354c receive the signals output by the delay detection unit 351 and perform different phase rotations to output the signals. The three phase identification units 352 receive the signals output from the first to third phase rotation units 354a to 354c, respectively, identify the reference signals in the same phase identification area, and decode the data. The collation unit 353 includes three phase identification units 35
Each of the signals output from the frame synchronization signal 2 is compared with a predetermined frame synchronization signal, and the start position of the frame is detected for any one of the signals that match the frame synchronization signal. As described above, the phase detection of the output of the delay detection unit 351 is equivalently the same as that shown in FIG.

In the description of the second and third embodiments, the signals subjected to the three types of phase rotation are collated. However, if the collation is performed using the signals subjected to the more types of phase rotation, In addition, the accuracy of frame synchronization by delay detection can be improved.

(Embodiment 4 of the Frame Synchronization Detector 35) FIG. 10 is a block diagram showing a configuration of an embodiment 4 of the frame synchronization detector 35 according to claim 34 . FIG.
In Example 4, the fourth embodiment includes a delay detection unit 351, a phase identification unit 352, an identification phase rotation unit 355, and a collation unit 353. The delay detection unit 351 includes the band limit filter 33
, And performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before.
The phase identification section 352 identifies the phase of the signal output from the delay detection section 351 and decodes the data. Here, the phase identification unit 352 determines that the frame synchronization signal to be detected is a BPS
Since it is a K-modulated signal, it has a 180-degree phase identification area (see FIG. 12). The collation unit 353 performs collation between the signal output from the phase identification unit 352 and a predetermined frame synchronization signal, and detects the head position of the frame.
Here, the reference signal referred to by the matching unit 353 is obtained by differentially decoding the frame synchronization signal. As shown in FIG. 16, the identification phase rotation unit 355 includes a phase identification unit 352.
Is rotated, and the rotation phase is changed until the frame synchronization detection is obtained in the matching unit 353.

(Fifth Embodiment of Frame Synchronization Detector 35) In the fourth embodiment, phase identification is performed by applying a phase rotation to the coordinate axes in the phase identification section, that is, by applying different phase rotations to the phase identification areas. . However, a method is also conceivable in which the phase discrimination unit does not perform phase rotation, and performs phase rotation on the output of the delay detection unit 351 to discriminate the phase. Therefore, the fifth embodiment corresponds to this.

[0146] Figure 11 corresponds to claim 35 is a block diagram showing a configuration of a fifth embodiment of the frame synchronization detection unit 35. In FIG. 11, the fifth embodiment is different from the delay detector 351 in FIG.
, A phase rotation unit 354, a phase identification unit 352, and a collation unit 353. The delay detection unit 351 receives the signal from the band limiting filter 33, and
The complex multiplication of the phase modulated signal before the symbol and the complex conjugate signal is performed. The phase rotation unit 354 receives the signal output from the delay detection unit 351, performs phase rotation, and outputs the signal. Here, the phase rotation unit 354 changes its rotation phase until the matching unit 353 obtains frame synchronization detection. The phase identification unit 352 identifies the phase of the signal output from the phase rotation unit 354 and decodes the data. Collation unit 353
Performs a comparison between the signal output from the phase identification unit 352 and a predetermined frame synchronization signal, and detects the head position of the frame. As described above, the phase identification of the output of the delay detection unit 351 is equivalent to that shown in FIG.
The same effects as in the fourth embodiment can be obtained.

Since the frame synchronization detecting section 35 of the first to fifth embodiments uses the delay detection, if the frequency synchronizing section 32 or later is used, its installation position is determined by the output of the frequency correcting section 32. There is no particular limitation as long as it is the output of the band limiting filter 33 or the output of the phase correction unit 34. As will be described later, since the frequency correction unit 32 also uses delay detection, the frame synchronization detection unit 3
5, the circuit scale can be reduced by sharing the delay detection unit 351 with the delay detection unit of the frequency correction unit 32.

Referring to FIG. 5 again, the frame head signal detected by frame synchronization detecting section 35 is input to timing generating section 36. The timing generator 36 detects a period of the frame synchronization signal / TMCC signal and a period of the carrier synchronization auxiliary signal in one communication frame based on the frame head signal detected by the frame synchronization detector 35,
A BPSK timing signal corresponding to the period as shown in FIG. 6B is generated (step S102). It should be noted that the BPSK timing signal according to only the period of the carrier synchronization auxiliary signal as shown in FIG. 6C can obviously provide the useful effects of the present invention.

Here, in the demodulation device according to the first embodiment, in order to reproduce the carrier in the BPSK period, the BP
The insertion interval and the insertion width (the number of symbols) of the SK-modulated carrier synchronization auxiliary signal are important. Regarding the insertion interval, the longer the interval is, the longer the holding state of the frequency correction unit 32 and the phase correction unit 34 is, and if any frequency error remains, the phase rotation of the modulation signal occurs between them. Synchronization phase is 180
They can be different, or even out of sync. Regarding the number of inserted symbols, at least two symbols are required since frequency error detection in the frequency correction unit 32 uses delay detection and detects a phase shift between one symbol as a frequency error. Therefore, as described above, in the modulation device, the carrier synchronization auxiliary signal is 2
It is preferable to insert more than one symbol continuously, and to set the insertion interval to about 200 symbols or less.

The timing generator 36 generates the BPSK timing signal (FIG. 6B or FIG. 6B).
(C)) is changed to the frequency error holding unit 32 of the frequency correction unit 32.
2 and to the phase error holding unit 342 of the phase correction unit 34 (see FIG. 4).

Next, referring to FIG.
Operation 2 will be described. In FIG. 17, the frequency correction unit 3
Reference numeral 2 denotes a frequency error detection unit 321 including a delay detection unit 321a and a phase error detection unit 321b;
a, a constant generator 322b, an adder 322c, and a delay unit 32
2d, a frequency error holding unit 322, an adder 323a, a delay unit 323b, and a cosine wave generation unit 323c.
A numerically controlled oscillation section 323 composed of a sine wave generation section 323d and a complex multiplication section 324 are provided.

The signal output from the quadrature detector 31 is input to the delay detector 321a of the frequency error detector 321 via the complex multiplier 324 and the band limiting filter 33. The delay detection unit 321a performs complex multiplication of the current n-phase PSK modulation signal (n = 2 ¹ , 2 ² , 2 ³ ..., The same hereinafter) and the complex conjugate signal of the n-phase PSK modulation signal one symbol before. Then, the delay detection output is calculated. The equation for calculating the delay detection output is shown in the following equation (1). Delay detection output = exp (j (2π / nｎ (D1) + 2π ・ Δf ・ t1))) exp (−j (2π / n ・ (D0) + 2π ・ Δf ・ t0)) = exp (j (2π / n · (D1-D0) + 2π · Δf · Ts)) (1) D1: The current symbol phase state of the n-phase PSK modulation signal
(0 to (n-1)) D0: Phase state of one symbol before the n-phase PSK modulation signal (0
((N-1)) Δf: frequency shift of equivalent low-frequency signal [Hz] t1: current time [t] t0: time [t] one symbol before Ts: symbol period [t]

In the case of BPSK, if there is no frequency shift according to the above equation (1), the phase state of the differential detection output is π · n (n = 0 to 1) as shown by a black circle in FIG. However, if there is a frequency shift Δf, 2π ·
The phase is shifted from the mark by Δf · Ts (= θ). Therefore, the phase error detecting unit 321b detects the phase difference from the mark x when there is a frequency shift as a frequency error by using the mark ● when there is no frequency shift as a reference on the receiving side. Since the processing is performed in the rectangular coordinate system, the phase difference is originally calculated by arctan (y / x). The error Δy of the orthogonal component in the detection signal may be output as a frequency error.

The frequency error detected by the phase error detecting section 321b is input to a loop filter including an adder 322c and a delay section 322d via a switching section 322a, and the frequency errors are averaged. Here, the frequency error holding unit 322 performs averaging on the frequency error obtained only during the period of the BPSK-modulated frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in one communication frame. The switching unit 322a is switched using the timing signal output from the generation unit 36. The switching unit 322a outputs the timing signal B
The frequency error output from the phase error detection unit 321b is input to the loop filter during the period of the PSK modulation signal (Hi level period in FIG. 6B or 6C), and the constant generation unit 322b is used during other periods. Switching is performed so that the generated “constant 0” is input to the loop filter. And
The output signal of the frequency error holding unit 322 controls a numerically controlled oscillation unit (NCO) 323, and the complex multiplication unit 324 cancels the frequency error by the oscillation signal obtained therefrom.
As a result, the frequency error is corrected (step S10).
3).

In the above description, the frequency error detector 3
Although the input signal of 21 was the output signal of the band limiting filter 33, since the frequency error detection unit 321 uses delay detection, if it is a signal after the complex multiplication unit 324,
That is, there is no particular limitation on the output signal of the complex multiplication unit 324, the output signal of the band limiting filter 33, or the output signal of the phase correction unit 34.

Next, referring to FIG.
Will be described. In FIG. 18, the phase correction unit 34
Is a phase error detection unit 341, a switching unit 342a, a constant generation unit 342b, adders 342c and 342e, and a delay unit 34.
2d, holding section 342f and amplifier 342g, phase error holding section 342, adder 343a and delay section 34
3b, cosine wave generator 343c, and sine wave generator 34
3d and a complex multiplication unit 344.

At the initial stage of the operation of the phase correction unit 34, the output signal of the band limiting filter 33 has the frequency control unit 32 whose frequency error has been canceled, but the numerically controlled oscillation unit 34.
The output of the complex multiplier 344 includes a phase error because the phase of the output signal is different from that of the output signal of No. 3. The output of the complex multiplication unit 344 including the phase error is input to the phase error detection unit 341. As shown in FIG. 19, the phase error detection in the phase error detection unit 341 detects a phase difference between a received signal and a mark having a phase shift ΔΦ with respect to a reference phase on the receiving side indicated by a mark. Since the processing is performed in the rectangular coordinate system (I and Q planes), arcta is originally used to detect the phase error.
Although it is calculated by n (Q / I), in the case of BPSK, the error ΔQ of the quadrature component may be output as a phase error as a quantity proportional to the phase error.

The phase error detected by phase error detecting section 341 is supplied to adders 342c and 342e, delay section 342d and amplifier 3 via switching section 342a and holding section 342f.
The signal is input to a loop filter composed of 42 g, and the phase error signal is averaged. The loop filter in the phase error holding unit 342 is connected to the adder 34 via the amplifying unit 342g.
2e, the adder 342c and the delay unit 34
The direct system is used to correct a phase error, and the integral system is used to correct a small frequency shift that could not be removed by the frequency correction unit 32. The amplifier 342g determines the gain distribution between the direct system and the integral system.

Here, the phase error holding section 342 averages the phase error obtained only during the period of the BPSK modulated frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in one communication frame. Therefore, the switching of the switching unit 342a and the control of the holding unit 342f are performed using the timing signal output from the timing generation unit 36. The switching and control are performed such that the phase error output from the phase error detection unit 341 is input to the loop filter during the period of the BPSK modulation signal of the timing signal (Hi level period in FIG. 6B or 6C). . In the integration system of the loop filter, the output signal of the phase error detection unit 341 is input to the adder 342c during the BPSK modulation signal period, and the constant generation unit 3 during the other periods.
The switching unit 3 is configured to input a “constant 0” at which the 42b is generated.
42a is switched. In the direct system of the loop filter, the BPSK modulation signal period is set to the phase error detector 34.
1 via an amplifier 342g to adder 342e.
In other periods, the holding unit 342f is controlled so as to hold the output signal of the phase error detection unit 341 in the previous BPSK modulation signal period and output the signal to the adder 342e.

The output signal of the phase error holding section 342 controls a numerically controlled oscillation section (NCO) 343, and the complex multiplication section 344 cancels the phase error by the oscillation signal obtained therefrom. Thus, the phase error is corrected (Step S104). After that, the process shifts to a regular demodulation process (step S105). Here, the steady demodulation process is a demodulation operation after the phase correction unit 34 is synchronized with the phase. Is changed so as not to lose the phase synchronization in the phase correction unit 34. For example, after the phase has been synchronized once, until the phase synchronization is lost for some reason, processing such as stopping updating the coefficient of the frequency error holding unit 322 of the frequency correction unit 32 or reducing the loop gain (reducing the sensitivity) is performed. . In the flowchart of FIG. 5, the operation of the frequency correction unit 32 (step S103) and the operation of the phase correction unit 34 (step S104) are described in individual steps, but the operation of the phase correction unit 34 in step S103 is described. This does not cause any problem (hereinafter, the same applies to the processing of step S103 in each embodiment).

As described above, according to the demodulator according to the first embodiment of the present invention, among the phase-modulated signals to be time-division multiplexed, BPSK including a carrier synchronization auxiliary signal dispersedly arranged in a packet is used. Carrier synchronization can be performed at high speed and stably even in a low C / N state by performing carrier wave regeneration using the carrier. Further, even when the input frequency error is large, it is possible to eliminate the malfunction of the frame synchronization detection by the delay detection and perform the carrier synchronization.

(Second Embodiment) A demodulator according to a second embodiment of the present invention, which is different from the demodulator according to the first embodiment, in that a malfunction caused by pseudo synchronization in the phase correction unit 34 is avoided. It is. Therefore,
Pseudo synchronization in the case where the phase is corrected using the BPSK-modulated carrier synchronization auxiliary signal will be described first.

The pseudo synchronization means that the insertion period of the carrier synchronization auxiliary signal in the modulation device is constant (see FIG. 2), and the frequency error input to the phase correction unit 34 is 180 in the insertion period of the carrier synchronization auxiliary signal. If the frequency is rotated by degrees × m (m is any integer other than 0), the phase correction unit 3
No. 4 cannot identify the original phase error in the carrier synchronization auxiliary signal period, and synchronizes with a different phase. For example, as shown in FIG. 20, when the phase is rotated by 180 degrees in the carrier synchronization auxiliary signal insertion cycle (→ in the figure) due to a frequency shift (A in the figure), the phase error detection in the phase correction unit 34 causes The phase change in the synchronization auxiliary signal insertion cycle (→ in the figure) cannot be detected, and in this case, each time (in the figure)
Only the phase error at the angle β is detected (B in the figure).

The phase correction section 34 performs phase correction based on the phase error signal detected in this way, and thus quasi-carrier-synchronized despite a frequency error, and shifts to a steady demodulation operation. It will be stable. The frequency Δf for the pseudo synchronization is as shown in the following equation (2). Δf = (m × 180 degrees) / 360 degrees × fsym / S (2) fsym: symbol frequency (modulation speed) [Hz] S: carrier synchronization auxiliary signal insertion cycle [symbol] m: arbitrary integer (± 1) , ± 2, ± 3, ...) For example, if the symbol frequency is 20 Mbaud and the cycle is 20
In the case of seven symbols, pseudo-synchronization can be performed at each frequency as shown in FIG.

Hereinafter, a demodulation device according to a second embodiment of the present invention for avoiding the above-described malfunction due to the pseudo synchronization will be described. FIG. 22 is a block diagram showing a configuration of a demodulation device according to a second embodiment of the present invention, corresponding to claims 9 , 36, and 40 . In FIG. 22, the demodulation device according to the second embodiment includes a quadrature detection unit 31 and a frequency correction unit 3
2, a band limiting filter 33, a phase correction unit 34A,
A frame synchronization detector 35, a timing generator 36,
Frequency pull-in detection section 42 and first error correction section 37
A second error correction unit 38, a video decoder 39,
It includes a TMCC decoder 40 and a BER measuring unit 41. FIG. 23 is a flowchart illustrating an operation performed by the demodulation device according to the second embodiment.

As shown in FIG. 22, the demodulation device according to the second embodiment is different from the demodulation device according to the first embodiment in that:
The configuration is such that a frequency pull-in detection unit 42 for detecting a frequency pull-in state in the frequency correction unit 32 is further added, and the phase correction unit 34 is replaced with a phase correction unit 34A. The rest of the configuration of the demodulation device according to the second embodiment is the same as the configuration of the demodulation device according to the first embodiment. Omitted. In FIG. 23, steps for performing the same processing as in FIG. 5 are denoted by the same step numbers, and description thereof is omitted.

First, the operation of the frequency pull-in detection unit 42 will be described with reference to FIG. FIG. 24 is a block diagram showing a more detailed configuration of the frequency pull-in detector 42 of FIG. In FIG. 24, the frequency pull-in detection unit 4
Reference numeral 2 denotes a frequency error detection unit 421 including a delay detection unit 421a and a phase error detection unit 421b, and a switching unit 422.
, A constant generator 423, an adder 424a, and a delay unit 42.
4b, a switching unit 424c, and a constant generation unit 424d.

The signal output from the band limiting filter 33 is
The signal is input to the delay detection unit 421a. Delay detection section 421a
Performs complex multiplication of the current n-phase PSK modulation signal and the complex conjugate signal of the n-phase PSK modulation signal one symbol before, and calculates a delay detection output, like the other delay detection units. The equation for calculating the delay detection output is as shown in the above equation (1). Then, as described above, the phase error detection unit 421b detects the phase difference from the mark x when there is no frequency deviation and the cross mark when there is a frequency deviation as a frequency error, as described above (FIG. 14). See).

The frequency error detected by the phase error detection section 421b is input to the adder 424a via the switching section 422, and the frequency error is averaged every certain period. Here, in order to perform frequency pull-in detection by the frequency correction unit 32 during the period of the BPSK-modulated frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in one communication frame, the timing generation unit 36
(FIG. 6 (b) or (c))
Is used to perform switching of the switching unit 422. This switching unit 42
2 is a period of the BPSK modulation signal of the timing signal (FIG. 6)
The frequency error output from the phase error detection unit 421b during the (Hi) period in (b) or (c) is integrated by the integration unit 424.
In other periods, switching is performed so that “constant 0” generated by the constant generation unit 423 is input to the integration unit 424. The timing generation section 425 generates a timing pulse having a constant period, and controls the switching section 424c. The integrator 424 outputs the input of the adder 424a to the feedback output of the delay unit 424b or the constant generator 424 according to the timing pulse generated by the timing generator 425.
By switching to one of the “constant 0” where d occurs,
The averaged frequency error for each fixed period is output. The averaged frequency error output from the integration unit 424 is calculated by the absolute value conversion unit 42.
After being converted to a positive value in 7, it is output to the frequency pull-in determination unit 426. Frequency pull-in determination unit 426
Is input as a positive value averaged frequency error output from the absolute value averaging unit 427, and determines whether the averaged frequency error falls below a predetermined threshold value when the timing generation unit 425 generates a timing pulse. Then, the frequency pull-in is determined (step S201). If the result of this determination is that the averaged frequency error falls below a predetermined threshold, the frequency pull-in determination unit 426 determines that the frequency has been pulled, that is, the frequency correction unit 32
, It is determined that the frequency has been corrected to a frequency that does not synchronize, and a signal for resetting the phase corrector 34 is output so that the phase corrector 34 is operated again.

Here, the threshold value in frequency pull-in determination section 426 may be set in advance so that phase correction section 34 can determine whether frequency correction section 32 has been able to correct the frequency up to a frequency at which pseudo synchronization is not achieved. In addition,
The frequency of the pseudo synchronization is as shown in the above equation (2). For example, when the symbol frequency is 20 Mbaud and the period is 207 symbols, there are pseudo-synchronous frequencies as shown in FIG. 21 and there is a pull-in frequency range of the phase correction unit 34 centered on each pseudo-synchronous frequency. It is desirable that the threshold value in the frequency pull-in determination unit 426 be set to be equal to or lower than the frequency Δf represented by the following equation (3). Δf = １ ／ × 180 degrees / 360 degrees × fsym / S (3) fsym: symbol frequency (modulation speed) [Hz] S: carrier synchronization auxiliary signal insertion period [symbol]

Next, referring to FIG.
The operation of A will be described. FIG. 25 is a block diagram illustrating an example of a more detailed configuration of the phase correction unit 34A. FIG.
As shown in the figure, the phase correction unit 34A includes a switching unit 342h in the phase error holding unit 342 in the configuration of the phase correction unit 34.
And a constant generation unit 342i. Note that, in FIG. 25, components denoted by the same reference numerals as those in FIG. 18 are components that perform the same operations, and thus description thereof will be omitted.

The reset signal output from the frequency pull-in determination section 426 is stored in the holding section 342f of the phase error holding section 342.
And the switching unit 342h. Holder 342f
Initializes the phase error signal in the direct system based on the reset signal. The switching unit 342h initializes the phase error signal in the integration system by switching the feedback signal to the adder 342c to “constant 0” output by the constant generation unit 342i based on the reset signal. Thereby, in the phase correction unit 34A, the output signal of the frequency correction unit 32 whose frequency has been corrected to the frequency at which the pseudo synchronization does not occur, with respect to the phase error signal input to the phase error holding unit 342 after the reset operation. , A new phase correction is performed (step S202).
Thereafter, the process proceeds to a steady demodulation process (step S10).
5).

As shown in FIG. 26, in the numerical control oscillator 343, the switching unit 343e and the constant generator 343
f, the switching unit 342h and the constant generation unit 34
Operation similar to 2i may be performed in parallel. By performing the reset operation in parallel in this manner, initialization can be performed more reliably.

As described above, the demodulation device according to the second embodiment of the present invention is provided with the frequency pull-in detection unit 42, and the frequency correction unit 32 performs the frequency correction up to the frequency at which the phase correction unit 34A does not perform pseudo synchronization. After that, the phase correction unit 34A is reset and operated again. This makes it possible to avoid pseudo-synchronization in the phase correction unit 34A in the frequency pull-in process by the frequency correction unit 32 and the like.

In the demodulation device according to the second embodiment, since the frequency pull-in detection unit 42 uses delay detection, if the frequency correction unit 32 or later is used, its installation position is the frequency correction unit 32 , The output of the band limiting filter 33, or the output of the phase correction unit 34A. Further, since the frequency error detection unit 421 of the frequency pull-in detection unit 42 has the same function as the frequency error detection unit 321 of the frequency correction unit 32, both frequency error detection units can be shared. is there. When shared, the circuit scale can be reduced.

(Third Embodiment) The demodulation device according to the third embodiment of the present invention is the same as the second embodiment described above, except that the phase correction unit 34 in the demodulation device according to the first embodiment described above. This avoids a malfunction due to the pseudo-synchronization. Hereinafter, a demodulation device according to a third embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

FIG. 27 is a block diagram showing a configuration of a demodulator according to a third embodiment of the present invention, corresponding to claims 10 , 36 and 41 . In FIG. 27, the demodulation device according to the third embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, and a phase correction unit 34A.
, A frame synchronization detection unit 35, and a timing generation unit 36
, A phase synchronization detection unit 43, an error correction detection unit 44, a pseudo synchronization determination unit 45, a first error correction unit 37, a second error correction unit 38, a video decoder 39, and a TMCC decoder 40. , BER measuring unit 41. FIG.
9 is a flowchart illustrating an operation performed by the demodulation device according to the third embodiment.

As shown in FIG. 27, the demodulation device according to the third embodiment differs from the demodulation device according to the first embodiment in that:
The configuration is such that a phase synchronization detection unit 43, an error correction detection unit 44, and a pseudo synchronization determination unit 45 are further added, and the phase correction unit 34 is replaced with a phase correction unit 34A. The rest of the configuration of the demodulation device according to the third embodiment is the same as the configuration of the demodulation device according to the first and second embodiments, and the components are denoted by the same reference numerals. The description is omitted. In FIG. 28, steps for performing the same processing as in FIG. 5 are denoted by the same step numbers, and description thereof is omitted.

First, the operation of the phase synchronization detector 43 will be described. The signal input via the tuner (not shown)
After the frequency correction and the phase correction are performed as described in the first embodiment (step S301), the signal is input to the phase synchronization detecting unit 43. The phase synchronization detection unit 43 detects the phase synchronization / asynchronization of only the period of the BPSK-modulated carrier synchronization auxiliary signal with respect to the input corrected signal. As the phase synchronization detection unit 43, two embodiments having specific configurations can be considered. Hereinafter, these two
Two embodiments will be described in order.

(Embodiment 1 of Phase Synchronization Detecting Section 43) FIG. 29 is a block diagram showing the configuration of Embodiment 1 of the phase synchronization detecting section 43. In FIG. 29, the phase synchronization detecting unit 4
3 is a phase error detection unit 431, an absolute value conversion unit 432,
Switching section 433, constant generating section 434, adder 435a
, Delay unit 435b, switching unit 435c, and constant generation unit 435.
d, an integrator 435, and a timing generator 4
36, and a phase synchronization determination unit 437.

The signal output from the phase corrector 34A is input to the phase error detector 431. Phase error detector 431
Detects the phase difference from the X mark when there is a phase shift and the X mark when there is a phase shift as a phase error ΔΦ [degree] as described above (see FIG. 19). . Phase error ΔΦ detected by phase error detection section 431
Is converted to a positive value | ΔΦ | by the absolute value conversion unit 432. Then, the phase error | output from the absolute value conversion section 432 |
ΔΦ | is input to the adder 435a via the switching unit 433, and the phase error | ΔΦ | is averaged every certain period. Here, in order to perform phase synchronization detection only during the period of the BPSK-modulated carrier synchronization auxiliary signal in one communication frame, the switching unit uses the timing signal (FIG. 6C) output by the timing generation unit 36. 433 is switched. The switching unit 433 outputs the phase error | ΔΦ output by the absolute value conversion unit 432 during the period of the BPSK modulation signal of the timing signal (Hi level period in FIG. 6C).
Is input to the integration unit 435, and in other periods, switching is performed so that “constant 0” generated by the constant generation unit 434 is input to the integration unit 435. Timing generator 436
Generates a timing pulse having a constant period,
5c. The integrator 435 includes the timing generator 4
According to the timing pulse generated by the adder 43, the adder 43
5a is switched to either the feedback output of the delay unit 435b or the “constant 0” generated by the constant generation unit 435d, so that the averaged phase error |
ΔΦ | is output. The phase synchronization determination unit 437 includes the integration unit 4
When the averaged phase error output from 35 is input and the timing generator 436 generates a timing pulse, the phase synchronization is determined based on whether or not the averaged phase error falls below a predetermined threshold (step S302). ). Then, as a result of this determination, if the averaged phase error falls below a predetermined threshold, the phase synchronization determination section 437 determines that phase synchronization has been achieved, and outputs the result to the pseudo synchronization determination section 45. I do.

Here, the threshold value in phase synchronization determination section 437 can be arbitrarily set according to the purpose of use or characteristics of the demodulation device. (When not synchronized), the phase rotation remains as shown in FIG.
Since the symbols exist with the same probability over the entire 360 degrees, a positive value (first
After performing (quadrant) conversion, the average value of the phase error is 45.
Degrees or less (see FIG. 31).
(B)).

(Embodiment 2 of Phase Synchronization Detector 43) FIG. 30 is a block diagram showing a configuration of an embodiment 2 of the phase synchronization detector 43. In FIG. 30, the phase synchronization detection unit 4
3 is an absolute value conversion unit 432A, 432B and a comparison unit 438.
, A switching unit 433, a constant generation unit 434, and an adder 43.
5a, delay unit 435b, switching unit 435c, and constant generation unit 4
35d, an integrator 435 composed of the D. 35d, a timing generator 436, and a phase synchronization determiner 437.

The signal output from phase correction section 34A is I
The (in-phase) component signal is sent to the absolute value conversion section 432A, and Q (quadrature)
The component signals are respectively input to 432B. Absolute value conversion section 432A converts the input I component signal to a positive value | I |. Absolute value conversion section 432B converts the input Q component signal into a positive value | Q |. The comparing section 438 is an absolute value converting section 4
The value | I | converted by the 32A and the value | Q | converted by the absolute value conversion unit 432B are input, and both values are compared, and | I |>
The comparison value “1” is output when | Q |, and the comparison value “0” is output when | I | ≦ | Q |. The comparison value output from the comparing unit 438 is input to the adder 435a via the switching unit 433, and is averaged every certain period. Here, since phase synchronization detection is performed only in the period of the carrier synchronization auxiliary signal in which BPSK modulation is performed in one communication frame,
The timing signal output by the timing generator 36 (FIG. 6)
Switching of the switching unit 433 is performed using (c)). The switching unit 433 operates during the period of the BPSK modulation signal of the timing signal (Hi level period in FIG. 6C).
Switching is performed so that the comparison value output by 8 is input to the integrator 435, and in other periods, “constant 0” generated by the constant generator 434 is input to the integrator 435. The timing generation section 436 generates a timing pulse having a constant period, and controls the switching section 435c. The integrator 435 switches the input of the adder 435a to either the feedback output of the delay unit 435b or the “constant 0” generated by the constant generator 435d in accordance with the timing pulse generated by the timing generator 436, for a certain period. Output the averaged comparison value for each. The phase synchronization determination unit 437 receives the averaged comparison value output from the integration unit 435, and determines whether the averaged comparison value falls below a predetermined threshold when the timing generation unit 436 generates a timing pulse. To determine the phase synchronization (step S302). Then, as a result of this determination, when the averaged comparison value falls below a predetermined threshold, the phase synchronization determination unit 437 determines that phase synchronization has been achieved, and outputs the result to the pseudo synchronization determination unit 45. I do.

Here, the threshold value in phase synchronization determination section 437 can be arbitrarily set according to the purpose of use or characteristics of the demodulation device. (When not synchronized), the phase rotation remains as shown in FIG.
Since the symbols exist with the same probability over the entire 360 degrees, the probability of entering the region of | I |> | Q |
Since this is 2, the number of integrations performed by the integration section 435 may be set to a majority or less (see FIG. 31).
(B)).

Next, the operation of the error correction detector 44 will be described. The error correction detection unit 44 includes the second error correction unit 3
Reference numeral 8 inputs a signal indicating that the error cannot be corrected and a signal indicating that the error remains, which are output during the error correction process. Then, the error correction detection unit 44 detects whether the TMCC signal has been correctly corrected (step S303).
The result of this detection is output to the pseudo-synchronization determination unit 45.

Next, the operation of the pseudo-synchronization determination section 45 will be described with reference to FIG. The detection result of the phase synchronization detection unit 43 and the detection result of the error correction detection unit 44 are input to the pseudo synchronization determination unit 45. The pseudo synchronization determination unit 45 first determines whether or not phase synchronization has been achieved based on the determination result of the phase synchronization detection unit 43. If the phase is synchronized by this judgment,
Next, the pseudo-synchronization determining unit 45 determines whether the phase synchronization is normal synchronization or pseudo-synchronization from the result of the determination by the error correction detection unit 44. Thus, the reason for making the determination is as follows.

Although the phase synchronization detecting section 43 can reliably determine the phase synchronization, the phase synchronization is determined only during the period of the carrier synchronization auxiliary signal. Therefore, even if the phase synchronization is achieved, the synchronization is not normally synchronized. Or pseudo-synchronization cannot be determined. For example, if the received signal has a frequency shift of 180 degrees in phase at the insertion interval of the carrier synchronization auxiliary signal, the apparent synchronization in the phase synchronization determination only during the period of the carrier synchronization auxiliary signal is as shown in FIG. It is determined that the upper synchronization has been achieved (that is, pseudo synchronization). On the other hand, in the case of the pseudo synchronization, the output signal of the phase correction unit 34A during the TMCC signal period is
As shown in (b), since the phase is largely rotated (arrows in the figure), bit errors (shaded areas in the figure) that cannot be completely corrected by the second error correction unit 38 are included. Become. Therefore, by detecting whether the second error correction unit 38 can correct the error of the TMCC signal normally,
It can be determined that the synchronization is pseudo.

As described above, the pseudo-synchronization determination section 45 determines phase synchronization / asynchronization based on the detection result of the phase synchronization detection section 43, and determines normal synchronization / pseudo-sync based on the detection result of the error correction detection section 44. I have. This determination method is shown in Table 1 below.

[Table 1]

Then, as a result of performing the above-described determination, the pseudo-synchronization determining unit 45 proceeds to a steady demodulation process if it is determined that the synchronization is normal (step S105). A signal for resetting the phase correction operation is output to the phase correction unit 34A (step S304). The reset signal can be arbitrarily set, for example, a pulse signal sufficient to operate the phase correction unit 34A.

The reset operation performed by the phase correction section 34A based on the reset signal output from the pseudo synchronization determination section 45 is the same as that described in the second embodiment.
Although the description is omitted here, the purpose of instructing the reset operation is different from each other. That is, in the above-described second embodiment, the instruction is a reset operation as an initialization operation for starting the phase correction operation after the frequency correction is normally performed. As a result, this is an instruction of a reset operation for re-performing the phase correction again when the normal synchronization is not performed.

As described above, the demodulation device according to the third embodiment of the present invention detects the phase synchronization during the period of the carrier synchronization auxiliary signal, and detects whether or not the error correction of the TMCC signal is possible. It is determined from the result whether or not the synchronization is normal. In the case of the pseudo synchronization, the phase correction unit 3
4A is reset and restarted. This makes it possible to avoid pseudo-synchronization in the phase correction unit 34A in the frequency pull-in process by the frequency correction unit 32 and the like.

When the first embodiment is used in the phase synchronization detecting section 43, the phase error detecting section 431 included therein has the same function as the phase error detecting section 341 included in the phase correcting section 34A. Therefore, it is possible to share the two phase error detectors. When shared, the circuit scale can be reduced.

(Fourth Embodiment) The demodulation device according to the fourth embodiment of the present invention is similar to the demodulation device according to the first embodiment in the same manner as the second and third embodiments. This is to avoid a malfunction due to the pseudo synchronization in the correction unit 34. Hereinafter, a demodulation device according to a fourth embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

FIG. 33 is a block diagram showing a configuration of a demodulation device according to a fourth embodiment of the present invention, which corresponds to claims 11, 36 and 42 . 33, the demodulation device according to the fourth embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, and a phase correction unit 34A.
, A frame synchronization detection unit 35, and a timing generation unit 36
, A first phase synchronization detection unit 43A, a second phase synchronization detection unit 43B, a pseudo synchronization determination unit 45, a first error correction unit 37, a second error correction unit 38, and a video decoder 3.
9, a TMCC decoder 40, and a BER measuring unit 41.

As shown in FIG. 33, the demodulation device according to the fourth embodiment is different from the demodulation device according to the first embodiment in that:
First phase synchronization detecting section 43A and second phase synchronization detecting section 4
3B and a pseudo-synchronization determination unit 45 are further added, and the phase correction unit 34 is replaced by a phase correction unit 34A. The configuration is such that the error correction detection unit 44 is replaced with a second phase synchronization detection unit 43B in the first phase synchronization detection unit 43A. The rest of the configuration of the demodulation device according to the fourth embodiment is the same as the configuration of the demodulation device according to the first to third embodiments, and the components are denoted by the same reference numerals. The description is omitted. Also, the processing steps performed by the demodulation device according to the fourth embodiment are the same as the processing steps shown in FIG. 28 in the third embodiment, and thus description thereof will be omitted.

Hereinafter, a portion in which the demodulation device according to the fourth embodiment performs an operation different from that of the demodulation device according to the third embodiment will be described. First, the timing generation unit 36
Based on the frame head signal detected by the frame synchronization detector 35, the timing signal (see FIG. 6B) for the period of the frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal, and the carrier synchronization auxiliary signal In addition to generating a timing signal only for the period (see FIG. 6C), a timing signal only for the period of the frame synchronization signal / TMCC signal (FIG. 34) is generated. The timing signal only during the period of the frame synchronization signal / TMCC signal is output to the second phase synchronization detection unit 43B.

The first and second phase synchronization detectors 43A and 43B have the same configuration (FIG. 29 or FIG. 30) as described in the third embodiment. In the first phase synchronization detection unit 43A, the timing signal only during the period of the carrier synchronization auxiliary signal is used for controlling the switching unit 433, and the signal after the frequency correction and the phase correction is used for the phase synchronization / asynchronization in the period. Detection is performed (Fig. 2
8, step S302). Second phase synchronization detection unit 43B
In the control of the switching unit 433, the frame synchronization signal /
The timing signal only during the period of the TMCC signal is used,
For the signal after the frequency correction and the phase correction, synchronization / asynchronization of the phase in the period is detected (FIG. 28, step S303). Then, the first phase synchronization detecting section 43
A and the second phase synchronization detection unit 43B output a detection result indicating whether or not phase synchronization has been achieved to the pseudo synchronization determination unit 45, respectively.

The pseudo-synchronization determining unit 45 makes a determination shown in Table 2 below based on the detection results of the first and second phase synchronization detection units 43A and 43B, and determines that the synchronization is normal. In this case, the process shifts to the normal demodulation processing as it is (FIG. 28, step S105), and when it is determined that the synchronization is pseudo synchronization, a signal for resetting the phase correction operation is output to the phase correction unit 34A (FIG. 28, step S30).
4).

[Table 2]

The reason for the above determination is the same as that in the above-described second error correction section 38, that is, in the first phase synchronization detection section 43A, the phase is detected during the period of the carrier synchronization auxiliary signal. Since the synchronization is detected, the synchronization is apparently achieved as shown in FIG. 35 (a) even during the pseudo synchronization, whereas the second phase synchronization detection unit 43B performs
Since the phase synchronization is detected during the period of the frame synchronization signal / TMCC signal, the phase is largely rotated as shown in FIG. 35B during the pseudo synchronization (arrow in the figure), and it is determined that the phase synchronization is not established. Because you can. Therefore, by detecting this phase asynchronism, it can be determined that the synchronization is pseudo-synchronous.

As described above, the demodulation device according to the fourth embodiment of the present invention detects the phase synchronization during the period of the carrier synchronization auxiliary signal and the phase synchronization during the period of the frame synchronization signal / TMCC signal. Then, it is determined whether or not the synchronization is normal based on the detection result. Then, in the case of the pseudo synchronization, the phase correction unit 34A is reset and operated again. This makes it possible to avoid pseudo-synchronization in the phase correction unit 34A in the frequency pull-in process by the frequency correction unit 32 and the like.

When the first embodiment is used in the first phase synchronization detecting section 43A and the second phase synchronization detecting section 43B, the phase error detecting section 431 included therein is included in the phase correcting section 34A. Since it has the same function as the phase error detector 341 to be used, both phase error detectors can be shared. When shared, the circuit scale can be reduced.

(Fifth Embodiment) The demodulation device according to the fifth embodiment of the present invention is similar to the demodulation device according to the first embodiment in the same manner as the second to fourth embodiments. This is to avoid a malfunction due to the pseudo synchronization in the correction unit 34. However, the above-mentioned second to fourth
While the demodulation device according to the fifth embodiment controls the phase correction unit, the demodulation device according to the fifth embodiment knows the pseudo-synchronous frequency (as described above, the symbol frequency and the The frequency correction unit is controlled by utilizing the fact that the frequency correction unit is uniquely determined by the insertion period of the carrier synchronization auxiliary signal. Hereinafter, a demodulation device according to a fifth embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

[0204] Figure 36 is a claim 12,36,38,4
It is a block diagram corresponding to 3,64 which shows the structure of the demodulation device which concerns on 5th Embodiment of this invention. In FIG. 36, the demodulation device according to the fifth embodiment includes a quadrature detection unit 31.
, A frequency correction unit 32A, a band limiting filter 33,
A phase correction unit 34, a frame synchronization detection unit 35, a timing generation unit 36, a phase synchronization detection unit 43, an error correction detection unit 44, a pseudo synchronization determination unit 45, a frequency step unit 46, a first error Correction unit 37 and second error correction unit 3
8, a video decoder 39, and a TMCC decoder 40
And a BER measurement unit 41. FIG. 37 is a flowchart illustrating an operation performed by the demodulation device according to the fifth embodiment.

As shown in FIG. 36, the demodulation device according to the fifth embodiment is different from the demodulation device according to the first embodiment in that:
In this configuration, a phase synchronization detection unit 43, an error correction detection unit 44, a pseudo synchronization determination unit 45, and a frequency step unit 46 are further added, and the frequency correction unit 32 is replaced with a frequency correction unit 32A. In the demodulation apparatus according to the embodiment, the frequency correction unit 32 is replaced with the frequency correction unit 32A, the phase correction unit 34A is returned to the phase correction unit 34, and a frequency step unit 46 is added. The rest of the configuration of the demodulation device according to the fifth embodiment is the same as the configuration of the demodulation devices according to the first and third embodiments, and the components are denoted by the same reference numerals. The description is omitted. Also, in FIG. 37, FIGS.
Steps that perform the same processing as those described above are assigned the same step numbers, and descriptions thereof are omitted.

Hereinafter, a description will be given of a portion where the demodulation device according to the fifth embodiment performs an operation different from that of the demodulation device according to the third embodiment. First, the operation of the pseudo synchronization determination unit 45 will be described. As described above, the pseudo synchronization determination unit 45
Based on the detection result of the phase synchronization detection unit 43 and the detection result of the error correction detection unit 44, it is determined whether the phase synchronization is normal synchronization or pseudo synchronization. Then, as a result of performing the above-described determination, the pseudo-synchronization determination unit 45 proceeds to a normal demodulation process if it is determined that the synchronization is normal (step S105), and if it is determined that the synchronization is pseudo, the frequency step unit Then, a signal (a signal form is the same as that of the above-described reset signal) for performing the step operation is output to step 46 (step S401).

Here, a method of generating a signal for performing a step operation in the pseudo-synchronous determination section 45 will be described with reference to FIG. FIG. 38 is a block diagram illustrating an example of the configuration of the pseudo synchronization determination unit 45. 38, the pseudo-synchronization determination section 45 includes a logical sum (OR) circuit 451, a counter 452, and a pulse output section 453.

[0208] The pseudo-synchronization judging section 45 includes the phase-synchronization detecting section 4.
The detection result of No. 3 is input to the input terminal of the counter 452, and the detection result of the error correction detection unit 44 is input to one terminal of the OR circuit 451. The counter 452 counts a period during which the detection result of the phase synchronization detection unit 43 is Hi, and clears the counted value when the output of the OR circuit 451 becomes Hi. The pulse output unit 453 determines whether or not the count value output by the counter 452 has reached a predetermined value, and outputs a pulse signal indicating a step operation when the count value has reached a predetermined value.
The pulse signal is fed back to the other terminal of the OR circuit 451 and clears the count value of the counter 452 simultaneously with the output of the pulse signal. Accordingly, when the synchronization is normal (that is, when the phase synchronization is detected, the counter 452 starts counting, but it is detected that the error correction is completed before the count value reaches a predetermined value), the pulse is output. No signal is output, and the phase is synchronized but pseudo-synchronized (that is, the phase synchronization is detected and the counter 452 starts counting, but the error correction is not completed and the count value has reached a predetermined value. ), A pulse signal is output.

Next, the operation of the frequency step section 46 will be described with reference to FIGS. FIG. 39 is a block diagram illustrating an example of a configuration of the frequency step unit 46. FIG.
0 is a diagram showing each signal waveform generated by the frequency step unit 46. FIG. 41 is a diagram illustrating the operation principle of the frequency step unit 46. 39, a frequency step unit 46 includes a control signal generation unit 461 including an exclusive OR (XOR) circuit 461a, a delay unit 461b, and a logical product (AND) circuit 461c, and a first constant generation unit 462.
, A second constant generation unit 463, a switching unit 464, an integration unit 465, a negative encoding unit 466, and a switching unit 467.

The pulse signal (FIG. 40 (a)) output from the pseudo synchronization determination section 45 is input to the XOR circuit 461a and the AND circuit 461c. XOR circuit 461a
Takes an exclusive OR of this pulse signal and a signal fed back via the delay section 461b, and generates and outputs a control signal B (FIG. 40 (c)). The AND circuit 461c calculates the logical product of the pulse signal and the control signal B, generates and outputs the control signal A (FIG. 40B).
The switching unit 464 outputs the first signal when the control signal A is at the Hi level.
A constant Fg (a numerical value in which the oscillation frequency of the numerical control oscillating unit 323 changes by the pseudo-synchronous frequency interval (fg)) generated by the constant generating unit 462 of FIG. Is switched so as to output the “constant 0” at which the occurs. The integration unit 465
Performs cumulative addition of input values and outputs. Switching unit 467
Converts the signal output from the integrator 465 when the control signal B is at the Lo level as it is, and converts the signal output from the integrator 465 when the control signal B is at the Lo level into a negative value by the negative encoder 466. Switch to output. Therefore, the frequency step section 46 outputs the pulse signal (FIG. 40).
Each time (a)) becomes Hi level, the frequency signal shown in FIG. 40 (d), that is, + Fg, -Fg, + 2Fg,
-2Fg,... Are sequentially output.

The reason for outputting the frequencies in order (step) will be described with reference to FIG. FIG. 41 shows that the frequency fg = 48.3 kHz and the frequency 9
This shows a case where pseudo synchronization is performed at 6.6 kHz. As described in the second embodiment, the frequency interval fg at which pseudo synchronization occurs can be obtained from the symbol frequency and the insertion period of the carrier synchronization auxiliary signal.
That is, the pseudo synchronization is performed at the frequency of the normal synchronization ± m · fg
(M is an integer other than 0). Therefore, based on this frequency fg, + Fg, −Fg, + 2Fg, −2Fg,. By forcibly shifting to a frequency at which phase synchronization can be performed by the phase correction unit 34, the phase can finally reach normal phase synchronization (FIG. 41).

In the demodulation device according to the fifth embodiment, the frequency of the phase synchronization in the phase correction section 34 is forcibly shifted in the frequency correction section 32A. Hereinafter, the operation of the frequency correction unit 32A will be described with reference to FIG. FIG.
6, the frequency correction unit 32A includes a frequency error detection unit 321, a frequency error holding unit 322, and an adder 325.
, A numerical control oscillator 323, and a complex multiplier 324.

As shown in FIG. 36, the frequency corrector 32A
Has a configuration in which an adder 325 is further added to the frequency correction unit 32 in FIG. The output signal of the frequency error holding unit 322 and the frequency step control signal output from the frequency step unit 46 are input to the adder 325. Adder 3
Numeral 25 forcibly shifts the oscillation frequency of the numerically controlled oscillator (NCO) 323 by adding both the input signals. Thereafter, the phase correction is performed again at the shifted frequency (steps S401 and S104).

As described above, the demodulation apparatus according to the fifth embodiment of the present invention detects the phase synchronization during the period of the carrier synchronization auxiliary signal and detects the presence or absence of a bit error during the period of the frame synchronization signal / TMCC signal. Is performed, and it is determined from the detection result whether or not the synchronization is normal. And
In the case of the pseudo synchronization, the frequency of the frequency correction unit 32A is controlled so that the phase correction unit 34 can perform normal synchronization. This makes it possible to avoid pseudo-synchronization in the phase correction unit 34 in the frequency pull-in process and the like by the frequency correction unit 32A.

(Sixth Embodiment) The demodulation device according to the sixth embodiment of the present invention is similar to the demodulation device according to the first embodiment in the same manner as the second to fifth embodiments. This is to avoid a malfunction due to the pseudo synchronization in the correction unit 34. However, the above-mentioned second to fourth
The demodulation device according to the sixth embodiment controls the phase correction unit, whereas the demodulation device according to the sixth embodiment has the fifth configuration.
In the same manner as in the first embodiment, the frequency compensating unit uses the fact that the pseudo-synchronous frequency is known (as described above, is uniquely determined by the symbol frequency and the insertion period of the carrier synchronization auxiliary signal). Control. Hereinafter, a demodulation device according to a sixth embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

[0216] Figure 42 is a claim 13,36,38,4
It is a block diagram corresponding to 4,64 which shows the structure of the demodulation device which concerns on the 6th Embodiment of this invention. In FIG. 42, the demodulator according to the sixth embodiment includes a quadrature detector 31
, A frequency correction unit 32A, a band limiting filter 33,
A phase correction unit 34, a frame synchronization detection unit 35, a timing generation unit 36, a first phase synchronization detection unit 43A, a second phase synchronization detection unit 43B, a pseudo synchronization determination unit 45,
Frequency step section 46, first error correction section 37, second error correction section 38, video decoder 39, TMC
A C decoder 40 and a BER measuring unit 41 are provided.

As shown in FIG. 42, the demodulation device according to the sixth embodiment differs from the demodulation device according to the first embodiment in that:
First phase synchronization detecting section 43A and second phase synchronization detecting section 4
3B, a pseudo-synchronization determination unit 45 and a frequency step unit 46 are further added, and the frequency correction unit 32 is replaced with a frequency correction unit 32A. The correction unit 32 is a frequency correction unit 32
A, the phase correction unit 34A is returned to the phase correction unit 34,
Further, the configuration is such that a frequency step unit 46 is added. Note that other configurations of the demodulation device according to the sixth embodiment are as follows.
The configuration is the same as that of the demodulation devices according to the first and fourth embodiments, and the same components are denoted by the same reference numerals and description thereof will be omitted. Also, the processing steps performed by the demodulation device according to the sixth embodiment are the same as the processing steps shown in FIG. 37 in the fifth embodiment, and thus description thereof will be omitted.

Hereinafter, a portion in which the demodulation device according to the sixth embodiment performs an operation different from that of the demodulation device according to the fourth embodiment will be described. As described above, the pseudo synchronization determination unit 45 compares the detection result of the first phase synchronization detection unit 43A with the second phase synchronization detection unit 43A.
It is determined whether the phase synchronization is normal synchronization or pseudo synchronization based on the detection result of the phase synchronization detection unit 43B. Then, as a result of performing the above-described determination, the pseudo-synchronization determination unit 45 proceeds to a normal demodulation process if it is determined that the synchronization is normal (step S105), and if it is determined that the synchronization is pseudo, the frequency step unit Then, a signal (a signal form is the same as that of the above-described reset signal) for performing the step operation is output to step 46 (step S401). In the pseudo synchronization determination unit 45, a method of generating a signal for performing a step operation and the configuration of the pseudo synchronization determination unit 45 are as follows.
Since the description has been given in the fifth embodiment, the description here is omitted.

As described in the fifth embodiment, the frequency step section 46 controls the pulse signal (FIG. 40).
Each time (a)) becomes Hi level, the frequency signal shown in FIG. 40 (d), that is, + Fg, -Fg, + 2Fg,
-2Fg,... Are sequentially output. Then, the frequency step unit 46 inputs the output frequency step control signal to the adder 325 of the frequency correction unit 32A. Adder 325
Adds the input frequency step control signal to the output signal of the frequency error holding unit 322 to forcibly shift the oscillation frequency of the numerical control oscillator (NCO) 323. Thereafter, the phase correction is performed again at the shifted frequency (steps S401 and S104).

As described above, the demodulator according to the sixth embodiment of the present invention detects the phase synchronization during the period of the carrier synchronization auxiliary signal and the phase synchronization during the period of the frame synchronization signal / TMCC signal. Then, it is determined whether or not the synchronization is normal based on the detection result. In the case of pseudo synchronization, the frequency of the frequency correction unit 32A is controlled so that the phase correction unit 34 can perform normal synchronization. This makes it possible to avoid pseudo-synchronization in the phase correction unit 34 in the frequency pull-in process and the like by the frequency correction unit 32A.

(Seventh Embodiment) The demodulation device according to the seventh embodiment of the present invention is similar to the demodulation device according to the first embodiment in the same way as the second to sixth embodiments described above. This is to avoid a malfunction due to the pseudo synchronization in the correction unit 34. The demodulation device according to the seventh embodiment controls the phase correction unit performed in the second embodiment and controls the frequency correction unit performed in the fifth embodiment. Hereinafter, a description will be given of a demodulation device according to a seventh embodiment of the present invention for avoiding the above-described malfunction due to pseudo synchronization.

FIG. 43 is a block diagram showing the arrangements of claims 14, 36, 38 and 4;
It is a block diagram corresponding to 5,64 which shows the structure of the demodulation device which concerns on the 7th Embodiment of this invention. In FIG. 43, the demodulation device according to the seventh embodiment includes a quadrature detection unit 31.
, A frequency correction unit 32A, a band limiting filter 33,
Phase correction section 34A, frame synchronization detection section 35, timing generation section 36, frequency pull-in detection section 42, phase synchronization detection section 43, error correction detection section 44, pseudo synchronization determination section 45, frequency step section 46, a first error correction unit 37, a second error correction unit 38, a video decoder 39, a TMCC decoder 40, and a BER measurement unit 41.

As shown in FIG. 43, the demodulation device according to the seventh embodiment is different from the demodulation device according to the second embodiment in that
The configuration is a combination of the demodulation device according to the fifth embodiment. Therefore, the configuration of the demodulation device according to the seventh embodiment is the same as the configuration of the demodulation devices according to the second and fifth embodiments, and the same reference numerals are given and the description is omitted. However, since the order of the processing steps is slightly different, the processing steps performed by the demodulation device according to the seventh embodiment will be described below with reference to FIG.

The demodulator first detects a frame synchronization signal in the frame synchronization detector 35 for a signal input to the quadrature detector 31 via a tuner (not shown) (step S101). The frame head signal detected by the frame synchronization detection unit 35 is input to the timing generation unit 36. The demodulation device detects the period of the frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in one communication frame based on the frame head signal detected by the frame synchronization detection unit 35 in the timing generation unit 36, A BPSK timing signal corresponding to the period as shown in FIG. 6B is generated (step S10).
2). Note that a BPSK timing signal corresponding only to the period of the carrier synchronization auxiliary signal as shown in FIG. 6C may be used. This BPSK timing signal (FIG. 6B)
Is output to the frequency correction unit 32A, the phase correction unit 34A, and the frequency pull-in detection unit 42. Further, a signal giving a period of the carrier synchronization auxiliary signal shown in FIG.

Next, the demodulator corrects the frequency error in the period of the BPSK timing signal in the frequency corrector 32A (step S103). Then, the demodulation device calculates an averaged frequency error for the frequency-corrected signal in the frequency pull-in detection unit 42, and determines the frequency pull-in state (step S201). If the demodulation device determines in step S201 that the frequency has not been pulled in, the demodulation device proceeds to step S201.
Returning to step 103, the frequency error correction process is performed again. On the other hand, if it is determined that the frequency has been locked, the phase correction operation is reset for the phase correction unit 34A (step S304), and the phase error is newly corrected. A correction process is performed (Step S104).

When the above series of frequency error and phase error correction processing is completed, the demodulation device
In the above, based on the phase synchronization state in the carrier synchronization auxiliary signal period detected by the phase synchronization detection unit 43 and the detection result of the error correction of the TMCC signal detected by the error correction detection unit 44, the current state is set to normal synchronization, It is determined whether the mode is pseudo-synchronous or asynchronous (steps S302 and S3).
03). Then, the demodulation device performs this step S302,
If it is determined in step S303 that the state is asynchronous, the process returns to step S104 and the phase error correction process is performed again. If it is determined that the state is pseudo-synchronous, the oscillation in the frequency correction unit 32A is performed by the frequency step unit 46. After stepping the frequency (step S401),
Returning to step S104, the phase error correction process is performed again. On the other hand, the demodulation device performs steps S302 and S302.
If it is determined in step 303 that the state is normal synchronization, the process directly proceeds to the normal demodulation process (step S1).
05).

As described above, the demodulation device according to the seventh embodiment of the present invention is provided with the frequency pull-in detection unit 42, and the frequency correction unit 32A performs the frequency correction up to the frequency at which the phase correction unit 34A does not perform pseudo synchronization. After that, the phase correction unit 34A is reset and operated again. Further, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of the presence or absence of a bit error during the period of the frame synchronization signal / TMCC signal are performed, and whether or not normal synchronization is determined based on the detection result, In the case of the pseudo synchronization, the frequency of the frequency correction unit 32A is controlled so that the phase correction unit 34A can perform normal synchronization. Thereby, the frequency correction unit 32A
Phase correction unit 34 in the frequency pull-in process by
Avoidance of the pseudo-synchronization in A becomes possible.

(Eighth Embodiment) The demodulation device according to the eighth embodiment of the present invention is similar to the demodulation device according to the first embodiment in the same manner as the second to seventh embodiments. This is to avoid a malfunction due to the pseudo synchronization in the correction unit 34. The demodulation device according to the eighth embodiment controls the phase correction unit performed in the second embodiment and controls the frequency correction unit performed in the sixth embodiment. Hereinafter, a demodulation device according to an eighth embodiment of the present invention that avoids the above-described malfunction due to pseudo synchronization will be described.

[0229] Figure 45 is a claim 15,36,38,4
It is a block diagram corresponding to 6,64 which shows the structure of the demodulation device which concerns on 8th Embodiment of this invention. In FIG. 45, the demodulator according to the eighth embodiment includes a quadrature detector 31
, A frequency correction unit 32A, a band limiting filter 33,
The phase correction unit 34A, the frame synchronization detection unit 35, the timing generation unit 36, the frequency pull-in detection unit 42, the first phase synchronization detection unit 43A, and the second phase synchronization detection unit 4
3B, a pseudo-synchronization determination unit 45, and a frequency step unit 46
, A first error correction unit 37, and a second error correction unit 38
, A video decoder 39, a TMCC decoder 40,
A BER measuring unit 41;

As shown in FIG. 45, the demodulation device according to the eighth embodiment is different from the demodulation device according to the second embodiment in that
The configuration is a combination of the demodulation device according to the sixth embodiment. Therefore, the configuration of the demodulation device according to the eighth embodiment is the same as the configuration of the demodulation devices according to the second and sixth embodiments, and the same reference numerals are given and the description is omitted. Also, the processing steps performed by the demodulation device according to the eighth embodiment are basically the same as those of the demodulation device according to the seventh embodiment, and the flowchart is omitted.
4 will be described below.

The demodulator first detects a frame synchronization signal in the frame synchronization detection unit 35 for a signal input to the quadrature detection unit 31 via a tuner (not shown) (step S101). The frame head signal detected by the frame synchronization detection unit 35 is input to the timing generation unit 36. The demodulation device detects the period of the frame synchronization signal / TMCC signal and the period of the carrier synchronization auxiliary signal in one communication frame based on the frame head signal detected by the frame synchronization detection unit 35 in the timing generation unit 36, A BPSK timing signal corresponding to the period as shown in FIG. 6B is generated (step S10).
2). Note that a BPSK timing signal corresponding only to the period of the carrier synchronization auxiliary signal as shown in FIG. 6C may be used. This BPSK timing signal (FIG. 6B)
Is output to the frequency correction unit 32A, the phase correction unit 34A, and the frequency pull-in detection unit 42. Further, a signal giving the period of the carrier synchronization auxiliary signal shown in FIG.
A signal giving the period of the frame synchronization signal / TMCC signal shown in FIG.

Next, in the demodulation device, the frequency correction section 32A corrects the frequency error for the period of the BPSK timing signal (step S103). Then, the demodulation device calculates an averaged frequency error for the frequency-corrected signal in the frequency pull-in detection unit 42, and determines the frequency pull-in state (step S201). If the demodulation device determines in step S201 that the frequency has not been pulled in, the demodulation device proceeds to step S201.
Returning to step 103, the frequency error correction process is performed again. On the other hand, if it is determined that the frequency has been locked, the phase correction operation is reset for the phase correction unit 34A (step S304), and the phase error is newly corrected. A correction process is performed (Step S104).

When the above series of frequency error and phase error correction processing is completed, the demodulation device
, The current state is determined based on the phase synchronization state of the carrier synchronization auxiliary signal period detected by the first phase synchronization detection section 43A and the phase synchronization state of the TMCC signal period detected by the second phase synchronization detection section 43B. It is determined whether it is normal synchronization, pseudo synchronization, or asynchronous (step S30).
2, S303). Then, the demodulation device performs step S
If it is determined in steps 302 and 303 that the state is asynchronous, the process returns to step S104 to perform the phase error correction process again. If it is determined that the state is pseudo-synchronous, the frequency correction unit 32A is determined by the frequency step unit 46. (Step S40)
1) Returning to step S104, the phase error correction process is performed again. On the other hand, the demodulation device performs step S30
2. If it is determined in step S303 that the state is normal synchronization, the process directly proceeds to a normal demodulation process (step S105).

As described above, the demodulation device according to the eighth embodiment of the present invention is provided with the frequency pull-in detection unit 42, and the frequency correction unit 32A performs the frequency correction up to the frequency at which the phase correction unit 34A does not simulate the synchronization. After that, the phase correction unit 34A is reset and operated again. Further, detection of phase synchronization during the period of the carrier synchronization auxiliary signal and detection of phase synchronization during the period of the frame synchronization signal / TMCC signal are performed, and it is determined whether or not the synchronization is normal based on the detection result. , The frequency correction unit 32A
And normal synchronization can be performed by the phase correction unit 34A. This makes it possible to avoid pseudo-synchronization in the phase correction unit 34A during the frequency pull-in process by the frequency correction unit 32A.

(Ninth Embodiment) The demodulation device according to the ninth embodiment of the present invention is different from the demodulation device according to the first embodiment in that the effect of phase jitter due to phase noise is reduced. It improves performance. Therefore, the phase jitter of the demodulated signal when the phase is corrected using the BPSK-modulated frame synchronization signal / TMCC signal and the carrier synchronization auxiliary signal will be described first.

As shown in FIG. 46, the communication frame input to the demodulation device, that is, the phase modulated signal has a phase as shown in FIG. It fluctuates slightly. This phase change is called phase jitter. By the way, the communication frame transmitted from the modulator is shown in FIG.
As shown in (1), the frame synchronization signal / TMCC signal and the carrier synchronization auxiliary signal to be BPSK-modulated exist in a dispersed manner. Therefore, in order to perform carrier synchronization in the period of this signal in the demodulation device, the frequency correction unit 32 and the phase correction unit 34 are provided as described in the first embodiment.
The operation is performed only in the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period. This allows
The phase jitter is corrected during the period in which the phase corrector 34 operates, but is not corrected during other periods. That is, in the period of the main signal (high-layer signal and low-layer signal) modulated by BPSK, QPSK and 8PSK other than the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period, demodulation is performed without correcting the phase jitter. Phase jitter remains in the signal.

Therefore, for example, in an 8PSK modulated signal, the C / N is low as shown in FIG. 47 (the shaded circles in the figure correspond, and the smaller the circle, the higher the C / N and the larger the C / N, the higher the C / N). / N is low), if the phase jitter remains, the output signal of the phase correction unit 34 exceeds the phase boundary line (indicated by a dotted line in the figure) for identifying each code point. It will happen.

Hereinafter, a demodulation apparatus according to a ninth embodiment of the present invention for improving the reception performance by reducing the influence of the above-mentioned phase jitter will be described. Figure 48 is a claim 16,3
It is a block diagram corresponding to No. 6,47 which shows the structure of the demodulation device which concerns on the 9th Embodiment of this invention. In FIG. 48, the demodulation device according to the ninth embodiment includes a quadrature detection unit 31.
, Frequency correction unit 32, band limiting filter 33, phase correction unit 34B, frame synchronization detection unit 35, timing generation unit 36, frame synchronization determination unit 47, C / N
A detection unit 48, a gate signal selection unit 49, a first error correction unit 37, a second error correction unit 38, a video decoder 39, a TMCC decoder 40, and a BER measurement unit 41 are provided. FIG. 49 is a flowchart illustrating an operation performed by the demodulation device according to the ninth embodiment.

As shown in FIG. 48, the demodulation device according to the ninth embodiment is different from the demodulation device according to the first embodiment in that:
The configuration is such that a frame synchronization determination unit 47, a C / N detection unit 48, and a gate signal selection unit 49 are further added, and the phase correction unit 34 is replaced with a phase correction unit 34B. The rest of the configuration of the demodulation device according to the ninth embodiment is the same as the configuration of the demodulation device according to the first embodiment. Omitted. In FIG. 49, steps for performing the same processing as in FIG. 5 are denoted by the same step numbers, and description thereof is omitted.

First, the operation of the frame synchronization determination section 47 will be described with reference to FIG. FIG. 50 is a block diagram illustrating a configuration of the frame synchronization determination unit 47. In FIG. 50, the frame synchronization determination unit 47 includes a phase identification unit 471,
And a collating unit 472. A signal input via a tuner (not shown) is subjected to frequency correction and phase correction as described in the first embodiment (step S1).
03, S104), the phase correction unit 34B to the phase identification unit 4
71 is input. The phase identifying section 471 identifies the phase of the input signal. The collation unit 353 includes a phase identification unit 471
Is compared with a predetermined frame synchronization signal to detect whether or not frame synchronization has been achieved, and outputs the result to the gate signal selection unit 49 (step S501).

Next, referring to FIG. 51, C / N detector 4
8 will be described. FIG. 51 is a block diagram showing a configuration of the C / N detection unit 48.
/ N is detected. 51, the C / N detector 48 includes a phase error detector 481 and an absolute value generator 48.
2, a switching unit 483, a constant generation unit 484, and an adder 4
85a, a delay section 485b, a switching section 485c, and a constant generating section 485d, an integrating section 485, a timing generating section 486, and a C / N high level determining section 487.

A signal input via a tuner (not shown) is subjected to frequency correction and phase correction as described in the first embodiment (steps S103 and S10).
4), input from the phase correction unit 34B to the phase error detection unit 481. As described above, the phase error detection unit 481
The phase difference from the mark x when there is a frequency shift is the phase error ΔΦ
[Degree] (see FIG. 19). The phase error ΔΦ detected by the phase error detection unit 481 is calculated by the absolute value conversion unit 482
Is converted to a positive value | ΔΦ | The phase error | ΔΦ | output from the absolute value conversion unit 482 is
3, and is input to the adder 485a, and the phase error | ΔΦ | is averaged every certain period. Here, since C / N detection is performed only during the period of the BPSK-modulated carrier synchronization auxiliary signal in one communication frame, the timing signal output from the timing generation unit 36 (FIG. 6).
Switching of the switching unit 483 is performed using (c)). The switching unit 483 inputs the phase error | ΔΦ | output by the absolute value conversion unit 482 to the integration unit 485 during the period of the BPSK modulation signal of the timing signal (Hi level period in FIG. 6C), During the period, switching is performed so that “constant 0” generated by the constant generation unit 484 is input to the integration unit 485. The timing generating section 486 generates a timing pulse having a constant period, and controls the switching section 485c. The integrator 485 outputs the input of the adder 485a to the delay unit 48 according to the timing pulse generated by the timing generator 486.
By switching to either the feedback output of 5b or the “constant 0” generated by the constant generation section 485d, an averaged phase error | ΔΦ | C /
The N high level determination unit 487 receives the averaged phase error output from the integration unit 485 and determines whether or not the averaged phase error falls below a predetermined threshold when the timing generation unit 486 generates a timing pulse. It is determined whether the C / N is high or low (step S502). Then, as a result of this determination, when the averaged phase error falls below a predetermined threshold, the C / N high level determination unit 487 determines whether the C / N
Is high, and the result is output to the gate signal selection unit 49.

Here, as for the threshold value in C / N high level determination section 487, the phase correction section 34 uses a modulation method having a large number of phases at low C / N to perform phase correction.
The determination must be made so that the phase error detection unit 341 in B does not output erroneous phase error information. For example, the n-phase PSK inter-symbol distance D is represented by the following equation (4), where A is the amplitude of the n-phase PSK signal. D = 2 · A · sin (π / n) ‥‥ (4) Based on this equation (4), the distance D between n-phase PSK codes is
D = 2A for BPSK modulation and D = √ for QPSK modulation.
For 2A and 8PSK modulation, D = 2A sin (π / 8). Generally, as shown in FIG. 47, if the effective amplitude value of the noise is equal to or less than １ ／ of the intersymbol distance D, it is considered that the phase error detection unit 341 does not output erroneous phase error information. Is expressed by the following equation (5). C / N = 20 · log (A / (D / 2)) [dB] ‥‥ (5) The C / N high level threshold value determines whether or not to perform phase correction in the 8PSK period. . Therefore, in the above equation (5), 8.3 dB obtained by substituting the inter-symbol distance of 8PSK into the n-phase PSK intersymbol distance D is a measure of the C / N high level threshold. The C / N detecting section 48 in FIG. 51 converts the phase error into an absolute value to obtain the C / N equivalently, and this 8.3 dB is obtained.
The threshold value in the C / N high-level determination unit 487 corresponding to is の of the angle difference between adjacent phase identification boundary lines (dotted line in FIG. 47) at the code point of 8PSK, that is, 11.25 [degrees]. Becomes

Next, the operation of gate signal selecting section 49 will be described with reference to FIG. FIG. 52 is a block diagram showing a configuration of gate signal selecting section 49. In FIG. 52,
The gate signal selection unit 49 includes an AND circuit 491, a constant generation unit 492, and a switching unit 493.

The one input terminal of the AND circuit 491 has
The determination result output from the frame synchronization determination unit 47 is input to the other input terminal, and the detection result output from the C / N detection unit 48 is input to the other input terminal. The switching unit 493 converts the timing signal (FIG. 6B or 6C) during the BPSK modulation signal period, which is the output signal of the timing generation unit 36, and the “constant 1 (Hi level)” generated by the constant generation unit 492. The output is switched based on a signal input by the AND circuit 491. Here, the switching unit 493 determines that the determination result output from the frame synchronization determination unit 47 is “with synchronization”
The detection result output by the / N detection unit 48 is “C / N is high”
, A gate signal for instructing the execution of the phase correction operation in the entire period of the communication frame is output (step S503), otherwise, the output signal of the timing generation unit 36 is output. , Ie, BP
A gate signal (FIG. 6 (b) or (c)) for instructing the execution of the phase correction operation only in the SK period is output (step S).
504). This gate signal is output to the phase error holding unit 342 of the phase correction unit 34B.

Next, the operation of the phase correction section 34B will be described. The phase correction unit 34B is different from the phase correction unit 34 of the demodulation device according to the first embodiment in that
Only the configuration of 41 is different. Therefore, the operation of the phase error detection unit 341 will be described below with reference to FIGS. FIG. 53 is a block diagram illustrating a configuration of the phase error detection unit 341. In FIG. 53, the phase error detection unit 34
1 includes a BPSK phase error detection unit 341a, an 8PSK phase error detection unit 341b, and a switching unit 341d.
FIG. 54 shows BPSK phase error detectors 341a and 8P
FIG. 14 is a diagram illustrating phase error detection performed by an SK phase error detection unit 341b.

The output of the complex multiplier 344 including the phase error is input to both the BPSK phase error detector 341a and the 8PSK phase error detector 341b. The BPSK phase error detection unit 341a outputs the BPSK modulation axis (0 degree, 18 degrees).
0 °) is detected (FIG. 54 (a)).
The 8PSK phase error detection unit 341b outputs the 8PSK modulation axes (0, 45, 90, 135, 180, and 225).
, 270 degrees, and 315 degrees) (FIG. 54B). The switching unit 341d uses the timing signal output from the timing generation unit 36 to output the phase error detected by the BPSK phase error detection unit 341a during the timing signal period (BPSK modulation period), and the 8PSK phase during the other periods. Switching is performed so that the phase error detected by the error detection unit 341b is output to the phase error holding unit 342.

The operation after the phase error holding unit 342 is the same as that described in the first embodiment, except that the timing generation unit 36 Instead of using the timing signal (gate signal), the gate signal output from the gate signal selection unit 49 is used (see FIG. 48).

As a result, the phase corrector 34B can perform phase correction based on the C / N state according to the timing signal and the gate signal (step S50).
5). The contents are shown in Table 3 below. In Table 3 below, the “BPSK synchronization signal period” refers to both the period of the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period (when the timing signal of FIG. 6B is used) or the carrier. 6 shows a period of only the synchronization auxiliary signal period (when the timing signal of FIG. 6C is used).

[Table 3]

As described above, the demodulation device according to the ninth embodiment of the present invention determines the C / N state when the phase is synchronized in the BPSK modulation signal period based on the phase error in the carrier synchronization auxiliary signal period. If the C / N is at a predetermined level, the phase error is corrected on the assumption that 8PSK modulation is also performed for the main signal period of the communication frame. As a result, carrier synchronization can be performed stably at high speed even in the low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

The phase error detecting section 481 of the C / N detecting section 48 is the same as the phase error detecting section 34 of the phase correcting section 34B.
Since it has the same function as that of No. 1, it is possible to share both phase error detection units. If shared,
The circuit scale can be reduced. Further, since the frame synchronization determination unit 47 is an example of a method for determining phase synchronization, the same effect can be obtained even if the phase synchronization detection unit 43 described in the third embodiment is used instead of the frame synchronization determination unit 47. Is obtained.

(Tenth Embodiment) The demodulation device according to the tenth embodiment of the present invention is the same as the ninth embodiment described above, except that the demodulation device according to the first embodiment is caused by phase noise. In this case, the effect of the phase jitter is reduced to improve the reception performance. Hereinafter, a demodulation device according to a tenth embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter will be described.

FIG. 55 is a block diagram showing a configuration of a demodulation device according to a tenth embodiment of the present invention, which corresponds to claims 17 , 36, and 48 . In FIG. 55, the demodulator according to the tenth embodiment includes a quadrature detector 31, a frequency corrector 32, a band limiting filter 33, and a phase corrector 34.
C, the frame synchronization detection unit 35, and the timing generation unit 3
6, an error correction detection unit 44, and a frame synchronization determination unit 47
, C / N detector 48A, and gate signal selector 49A
, Demodulation mode switching section 50, and first error correction section 37
A second error correction unit 38, a video decoder 39,
It includes a TMCC decoder 40 and a BER measuring unit 41. FIG. 56 is a flowchart showing the operation performed by the demodulation device according to the tenth embodiment.

As shown in FIG. 55, the demodulation device according to the tenth embodiment differs from the demodulation device according to the first embodiment in that the error correction detection unit 44, the frame synchronization determination unit 47, and the C
/ N detection unit 48A, gate signal selection unit 49A, and demodulation mode switching unit 50, and the phase correction unit 34 is replaced with a phase correction unit 34C. The demodulation device according to the ninth embodiment is also provided. , An error correction detection unit 44 and a demodulation mode switching unit 50 are further added.
8 is replaced by a C / N detector 48A, and the gate signal selector 49 is replaced by a gate signal selector 49A. The first
Other configurations of the demodulation device according to the zeroth embodiment are the same as the configurations of the demodulation devices according to the first and ninth embodiments, and the components are denoted by the same reference numerals and will not be described. Omitted. In FIG. 56, steps for performing the same processing as in FIGS. 5 and 49 are denoted by the same step numbers, and description thereof is omitted.

First, the operation of the error correction detector 44 will be described. The error correction detection unit 44 includes the second error correction unit 3
Reference numeral 8 inputs a signal indicating that the error cannot be corrected and a signal indicating that the error remains, which are output during the error correction process. Then, the error correction detection unit 44 detects whether or not correct error correction has been performed on the TMCC signal, and outputs the result of this detection to the gate signal selection unit 49A (step S60).
1).

Next, referring to FIG. 57, C / N detector 4
The operation of 8A will be described. FIG. 57 shows a C / N detector 48A.
FIG. 3 is a block diagram showing a configuration of the present embodiment, which detects C / N equivalently based on a phase error. In FIG. 57, C /
The N detection unit 48A includes a phase error detection unit 481, an absolute value conversion unit 482, a switching unit 483, a constant generation unit 484, an adder 485a, a delay unit 485b, a switching unit 485c, and a constant generation unit 485d. An integration unit 485, a timing generation unit 486, a C / N high level determination unit 487,
A C / N low level determination unit 488 is provided.

As shown in FIG. 57, the C / N detector 48A
Is the configuration of the C / N detector 48 of the ninth embodiment,
This is a configuration in which a C / N low level determination unit 488 is further added. The C / N high level determination unit 487 receives the averaged phase error output from the integration unit 485 and inputs the averaged phase error.
6 generates a timing pulse, it is determined whether the C / N is high based on whether or not the averaged phase error is below a predetermined first threshold (step S502). If the result of this determination is that the averaged phase error falls below a predetermined first threshold, the C / N high level determination unit 4
87 determines that the C / N is high, and outputs the result to the gate signal selection unit 49A. On the other hand, the C / N low level determination unit 488 receives the averaged phase error output from the integration unit 485, and when the timing generation unit 486 generates a timing pulse, the averaged phase error has a second predetermined value. It is determined whether the C / N is low based on whether or not the threshold is exceeded (step S602). Then, as a result of this determination, when the averaged phase error exceeds a second predetermined threshold value, C / N high level determination section 488 determines that C / N is low, and outputs the result to the gate signal. Output to selection section 49A.

Here, for example, the C / N high level judgment section 4
The first threshold value in 87 may be determined using 11.25 [degrees] as a guide as described above. Also, C
The / N low level threshold value determines whether or not to perform phase correction only during the BPSK period. Therefore, in the above equation (5), QPSK is added to the distance D between the n-phase PSK codes.
3 dB obtained by substituting the inter-code distance is a standard of the C / N low level threshold. The threshold value in the C / N low level determination unit 488 corresponding to 3 dB is
At the code point of QPSK, it is の of the angle difference between adjacent phase identification boundaries, that is, 22.5 [degrees]. Therefore, in this case, the output of the C / N detector 48A is as shown in Table 4 below.

[Table 4]

Next, the operation of gate signal selecting section 49A will be described with reference to FIG. FIG. 58 is a block diagram showing a configuration of gate signal selection section 49A. In FIG. 58, gate signal selecting section 49A includes AND circuits 491, 4
95, a constant generation unit 492, switching units 493, 494
And OR circuits 496 and 497.

The switching unit 493 outputs the BPSK of the main signal input from the TMCC decoder 40 via the OR circuit 497.
A timing signal giving both the modulation period and the QPSK modulation period and “constant 1” generated by the constant generation unit 492 are input, and the output is made based on the determination result output by the C / N high level determination unit 487. Switch. Switching unit 494
Is the BP of the main signal input from the TMCC decoder 40.
The timing signal of the SK modulation period and the signal output by the switching unit 493 are input, and the output is switched based on the determination result output by the C / N low level determination unit 488. Here, when the C / N determination is “high”, switching units 493 and 494 output “constant 1”, that is, a gate signal that instructs execution of the phase correction operation during the entire period of the communication frame (step S503). When the C / N determination is "medium", the timing signal of the main signal during the QPSK and BPSK modulation periods is set (step S603). When the C / N determination is "low", the timing signal during the BPSK modulation period of the main signal is used. (Step S504) is switched to output. On the other hand, A
The determination result output by the frame synchronization determination unit 47 and the detection result output by the error correction detection unit 44 are input to the ND circuit 491. The output of the AND circuit 491 is input to the AND circuit 495 together with the signal output from the switching unit 494. Also, the OR circuit 496 has
The output of the D circuit 495 and the BPSK timing signal output by the timing generator 36 are input. Therefore, AND
The circuits 491 and 495 and the OR circuit 496 output the output signal of the switching unit 494 as a gate signal only when the phase is synchronized and the TMCC is correctly corrected. The BPSK timing signal (FIG. 6B or 6C) is output as a gate signal. This gate signal is supplied to the phase correction unit 34
It is output to the phase error holding unit 342 of C.

Next, the operation of the demodulation mode switching section 50 will be described with reference to FIG. FIG. 59 is a diagram showing each timing signal input to the demodulation mode switching unit 50 and the demodulation mode signal output. The demodulation mode switching unit 50 receives the timing signal (FIG. 59 (a)) of the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period from the timing generation unit 36, and the main signal QPSK timing signal (FIG. 59 ( b)), main signal BP
An SK timing signal (FIG. 59 (c)) is input. Based on these timing signals, the demodulation mode switching unit 50 performs a first demodulation mode signal (FIG. 59 (d)) indicating the period of the BPSK modulation signal and a second demodulation mode signal indicating the period of the QPSK modulation signal. A signal (FIG. 59 (e)) is generated and output to the phase error detection unit 341. The first and second demodulation mode signals are used to switch the demodulation mode of the phase error detection unit 341.

Next, the operation of the phase correction section 34C will be described. This phase correction unit 34C is different from the phase correction unit 34 of the demodulation device according to the first embodiment in that
Only the configuration of 41 is different. Therefore, the operation of the phase error detection unit 341 will be described below with reference to FIGS. FIG. 60 is a block diagram illustrating a configuration of the phase error detection unit 341. In FIG. 60, the phase error detection unit 34
Reference numeral 1 denotes a BPSK phase error detector 341a, a QPSK phase error detector 341b, and an 8PSK phase error detector 34.
1c, and switching units 341d and 341e. FIG.
Are the BPSK phase error detector 341a, the QPSK phase error detector 341b, and the 8PSK phase error detector 341.
It is a figure explaining phase error detection performed by c.

The output of complex multiplication section 344 including the phase error is output to BPSK phase error detection section 341a, QPSK phase error detection section 341b and 8PSK phase error detection section 341.
c. BPSK phase error detector 341
“a” detects a phase error with respect to the BPSK modulation axis (0 °, 180 °) (FIG. 61A). The QPSK phase error detection unit 341b outputs the QPSK modulation axis (45 degrees, 135 degrees,
225 degrees and 315 degrees) (FIG. 61 (b)). 8PSK phase error detection section 341c
PSK modulation axis (0 degree, 45 degree, 90 degree, 135 degree, 18
Phase errors corresponding to 0, 225, 270, and 315 degrees are detected (FIG. 61 (c)). The switching unit 341d uses the second demodulation mode signal (see FIG. 59 (c)) output from the demodulation mode switching unit 50, and outputs the Q signal during the Hi signal period.
The phase error detected by the PSK phase error detection unit 341b is
During the other periods, switching is performed so that the phase error detected by the 8PSK phase error detection unit 341c is output to the switching unit 341e. The switching unit 341e uses the first demodulation mode signal (see FIG. 59 (d)) output from the demodulation mode switching unit 50 to control the BPSK phase error detection unit 34 during the Hi signal period.
The phase error detected by 1a is switched so that the phase error output from the switching unit 341d is output to the phase error holding unit 342 during the other periods. That is, BPSK> QP
The demodulation mode of the phase error detection unit 341 is switched in the priority order of SK> 8PSK.

The operation after the phase error holding section 342 is the same as that described in the first embodiment, except that the timing generation section 36 outputs a signal for controlling the switching section 342a and the holding section 342f. Not a timing signal (gate signal), but a gate signal selector 49A
Are used (see FIG. 55).

Thus, the phase corrector 34C operates according to the first and second demodulation mode signals and the gate signal.
Phase correction can be performed based on the state of C / N (step S505). The contents are shown in Table 5 below. In Table 5 below, "BPSK synchronization signal period"
6B, the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period (when the timing signal of FIG. 6B is used), or the carrier synchronization auxiliary signal period alone (FIG. 6C). (When a timing signal is used).

[Table 5]

As described above, the demodulation device according to the tenth embodiment of the present invention determines the C / N state when the phase is synchronized in the BPSK modulation signal period based on the phase error in the carrier synchronization auxiliary signal period. According to the C / N state and the reference phase corresponding to the plurality of phase modulation schemes provided in the phase error detection section 341, the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal which are BPSK-modulated in the initial carrier wave recovery. The phase correction is performed using the signal period, and after the phase synchronization, the phase correction is performed also in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the influence of the phase jitter of the demodulated signal during the period of the main signal subjected to BPSK, QPSK and 8PSK modulation is reduced, and Performance can be improved.

The phase error detecting section 481 of the C / N detecting section 48A is the same as the phase error detecting section 3 of the phase correcting section 34C.
Since it has the same function as 41, both phase error detectors can be shared. When shared, the circuit scale can be reduced. Further, the frame synchronization determination unit 47 is an example of a method of determining phase synchronization.
The same effect can be obtained by using the phase synchronization detection unit 43 described in the embodiment.

(Eleventh Embodiment) The demodulation device according to the eleventh embodiment of the present invention is the same as the ninth and tenth embodiments described above, except that the demodulation device according to the first embodiment has The purpose is to reduce the influence of phase jitter caused by noise and improve the reception performance. Hereinafter, a description will be given of a demodulation device according to an eleventh embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter.

FIG. 62 is a block diagram showing a configuration of a demodulator according to an eleventh embodiment of the present invention, corresponding to claims 18 , 36 and 49 . 62, the demodulation device according to the eleventh embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band-limiting filter 33, and a phase correction unit 34.
C, the frame synchronization detection unit 35, and the timing generation unit 3
6, an error correction detection unit 44, and a frame synchronization determination unit 47
, C / N detector 48A, and gate signal selector 49B
, Demodulation mode switching section 50A, and first error correction section 37
A second error correction unit 38, a video decoder 39,
It includes a TMCC decoder 40 and a BER measuring unit 41. FIG. 63 is a flowchart showing the operation performed by the demodulation device according to the eleventh embodiment.

As shown in FIG. 62, the demodulation device according to the eleventh embodiment is different from the demodulation device according to the first embodiment in that the error correction detection unit 44, the frame synchronization determination unit 47, and the C
/ N detection unit 48A, gate signal selection unit 49B, and demodulation mode switching unit 50A, and the phase correction unit 34 is replaced with a phase correction unit 34C. The demodulation device according to the tenth embodiment is also described. For the gate signal selection unit 4
9A to the gate signal selection unit 49B and the demodulation mode switching unit 5
0 is replaced by the demodulation mode switching unit 50A. The other configuration of the demodulation device according to the eleventh embodiment is the same as the configuration of the demodulation device according to the first and ninth to tenth embodiments, and the same reference numerals are used for the components. The description is omitted here. FIG. 63
In FIG. 5, steps that perform the same processing as in FIGS. 5, 49 and 56 are denoted by the same step numbers, and description thereof is omitted.

First, the operation of gate signal selecting section 49B will be described with reference to FIG. FIG. 64 is a block diagram showing a configuration of the gate signal selection unit 49B. In FIG. 64, gate signal selecting section 49B includes AND circuits 491, 4
91a, 495, constant generation units 492, 492a, switching units 493, 494, 499, and OR circuits 496, 49
7 and a NOT circuit 498.

In the gate signal selecting section 49B, the operations up to the output of the OR circuit 496 are as described in the tenth embodiment. The AND circuits 491 and 495 and the OR circuit 496 achieve the phase synchronization and the TMCC
The output signal of the switching unit 494 is output as a gate signal only when is corrected correctly, otherwise, the BPSK timing signal (FIG. 6B or 6C) is output as a gate signal as before. Is done. On the other hand, AND
The circuit 491a includes a signal of the opposite logic of the determination result output by the C / N high level determination unit 487, the determination result output by the frame synchronization determination unit 47, and the detection result output by the error correction detection unit 44 (by the NOT circuit 498). (The logical value is inverted). The switching unit 499 outputs the frame synchronization signal / TMCC
The timing signal of the signal period and the carrier synchronization auxiliary signal period and “constant 1” generated by the constant generation unit 492a are input, and the output is switched based on the output of the AND circuit 491a. Here, the switching unit 499 performs phase synchronization,
When the TMCC is not correctly corrected and in the high C / N state, the “constant 1” generated by the constant generation unit 492a is output. Otherwise, the signal output by the OR circuit 496 is output. Switching is performed so as to output as a gate signal (step S701). Thereby, even when the TMCC is not correctly corrected, that is, when the signal indicating the timing of the main signal generated from the TMCC decoder 40 is unreliable, the phase synchronization is maintained and the high C / C
If the state is the N state, “constant 1” instructing execution of the phase correction operation is output as a gate signal during the entire period of the communication frame (step S702). In addition, low C /
If it is in the N state, a signal during the BPSK period is output as a gate signal (step S703). This gate signal is output to the phase error holding unit 342 of the phase correction unit 34C.

Next, the operation of demodulation mode switching section 50A will be described with reference to FIG. FIG. 65 is a block diagram illustrating a configuration of the demodulation mode switching unit 50A. In FIG. 65, demodulation mode switching section 50A includes AND circuits 501-5.
03 and an OR circuit 504. AND circuit 501
Inputs the determination result output by the frame synchronization determination unit 47 and the detection result output by the error correction detection unit 44. AN
The D circuit 502 receives the main signal BPSK timing signal (FIG. 5).
9 (c)) and the output of the AND circuit 501. AND circuit 503 receives the main signal QPSK timing signal (see FIG. 59B) and the output of AND circuit 501, and outputs a logical result as a second demodulation mode signal. The OR circuit 504 outputs the frame synchronization signal / TMCC
A timing signal (see FIG. 59A) in the signal period and the carrier synchronization auxiliary signal period and an output of the AND circuit 502 are input, and a logical result is output as a first demodulation mode signal.

As described above, the gate signal selection section 49B and the demodulation mode switching section 50A control the phase correction section 34C so that the TMCC signal is correctly corrected, and the phase correction corresponding to each modulation method of the main signal is performed. Before you do,
In the case of the high C / N state, as described in the ninth embodiment, the period of the main signal is regarded as 8PSK, and the phase is corrected (steps S704 and S601). After that, in the same manner as described in the tenth embodiment, phase correction is performed for each modulation method (step S502).
To S505, S602 to S603). The contents are shown in Table 6 below. In the following Table 6, “BPSK synchronization signal period” refers to both the frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period (see FIG.
FIG. 6B shows a case where the timing signal of FIG. 6C is used, or a period of only the carrier synchronization auxiliary signal period (when the timing signal of FIG. 6C is used).

[Table 6]

As described above, in the demodulation device according to the eleventh embodiment of the present invention, the C / N state when the phase is synchronized in the BPSK modulation signal period is based on the phase error in the carrier synchronization auxiliary signal period. If the C / N is at a predetermined level, the C / N is 8
The phase error is corrected assuming that the PSK modulation has been performed, and the frame synchronization signal / BPSK modulated by the BPSK modulation in the initial carrier wave reproduction according to the reference phase corresponding to a plurality of phase modulation methods provided in the phase error detection unit 341. TM
The phase correction is performed using the CC signal period and the carrier synchronization auxiliary signal period, and after the phase synchronization, the phase correction is also performed in the modulation period of the main signal other than the period. Thereby, low C
/ N state, carrier synchronization can be performed quickly and stably, and BPSK, QPSK and 8PS
It is possible to reduce the influence of the phase jitter of the demodulated signal during the period of the K-modulated main signal and improve the reception performance.

(Twelfth Embodiment) The demodulation device according to the twelfth embodiment of the present invention is the same as the ninth to eleventh embodiments, except that the The purpose is to reduce the influence of phase jitter caused by noise and improve the reception performance. Hereinafter, a demodulation device according to a twelfth embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter will be described.

FIG. 66 is a block diagram showing a configuration of a demodulator according to a twelfth embodiment of the present invention, corresponding to claims 19 , 36, and 50 . In FIG. 66, the demodulation device according to the twelfth embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, and a phase correction unit 34.
C, the frame synchronization detection unit 35, and the timing generation unit 3
6, a frame synchronization determination unit 47, and a BER detection unit 51
, A gate signal selection unit 49, and a first error correction unit 37.
A second error correction unit 38, a video decoder 39,
It includes a TMCC decoder 40 and a BER measuring unit 41.

As shown in FIG. 66, the demodulation device according to the twelfth embodiment differs from the demodulation device according to the first embodiment in that a frame synchronization determination unit 47, a BER detection unit 51, a gate signal selection unit 49 In addition, the phase correction unit 34 is replaced with a phase correction unit 34C, and the C / N detection unit 48 is replaced with a BER detection unit 51 in the demodulation device according to the ninth embodiment. Configuration. The rest of the configuration of the demodulation device according to the twelfth embodiment is the same as the configuration of the demodulation devices according to the first and ninth embodiments, and the components are denoted by the same reference numerals. The description is omitted. Also, the processing steps performed by the demodulation device according to the twelfth embodiment are the same as the processing steps shown in FIG. 49 in the ninth embodiment, and thus description thereof will be omitted.

Hereinafter, a BER detecting section 51 having a different configuration will be described.
Will be described with reference to FIG. FIG. 67 is a block diagram illustrating a configuration of the BER detection unit 51. In FIG. 67, BER detection section 51 includes error correction re-encoding section 511.
And a comparison unit 512 and a C / N high level determination unit 513.

The error correction re-encoding unit 511 receives the error-corrected TMCC signal output from the second error correction unit 38. Then, the error correction re-encoding unit 511
Based on the timing signal of the frame synchronization signal / TMCC signal period, the input error-corrected TMCC signal is re-encoded. The comparison unit 512 receives the re-encoded TMCC signal output from the error correction re-encoding unit 511 and the uncorrected signal output from the phase correction unit 34C. Then, the comparing unit 512, based on the timing signal of the frame synchronization signal / TMCC signal period,
The period of the TMCC signal is extracted from the signal output by the phase corrector 34C, and the bit error rate is calculated by comparing the uncorrected TMCC signal with the re-encoded TMCC signal. C / N high level determining section 513 receives the bit error rate output from comparing section 512, and determines whether the bit error rate is below a predetermined threshold value.
It is determined whether N is high or low (FIG. 49, step S50)
2). Then, as a result of this determination, if the bit error rate falls below a predetermined threshold, C / N high level determination section 513 determines that C / N is high, and sends the result to gate signal selection section 49. Output to

Here, as for the threshold value in C / N high level determination section 513, as described in the ninth embodiment, a modulation method having a large number of phases at low C / N is used for phase correction. Thus, the phase error detection unit 341 in the phase correction unit 34C must determine such that the erroneous phase error information is not output. For example, a threshold value will be calculated for the value 11.25 deg used in the ninth embodiment. As described above, 11.25 de
C / N in g is 8.3 dB from the above equation (5). On the other hand, the relationship between the C / N and the bit error rate in BPSK modulation is generally known to be as shown in FIG. 68. Therefore, when the bit error rate at 8.3 dB is read from FIG. 1 × 10 ^-4 is obtained.
Therefore, the threshold value may be set to approximately 1 × 10 ⁻⁴ .

As described above, the demodulation device according to the twelfth embodiment of the present invention detects the C / N state when the phase is synchronized during the BPSK modulation signal period based on the bit error rate of the TMCC signal. However, when the C / N is at a predetermined level, 8P is also applied to the main signal period of the communication frame.
The phase error is corrected assuming that the SK modulation is performed. As a result, carrier synchronization can be performed stably at high speed even in the low C / N state, and the effect of the phase jitter of the demodulated signal can be reduced to improve the reception performance.

(Thirteenth Embodiment) The demodulation device according to the thirteenth embodiment of the present invention is the same as the ninth to twelfth embodiments, except that the demodulation device according to the first embodiment has The purpose is to reduce the influence of phase jitter caused by noise and improve the reception performance. Hereinafter, a demodulation device according to a thirteenth embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter will be described.

FIG. 69 is a block diagram showing a configuration of a demodulation device according to a thirteenth embodiment of the present invention, corresponding to claims 20 , 36, and 51 . In FIG. 69, the demodulator according to the thirteenth embodiment includes a quadrature detector 31, a frequency corrector 32, a band limiting filter 33, and a phase corrector 34.
C, the frame synchronization detection unit 35, and the timing generation unit 3
6, an error correction detection unit 44, and a frame synchronization determination unit 47
BER detection unit 51A, gate signal selection unit 49A
, Demodulation mode switching section 50, and first error correction section 37
A second error correction unit 38, a video decoder 39,
It includes a TMCC decoder 40 and a BER measuring unit 41.

As shown in FIG. 69, the demodulation device according to the thirteenth embodiment is different from the demodulation device according to the first embodiment in that an error correction detection unit 44, a frame synchronization determination unit 47,
An ER detection unit 51A, a gate signal selection unit 49A, and a demodulation mode switching unit 50 are further added, and the phase correction unit 34 is replaced with a phase correction unit 34C. In the demodulation device according to the tenth embodiment, On the other hand, the configuration is such that the C / N detector 48A is replaced with a BER detector 51A. The thirteenth
Other configurations of the demodulation device according to the embodiment
The configuration is the same as that of the demodulation device according to the tenth embodiment, and the same components are denoted by the same reference numerals and description thereof is omitted. Also, the processing steps performed by the demodulation device according to the thirteenth embodiment are the same as the processing steps shown in FIG. 56 in the tenth embodiment.
The description is omitted.

Hereinafter, a BER detecting section 51 having a different configuration will be described.
A will be described with reference to FIG. FIG. 70 is a block diagram illustrating a configuration of the BER detection unit 51A. 70, a BER detection unit 51A includes an error correction re-encoding unit 51
1, a comparison unit 512, and a C / N high level determination unit 513
And a C / N low level determination unit 514.

The error correction re-encoding unit 511 receives the error-corrected TMCC signal output from the second error correction unit 38. Then, the error correction re-encoding unit 511
Based on the timing signal of the frame synchronization signal / TMCC signal period, the input error-corrected TMCC signal is re-encoded. The comparison unit 512 receives the re-encoded TMCC signal output from the error correction re-encoding unit 511 and the uncorrected signal output from the phase correction unit 34C. Then, the comparing unit 512, based on the timing signal of the frame synchronization signal / TMCC signal period,
The period of the TMCC signal is extracted from the signal output by the phase corrector 34C, and the bit error rate is calculated by comparing the uncorrected TMCC signal with the re-encoded TMCC signal. C / N high level determination section 513 receives the bit error rate output from comparison section 512, and determines whether the C / N is high based on whether the bit error rate falls below a predetermined first threshold. Judgment (FIG. 56, step S50)
2). On the other hand, C / N low level determining section 514 receives the bit error rate output from comparing section 512 and determines whether the C / N is low based on whether or not the bit error rate exceeds a predetermined second threshold value. (FIG. 56, step S
602). When the bit error rate falls below a predetermined first threshold value as a result of this determination, C / N
High-level determining section 513 determines that C / N is high, outputs the result to gate signal selecting section 49A, and when the bit error rate exceeds a predetermined second threshold value,
/ N low level determination unit 514 determines that C / N is low,
The result is output to gate signal selection section 49A.

Here, for example, the C / N high level judgment section 5
The first threshold value at 13 may be 1 × 10 ⁻⁴ as described above. Further, the second threshold value in C / N low level determination section 514 is determined by the first threshold value.
0 at the value of 22.5 [deg] used in the embodiment of FIG.
When read from FIG. 68 according to / N = 3 dB, 2.3 ×
10 ^-2 is obtained. Therefore, the first threshold value is 1 × 10
^-4 and the second threshold value may be set at 2.3 × 10 ^-2 as a guide.

As described above, the demodulation device according to the thirteenth embodiment of the present invention detects the C / N state when the phase is synchronized during the BPSK modulation signal period based on the bit error rate of the TMCC signal. However, according to the C / N state and the reference phase corresponding to a plurality of phase modulation schemes provided in the phase error detection section 341, BPSK is performed in the initial carrier wave recovery.
The phase correction is performed using the frame synchronization signal / TMCC signal period to be modulated and the carrier synchronization auxiliary signal period, and after the phase synchronization, the phase correction is also performed in the modulation period of the main signal other than the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the influence of the phase jitter of the demodulated signal during the period of the main signal subjected to BPSK, QPSK and 8PSK modulation is reduced, and Performance can be improved.

(Fourteenth Embodiment) The demodulation device according to the fourteenth embodiment of the present invention is the same as the ninth to thirteenth embodiments, except that the demodulation device according to the first embodiment has a phase The purpose is to reduce the influence of phase jitter caused by noise and improve the reception performance. Hereinafter, a demodulation device according to a fourteenth embodiment of the present invention that improves the reception performance by reducing the influence of the above-described phase jitter will be described.

FIG. 71 is a block diagram showing a configuration of a demodulation apparatus according to a fourteenth embodiment of the present invention, corresponding to claims 21 , 36, and 52 . 71, the demodulation device according to the fourteenth embodiment includes a quadrature detection unit 31, a frequency correction unit 32, a band limiting filter 33, and a phase correction unit 34.
C, the frame synchronization detection unit 35, and the timing generation unit 3
6, an error correction detection unit 44, and a frame synchronization determination unit 47
, BER detection section 51A, and gate signal selection section 49B
, Demodulation mode switching section 50A, and first error correction section 37
A second error correction unit 38, a video decoder 39,
It includes a TMCC decoder 40 and a BER measuring unit 41.

As shown in FIG. 71, the demodulation device according to the fourteenth embodiment is different from the demodulation device according to the first embodiment in that an error correction detection unit 44, a frame synchronization determination unit 47,
An ER detection unit 51A, a gate signal selection unit 49B, and a demodulation mode switching unit 50A are further added, and the phase correction unit 34 is replaced with a phase correction unit 34C. In the demodulation device according to the eleventh embodiment, On the other hand, the C / N detector 48A
Is replaced by a BER detection unit 51A. The first
Other configurations of the demodulation device according to the fourth embodiment are the same as the configurations of the demodulation devices according to the first and eleventh embodiments, and the same components are denoted by the same reference numerals and will not be described. Omitted. Also, the processing steps performed by the demodulation device according to the fourteenth embodiment are the same as the processing steps shown in FIG. 63 in the eleventh embodiment, and thus description thereof will be omitted.

As described above, the demodulation device according to the fourteenth embodiment of the present invention detects the C / N state when the phase is synchronized during the BPSK modulation signal period based on the bit error rate of the TMCC signal. However, when the C / N is at a predetermined level, it is assumed that 8PSK modulation is performed during the entire communication frame, and the phase error is corrected. According to the reference phase corresponding to the system, the phase is corrected using the BPSK-modulated frame synchronization signal / TMCC signal period and the carrier synchronization auxiliary signal period in the initial carrier recovery, and after the phase synchronization, the modulation of the main signal other than the period is performed. Phase correction is also performed during the period. As a result, carrier synchronization can be performed quickly and stably even in the low C / N state, and the influence of the phase jitter of the demodulated signal during the period of the main signal subjected to BPSK, QPSK and 8PSK modulation is reduced, and Performance can be improved. In the demodulators according to the ninth to fourteenth embodiments, even after steady demodulation, the state of C / N is monitored, and the target of phase correction is changed based on the C / N detection result. Thus, it is needless to say that the effect of the phase jitter of the demodulated signal can be reduced and the receiving performance can be improved.

The demodulators according to the second to eighth embodiments have the object of avoiding pseudo-synchronization with respect to the demodulator according to the basic first embodiment, respectively. The demodulators according to the fourteenth embodiment have been individually described for the purpose of reducing the influence of phase jitter on the basic demodulator according to the first embodiment. However, by combining the configurations of the demodulation devices according to the second to eighth embodiments with the configurations of the demodulation devices according to the ninth to fourteenth embodiments, it is possible to avoid the pseudo-synchronization and the influence of the phase jitter. Can be simultaneously realized (claims 22 to 31, 53 to 62 ).

In the first to fourteenth embodiments,
BPSK, QPSK,
Although 8PSK has been described, if the modulation scheme of the carrier synchronization auxiliary signal is the phase modulation having the smallest number of phases n among the n-phase phase modulations that are time-division multiplexed, the same effect as described above can be obtained in other modulation schemes. Can be obtained.

Further, when the installation position of the frame synchronization signal in each communication frame is somewhat close to the position corresponding to the insertion period of the carrier synchronization auxiliary signal, the frame synchronization determination unit 47 (see FIG. The configuration 50) is used for the phase synchronization detection unit 43 in the third, fifth, and seventh embodiments, and for the first phase synchronization detection unit 43A in the fourth, sixth, and eighth embodiments. It is possible to simplify the circuit.

(3) Other transmission system and reception system In the description of the above (1) transmission system and (2) reception system, a carrier synchronization auxiliary signal of BPSK modulation is dispersedly inserted into a communication frame, and this carrier synchronization auxiliary The modulation / demodulation device and method for frequency / phase correction using signals have been described. Here, as described above, the main signal includes a low-layer signal, that is, a signal that is BPSK-modulated (see FIG. 2). Therefore, if the lower layer signal, which is the main signal of the BPSK modulation, is also used for the initial carrier wave reproduction, the synchronization can be performed at higher speed and more stably. Therefore, in the following, a modulation / demodulation apparatus and method capable of reproducing a carrier wave by using a low-layer signal that is BPSK-modulated will be described.

(Another Embodiment of Modulating Apparatus and Method) FIG. 72 is a block diagram showing a configuration of another modulating apparatus according to an embodiment of the present invention, corresponding to claims 3 and 6.
In FIG. 72, another modulation device according to an embodiment of the present invention includes a frame synchronization signal / TMCC signal generation unit 11,
TS packet combining section 12, TMCC error correction coding section 13, first error correction coding section 14, second error correction coding section 15, first BPSK mapping section 16
BPSK / QPSK mapping section 17 and 8PSK
A mapping unit 18, a multiplexing / orthogonal modulation unit 19, a synchronization auxiliary signal generation unit 22, a differential encoding unit 23, and a second B
A PSK mapping unit 21. FIG. 73 is a diagram showing an example of a communication frame generated in another modulation device according to an embodiment of the present invention.

As shown in FIG. 72, another modulation apparatus further includes a differential encoding section 23 in addition to the above-described modulation apparatus (see FIG. 1), and a synchronization auxiliary signal generation section 20 is provided. It becomes the structure which replaced. The other configurations of the other modulation devices are the same as those of the above-described modulation device, and the same components are denoted by the same reference numerals and description thereof will be omitted.

The operation of the synchronization auxiliary signal generation section 22 and the differential encoding section 23 in which another modulation apparatus has a different configuration from the above modulation apparatus will be described below. Synchronization auxiliary signal generator 22
Generates the carrier synchronization auxiliary signal as described above.
At this time, the synchronization auxiliary signal generation unit 22
Based on the C information, as shown in FIG. 73, information defining a modulation scheme to be applied to the packet next to the position where the carrier synchronization auxiliary signal is inserted is superimposed. The differential encoding unit 23
A carrier synchronization auxiliary signal on which modulation scheme information is superimposed is input, and the modulation scheme information is differentially encoded so that the demodulation apparatus can decode the modulation scheme information even when the carrier is not synchronized. The carrier synchronization auxiliary signal on which the differentially encoded modulation scheme information is superimposed is the second B
It is input to the PSK mapping unit 21. After that,
As described above.

The operation performed by the synchronization auxiliary signal generation section 22 and the differential encoding section 23 will be described by taking specific values as an example. Now, 4 symbols (= 4 bits) in one packet
A case where a communication frame in which four carrier synchronization auxiliary signals are inserted is generated. At this time, the carrier synchronization auxiliary signal (4
× 4 = 16 bits) is set as follows. 8PSK: 0111111111111111 QPSK: 00101010110101010 BPSK: 0101101101010101 The differential encoding unit 23 converts this carrier synchronization auxiliary signal into
When differential encoding is performed for each, the following is obtained. 8PSK: 0101010101010101 QPSK: 0011001100110011 BPSK: 0110011001100110 When the carrier synchronization auxiliary signal after differential encoding is decoded by a demodulation device described later, the following is obtained. 8PSK: X111111111111111 QPSK: X0101010110101010 BPSK: X1010101010101101 Thus, the carrier synchronization auxiliary signal after differential encoding is:
Since 1s or 0s do not continue, there is no carrier in the modulated wave, and since the same pattern appears 7 times every 2 bits after differential decoding, the demodulator improves reliability by using a majority decision. be able to.

As described above, according to another modulation apparatus according to an embodiment of the present invention, a signal for assisting carrier synchronization in which information defining the modulation scheme of the next packet is superimposed in the demodulation apparatus is converted to a low C signal. A communication frame modulated by BPSK that is strong against the / N state and dispersed and inserted in a packet is output. Thereby, in the demodulation device, low C / N
Even in this state, carrier synchronization can be performed quickly and stably using the carrier synchronization auxiliary signal of BPSK dispersed in the packet and the BPSK modulated main signal.

(Another Embodiment of Demodulation Apparatus and Method) Next, a demodulation apparatus and method for demodulating a communication frame generated in another modulation apparatus according to an embodiment of the present invention will be described below. . FIG. 74 shows claim 37,
It is a block diagram corresponding to 63 which shows the structure of another demodulation device which concerns on one Embodiment of this invention. In FIG. 74, another demodulation device according to one embodiment of the present invention includes a quadrature detector 3
1, a frequency correction unit 32, a band limiting filter 33,
Phase correction section 34, frame synchronization detection section 35, timing generation section 36A, carrier synchronization auxiliary signal decoder 5
2, a first error correction unit 37, and a second error correction unit 38
, A video decoder 39, a TMCC decoder 40,
A BER measuring unit 41;

As shown in FIG. 74, another demodulation device according to one embodiment is different from the demodulation device according to the first embodiment in that:
This is a configuration in which a carrier synchronization auxiliary signal decoder 52 is further added, and the timing generator 36 is replaced with a timing generator 36A. The other configurations of the other demodulation devices according to the embodiment are the same as the configurations of the demodulation device according to the first embodiment, and the components are denoted by the same reference numerals and will not be described. Omitted.

Hereinafter, another demodulation device according to one embodiment has a different configuration from the demodulation device according to the first embodiment.
The operations of the carrier synchronization auxiliary signal decoder 52 and the timing generator 36A will be described in order.

FIG. 75 is a block diagram showing a configuration of carrier synchronization auxiliary signal decoder 52. In FIG. 75,
The carrier synchronization auxiliary signal decoder 52 includes a delay detection unit 52
1, a phase identification unit 522, a BPSK synchronization auxiliary signal pattern matching unit 523, and a main signal BPSK gate generation unit 52
4 is provided. The delay detection unit 521 receives the signal from the band limiting filter 33, and performs complex multiplication of the current phase modulation signal and the complex conjugate signal of the phase modulation signal one symbol before. The phase identification unit 522 identifies the phase of the signal output from the delay detection unit 521 and decodes the data. The BPSK synchronization auxiliary signal pattern matching unit 523 detects the position of the carrier synchronization auxiliary signal from the signal output from the phase identification unit 522, extracts the modulation method information superimposed on the carrier synchronization auxiliary signal, and generates the main signal BPSK gate. Output to the unit 524. The main signal BPSK gate generation unit 524 generates a timing signal (gate signal) for giving the period of the main signal whose modulation scheme is BPSK, based on the input modulation scheme information (FIG. 76 (b)). This timing signal is output to the timing generation unit 36A.

[0307] The timing generation unit 36A first determines the frame synchronization signal / TMCC in one communication frame based on the frame head signal detected by the frame synchronization detection unit 35.
A signal period and a carrier synchronization auxiliary signal period are detected, and an auxiliary signal BPSK timing signal corresponding to the period is generated as shown in FIG. Next, the timing generation unit 36A compares the generated BPSK timing signal (FIG. 76 (a)) with the carrier synchronization auxiliary signal decoder 5.
2 outputs the main signal BPSK timing signal (FIG. 76)
Based on (b)), an all BPSK timing signal (FIG. 76 (c)) for giving a period during which the BPSK modulation is performed in the communication frame is generated. This all BPSK timing signal is output to the frequency correction unit 32 and the phase correction unit 34, and correction is performed according to the signal.

As described above, according to another demodulation device according to an embodiment of the present invention, among the phase-modulated signals that are time-division multiplexed, the BPSK including the carrier synchronization auxiliary signal dispersedly arranged in the packet is used. In addition, carrier wave reproduction is performed using the main signal that has been subjected to BPSK modulation. Thereby, even in the low C / N state, the BPSK dispersed in the packet
Carrier synchronization can be performed quickly and stably using the carrier synchronization auxiliary signal and the BPSK modulated main signal.

In the above embodiment, the carrier synchronization auxiliary signal decoder 52 and the timing generator 36
The case where the configuration A is used in the demodulation device according to the first embodiment has been described. However, the configurations of the carrier synchronization auxiliary signal decoder 52 and the timing generator 36A are as follows.
The present invention can be used for the demodulation devices according to the above-described second to fourteenth embodiments. Here, when the configurations of the carrier synchronization auxiliary signal decoder 52 and the timing generator 36A are used in the demodulators according to the tenth, eleventh, thirteenth, and fourteenth embodiments, the modulation of the main signal obtained from the TMCC decoder 40 is performed. Of course, it is also possible to obtain the information of the system from the carrier synchronization auxiliary signal decoder 52.

Further, in each of the embodiments relating to the demodulation device described above, the frequency of the local oscillation signal in the quadrature detection unit 31 can be changed by the output of the frequency error holding unit 322 of the frequency correction unit 32. 32, the quadrature detector 31 instead of the complex multiplier 324
It is needless to say that the same effect can be obtained even if the frequency error is corrected.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a modulation device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a communication frame generated in a modulation device according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a configuration of a multiplexing / quadrature modulation unit 19 in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a demodulation device according to the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation performed by the demodulation device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a signal detected by a frame synchronization detection unit 35 and a timing signal generated by a timing generation unit 36.

FIG. 7 is a block diagram illustrating a configuration of a first embodiment of the frame synchronization detection unit 35;

FIG. 8 is a block diagram illustrating a configuration of a second embodiment of the frame synchronization detection unit 35;

FIG. 9 is a block diagram illustrating a configuration of a third embodiment of the frame synchronization detection unit 35;

FIG. 10 is a block diagram illustrating a configuration of a fourth embodiment of the frame synchronization detection unit 35;

FIG. 11 is a block diagram illustrating a configuration of a fifth embodiment of the frame synchronization detection unit 35;

FIG. 12 is a diagram illustrating a phase relationship in frame synchronization detection.

FIG. 13 is a diagram illustrating a phase relationship in frame synchronization detection.

FIG. 14 is a diagram illustrating a frequency shift in frequency correction.

FIG. 15 is a diagram illustrating a phase relationship in frame synchronization detection.

FIG. 16 is a diagram illustrating a phase relationship in frame synchronization detection.

FIG. 17 is a block diagram showing a more detailed configuration of the frequency correction unit 32.

FIG. 18 is a block diagram showing a more detailed configuration of the phase correction unit 34.

FIG. 19 is a diagram illustrating a phase shift in the phase correction.

FIG. 20 is a diagram for explaining pseudo-synchronization generated in the phase correction unit 34.

FIG. 21 is a diagram for explaining pseudo-synchronization generated in the phase correction unit 34.

FIG. 22 is a block diagram illustrating a configuration of a demodulation device according to a second embodiment of the present invention.

FIG. 23 is a flowchart illustrating an operation performed by the demodulation device according to the second embodiment of the present invention.

FIG. 24 is a block diagram showing a more detailed configuration of a frequency pull-in detector 42.

FIG. 25 is a block diagram showing an example of a more detailed configuration of a phase correction unit 34A.

FIG. 26 is a block diagram illustrating an example of a more detailed configuration of a phase correction unit 34A.

FIG. 27 is a block diagram illustrating a configuration of a demodulation device according to a third embodiment of the present invention.

FIG. 28 is a flowchart illustrating an operation performed by the demodulation device according to the third embodiment of the present invention.

FIG. 29 is a block diagram illustrating a configuration of a first embodiment of the phase synchronization detection unit 43.

FIG. 30 is a block diagram illustrating a configuration of a second embodiment of the phase synchronization detection unit 43.

FIG. 31 shows a phase synchronization determination unit 437 of the phase synchronization detection unit 43.
FIG. 3 is a diagram for explaining an example of a threshold value set in FIG.

FIG. 32 is a diagram for explaining the operation principle of pseudo-synchronization determination performed by the pseudo-synchronization determination unit 45 of FIG.

FIG. 33 is a block diagram illustrating a configuration of a demodulation device according to a fourth embodiment of the present invention.

FIG. 34 is a diagram showing another timing signal generated by the timing generation unit 36.

FIG. 35 is a diagram for explaining the operation principle of pseudo-synchronization determination performed by the pseudo-synchronization determination unit 45 of FIG.

FIG. 36 is a block diagram illustrating a configuration of a demodulation device according to a fifth embodiment of the present invention.

FIG. 37 is a flowchart showing an operation performed by the demodulation device according to the fifth embodiment of the present invention.

FIG. 38 is a block diagram illustrating an example of a configuration of a pseudo-synchronization determination unit 45 in FIG. 36.

39 is a block diagram showing a configuration of a frequency step unit 46. FIG.

40 is a diagram showing each signal waveform in the frequency step unit 46. FIG.

FIG. 41 is a diagram illustrating the operation principle of the frequency step.

FIG. 42 is a block diagram illustrating a configuration of a demodulation device according to a sixth embodiment of the present invention.

FIG. 43 is a block diagram illustrating a configuration of a demodulation device according to a seventh embodiment of the present invention.

FIG. 44 is a flowchart showing an operation performed by the demodulation device according to the seventh embodiment of the present invention.

FIG. 45 is a block diagram illustrating a configuration of a demodulation device according to an eighth embodiment of the present invention.

FIG. 46 is a diagram illustrating phase jitter.

FIG. 47 is a diagram illustrating the relationship between phase jitter and C / N.

FIG. 48 is a block diagram illustrating a configuration of a demodulation device according to a ninth embodiment of the present invention.

FIG. 49 is a flowchart showing an operation performed by the demodulation device according to the ninth embodiment of the present invention.

50 is a block diagram illustrating a configuration of a frame synchronization determination unit 47. FIG.

FIG. 51 is a block diagram illustrating a configuration of a C / N detection unit 48.

FIG. 52 is a block diagram showing a configuration of a gate signal selection unit 49.

FIG. 53 is a block diagram showing a configuration of a phase error detection section 341 of the phase correction section 34B.

FIG. 54 is a diagram illustrating a phase error detection operation performed by a phase error detection unit 341 of the phase correction unit 34B.

FIG. 55 is a block diagram illustrating a configuration of a demodulation device according to a tenth embodiment of the present invention.

FIG. 56 is a flowchart showing an operation performed by the demodulation device according to the tenth embodiment of the present invention.

FIG. 57 is a block diagram showing a configuration of a C / N detection unit 48A.

FIG. 58 is a block diagram showing a configuration of a gate signal selection unit 49A.

FIG. 59 is a diagram illustrating each timing signal input to the demodulation mode switching unit 50 and a demodulation mode signal output.

FIG. 60 is a block diagram showing a configuration of a phase error detection section 341 of the phase correction section 34C.

FIG. 61 is a diagram illustrating a phase error detection operation performed by a phase error detection unit 341 of a phase correction unit 34C.

FIG. 62 is a block diagram illustrating a configuration of a demodulation device according to an eleventh embodiment of the present invention.

FIG. 63 is a flowchart showing an operation performed by the demodulation device according to the eleventh embodiment of the present invention.

FIG. 64 is a block diagram showing a configuration of a gate signal selection unit 49B.

FIG. 65 is a block diagram showing a configuration of a demodulation mode switching unit 50A.

FIG. 66 is a block diagram illustrating a configuration of a demodulation device according to a twelfth embodiment of the present invention.

FIG. 67 is a block diagram illustrating a configuration of a BER detection unit 51.

FIG. 68 is a diagram illustrating a relationship between C / N and a bit error rate.

FIG. 69 is a block diagram illustrating a configuration of a demodulation device according to a thirteenth embodiment of the present invention.

FIG. 70 is a block diagram showing a configuration of a BER detection unit 51A.

FIG. 71 is a block diagram illustrating a configuration of a demodulation device according to a fourteenth embodiment of the present invention.

FIG. 72 is a block diagram illustrating a configuration of another modulation device according to an embodiment of the present invention.

FIG. 73 is a diagram showing an example of a communication frame generated in another modulation device according to an embodiment of the present invention.

FIG. 74 is a block diagram illustrating a configuration of another demodulation device according to an embodiment of the present invention.

FIG. 75 is a block diagram showing a configuration of a carrier synchronization auxiliary signal decoder 52.

FIG. 76 is a diagram showing a timing signal generated by a timing generation unit 36A.

FIG. 77 is a block diagram illustrating a configuration of a conventional modulation device.

FIG. 78 is a diagram illustrating an example of a communication frame generated in a conventional modulation device.

FIG. 79 is a diagram illustrating mapping of BPSK, QPSK, and 8PSK to code constellations.

FIG. 80: MPEG in conventional modulation apparatus and method
3 is a diagram showing a data structure and a frame structure of FIG.

FIG. 81 is a block diagram illustrating a configuration of a conventional demodulation device.

[Explanation of symbols]

11, 1001 ... frame synchronization signal / TMCC signal generation unit 12, 1002 ... TS packet synthesis unit 13-15, 1003-1005 ... error correction coding unit 16, 21, 1006 ... BPSK mapping unit 17, 1007 ... BPSK / QPSK mapping Unit 18, 1008 ... 8PSK mapping unit 19, 1009 ... Multiplexing / quadrature modulation unit 20, 22 ... Synchronization auxiliary signal generation unit 23 ... Differential coding unit 31, 1101 ... Quadrature detection unit 32, 32A ... Frequency correction unit 33 ... Band limit filters 34, 34A to 34C Phase correction unit 35 Frame synchronization detection unit 36, 36A Timing generation unit 37, 38, 1105 Error correction unit 39, 1106 Video decoder 40, 1104 TMCC decoder 41, 1103 BER measurement unit 42: frequency pull-in detection unit 43 43A, 43B ... Phase synchronization detection unit 44 ... Error correction detection unit 45 ... Pseudo synchronization determination unit 46 ... Frequency step unit 47 ... Frame synchronization determination unit 48,48A ... C / N detection unit 49,49A, 49B ... Gate signal selection unit 50, 50A demodulation mode switching section 51, 51A BER detection section 52 carrier synchronization auxiliary signal decoder 321, 421 frequency error detection section 321a, 351, 421a, 521 delay detection section 321b, 341, 341a to 341c, 421b , 4
31, 481 phase error detector 322 frequency error holder 322a, 341d, 341e, 342a, 342h,
343e, 422, 424c, 433, 435c, 46
4,467,483,485c, 493,494,49
9 switching units 322b, 342b, 342i, 343f, 423, 4
24d, 434, 435d, 462, 463, 484,
485d, 492, 492a... Constant generation units 322c, 323a, 342c, 342e, 343a,
424a, 435a, 325, 485a ... adders 322d, 323b, 342d, 343b, 424b,
435b, 461b, 485b Delay units 323, 343 Numerically controlled oscillators 323c, 343c Cosine wave generators 323d, 343d Sine wave generators 324, 344 Complex multipliers 342 Phase error holding units 342f Holding units 342g .. Amplifying sections 352, 352a to 352c, 471, 522. Phase discriminating sections 353, 472.... 426 ... frequency pull-in determination section 427, 432, 432A, 432B, 482 ... absolute value conversion section 437 ... phase synchronization determination section 438, 453, 512 ... comparison section 451, 496, 497, 504 ... OR circuit 452 ... counter 461 ... control Signal generation unit 461a... XOR circuit 461c, 49 1,491a, 495,501-503
... AND circuit 466... Negative coding units 487, 488, 513, 514... C / N level judgment unit 498... NOT circuit 511... Error correction re-encoding unit 523 BPSK synchronization auxiliary signal pattern matching unit 524. Generation unit 1102: PSK demodulation unit

Continuation of the front page (51) Int.Cl. ⁷ identification symbol FI H04N 7/08 H04N 7/08 Z 7/081 (56) References JP-A-5-327807 (JP, A) JP-A-58-178683 ( JP, A) JP-A-53-137657 (JP, A) JP-A-56-1554859 (JP, A) JP-A-9-321813 (JP, A) JP-A-10-215291 (JP, A) JP-A-8-330910 (JP, A) JP-A-3-102943 (JP, A) JP-A-6-14069 (JP, A) JP-A-5-236042 (JP, A) JP-A-3-19456 (JP) , A) Technical Report of the Image Media Society of Japan, Vol. 25, p. 1-5 (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (64)

(57) [Claims] 1. A modulator for generating a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiency for each layer of data on a plurality of data to be communicated, Phase modulation means for performing a phase modulation corresponding to the data content on each of the plurality of data to generate a modulation signal; and a phase modulation in which the number of phases among the plurality of phase modulations performed on the data is the smallest (hereinafter, referred to as Signal generating means for generating a carrier synchronization auxiliary signal that has been subjected to phase modulation using minimum phase modulation), and the modulation signal and the carrier synchronization auxiliary signal are dispersed at equal time intervals within the communication frame. Multiplexing means for time-division multiplexing the carrier synchronization auxiliary signal, wherein the carrier synchronization auxiliary signal is transmitted in a next packet to a time division multiplexed position in the communication frame. Characterized by superimposing the information for identifying the phase modulation is applied to become the modulation signal, the modulation device. 2. A modulator for generating a predetermined fixed-length communication frame by subjecting a plurality of data to be communicated to phase modulation having a different transmission efficiency for each layer of the data. Phase modulation means for performing a phase modulation corresponding to the data content on each of the plurality of data to generate a modulation signal; and a phase modulation in which the number of phases among the plurality of phase modulations performed on the data is the smallest (hereinafter, referred to as Signal generation means for generating a carrier synchronization auxiliary signal that has been subjected to phase modulation using minimum phase modulation), and the carrier synchronization auxiliary signal is continuously distributed at equal time intervals within the communication frame for two or more symbols. Multiplexing means for time-division multiplexing the modulated signal and the carrier synchronization auxiliary signal, wherein the carrier synchronization auxiliary signal is time-division multiplexed in the communication frame. Characterized by superimposing the information for identifying the phase modulation that is applied to the modulated signal as a next packet relative location, modulator. 3. The apparatus according to claim 1, further comprising: differential encoding means for performing differential encoding on an input signal and outputting the signal, wherein said signal generating means includes a signal which has been differentially encoded by said differential encoding means. 3. The modulation device according to claim 1, wherein a carrier synchronization auxiliary signal subjected to the minimum phase modulation among a plurality of phase modulations applied to the data is generated. 4. 4. A modulation method for generating a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiency for each layer of the data on a plurality of data to be communicated, A carrier synchronization auxiliary signal that has been subjected to phase modulation using the phase modulation having the smallest number of phases (hereinafter, referred to as minimum phase modulation) among a plurality of phase modulations applied to data is generated, and the carrier synchronization auxiliary signal is used for the communication. The carrier synchronization auxiliary signal is time-division multiplexed so as to be distributed at equal time intervals in a frame, and the carrier synchronization auxiliary signal is a phase applied to a modulation signal to be a next packet with respect to a time division multiplexed position in the communication frame. A modulation method comprising superimposing information for identifying modulation. 5. A modulation method for generating a predetermined fixed-length communication frame by performing phase modulation with different transmission efficiency for each layer of the data on a plurality of data to be communicated, A carrier synchronization auxiliary signal that has been subjected to phase modulation using the phase modulation having the smallest number of phases (hereinafter, referred to as minimum phase modulation) among a plurality of phase modulations applied to data is generated. Time-division multiplexing is performed so as to be continuously dispersed in the communication frame at equal time intervals, and the carrier synchronization auxiliary signal is a modulated signal that becomes a next packet with respect to the position where the time-division multiplexing is performed in the communication frame. A modulation method for superimposing information for identifying phase modulation performed on the data. 6. The carrier synchronization auxiliary signal is generated by subjecting a signal after differential encoding to the minimum phase modulation among a plurality of phase modulations applied to the data. The modulation method according to claim 4 or 5, wherein 7. A communication frame together with a plurality of phase modulated signals.
Phase modulation with the least number of phases in the
Carrier that has been phase-modulated using phase modulation)
Time division so that the synchronization auxiliary signal is distributed at equal time intervals
A demodulation device that receives the multiplexed communication frame.
Te, by detecting the synchronizing signal of said communication frame, frame
Frame synchronization detecting means for detecting a frame start position, and the minimum phase modulation is performed based on the frame start position.
At least the carrier synchronization auxiliary signal in the
Time giving the period of the signal (hereinafter referred to as the synchronization signal period)
Timing generating means for generating a timing signal, and using a period given by the timing signal a plurality of times.
With the frequency correction operation according to the minimum phase modulation and
A demodulation device comprising: a correction unit that performs a phase correction operation. 8. A carrier synchronization auxiliary signal that has been phase-modulated using a phase modulation having the smallest number of phases in a communication frame (hereinafter referred to as a minimum phase modulation) together with a plurality of phase-modulated signals is distributed at equal time intervals. A demodulation device that receives the communication frame that has been time-division multiplexed, wherein a frequency correction unit that detects a frequency error of a predetermined signal period in the communication frame and corrects a frequency shift, A phase correction unit that detects a phase error of a predetermined signal period in a communication frame and corrects a phase shift, and an output signal of any one of the frequency correction unit and the phase correction unit, and performs delay detection. Frame synchronization detecting means for detecting a frame start position by detecting a synchronization signal of the communication frame using the communication frame; Based on the frame start position, at least the period of the carrier sync auxiliary signal of the minimum phase duration modulation is performed (hereinafter,
A synchronization signal period), and a timing generation unit that generates a timing signal for providing the synchronization signal period. The frequency correction unit and the phase correction unit are configured to detect the synchronization signal period in the synchronization signal period provided by the timing signal. A demodulation device that performs a correction operation according to minimum phase modulation. 9. A frequency pull-in detection for receiving an output signal of either the frequency correction means or the phase correction means, detecting a frequency pull-in state, and determining whether the frequency of the phase correction means is a pseudo-synchronous frequency. Means, as a result of the determination of the frequency pull-in detection means, when the frequency correction in the frequency correction means is completed up to a frequency at which the phase correction means is not pseudo-synchronized, a phase correction reset means for initializing the phase correction means; The demodulation device according to claim 8 , further comprising: 10. A phase synchronization detecting means for receiving an output signal of the phase correcting means and detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal, and a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detection means for detecting a correction state of the error correction processing of the C signal), pseudo-synchronization determination means for determining whether or not pseudo-synchronization is performed based on detection results of the phase synchronization detection means and the error correction detection means; 9. The demodulation device according to claim 8 , further comprising: a phase correction reset unit that initializes the phase correction unit when the result of the determination by the pseudo synchronization determination unit is a pseudo synchronization. 11. An output signal of the phase correction means, a first phase synchronization detection means for detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal, and an output signal of the phase correction means. A second phase synchronization detecting means for detecting a state of phase synchronization during a transmission control signal (TMCC signal) included in the frame synchronization signal; a first phase synchronization detecting means; and a second phase synchronization detection. A pseudo-synchronous determination unit that determines whether or not a pseudo-synchronization is performed based on a detection result of the unit; and a phase-correction reset unit that initializes the phase correction unit when the pseudo-synchronization is determined to be pseudo-synchronous. The demodulation device according to claim 8 , further comprising: 12. A phase synchronization detection means for receiving an output signal of the phase correction means and detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal, and a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detection means for detecting a correction state of the error correction processing of the C signal), pseudo-synchronization determination means for determining whether or not pseudo-synchronization is performed based on detection results of the phase synchronization detection means and the error correction detection means; 9. The demodulation according to claim 8 , further comprising frequency step means for changing a frequency input to said phase correction means in a stepwise manner when the result of the judgment by the pseudo synchronization judgment means is that the pseudo synchronization is found. apparatus. 13. An output signal of the phase correction means, a first phase synchronization detection means for detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal, and an output signal of the phase correction means. A second phase synchronization detecting means for detecting a state of phase synchronization during a transmission control signal (TMCC signal) included in the frame synchronization signal; a first phase synchronization detecting means; and a second phase synchronization detection. A pseudo-synchronization determining means for determining whether or not a pseudo-synchronization is performed based on a detection result with the means; The demodulation device according to claim 8 , further comprising frequency step means for causing the frequency to be stepped. 14. A frequency pull-in detection for receiving an output signal of either the frequency correction means or the phase correction means, detecting a frequency pull-in state, and determining whether or not the frequency of the phase correction means is pseudo-synchronous. Means, as a result of the determination of the frequency pull-in detection means, when the frequency correction in the frequency correction means is completed up to a frequency at which the phase correction means is not pseudo-synchronized, a phase correction reset means for initializing the phase correction means; The demodulation device according to claim 12 , further comprising: 15. A frequency pull-in detection which receives an output signal of either the frequency correction means or the phase correction means, detects a frequency pull-in state, and determines whether or not the frequency of the phase correction means is pseudo-synchronous. Means, as a result of the determination of the frequency pull-in detection means, when the frequency correction in the frequency correction means is completed up to a frequency at which the phase correction means is not pseudo-synchronized, a phase correction reset means for initializing the phase correction means; The demodulation device according to claim 13 , further comprising: 16. An output signal of the phase correction means, a frame synchronization determination means for detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal, and an output signal of the phase correction means, C /
C / N detection means for detecting the state of N (carrier power / noise power), phase synchronization based on the detection results of the frame synchronization determination means and the C / N detection means, and the timing signal, and A gate signal for generating a gate signal for providing the entire period of the communication frame when C / N is higher than a predetermined threshold value; otherwise, a gate signal for generating a gate signal for providing the synchronization signal period Generating means, wherein the phase correction means detects a phase error due to minimum phase modulation in the synchronization signal period provided by the timing signal, and detects a phase having the largest number of phases in the communication frame other than the synchronization signal period. The demodulation device according to claim 8 , wherein after detecting a phase error due to modulation, a correction operation is performed according to a period given by the gate signal. 17. An output signal of the phase correction means, a frame synchronization determination means for detecting phase synchronization in the phase correction means, and an output signal of the phase correction means,
C / N detection means for detecting the state of N (carrier power / noise power); and a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detection means for detecting a correction state of the error correction processing of the C signal), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, A demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with a phase modulation method based on a signal output from a period providing means and the timing signal; Based on the detection results of the C / N detection means and the error correction detection means, and the signal output from the signal period giving means and the timing signal, when phase synchronization is achieved and error correction is completed. , When C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and And a gate signal generating unit that generates a gate signal that gives the synchronization signal period, except when the error correction is completed, wherein the phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal. The demodulation device according to claim 8 , wherein the demodulation device detects and performs a correction operation in accordance with a period given by the gate signal. 18. An output signal of the phase correction means, a frame synchronization determination means for detecting phase synchronization in the phase correction means, and an output signal of the phase correction means,
C / N detection means for detecting the state of N (carrier power / noise power); and a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detecting means for detecting a correction state of the error correction processing of the C signal), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, Demodulation for switching the demodulation method in the phase correction means based on the detection results of the synchronization determination means and the error correction detection means, and the signal output by the signal period giving means and the timing signal, in accordance with the phase modulation method. Demodulation mode switching means for outputting a mode signal, based on detection results of the frame synchronization determination means, the C / N detection means and the error correction detection means, and a signal output from the signal period giving means and the timing signal, In the case where there is phase synchronization and error correction is completed, C / C with respect to a predetermined first threshold value If it is high,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and If error correction has not been completed and C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
A gate signal generation unit that generates a gate signal that provides the synchronization signal period; and a gate signal generation unit that generates a gate signal that provides the synchronization signal period when there is no phase synchronization, wherein the phase correction unit completes error correction. If not,
In the synchronization signal period provided by the timing signal, a phase difference due to the minimum phase modulation is detected, and in a period other than the synchronization signal period, a phase error due to the phase modulation having the largest number of phases in the communication frame is detected, and error correction is completed. 9. The method according to claim 8 , wherein, when detecting the phase error, a phase error by a phase modulation method according to the demodulation mode signal is detected, and then a correction operation is performed according to a period given by the gate signal.
3. The demodulation device according to claim 1. 19. A frame synchronization determining unit which receives an output signal of the phase correcting unit and detects phase synchronization in the phase correcting unit, and a transmission control signal (TMC) included in the frame synchronizing signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
BER detection means for detecting the state of the signal, phase detection based on the detection results of the frame synchronization determination means and the BER detection means, and the C / N with respect to a predetermined threshold value based on the timing signal. Is high, further comprising a gate signal generating means for generating a gate signal for providing the entire period of the communication frame, otherwise, a gate signal generating means for generating a gate signal for providing the synchronous signal period, Detecting the phase error due to the minimum phase modulation in the synchronization signal period provided by the timing signal, and detecting the phase error due to the phase modulation having the largest number of phases in the communication frame in other than the synchronization signal period, and then detecting the gate signal. The demodulation device according to claim 8 , wherein the correction operation is performed in accordance with a period given by (1). 20. A frame synchronization determining unit which receives an output signal of the phase correcting unit and detects phase synchronization in the phase correcting unit, and a transmission control signal (TMC) included in the frame synchronizing signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
And a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detection means for detecting a correction state of the error correction processing of the C signal), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, A demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with a phase modulation method based on a signal output from a period providing means and the timing signal; Based on the detection results of the BER detection means and the error correction detection means, and the signal output from the signal period giving means and the timing signal, when phase synchronization is established and error correction is completed, When C / N is high with respect to the determined first threshold,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and And a gate signal generating unit that generates a gate signal that gives the synchronization signal period, except when the error correction is completed, wherein the phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal. The demodulation device according to claim 8 , wherein the demodulation device detects and performs a correction operation in accordance with a period given by the gate signal. 21. A frame synchronization determining unit which receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit, and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
And a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detecting means for detecting a correction state of the error correction processing of the C signal), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, Demodulation for switching the demodulation method in the phase correction means based on the detection results of the synchronization determination means and the error correction detection means, and the signal output by the signal period giving means and the timing signal, in accordance with the phase modulation method. Phase demodulation mode switching means for outputting a mode signal; phase synchronization based on detection results of the frame synchronization determination means, the BER detection means and the error correction detection means, and a signal output by the signal period giving means and the timing signal. And error correction has been completed, and C / C with respect to a predetermined first threshold value If it is high,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and If error correction has not been completed and C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
A gate signal generation unit that generates a gate signal that provides the synchronization signal period; and a gate signal generation unit that generates a gate signal that provides the synchronization signal period when there is no phase synchronization, wherein the phase correction unit completes error correction. If not,
In the synchronization signal period provided by the timing signal, a phase difference due to the minimum phase modulation is detected, and in a period other than the synchronization signal period, a phase error due to the phase modulation having the largest number of phases in the communication frame is detected, and error correction is completed. 9. The method according to claim 8 , wherein, when detecting the phase error, a phase error by a phase modulation method according to the demodulation mode signal is detected, and then a correction operation is performed according to a period given by the gate signal.
3. The demodulation device according to claim 1. 22. An input signal of the phase correction means, a frame synchronization determination means for detecting a phase synchronization in the phase correction means, and an output signal of the phase correction means,
C / N detection means for detecting the state of N (carrier power / noise power), phase synchronization based on the detection results of the frame synchronization determination means and the C / N detection means, and the timing signal, and A gate signal for generating a gate signal for providing the entire period of the communication frame when C / N is higher than a predetermined threshold value; otherwise, a gate signal for generating a gate signal for providing the synchronization signal period Generating means, wherein the phase correction means detects a phase error due to minimum phase modulation in the synchronization signal period provided by the timing signal, and detects a phase having the largest number of phases in the communication frame other than the synchronization signal period. after detecting a phase error due to modulation, and performs a correction operation in accordance with the period in which the gate signal on, serial to claim 9 to 15 Of the demodulator. 23. A frame synchronization judging means for inputting an output signal of the phase correction means and detecting a phase synchronization in the phase correction means, and an output signal of the phase correction means for receiving C /
C / N detection means for detecting the state of N (carrier power / noise power); and a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detection means for detecting a correction state of the error correction processing of the C signal), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, A demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with a phase modulation method based on a signal output from a period providing means and the timing signal; Based on the detection results of the C / N detection means and the error correction detection means, and the signal output from the signal period giving means and the timing signal, when phase synchronization is achieved and error correction is completed. , When C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and And a gate signal generating unit that generates a gate signal that gives the synchronization signal period, except when the error correction is completed, wherein the phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal. 16. The demodulation device according to claim 9 , wherein the demodulation device detects and performs a correction operation in accordance with a period given by the gate signal. 24. An output signal of the phase correction means, a frame synchronization determination means for detecting phase synchronization in the phase correction means, and an output signal of the phase correction means,
C / N detection means for detecting a state of N (carrier power / noise power); signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame; A demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with a phase modulation method based on a signal output by a signal period providing means and the timing signal; Means, phase synchronization based on the detection results of the C / N detecting means and the error correction detecting means, and the signal output by the signal period giving means and the timing signal, and when the error correction is completed. Therefore, when C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and And a gate signal generating unit that generates a gate signal that gives the synchronization signal period, except when the error correction is completed, wherein the phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal. 15. The demodulation device according to claim 10 , wherein the demodulation device detects and performs a correction operation in accordance with a period given by the gate signal. 25. A frame synchronization judging means for receiving an output signal of the phase correction means and detecting a phase synchronization in the phase correction means, and an output signal of the phase correction means for receiving C / C of a received signal.
C / N detection means for detecting the state of N (carrier power / noise power); and a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detecting means for detecting a correction state of the error correction processing of the C signal), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, Demodulation for switching the demodulation method in the phase correction means based on the detection results of the synchronization determination means and the error correction detection means, and the signal output by the signal period giving means and the timing signal, in accordance with the phase modulation method. Demodulation mode switching means for outputting a mode signal, based on detection results of the frame synchronization determination means, the C / N detection means and the error correction detection means, and a signal output from the signal period giving means and the timing signal, In the case where there is phase synchronization and error correction is completed, C / C with respect to a predetermined first threshold value If it is high,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and If error correction has not been completed and C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
A gate signal generation unit that generates a gate signal that provides the synchronization signal period; and a gate signal generation unit that generates a gate signal that provides the synchronization signal period when there is no phase synchronization, wherein the phase correction unit completes error correction. If not,
In the synchronization signal period provided by the timing signal, a phase difference due to the minimum phase modulation is detected, and in a period other than the synchronization signal period, a phase error due to the phase modulation having the largest number of phases in the communication frame is detected, and error correction is completed. The method according to claim 1, wherein after detecting a phase error by a phase modulation method according to the demodulation mode signal, performing a correction operation according to a period given by the gate signal.
The demodulation device according to any one of 9, 11, 13 and 15 . 26. An output signal of the phase correction means, a frame synchronization determination means for detecting phase synchronization in the phase correction means, and an output signal of the phase correction means,
C / N detection means for detecting a state of N (carrier power / noise power); signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame; A demodulation method in the phase correction means is switched in accordance with a phase modulation method based on a detection result of the frame synchronization determination means and the error correction detection means, and a signal output from the signal period giving means and the timing signal. A demodulation mode switching unit that outputs a demodulation mode signal; a detection result of the frame synchronization determination unit, the C / N detection unit and the error correction detection unit; and a signal output by the signal period assignment unit and the timing signal. Where phase synchronization has been performed and error correction has been completed, and C / N with respect to a predetermined first threshold value If high,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal providing a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal providing the minimum phase modulation period and a predetermined modulation signal period, there is phase synchronization, and If error correction has not been completed and C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
A gate signal generation unit that generates a gate signal that provides the synchronization signal period; and a gate signal generation unit that generates a gate signal that provides the synchronization signal period when there is no phase synchronization, wherein the phase correction unit completes error correction. If not,
In the synchronization signal period provided by the timing signal, a phase difference due to the minimum phase modulation is detected, and in a period other than the synchronization signal period, a phase error due to the phase modulation having the largest number of phases in the communication frame is detected, and error correction is completed. If you are, after detecting a phase error based on the phase modulation method in accordance with the demodulation mode signal, and performs a correction operation in accordance with the period in which the gate signal on claim 1
15. The demodulation device according to any one of 0, 12 , and 14 . 27. A frame synchronization judging unit which receives an output signal of the phase correction unit and detects phase synchronization in the phase correction unit, and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
BER detection means for detecting the state of the signal, phase detection based on the detection results of the frame synchronization determination means and the BER detection means, and the C / N with respect to a predetermined threshold value based on the timing signal. Is high, further comprising a gate signal generating means for generating a gate signal for providing the entire period of the communication frame, otherwise, a gate signal generating means for generating a gate signal for providing the synchronous signal period, Detecting the phase error due to the minimum phase modulation in the synchronization signal period provided by the timing signal, and detecting the phase error due to the phase modulation having the largest number of phases in the communication frame in other than the synchronization signal period, and then detecting the gate signal. The demodulation device according to any one of claims 9 to 15 , wherein a correction operation is performed in accordance with a period given by (1). 28. A frame synchronization determining unit which receives an output signal of the phase correcting unit and detects phase synchronization in the phase correcting unit, and a transmission control signal (TMC) included in the frame synchronizing signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
And a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detection means for detecting a correction state of the error correction processing of the C signal), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, A demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with a phase modulation method based on a signal output from a period providing means and the timing signal; Based on the detection results of the BER detection means and the error correction detection means, and the signal output from the signal period giving means and the timing signal, when phase synchronization is established and error correction is completed, When C / N is high with respect to the determined first threshold,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and And a gate signal generating unit that generates a gate signal that gives the synchronization signal period, except when the error correction is completed, wherein the phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal. 16. The demodulation device according to claim 9 , wherein the demodulation device detects and performs a correction operation in accordance with a period given by the gate signal. 29. A frame synchronization determining unit which receives an output signal of the phase correcting unit and detects phase synchronization in the phase correcting unit, and a transmission control signal (TMC) included in the frame synchronizing signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
BER detection means for detecting the state of the signal frame, signal period providing means for outputting a signal for providing a period of each phase modulation signal other than the synchronization signal period in the communication frame, and signal output by the signal period providing means A demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with the phase modulation method based on the timing signal; the frame synchronization determination means, the BER detection means, and the error correction Based on the detection result of the detecting means and the signal output from the signal period providing means and the timing signal, the phase synchronization is performed, and the error correction is completed. On the other hand, when C / N is high,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and And a gate signal generating unit that generates a gate signal that gives the synchronization signal period, except when the error correction is completed, wherein the phase correction unit detects a phase error by a phase modulation method according to the demodulation mode signal. 15. The demodulation device according to claim 10 , wherein the demodulation device detects and performs a correction operation in accordance with a period given by the gate signal. 30. A frame synchronization determining unit which receives an output signal of the phase correcting unit and detects phase synchronization in the phase correcting unit, and a transmission control signal (TMC) included in the frame synchronizing signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
And a transmission control signal (TMC) included in the frame synchronization signal.
Error correction detecting means for detecting a correction state of the error correction processing of the C signal), a signal period providing means for outputting a signal giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, Demodulation for switching the demodulation method in the phase correction means based on the detection results of the synchronization determination means and the error correction detection means, and the signal output by the signal period giving means and the timing signal, in accordance with the phase modulation method. Phase demodulation mode switching means for outputting a mode signal; phase synchronization based on detection results of the frame synchronization determination means, the BER detection means and the error correction detection means, and a signal output by the signal period giving means and the timing signal. And error correction has been completed, and C / C with respect to a predetermined first threshold value If it is high,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and If error correction has not been completed and C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
A gate signal generation unit that generates a gate signal that provides the synchronization signal period; and a gate signal generation unit that generates a gate signal that provides the synchronization signal period when there is no phase synchronization, wherein the phase correction unit completes error correction. If not,
In the synchronization signal period provided by the timing signal, a phase difference due to the minimum phase modulation is detected, and in a period other than the synchronization signal period, a phase error due to the phase modulation having the largest number of phases in the communication frame is detected, and error correction is completed. The method according to claim 1, wherein after detecting a phase error by a phase modulation method according to the demodulation mode signal, performing a correction operation according to a period given by the gate signal.
The demodulation device according to any one of 9, 11, 13 and 15 . 31. A frame synchronization determining unit which receives an output signal of the phase correcting unit and detects phase synchronization in the phase correcting unit, and a transmission control signal (TMC) included in the frame synchronizing signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
BER detection means for detecting a state of the signal, signal period providing means for outputting a signal for giving a period of each phase modulation signal other than the synchronization signal period in the communication frame, frame synchronization determination means and error correction detection means Demodulation mode switching means for outputting a demodulation mode signal for switching a demodulation method in the phase correction means in accordance with a phase modulation method, based on the detection result of the signal period and the signal output by the signal period providing means and the timing signal. Phase synchronization based on the detection results of the frame synchronization determination means, the BER detection means and the error correction detection means, and the signal output by the signal period providing means and the timing signal, and the error correction is completed. If the C / N is higher than the predetermined first threshold,
When the C / N is low with respect to a second predetermined threshold value,
Generating a gate signal that provides a period of the signal subjected to the minimum phase modulation; otherwise, generating a gate signal that provides the minimum phase modulation period and a predetermined modulation signal period; there is phase synchronization; and If error correction has not been completed and C / N is higher than a predetermined first threshold value,
When the C / N is low with respect to a second predetermined threshold value,
A gate signal generation unit that generates a gate signal that provides the synchronization signal period; and a gate signal generation unit that generates a gate signal that provides the synchronization signal period when there is no phase synchronization, wherein the phase correction unit completes error correction. If not,
In the synchronization signal period provided by the timing signal, a phase difference due to the minimum phase modulation is detected, and in a period other than the synchronization signal period, a phase error due to the phase modulation having the largest number of phases in the communication frame is detected, and error correction is completed. If you are, after detecting a phase error based on the phase modulation method in accordance with the demodulation mode signal, and performs a correction operation in accordance with the period in which the gate signal on claim 1
15. The demodulation device according to any one of 0, 12 , and 14 . 32. The frame synchronization detecting means includes: a delay detecting means for delay-detecting a signal; one or two or more phase identifying means for identifying a transmitted signal from a delay-detected phase-modulated signal; Or matching means for performing pattern matching between an output of two or more phase identification means and the frame synchronization signal, wherein the one or more phase identification means comprises a phase corresponding to a phase modulation for transmitting the frame synchronization signal. Each of the phase identification regions has an identification region, and two or more of the phase identification regions are installed in parallel by performing different phase rotations, and the matching unit is configured to set a phase rotation amount of the phase identification region different from each other. The demodulator according to any one of claims 8 to 31 , wherein pattern matching is performed on the output. 33. The frame synchronization detecting means includes: delay detecting means for delay-detecting a signal; a plurality of phase rotating means for applying a predetermined number of types of phase rotation to the delayed detected signal; and a plurality of phase rotating means, respectively. With respect to the output of, the phase identification means comprising: a phase identification means for performing phase identification; and a matching means for performing pattern matching between the output of the phase identification means and the frame synchronization signal, wherein the phase identification means receives the frame synchronization signal. Having a phase identification region corresponding to the phase modulation to identify a signal transmitted for each phase modulation signal subjected to differential detection and given a different phase rotation, the collation means, and performing pattern matching for each output, according to claim 8
32. The demodulation device according to any one of -31 . 34. The frame synchronization detecting means includes: a delay detecting means for delay-detecting a signal; a phase identifying means for identifying a signal transmitted from the phase-detected phase-modulated signal; and an identifying phase of the phase identifying means. A phase identification unit that rotates, and a matching unit that performs pattern matching of the output of the phase identification unit and the frame synchronization signal, wherein the phase identification unit performs phase identification corresponding to phase modulation that transmits the frame synchronization signal. 32. The apparatus according to claim 8 , further comprising a region, wherein the phase rotation unit rotates the phase of the phase identification region in the phase identification unit until the frame synchronization signal is detected by the matching unit.
The demodulator according to any one of the above. 35. The frame synchronization detecting means includes: a delay detecting means for delay-detecting a signal; a phase rotating means for performing a phase rotation on the delayed detection signal; and a phase detected by receiving an output of the phase rotating means. A phase identification unit that identifies a signal transmitted from the modulated signal, and a comparison unit that performs pattern matching of the output of the phase identification unit and the frame synchronization signal, until the frame synchronization signal is detected by the comparison unit. 32. The demodulation device according to claim 8 , wherein a phase of said phase rotation means is rotated. 36. The apparatus according to claim 36, further comprising a band-limiting filter that receives an output signal of the frequency correction unit, limits a band of the output signal, and outputs the band-limited signal to the phase correction unit. 36. The demodulation device according to claim 8 , wherein an output signal of any one of a unit, the band-limiting filter, and the phase correction unit is input, and the frame start position is detected. 37. A case where the carrier synchronization auxiliary signal superimposes information for identifying phase modulation applied to a modulation signal to be a next packet at a position to be time-division multiplexed in the communication frame. An information detection unit that detects a period of the signal subjected to the minimum phase modulation based on the information, and outputs a signal providing the minimum phase modulation period to the timing generation unit, wherein the timing generation unit includes: , In addition to the synchronization signal period,
37. The demodulation device according to claim 8 , wherein a timing signal for giving the minimum phase modulation period is generated. 38. When the frequency at which the pseudo-synchronization occurs is fg [Hz], the frequency step means sets (-1)
^{n-1 × n × fg [} Hz] (n = 1,2, ...) , characterized in that the shifting stepwise the frequency to be input to the phase correcting means based on, in any one of claims 12 to 15 The demodulator according to any of the preceding claims. 39. A carrier synchronization auxiliary signal that has been phase-modulated using a phase modulation having the smallest number of phases in a communication frame (hereinafter, referred to as a minimum phase modulation), together with a plurality of phase-modulated signals, is dispersed at equal time intervals. in so that the, when a division multiplexed demodulation method of the communication frame, by detecting the synchronizing signal of said communication frame, frame
Detecting a system start position, and providing at least a period of the carrier synchronization auxiliary signal (hereinafter referred to as a synchronization signal period) in the period in which the minimum phase modulation is performed based on the frame start position .
Generating a timing signal, and using a period given by the timing signal a plurality of times.
With the frequency correction operation according to the minimum phase modulation and
Performing a phase correction operation . 40. A step of detecting a frequency pull-in state and determining whether or not the frequency is a frequency at which pseudo-synchronization occurs. If the result of the determination in the determining step is a frequency at which pseudo-synchronization does not occur, phase correction is performed. 40. The demodulation method according to claim 39 , further comprising: initializing an operation. 41. A step of detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal; and a transmission control signal (TMC) included in the frame synchronization signal.
C) detecting a correction state of an error correction process; a phase synchronization state during the carrier synchronization auxiliary signal period;
A step of determining whether or not pseudo-synchronization is performed based on an error correction state during an MCC signal period; and, if the result of the determination in the determination step is pseudo-synchronization, a step of initializing a phase correction operation. Item 39. The demodulation method according to Item 39 . 42. A step of detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal; and a transmission control signal (TMC) included in the frame synchronization signal.
(C signal), detecting a phase synchronization state during the period, the phase synchronization state during the carrier synchronization auxiliary signal period, and
A step of determining whether or not a pseudo-synchronization is performed based on the phase synchronization state during the MCC signal period; and, if the result of the determination in the determination step is a pseudo-synchronization, a step of initializing a phase correction operation. Item 39. The demodulation method according to Item 39 . 43. A step of detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal; and a transmission control signal (TMC) included in the frame synchronization signal.
C) detecting a correction state of an error correction process; a phase synchronization state during the carrier synchronization auxiliary signal period;
A step of determining whether or not a pseudo-synchronization is performed based on the error correction state during the MCC signal period; and, if the result of the determination in the determination step is a pseudo-synchronization, a step of stepwise changing the frequency at which the phase correction operation is performed The demodulation method according to claim 39 , further comprising: 44. A step of detecting a state of phase synchronization during a period of the carrier synchronization auxiliary signal; and a transmission control signal (TMC) included in the frame synchronization signal.
(C signal), detecting a phase synchronization state during the period, the phase synchronization state during the carrier synchronization auxiliary signal period, and
A step of determining whether or not a pseudo-synchronization is performed based on the phase synchronization state during the MCC signal period; The demodulation method according to claim 39 , further comprising: 45. A step of detecting a frequency pull-in state and determining whether or not the frequency is a frequency at which pseudo-synchronization occurs. If the result of the determination in the determining step is a frequency at which pseudo-synchronization does not occur, phase correction is performed. 44. The demodulation method according to claim 43 , further comprising: initializing an operation. 46. A step of detecting a frequency pull-in state to determine whether or not a frequency at which pseudo-synchronization occurs. If the result of the determination in the determining step is a frequency at which pseudo-synchronization does not occur, phase correction is performed. 45. The demodulation method according to claim 44 , further comprising: initializing an operation. 47. A step of detecting a state of phase synchronization; a step of detecting a state of C / N (carrier power / noise power) of a received signal; For C /
When N is high, after detecting the phase error due to the minimum phase modulation in the synchronization signal period, and detecting the phase error due to the phase modulation having the largest number of phases in the communication frame other than the synchronization signal period of the communication frame, 40. The demodulation method according to claim 39 , further comprising: performing a phase correction operation during the entire period of the communication frame. 48. A step of detecting a state of phase synchronization, a step of detecting a state of C / N (carrier power / noise power) of a received signal, and a transmission control signal (TMC) included in the frame synchronization signal.
Detecting the correction state of the error correction processing of the C signal), and when the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting a phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and a predetermined second threshold value, , The phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed, and if the C / N is lower than the second threshold value, 40. The demodulation method according to claim 39 , further comprising: performing a phase correction operation after detecting a phase error due to the minimum phase modulation during a period in which the minimum phase modulation is performed. 49. A step of detecting a state of phase synchronization, a step of detecting a state of C / N (carrier power / noise power) of a received signal, and a transmission control signal (TMC) included in the frame synchronization signal.
Detecting the correction state of the error correction processing of the C signal), and when the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting a phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and a predetermined second threshold value, Within the period other than the period in which the phase modulation having the largest number of phases (hereinafter, referred to as the maximum phase modulation) is performed, the phase error due to the corresponding phase modulation is detected. If it is low, performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and performing phase synchronization and completing error correction. I If the C / N is higher than the first threshold value, a phase error due to the minimum phase modulation is detected in the synchronization signal period, and the communication is performed in a period other than the synchronization signal period of the communication frame. after detecting a phase error by the maximum phase modulation in the frame, further comprising the step of performing a phase correction operation, the demodulation method according to claim 39. 50. A step of detecting a state of phase synchronization; and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
There is a step of detecting the state of
When N is high, after detecting the phase error due to the minimum phase modulation in the synchronization signal period, and detecting the phase error due to the phase modulation having the largest number of phases in the communication frame other than the synchronization signal period of the communication frame, 40. The demodulation method according to claim 39 , further comprising: performing a phase correction operation. 51. A step of detecting a state of phase synchronization; and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
A transmission control signal (TMC) included in the frame synchronization signal.
Detecting the correction state of the error correction processing of the C signal), and when the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting a phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and a predetermined second threshold value, , The phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed, and if the C / N is lower than the second threshold value, 40. The demodulation method according to claim 39 , further comprising: performing a phase correction operation after detecting a phase error due to the minimum phase modulation during a period in which the minimum phase modulation is performed. 52. A step of detecting a state of phase synchronization; and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
A transmission control signal (TMC) included in the frame synchronization signal.
Detecting the correction state of the error correction processing of the C signal), and when the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting a phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and a predetermined second threshold value, Within the period other than the period in which the phase modulation having the largest number of phases (hereinafter, referred to as the maximum phase modulation) is performed, the phase error due to the corresponding phase modulation is detected. If it is low, performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and performing phase synchronization and completing error correction. I If the C / N is higher than the first threshold value, a phase error due to the minimum phase modulation is detected in the synchronization signal period, and the communication is performed in a period other than the synchronization signal period of the communication frame. after detecting a phase error by the maximum phase modulation in the frame, further comprising the step of performing a phase correction operation, the demodulation method according to claim 39. 53. A step of detecting a state of phase synchronization; a step of detecting a state of C / N (carrier power / noise power) of a received signal; For C /
When N is high, after detecting the phase error due to the minimum phase modulation in the synchronization signal period, and detecting the phase error due to the phase modulation having the largest number of phases in the communication frame other than the synchronization signal period of the communication frame, further comprising the step of performing a phase correction operation, 40 claims
46. The demodulation method according to any one of 46 . 54. A step of detecting a state of phase synchronization, a step of detecting a state of C / N (carrier power / noise power) of a received signal, and a transmission control signal (TMC) included in the frame synchronization signal.
Detecting the correction state of the error correction processing of the C signal), and when the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting a phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and a predetermined second threshold value, , The phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed, and if the C / N is lower than the second threshold value, 47. The demodulation according to claim 40 , further comprising a step of performing a phase correction operation after detecting a phase error due to the minimum phase modulation during a period in which the minimum phase modulation is performed. Method. 55. A step of detecting a state of phase synchronization, a step of detecting a state of C / N (carrier power / noise power) of a received signal, and a step in which phase synchronization is performed and error correction is completed. If the C / N is higher than the predetermined first threshold, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the first threshold and the predetermined threshold are determined. If the C / N is between the second threshold value and a phase error due to the corresponding phase modulation in a period other than the period where the phase modulation with the largest number of phases is performed in the communication frame, the phase error is detected. Performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, when the C / N is lower than the second threshold value; The Comprising a demodulation method according to any one of claims 41, 43 or 45. 56. A step of detecting a state of phase synchronization; a step of detecting a state of C / N (carrier power / noise power) of a received signal; and a transmission control signal (TMC) included in the frame synchronization signal.
Detecting the correction state of the error correction processing of the C signal), and when the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting a phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and a predetermined second threshold value, Within the period other than the period in which the phase modulation having the largest number of phases (hereinafter, referred to as the maximum phase modulation) is performed, the phase error due to the corresponding phase modulation is detected. If it is low, performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and performing phase synchronization and completing error correction. I If the C / N is higher than the first threshold value, a phase error due to the minimum phase modulation is detected in the synchronization signal period, and the communication is performed in a period other than the synchronization signal period of the communication frame. after detecting a phase error by the maximum phase modulation in the frame, further comprising the step of performing a phase correction operation, according to claim 40, 42, 44 or 4
7. The demodulation method according to any one of 6 . 57. A step of detecting a state of phase synchronization, a step of detecting a state of C / N (carrier power / noise power) of a received signal, and a step in which phase synchronization is performed and error correction is completed. If the C / N is higher than the predetermined first threshold, a phase error due to the corresponding phase modulation is detected in the entire period of the communication frame, and the first threshold and the predetermined threshold are determined. If C / N between the second threshold value and the second threshold value, the corresponding phase modulation is performed in a period other than the period in which phase modulation having the largest number of phases (hereinafter, referred to as maximum phase modulation) is performed in the communication frame. And if the C / N is lower than the second threshold, after detecting the phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed ,phase Performing a correct operation; and performing phase synchronization and not completing error correction, and when C / N is higher than the first threshold value, the minimum phase in the synchronization signal period. Detecting a phase error due to modulation and detecting a phase error due to the maximum phase modulation within the communication frame during a period other than the synchronization signal period of the communication frame, and then performing a phase correction operation . 43. The demodulation method according to any one of 43 and 45 . 58. A step of detecting a state of phase synchronization; and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
There is a step of detecting the state of
When N is high, after detecting the phase error due to the minimum phase modulation in the synchronization signal period, and detecting the phase error due to the phase modulation having the largest number of phases in the communication frame other than the synchronization signal period of the communication frame, further comprising the step of performing a phase correction operation, 40 claims
46. The demodulation method according to any one of 46 . 59. A step of detecting a state of phase synchronization; and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
A transmission control signal (TMC) included in the frame synchronization signal.
Detecting the correction state of the error correction processing of the C signal), and when the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting a phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and a predetermined second threshold value, , The phase error due to the corresponding phase modulation is detected in a period other than the period in which the phase modulation with the largest number of phases is performed, and if the C / N is lower than the second threshold value, 47. The demodulation according to claim 40 , further comprising a step of performing a phase correction operation after detecting a phase error due to the minimum phase modulation during a period in which the minimum phase modulation is performed. Method. 60. A step of detecting a state of phase synchronization; and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
Detecting the state of (1) and (2) when phase synchronization has been performed and error correction has been completed, and when C / N is higher than a predetermined first threshold value, A phase error due to the corresponding phase modulation is detected, and if C / N is between the first threshold value and a predetermined second threshold value, the phase having the largest number of phases in the communication frame is detected. A phase error due to the corresponding phase modulation is detected in a period other than the period in which the modulation is performed, and when the C / N is lower than the second threshold value, the synchronization signal period and the minimum phase modulation are performed. Performing a phase correction operation after detecting a phase error due to the minimum phase modulation during a period of time, the demodulation method according to any one of claims 41, 43, and 45 . 61. A step of detecting a state of phase synchronization; and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
A transmission control signal (TMC) included in the frame synchronization signal.
Detecting the correction state of the error correction processing of the C signal), and when the phase synchronization is performed and the error correction is completed, and the C / N is higher than a predetermined first threshold value. Detecting a phase error due to the corresponding phase modulation in the entire period of the communication frame, and if the C / N is between the first threshold value and a predetermined second threshold value, Within the period other than the period in which the phase modulation having the largest number of phases (hereinafter, referred to as the maximum phase modulation) is performed, the phase error due to the corresponding phase modulation is detected. If it is low, performing a phase correction operation after detecting a phase error due to the minimum phase modulation in the synchronization signal period and the period in which the minimum phase modulation is performed, and performing phase synchronization and completing error correction. I If the C / N is higher than the first threshold value, a phase error due to the minimum phase modulation is detected in the synchronization signal period, and the communication is performed in a period other than the synchronization signal period of the communication frame. after detecting a phase error by the maximum phase modulation in the frame, further comprising the step of performing a phase correction operation, according to claim 40, 42, 44 or 4
7. The demodulation method according to any one of 6 . 62. A step of detecting a state of phase synchronization; and a transmission control signal (TMC) included in the frame synchronization signal.
The bit error rate of the C signal before error correction is measured, and C / N (carrier power / noise power) is determined based on the bit error rate.
Detecting the state of (1) and (2) when phase synchronization has been performed and error correction has been completed, and when C / N is higher than a predetermined first threshold value, A phase error due to the corresponding phase modulation is detected, and if C / N is between the first threshold value and a predetermined second threshold value, the phase having the largest number of phases in the communication frame is detected. A phase error due to the corresponding phase modulation is detected in a period other than the period in which the modulation (hereinafter, referred to as the maximum phase modulation) is performed, and when the C / N is lower than the second threshold value, the synchronization signal period And performing a phase correction operation after detecting a phase error due to the minimum phase modulation during the period in which the minimum phase modulation is performed, and when there is phase synchronization and error correction is not completed, Said When the C / N is high with respect to the threshold value of 1, a phase error due to the minimum phase modulation is detected in the synchronization signal period, and the phase error due to the maximum phase modulation in the communication frame other than the synchronization signal period in the communication frame is detected. 46. The demodulation method according to claim 41 , further comprising: performing a phase correction operation after detecting a phase error. 63. A case where the carrier synchronization auxiliary signal superimposes information for identifying phase modulation applied to a modulation signal to be a next packet at a time division multiplexed position in the communication frame. Detecting a period of the signal on which the minimum phase modulation is performed based on the information, outputting a signal giving the minimum phase modulation period to the step of generating the timing signal, and generating the timing signal. 63. The demodulation method according to claim 39 , further comprising generating a timing signal that gives the minimum phase modulation period in addition to the synchronization signal period. 64. The step of changing the frequency stepwise includes the step of: (-1) ⁿ⁻¹ × n × fg [Hz] (n = 1, where fg [Hz] is a frequency at which pseudo synchronization occurs.
47. The demodulation method according to claim 43 , wherein the frequency at which the phase correction operation is performed is shifted stepwise based on (2,...).