WO1996034393A1

WO1996034393A1 - Semiconductor storage device, and method and system for modulating pulse used for the device

Info

Publication number: WO1996034393A1
Application number: PCT/JP1996/000972
Authority: WO
Inventors: Masakazu Aoki; Katsuhiro Shimohigashi; Kazuo Yamakido; Kanji Oishi; Katsuyuki Sato; Kazumasa Yanagisawa; Masashi Horiguchi; Takeshi Sakata; Tomonori Sekiguchi
Original assignee: Hitachi, Ltd.
Priority date: 1995-04-26
Filing date: 1996-04-09
Publication date: 1996-10-31

Abstract

A semiconductor storage device is provided with an address input circuit to which a row address signal is inputted synchronously with a row address strobe signal and a column address signal is inputted synchronously with a column address strobe signal, a memory array in which a plurality of dynamic memory cells are arranged in a matrix and address selection is performed in units of bits based on the address signal inputted through the address input circuit, a modulation circuit which pulse-modulates the data read out in the units of a plurality of bits by using the column address strobe signal as a reference signal, or a clock signal as the reference clock in the case of a synchronous dynamic RAM, and a demodulation circuit which demodulates the inputted pulse-modulated write signals. Therefore, the access speed to a memory can be substantially increased by inputting/outputting a large amount of data through pulse modulation while the input/ouput interface of an existing dynamic RAM or synchronous dynamic RAM is used as it is.

Description

Description: Semiconductor memory device and pulse modulation method and system used therefor

The present invention relates to a semiconductor memory device and a pulse modulation method and system used therefor, and mainly relates to a dynamic RAM (random access memory), a pulse modulation method used for data input / output thereof, and a microcomputer using the same. It relates to technology that is effective for use in data processing systems. Background art

A general proposal for applying communication technology to LSI design has been made in "Nikkei Microdevices", pages 100 to 106, published by Nikkei Tuna & Hill Inc., September 1994.

In a data processing device such as a microcomputer system, the operating speed of a semiconductor memory device cannot follow the speeding up of a microprocessor, and as a result, a memory device and its management are used, such as using a cache memory having a plurality of layers. Has the problem of becoming complicated. In addition, there is a demand for highly flexible multi-bit systems for system expansion. However, such multi-bit systems cannot help increasing the chip area due to the increase in input / output circuits, and greatly reduce the degree of integration. Become. As for measures against high speed, simply increasing the operating frequency would require extra power measures such as air cooling from the viewpoint of mounting system design due to the increase in power consumption, and it would be advisable to increase the operating current. is not. Therefore, the inventor of the present application has substantially applied the above-described communication technology to a semiconductor memory device. We considered a method for speeding up memory access and a suitable pulse modulation method and system.

Accordingly, it is an object of the present invention to provide a substantially faster memory access with a simple configuration, and to provide a pulse modulation method and a system suitable therefor. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The present invention provides an address input circuit in which a row address signal is input in synchronization with a row address strobe signal and a column address signal is input in synchronization with a column address strobe signal, and a plurality of dynamic memory cells. A memory array that is arranged in a matrix and selects an address in units of a plurality of bits based on an address signal input through the address input circuit, and uses the column address strobe signal as a reference clock or a synchronous dynamic type In the RAM, using a clock signal as a reference clock, a modulation circuit that pulse-modulates the data read in units of multiple bits as described above and a demodulation circuit that demodulates the pulse-modulated input write signal are provided. Dynamic RAM or Synchronous Dynamic While the input and output interface one face of R AM and for as interest, to allow input and output of large amounts of data by pulse modulation, to realize high-speed substantial memory access.

The present invention also provides a pulse modulation method for inputting / outputting data to / from a dynamic RAM of an address multiplex type, which includes capturing a column address signal by a column address strobe signal input at least first. Invalidate, reset the data terminal to low level at this timing, and prepare the data to be transmitted in the output section The pulse signal at the data terminal is raised from low level to high level based on the timing, and the pulse signal is changed from high level to low level in accordance with the data consisting of multiple bits to be transmitted. In AM, the data terminal is reset to the low level in synchronization with the low level of the clock signal, and the rising or falling timing of the pulse signal or both the rising and falling timings are changed in accordance with the data to be transmitted. By using the existing dynamic RAM or synchronous dynamic RAM input / output interface as it is, it is possible to input / output a large amount of data by pulse modulation with a simple configuration.

The present invention further includes a modulation circuit for pulse-modulating data consisting of a plurality of bits read from a memory cell in units of a plurality of bits, and a demodulation circuit for demodulating a pulse-modulated input write signal. A plurality of semiconductor storage devices, a demodulation circuit for generating an address signal and a control signal required for the operation of the plurality of semiconductor storage devices, demodulating a read modulation signal, a modulation circuit for forming a write modulation signal, and By providing a memory controller including an interface circuit for performing input / output of data to and from a microprocessor, high-speed data transfer between the memory controller and the semiconductor storage device is achieved by pulse modulation. High-speed data transfer is performed, and the above interface circuit is connected to a corresponding microphone processor. It may be faster to fit, to enable high speed operation while simplifying the entire system. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic block diagram showing an embodiment of a dynamic RAM according to the present invention and a DRAM controller used therein. FIG. 3 is a schematic timing chart for explaining an example of the operation of the dynamic RAM of FIG. 1; and FIG. 3 is a timing chart for explaining the refresh mode of the dynamic RAM of FIG. FIG. 4 is a timing chart for explaining the pulse modulation method according to the present invention, and FIG. 5 is a state transition chart for explaining the operation of the dynamic RAM according to the present invention. FIG. 6 is a schematic circuit diagram showing one embodiment of the pulse modulation circuit according to the present invention. FIG. 7 is a schematic circuit diagram showing one embodiment of the pulse demodulation circuit according to the present invention. FIG. 8 is a timing chart for explaining a training operation used in the pulse modulation method according to the present invention, and FIG. 9 is a detail showing the first and second cycle parts in FIG. FIG. FIG. 10 is a schematic circuit diagram showing an embodiment of a demodulation circuit having a learning function according to the present invention. FIG. 11 is a diagram showing another embodiment of a dynamic RAM according to the present invention. FIG. 12 is a schematic block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied and a controller corresponding to the synchronous DRAM. FIG. FIG. 14 is a timing chart for explaining an example of the operation of the synchronous dynamic RAM in the figure. FIG. 14 shows one embodiment of the modulator mounted on the synchronous dynamic RAM in FIG. FIG. 15 is a schematic circuit diagram showing an example. FIG. 15 is a schematic circuit diagram showing one embodiment of a demodulator mounted on the synchronous dynamic RAM of FIG. 12 described above. The figure is a block diagram showing one embodiment of a PLL circuit used in the present invention. FIG. 7 is a schematic circuit diagram showing an embodiment of the memory circuit for starting the PLL circuit of FIG. 16 described above. FIG. 18 is a PLL circuit according to the present invention and the memory for starting the PLL circuit. FIG. 19 is a timing chart for explaining an example of the operation of the circuit, FIG. 19 is a characteristic chart for explaining the pulse modulation mode according to the present invention, and FIG. Applied convenience FIGS. 21A and 21B are main views of a memory board serving as a memory storage unit in the overnight system. FIGS. 21A and 21B show a configuration of an embodiment of a personal computer system using a dynamic RAM to which the present invention is applied. FIG. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 shows a schematic block diagram of a dynamic RAM (hereinafter sometimes simply referred to as DRAM) according to the present invention and a DRAM controller used in the dynamic RAM. The DRAM and the DRAM controller are each formed on a single semiconductor substrate, and are mounted on a common mounting substrate constituting a memory device. A plurality of DRAMs are mounted on the mounting board constituting the memory device with respect to the DRAM controller. In the drawing, one DRAM is exemplarily shown as a representative.

DRAM has the following configuration. In the memory array, dynamic memory cells are arranged in a matrix at intersections of word lines and complementary data lines (or complementary bits Di). The memory array's code line is selected by the row decoder. Row (row or X) decoders also include word line drivers. The complementary data line of the memory array is provided with a sense amplifier that amplifies a minute signal read from the memory cell to the complementary data line and amplifies the complementary data line to a high level Z low level. In the figure, the power is omitted. The complementary data line includes a precharge circuit and the like. A column selection switch is provided between the complementary data line and the common 1/0 (input / output) data line. A column (column or Y) decoder forms a selection signal for the power selection switch and selects from among the complementary data lines. The connected complementary data line and the common I / O data line.

The address buffer captures the row and column addresses input in chronological order. That is, a row address input in synchronization with the row address strobe signal ZRAS is fetched and supplied to the row decoder. In addition, it captures the input column address in synchronization with the column address strobe signal / CAS and supplies it to the column decoder. However, although not shown, an address buffer capacity is usually provided for each of the row address and the column address. The RAS buffer is an input circuit for receiving the row address strobe signal AS, and the CAS buffer is an input circuit for receiving the column address strobe signal ZCAS. The symbol / means that the signal to which this is attached is a low (level) enable signal. The same applies to the symbol Z attached to signals appearing thereafter.

The control unit is equipped with control logic, timing generation and mode registration. The control logic receives the above-mentioned signals ZRAS and ZCAS and a write enable signal ZWE (not shown) or an output enable signal / OE together therewith, and identifies the determination of the operation mode. The timing generation circuit generates a timing signal corresponding to the above operation mode. For the control logic and timing generation, the operation mode is determined based on the control signal from the host system, and ZRAS and ZCAS and ZWE and ZOE (not shown) are generated by timing generation in response to the determination. The mode register is provided for controlling input / output of data by pulse modulation as described later according to the present invention, and sets a pulse modulation mode corresponding to the operation mode of the DRAM.

The common IZO data line is connected on one side to the input terminal of the main amplifier, and on the other side to the output terminal of the write buffer. Toes In read mode, the signal read to the common I / O data line is

The signal is amplified and output by the main amplifier. In the write mode, the write signal output by the write buffer is transmitted to the selected memory cell via the path of the complementary data line of the column selection switch memory array which is turned on by the common IZO data line. In this example

A modulation circuit for pulse-modulating a read signal and a demodulation circuit for demodulating a pulse-modulated input write signal to an original signal are provided for substantially speeding up memory access. That is, the output signal of the main amplifier causes the output buffer to transmit the output signal in the form of pulse modulation via the modulation circuit. The write signal in the form of pulse modulation is supplied to a demodulation circuit via an input buffer, where it is demodulated into an original binary signal and transmitted to a write buffer.

A PLL (Phase Locked Loop) circuit generates a reference timing signal for pulse modulation and demodulation as described later, using a CAS signal as a reference clock, although not particularly limited. The voltage limiter generates a constant voltage VCL necessary for the operation of the internal circuit. Although not particularly limited, the constant voltage VCL is used for stabilizing the PLL circuit.

The DRAM controller receives an address signal and a control signal supplied from a host system such as a microprocessor and the main clock M-CLK, synchronizes a row address with a row address strobe signal RAS generated by generation of a RAS signal, and outputs a CAS signal. The row address is synchronized with the address strobe signal ZCAS generated by the signal generation, multiplexed and supplied to the DRAM.

The 10 buffer transmits and receives pulse-modulated data to and from the DRAM. In a write operation to the DRAM, the write data input from the host system is pulse-modulated by the modulator. In the read operation from the DRAM, the signal read from the DRAM in the form of pulse modulation is demodulated by the demodulator and transmitted to the host system. The PLL circuit generates a reference timing signal necessary for modulation and demodulation as described above. Like the DRAM above, the operating voltage of the PLL circuit is the constant voltage E formed by voltage limiting.

FIG. 2 is a schematic timing chart for explaining an example of the operation of the DRAM. To operate the above DRAM in the pulse modulation mode, the signal ZCAS is set to the low level N times while the signal ZRAS is set to the high level. As a result, the pulse modulation mode is set, and for example, logic 1 is set in the mode register. The mode setting and the PLL circuit are locked by the input of such N signals ZCAS.

When a logic 1 is set in the mode register, even if the signal ZCAS is also set to the π level at the timing tC0 slightly after the row address fetch timing tR due to the level of the signal / RAS, The column address fetch operation by the low level of this signal ZCAS is invalidated. In this embodiment, the output terminal Dout in the high-impedance state (undefined level) is reset to the low-level reference potential by the level of the signal ZCAS.

The reason for disabling the capture of the column address by the signal ZCAS at the timing tC0 is that, in addition to making the signal CAS a continuous level N times as described above, WCBR (ZRAS = H, Address key-in by ZCAS = L, ZWE = L), fuse Z mask option, and input from external DC voltage terminal may be combined. Here, H indicates a high level and L indicates a low level.

The second signal after the above RAS is set to low level. At the timing t C 1 when the level is set, the first column address Col-1 is captured. Subsequently, the second and third column addresses Col-2 and Col-3 are fetched sequentially in the same manner as in the normal high-speed page mode. A plurality of bits of the read signal are read by the column addresses Col-1, Col-2, and Col_3, respectively, and the read signal Dout changes from a high level to a low level in response to the read signal tTf tTf2 and tTf. 3 is changed and output by pulse modulation.

In the write mode, which is omitted in the figure, in the write mode, a write signal is input in which the fall to the low level is pulse-modulated based on the rise of the signal itself to the high level. It is demodulated and written through the write buffer.

FIG. 3 shows an evening diagram for explaining the refresh mode of the DRAM. Entering refresh mode by CBR (CAS before RAS refresh) is similar to conventional DRAM. Times SB 1, SB 2, and RF indicating the relationship between the signal / RAS and ZCAS in the figure correspond to the operation state in the chip in the state transition diagram of FIG. 5 described later. That is, SB 1 is in standby state 1, SB 2 is in standby state 2, and RF is in the refresh state. In order to reduce the power consumption, in the above-mentioned refresh mode and the above-mentioned N times of the ZCAS reference continuous pulse input, the address buffer activation current and the like by the power and the signal ZCAS are cut off.

FIG. 4 is a timing chart for explaining the pulse modulation method according to the present invention. In this embodiment, for the sake of simplicity of explanation, a case is shown in which data is modulated (multiplexed) by converting two bits into four values (= 2 ² ). The relationship between the signals ZR AS and CAS in the pulse modulation mode is the same as in FIG. In the figure, the part surrounded by the square 21 is the first signal. Signal / CAS is ignored and the second signal ZCAS captures the column address Col-1 to indicate the timing. Timings SB1, AKA2, and A3 in the figure correspond to the operation states in the chip in the state transition diagram in FIG. 5 described later.

Time t PC:, t CP, and t CAS are the high-speed page mode cycle time in conventional DRAM, the ZCAS precharge time in the high-speed page mode, and the no CAS pulse width in the high-speed page mode, respectively. Shows. The respective times t PC, t CP, and tCAS in the current high-speed DRAM are at least about 40 ns, 10 ns, and 15 ns. Therefore, since the operation time of the RAS circuit is currently at least about 45 ns at present, by ignoring the first ZCAS as in this embodiment, the time t CP can be reduced (for example, 10ns) ZCAS can be supplied at high speed. If the operation time of the CAS circuit is further shortened (speeded up), a mode that ignores ZCAS consisting of multiple cycles such as the second and third cycles may be provided to increase the data rate.

The data terminal Dout is reset from the undefined level in the high impedance state (High-Z) to the reference level at the toe level at the first low-level timing t st of / CAS. Then, at the timing tTr 1 when the data is transferred to the I / O part, the data is changed from the low level to the high level. The receiving side (DRAM controller in the embodiment of FIG. 1) detects this at the high-level threshold V i H (t R r 1).

The data terminal Dout is shifted to a low level at a predetermined timing tTf1 according to the data multiplexed into the multilevel information by the modulation circuit. On the receiving side, this is detected at the threshold V i L on the oral level (tRf 1). In the figure, an example in which the binary data 11 is multiplexed and transmitted as "3" is shown in a portion surrounded by a square 22. And In the reading operation performed subsequently in the high-speed page mode, an example is shown in which the binary data 01 is multiplexed to "" and the binary data 00 is multiplexed and transmitted as "0".

The enlarged portion 23 is an enlarged view of a portion surrounded by the square 22. In the pulse modulation method according to the present invention, a modulation reference pulse 0Ti and a demodulation reference pulse 0Rj based on the frequency of ZCAS are formed as reference clocks on both the transmission side and the reception side by respective PLL circuits. I have. On the transmitting side (modulation circuit), when the binary data is read from the memory array to the I0 portion, the reference clock is reset (〇ut-Reset), and the data terminal Dout is raised to a high level (0T 0). The binary data is converted into multi-level data between the reference clocks 0T1 to 0T7, and the binary data is dropped to a low level in synchronization with any one of the reference clocks 0 クロック 8 to 0Τ11. When "3" is output as described above, it is set to low level by the reference clock 0Τ11.

On the receiving side, the rising edge of the data terminal Dout is detected at the threshold ViH, and the reference clock 0Rj is reset (In-Reset). From this point, the clock øRj is counted and a pulse (0R11 in the example in the figure) corresponding to the falling edge of the transfer signal Dout detected at the threshold Vi is sent to the demodulation circuit. Return to 1 for binary values. In the figure, in order to facilitate understanding of the invention, a transfer signal Dout is shown commonly on the transmission side and the reception side so that the DRAM output signal Dout is input as a reception signal of the DRAM controller without delay. I have. In the pulse modulation method described above, the rising and falling waveforms are symmetric if the transmission line of the transmission signal Dout is linear while using the existing timing signal ZCAS. Therefore, the delay of the reference clocks 0TO to 0RO can be made equal to the delay of 0T11 to 0R11. This As a result, even if it takes time for the rise and fall of the transmission signal Dout, the reference clock øTl1 generated at the first timing on the transmitting side, for example, and the first pulse 0R1 1 on the receiving side can be used. Can be received correctly.

Here, if the signal Dout is not set to the low-level reference potential, the rising and falling waveforms become asymmetrical as indicated by the dotted line, so that the delay of the reference clock 0TO to 0R0 and 0T11 to 0R11 And the delay on the transmitting side may not be equal, and the pulse count on the transmitting side may not match that on the receiving side. In addition, the waveform of the first transfer signal Dout is different from that of the second transfer signal, so that waveform distortion is likely to occur. Therefore, in the present invention, the above-mentioned problem is solved by resetting the data terminal Dout to the low level at once by the low level of the first signal ZCAS as described above.

In the above description, the timing at which the level of the data terminal Dout changes from the low level (reference potential) to the high level is the timing at which data is transferred to the 10 portion, but is not limited to this. Instead, various changes can be made. For example, after the ZRAS has fallen, the level of the data terminal D out may be changed from a low level to a high level in response to the ZCAS falling a predetermined number of times (for example, twice).

FIG. 5 is a state transition diagram for explaining the operation of the dynamic RAM according to the present invention. The transition between the standby state 1 (Standbyl; SB 1) and the standby state 2 (Standby 2; SB 2) and the refresh state (Refresh; RF) are the same as those of a normal DRAM. That is, the standby state 1 is when both / RAS and / CAS are high level.

H is in the state of sleepy 2 / RAS and ZC AS high level It is in the low level (HZL). Standby state 2 is a preparation mode for entering CBR refresh. That is, if ZRAS is also set to the low level in standby state 2, the above-mentioned refresh state (RF) is entered. Here, by setting ZRAS to the high level and the low level, the standby state 2 and the refresh state (RF) are alternately performed, and the refresh address is incremented. Then, when both the signals ZRAS and ZCAS are set to the high level HZH in the refresh state (RF) or the standby state 2, the state returns to the standby state 1.

In this embodiment, an active state 1 (Active1; A1) and an active state 2 (Active2; A2) are provided for the pulse modulation mode. That is, the active state 1 is set by the signal ZRAS and the LZH of the signal ZCAS, and the active state 2 is changed by setting the signal ZCAS to low level with a slight delay as described above. By providing such two states A 1 and A 2, the capture of the column address is invalidated even when the first signal ZCAS is set to the low level, and the data terminal Dout is reset to the low level during this period. .

When signal ZRAS and signal ZCAS are set to LZH, active state 3 (Active3; A3) transits and memory access including column selection operation is performed. In the normal DRAM mode, the state transits from the standby state 1 to the active state 3 as shown by a dotted line in FIG. Such two types of state transition are selectively performed by setting the mode register.

FIG. 6 is a schematic circuit diagram of an embodiment of the pulse modulation circuit according to the present invention. Although not particularly limited, this embodiment shows an example in which 4-bit data is multiplexed into 16 values. The 4-bit data sent from the memory array to the 10 part via the main amplifier is a latch circuit. It is taken in. The oscillator is reset at the timing when the data is taken into this latch circuit, and 1, 0 T 2 ········ are generated sequentially by the element delay circuit DE. In the figure, 0 TO is a virtual pulse representing the delay of the reset node part RZS. For example, the one-shot pulse øT0 generated at the above timing is sequentially transmitted by the element delay circuit DE with a delay of a unit delay time. In the reset Z start part (RZS), the pulse may be simply raised from a low level to a high level. In this case, the rise of the pulse is sequentially transmitted by the element delay circuit DE with a delay of a unit delay time.

From the control circuit, the timing signal DOL is supplied to the output buffer in synchronization with the high level of the first signal ZCAS after the fall of RAS, and the output terminal Dout is lowered to the low level. The output buffer changes the output terminal Dout from the low level to the high level in synchronization with the timing when the binary data is taken into the latch circuit. The binary data received by the latch circuit is decoded by a 4-bit decoder, and one of 16 levels from "0" to "15" is set to a high level to turn on the switch MOSFET. Let it go. For example, if the binary data is 1 1 1 1, the decoded signal “1 5” is set to high level, and the timing signal 0 Ti corresponding to the delay signal of the final stage is supplied to the output buffer. Fall from high level to low level.

The reference data counter is used for training as described below. In other words, the training data formed by the reference data counter is transmitted between the transmitting side and the receiving side, and the receiving side generates a correction value that compensates for variations such as delay in the signal transmission path. . The reference data counter generates a plurality of types of test data in a predetermined order instead of data read from the memory array and inputs the generated test data to the latch circuit. The above oscillator does not constitute an oscillating circuit in a strict sense in the circuit as it is. However, the delay time of the element delay circuit DE is controlled by a control voltage VCTL formed by a PLL circuit as described later, so that the delay time is synchronized with the signal ZCAS and multiplied with respect to the frequency. Then, the reference timing signal 0T1, 0Τ2 ··· 'is generated by equally dividing the period of the signal ZCAS into a plurality of parts, so it can be regarded as an oscilloscope.

FIG. 7 is a schematic circuit diagram of an embodiment of the demodulation circuit according to the present invention. Although not particularly limited, this embodiment shows an example in which the modulated pulse multiplexed into 16 values as described above is demodulated in 4-bit data. The rising edge of the input pulse is detected by the input buffer, the other circuits (oscillation and fall detection, latch and demodulation tables) are reset (In-Reset), and the oscillation is started at the same time. In the oscillator, 0R 1 and R 2-... ′ Are sequentially generated by the element delay circuit DE similar to the above. In the figure, 0RO is a virtual pulse representing the delay of the reset Z-set portion RZS. Next, by detecting the falling edge, the pulse 0Ri that matches the timing is taken out, taken into the latch circuit, and converted into binary data in the demodulation table. It is the same as the modulation circuit described above in that the oscillator receives the control voltage VCTL from the PLL (or DLL; digital locked loop) and stabilizes it with high accuracy by synchronizing it.

FIG. 8 is a timing chart for explaining a training operation used in the pulse modulation method according to the present invention. The figure shows an example in which 2-bit data is multiplexed into four values and transmitted. The signal transmission line has nonlinearity, and the rise time tr and fall time tf of the pulse may be different, or tr and tf may vary. You. In order to compensate for the distortion of the transmission pulse due to such a cause, the following training is performed prior to data transmission.

In the same way as above, the first signal CAS after the RAS fall is continuously applied, and the training pulses TRN0 to TRN3 are generated. That is, the signal ZRAS is reset each time to create the condition of the first signal AS. When the signal ZRAS is kept at the low level, the operation in the pulse modulation mode as described above is performed.

In this embodiment, in synchronization with the timings TRN0 to TRN3, 00, 01, 10 and 11 are generated in the reference data counter, and "0", "'", "2", On the receiving side, the multiplexed input signals "0", "'," are output so that the data output from the demodulation table becomes 00, 01, 10 and 11 Perform correction (assignment) so that 2 "and" 3 "correspond to the above output data. The first and second cycle parts indicated by square A in the figure are explained with reference to the following detailed diagram.

FIG. 9 shows a detailed view of the first and second cycle portions in FIG. FIG. (A) shows an example where the rise time tr and the fall time tf do not match, and FIG. (B) shows a case where the rise time tr and the fall time tf vary. It is shown. In the same figure (A), since the rise time tr is shorter than the fall time t, the transmitter outputs a modulation pulse corresponding to "0" at the eighth reference pulse 0T8 from reset timing 0. However, on the receiving side, it is captured by the 10th reference pulse 0R10 from reset timing 0. On the transmitting side, a modulation pulse corresponding to “1” is output at the ninth reference pulse 0 T9 from reset timing 0, but on the receiving side, the first reference pulse 0R 1 from reset timing 0 is reset. Captured at 1. Therefore, in the demodulation table, the above-described reference pulse 0R10 forms binary data 00 corresponding to "0", and the reference pulse 0R11 forms binary data 01 corresponding to "1". Make the assignment.

In the same figure (B), since the rise time tr varies in the fall time tf, for example, on the transmitting side, the modulation pulse corresponding to "0" in the eighth reference pulse 0T8 from reset timing 0 It is output, but is received at the 10th reference pulse 0R10 from the reset timing 0 on the receiving side. On the other hand, on the transmitting side, the modulation pulse corresponding to "1" is output at the ninth reference pulse 0T9 from the reset timing 0. On the receiving side, the 12th reference pulse from the reset timing 0 Captured at φR12. Therefore, the above-mentioned reference pulse 0R10 forms a binary data 00 corresponding to "0", and the reference pulse 0R12 forms a binary data 01 corresponding to "1". To the demodulation table. As described above, the same demodulation table is allocated to the other multiplexed pulses "2" and "3". In addition, as described above, all multiplexed pulses are transferred, and a demodulation table is allocated for each multiplexed pulse. Alternatively, the minimum "0" and the maximum "3" are transmitted, and "" and "2" between them are transferred. It is also possible to make an assignment by predicting from the above two training results, or transfer one representative "0" and transfer it to the other "," 2 "and" 3 " In other words, the allocation may be performed by predicting from the above one training result.

FIG. 10 is a schematic circuit diagram of an embodiment of a demodulation circuit having a learning function. The figure shows an example in which 4-bit data is multiplexed into 16 values and transferred. The reference data ROM stores 16 kinds of data from binary data 0000 to 1 1 1 1 corresponding to "0" to "15". The driver counter uses the training signal TRN With j, the multi-level signal transferred from the predetermined number of trainings is selected.

On the other hand, the fall timing of the actually received reception pulse is taken into the latch driver through the switch MOSFET which is turned on by the timing signal formed by the fall detection circuit. For example, if the multi-level data "0" is transferred in the first training TRN0 and it is the receiving-side reference timing signal 0R10, it is selected by the selection signal 10 corresponding to the timing 0R10. The 0000 bit pattern read from the reference data ROM is taken into the 4-bit RAM. Hereinafter, similarly, multi-valued data transfer corresponding to "'to" 15 "is performed, and each bit pattern of the reference data ROM is assigned to each set of RAM at the reception timing corresponding to each transfer. In the data ROM, the reference data is amplified by the amplifier and transmitted to the complementary data di D0, D0 to D3, and ZD3 on the RAM side through the switch MOSFET which is turned on by the training signal TRNj. At this time, the data from the reference data ROM is written into the 4-bit static RAM whose code is selected by the selection signal corresponding to the timing signal received at this time. The data from AM is read out as demodulated data During training, the timing 0R i to the demodulation table is set to a different path from the actual data transfer path. As such obtain, the SRA M corresponding to 5 to 0 0000, 1 1, 1 to 2 is also possible to interpolate the entire table as 000 Mr .....

FIG. 11 is a schematic block diagram showing another embodiment of the dynamic RAM according to the present invention. In this embodiment, the memory array is divided into four parts, and four bits are transmitted to four main amplifiers. 16 bits of data are read out as a whole, and 4 bits are modulated into 16-level multi-valued data by four modulators M, respectively, and the data is effectively transmitted from four data terminals IZ 00 to 1/03. Output 16-bit data. The write signals multiplexed and input as described above are demodulated into data of 4 bits each by 4 demodulators D, and 4 bits are written by 4 sets of write buffers, a unit of 16 bits in total. It is made to perform the write operation in.

The memory array is divided into four memory arrays as a whole, and each is divided into four in the column direction. The sense amplifier and the first common data line in one memory array are divided into four, and the first common data line is led to the IZO portion through the second common data line extending in the row direction. That is, when one of the four memory arrays is selected, one word line is selected by the row decoder. In the figure, the selected memory array is indicated by oblique lines.

The memory array is divided into four, and in each divided array, four pairs of complementary data lines are connected to four pairs of first common complementary data lines. As the first common data Di, the data corresponding to the selected memory array is connected to the second common data line and guided to the above-mentioned I / O portion. In the case of the read operation, the read signal is amplified by the main amplifier. Is performed. In the case of a write operation, a write signal is transmitted by a write buffer.

The command decoder is included in the control logic and determines various operation modes and generates a control signal necessary for the determination. In the mode register, an operation mode including the above-described pulse modulation mode is set. In addition to generating the timing signal necessary for the operation of the dynamic RAM, the timing generation circuit generates the signal DOL in the pulse modulation mode, and controls the output buffer 0 B during signal modulation to control the data terminal. IZ〇 0 to Reset IZO3 from the high impedance state to the low level reference potential. .

The signal ZCAS input from the CAS buffer is supplied to a PLL circuit, where a control voltage VCTL is generated. The voltage limiter receives the power supply voltage Vcc and generates a constant voltage VCL required for the operation of the internal circuit. In addition, there are a refresh circuit, an address buffer circuit, an input buffer corresponding to the signals / WE and OE, and a control circuit for receiving the input buffer, but they are omitted in FIG.

FIG. 12 is a schematic block diagram of an embodiment of a synchronous DRAM (hereinafter simply referred to as SDRAM) to which the present invention is applied and a controller corresponding thereto. Although a plurality of SDRAMs are provided for the controller, one SDRAM is exemplarily shown in FIG. This SDRAM includes a memory array forming a memory bank 1 and a memory array forming a memory bank 2. Each memory array has dynamic memory cells arranged in a matrix, the selection terminals of the memory cells are coupled to word lines (not shown), and the data input / output terminals of the memory cells arranged in the same column have complementary data. Connected to a line (not shown).

One of the not-shown read lines of the memory bank 1 is driven to a selected level in accordance with the result of decoding the row address signal by the row decoder. A complementary data line (not shown) of the memory bank 1 is connected to a sense amplifier and a column selection circuit. The sense amplifier is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column selection circuit in that case is a switch circuit for selecting complementary data lines individually and conducting them to a common IZO data line. The column selection circuit outputs the result of decoding the column address signal by the column decoder. Therefore, the selection operation is performed. Similarly, a row decoder, a sense amplifier, a common IZO data line, and a column decoder are provided on the memory bank 2 side. The common I / O data line is connected on one side to the input terminal of the main amplifier and on the other side to the output terminal of the write buffer.

The row address signal and column address signal supplied from the address input terminal are taken into the row address buffer and column address buffer in the address multiplex format. The supplied address signal is held by each buffer. Although the row address buffer is omitted in the figure, in the refresh operation mode, a function is provided to capture a refresh address signal output from the refresh counter as a row address signal. The output of the column address buffer is supplied as the reset data of the column (column) address counter, and the column address count is set according to the operation mode specified by a command or the like to be described later. Alternatively, a value obtained by sequentially incrementing the column address signal is output to the column decoder.

The command decoder is not particularly limited, but includes a clock signal M-CLK, a chip select signal ZCS, a column address strobe signal ZPCAS, a row address strobe signal ZPRAS, and a clock enable signal CKE and a write enable signal ZWE (not shown). External control signals and control data from address inputs are supplied, and internal timing for controlling the operation mode of the SDRAM and the operation of the above-mentioned circuit block based on the level change and timing of those signals. It forms the signal, and has control logic (not shown) and a mode register (initial setting register) for that.

The clock signal M-CLK is input to a phase comparator of a PLL circuit (or DLL circuit) used for pulse modulation in the present invention. It is used to synchronize with the internal clock formed by. The control voltage VCTL formed by the PLL circuit is used as a control voltage of an oscillator provided in the modulator or the demodulator as described above, is synchronized with the clock signal M-CLK, and is substantially synchronized therewith. Generates reference clocks 0T i and 0R i that are delayed.

The chip select signal / CS indicates the start of a command input cycle by its low level. When the chip select signal ZCS is at high level (chip is not selected), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. The / PRAS, / PCAS, and / WE signals have different functions from the corresponding signals in the normal DRAM, and are significant signals when defining a command cycle described later. The clock enable signal CKE indicates the validity of the next clock signal. When the signal CKE is at a high level, the rising edge of the next clock signal M-CLK is valid, and when it is at a low level, it is invalid. It is said. The row address signal is defined by a row address strobe synchronized with a rising edge of a clock signal M-CLK (internal clock signal). The level of the address signal in a non-active command cycle.

The specific address signal is regarded as a bank selection signal in the row address strobe's non-active command cycle. That is, when the specific address signal is at a low level, the memory bank 1 is selected, and when the specific address signal is at a high level, the memory bank 2 is selected. The selection control of memory banks 1 and 2 is not particularly limited, but only the row decoder on the selected memory bank is activated, all the column switch circuits on the unselected memory bank are not selected, and the input buffer is on the selected memory bank only. And connection to output buffer Can be performed.

Other specific address signals in the precharge command cycle indicate the mode of precharge operation with respect to the complementary data line, etc., and the high level indicates that the target of precharge is both memory banks, and the low level indicates that. Indicates that one of the memory banks specified by the specific address signal is a target of precharging.

The column address signal is defined by the level of the address signal in a read or write command (column address read command, column address write command) cycle synchronized with the rising edge of the clock signal M-CLK (internal clock). . The column address defined in this way is used as the start address for burst access.

Next, the main operation modes of the SDRAM specified by the command will be briefly described. In the mode register set command, the data to be set (register set data) is given via the address terminal. The register setting data is not particularly limited, but includes burst length, CAS latency, and write mode. Although not particularly limited, the burst length that can be set is 1, 2, 4, 8, and full page (256), the CAS latency that can be set is 1, 2, 3, and the write mode that can be set. Are burst write and single write. In addition, the pulse modulation mode according to the present invention is assigned by utilizing the vacant portion of the command as described above.

The above CAS latency indicates how many cycles of the internal clock signal are spent from the fall of ZP CAS to the output operation of the output buffer in the read operation specified by the column address and read command described later. . Data read before read data is determined This requires an internal operating time, which is set according to the operating frequency of the internal clock signal. .

The row address strobe 'bank active command (A c) is a command to enable the instruction of the address strobe and the selection of the memory bank by a specific address signal. The signal is taken in as a low address signal other than the specific address signal as a select signal of the specific address signal memory bank. The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is specified, the word line in the specified memory bank is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

The column address' read command (R e) is a command necessary to start the burst read operation and a command to give a column address strobe instruction. At this time, a predetermined address signal is captured as a column address signal. The column address signal thus captured is supplied to the column address counter as a burst start address. In the burst read operation instructed by this, the memory bank and the code line in it are selected by the row address strobe / bank active command cycle, and the memory cell of the selected word line is In accordance with the address signal output from the column address counter in synchronization with the internal clock signal, the data is sequentially selected and continuously read. The number of data read continuously is the number specified by the burst length. Also, the start of reading data from the output buffer is performed after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

The column address write command (W r) is used as a mode of write operation. When a burst write is set in the mode register, the command is necessary to start the burst write operation.When a single write is set in the mode register in the write operation mode, This is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The column address signal thus captured is supplied to the column address counter as a burst start address in burst write. The procedure of the burst write operation instructed thereby is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address' write command cycle.

The precharge command (P r) is a command for starting a precharge operation for the selected memory bank. An auto-refresh command is a command needed to initiate an auto-refresh. The burst stop 'in' full page command is a command necessary to stop the burst operation for a full page for all memory banks. The no operation command (N op) is a command for not performing a substantial operation.

In SDRAM, when a burst operation is being performed in one memory bank, another memory bank is specified in the middle of the burst operation, and the row address strobe's bank active command is supplied. The operation of the row address system in the other memory bank is enabled without affecting the operation in the other memory bank. For example, SDRAM has means for internally storing data, addresses, and control signals supplied from the outside, and the stored contents, especially addresses and control signals, are now stored for each memory bank. ing. Or row addresses The data for one lead line in the memory rib selected by the drive command cycle is latched to a latch circuit (not shown) for a read operation before the column operation. It has been

Therefore, as long as data does not collide at the data input / output terminals, during execution of a command whose processing has not been completed, a precharge command or row command for a memory bank different from the memory bank to be processed by the command being executed is executed. Address strobe · It is possible to issue a bankactive command to start the internal operation in advance.

SDRAM can input and output data, address, and control signals in synchronization with the clock signal M-CLK, so that large-capacity memories similar to DRAM can operate at high speed comparable to SRAM, and By specifying the number of data to be accessed for one lead line by the burst length, the selection status of the column system is sequentially switched by the built-in column address counter, and a plurality of data are accessed. The ability to read or write in the evening continuously will be appreciated.

In this embodiment, pulse modulation and demodulation functions are provided for the SDRAM as described above. The clock signal M-CLK is used as a reference timing signal required for the pulse modulation and demodulation. In other words, since the clock signal M-CLK is supplied constantly, a reference clock synchronized with it can be formed by the PLL (DLL) circuit. In addition, since the operation mode is specified by the command, the pulse modulation mode can be set by the command, and the SDRAM can be used as is, except for adding a modulation circuit and a demodulation circuit as described below. it can.

Of the I0 part, the read path that receives the output signal of the main amplifier Is provided with a latchnoresist evening. In the latch register, transfer data for training is also stored. Although not particularly limited, the read signal is

Parity bits for error detection and correction are generated by the ECC or ED circuit and supplied to the modulator. The modulator multiplexes the output data and the corresponding parity bit and outputs the result. At this time, the clock signal M-CLK is used. The clock signal M-CLK is used not only for the frequency of the pulse but also as a reference for timing, so that both the rising and falling edges are modulated as described later. .

In this case, to improve the data transfer accuracy, (1) Dout is output during one CAS latency period to transfer the reference data. (2) Send data at the rising edge of Dout and send parity bit (verification or correction) data at the falling edge of Dout. Verification may be performed by sending the same data twice at both rising and falling times. In a Hamming code, a 3-bit parity bit can correct a 1-bit error in 4-bit data, so error correction is possible with 4-bit modulation.

A demodulator and an ECC (error detection and correction) circuit or ED (error detection circuit) as described above are also provided in the I0 portion of the write system between the input buffer and the write buffer. In the timing generation circuit, in addition to generating various timings required for normal SDRAM operation, a signal DOL is generated, and an output buffer is controlled when a modulation signal is transmitted. Reset from high impedance state to low level reference potential. The signal TRNk is a timing signal required for the training operation, and controls the latch Z register to transmit predetermined training data instead of the main embed read signal.

The constant current E formed by the voltage limiter In addition to being used as the operating voltage of the constant circuit, it is also used as the operating voltage of the PLL to stabilize its operation. ―

In the SDRAM controller corresponding to the above-mentioned SDRAM, a modulator Z demodulator and an EC CZED circuit are provided between the 10 buffer on the memory side and the 1〇 buffer on the host system side. In addition to generating a control signal for accessing the SDRAM, the command generation circuit has a function of generating a timing signal DOL or TRNk required for pulse modulation according to the present invention. The constant voltage generated by the voltage limiter is used not only as an operating voltage of a predetermined circuit constituting the controller, but also as an operating voltage of the PLL circuit. FIG. 13 is an evening diagram for explaining an example of the operation of the SDRAM. The low address is fetched by the low level of the signal ZCS, the low level of the signal ZPRAS, and the high level of the signal ZPCAS, and the row address is selected. After that, a reference cycle of changing Dout to high level Z low level in synchronization with the clock signal M-CLK is performed over three cycles. This rising cycle and the falling edge are assigned on the receiving side as the training cycle.

The column signal is fetched three cycles after the clock signal M-CLK, and the read signal is multi-valued at the rising and falling edges of Dout. In the same figure, the same multi-valued "1" is output twice. An example of return and output is shown. When the burst length is 4, the multi-valued data is sequentially output over 4 cycles. Instead of performing the verification by sending the same data twice as described above, multi-values corresponding to the data are sent at the rising edge, and the corresponding error correction bits are sent at the falling edge as described above. May be sent. FIG. 14 shows a schematic circuit diagram of an embodiment of the modulator mounted on the SDRAM. The modulation circuit is basically the same as the modulation circuit described above. However, as in the above-described embodiment, data is sent at both the rising and falling edges of the output terminal Dout. Two timing signal output circuits are provided, one for the falling decoder and the other. Therefore, the oscillator is operated based on the rising edge of the clock signal M-CLK. The data of the clock signal M-CLK one clock before is sent to the decoder, and the next data is prepared in the latch circuit. Therefore, data can be transferred (modulation signal formation) immediately after the input of the clock signal M-CLK. The operation of the signal TRN k and the reference data is the same as described above. The setting of the training mode is performed by setting a command by an address key-in.

FIG. 15 shows a schematic circuit diagram of an embodiment of the demodulator mounted on the SDRAM. It is basically the same as the demodulation circuit described above, but since the data is sent at both the rising and falling edges of the output Dout as in the above embodiment, there are two systems for rising and falling. Circuit is provided. That is, the modulation signal at the rising edge is demodulated in the demodulation table corresponding to the rising edge detection circuit, and the modulation signal at the falling edge is demodulated in the demodulation table corresponding to the falling edge detection circuit. When the demodulated signal at the falling edge is a Hamming code, it is supplied to an ECC circuit to perform data error detection and correction. When only error detection is performed, the write operation is stopped. In addition, processing such as setting a flag to indicate an error or recording the error may be performed. In the training mode, the setting of the demodulation table allocation is performed in the same manner as described above. Note that the modulator and demodulator in the SDRAM replace the modulated signal obtained by multi-leveling the falling edge of Dout with the rising edge of the clock signal M-CLK instead of the ordinary dynamic RAM as described above. It goes without saying that it may be formed.

FIG. 16 is a block diagram of an embodiment of the PLL circuit used in the present invention. The external clock signal EXT.CLK input through the clock input buffer is supplied to one input of a phase frequency comparator (hereinafter, simply referred to as a phase comparator). The internal clock signal INT.CLK formed by a voltage-controlled oscillation circuit (hereinafter simply referred to as VC〇) is supplied to the other input of the phase comparator. The phase comparator compares the phases (frequency) of the two external clocks EXT. CLK and the internal clock INT. CLK, and forms an up signal and a down signal corresponding to the phase difference.

The ab signal and the down signal formed by the phase comparator are input to a loop filter composed of a charge pump circuit. In this roof fill, the control signal is increased by charging up the capacity according to the pulse width (phase difference) of the up signal, and the capacity is dis- posed according to the pulse width (phase difference) of the down signal. The control voltage is lowered by charging. That is, the loop filter integrates the up signal or the down signal as described above and converts it into a direct current. The output voltage of the loop filter is current-amplified by the buffer G and output as the control voltage VCTL.

The VCO is composed of a ring oscillator in which voltage variable delay stages are connected in cascade in a ring, and the delay time of the delay stage is controlled by the control voltage VCTL. The VCO has an oscillation frequency determined in accordance with the reciprocal ratio of the delay time, and is operated as a voltage-controlled oscillation circuit. In other words, the phase (frequency) of the internal clock INT.CLK matches the external clock EXT.CLK. If the phase is delayed (the frequency is lowered), the phase comparator forms an ap signal corresponding to the phase difference, so that the filter voltage increases the control voltage. As the control voltage is increased, the delay time of the voltage variable delay stage is shortened, the phase of the internal clock INT.CLK is advanced (the frequency is increased), and synchronization with the external clock EXT.CLK is achieved. Conversely, when the phase (frequency) of the internal clock INT. CLK is ahead of the external clock EXT. CLK (the frequency is increased), the phase comparator outputs the down signal corresponding to the above phase difference. As it forms, the charge pump circuit lowers the control voltage. As the control voltage is lowered, the delay time of the voltage variable delay stage is lengthened, the phase of the internal clock INT.CLK is delayed (the frequency is lowered), and the external clock EXT.CLK is synchronized.

Although not shown, in the DLL circuit, the VCO is a voltage variable delay circuit, and a delay time that is delayed by one clock with respect to the external clock EXT.INT is adjusted so that the internal clock INT.CLK is synchronized. The control voltage VCTL is supplied to an element delay circuit DE of the modulator and the demodulator. The same circuit as the above-mentioned element delay circuit is used for the variable voltage delay stage constituting the VC0. Although not particularly limited, the number of voltage variable delay stages of the VCO is equal to or greater than the number of stages of the element delay circuit in the above-mentioned oscillator. This makes it possible to generate a reference timing signal 0T i or 0R i required for the above-mentioned modulation or demodulation of one cycle of the reference clock ZCAS or M-CLK. In other words, the oscillator in the modulator or demodulator is controlled by the same control voltage VCTL as the same delay circuit as VC0 of the PLL circuit, so that the delay operation following the VCO is performed. The voltages 0Ti and 0R i can be synchronized with the clock signal ZCAS or M-CLK. FIG. 17 is a schematic circuit diagram of an embodiment of a storage circuit for starting a PLL circuit. When DRAJvI or SDRAM is in the data retention state for low power consumption, the PLL (or DLL) circuit stops its operation. However, in this case, it takes time until the PLL (or DLL) circuit operates stably when memory access is started, which substantially delays memory access.

The PLL starting memory circuit shown in the figure performs an AZD conversion operation and stores it in the shift register so that the control voltage VCLT formed during operation matches the voltage Vrr generated by the resistance voltage dividing circuit. . That is, a bit pattern is generated and stored in the shift register by the voltage comparison circuit so that the two voltages VCTL and Vrr match. Although not particularly limited, the internal clock signal INT.CLK is used for such AZD conversion operation.

When the memory access is resumed, a signal ørr is generated to turn on the switch MOSFET to short-circuit the inverted input and the output of the voltage comparison circuit. In this state, the voltage comparison circuit operates as a voltage follower circuit, and supplies the voltage Vrr as the control voltage VCTL to the PLL circuit in accordance with the bit pattern recorded in the shift register. The circuit can be stabilized at a high speed by restarting the circuit corresponding to the voltage Vrr.

FIG. 18 is a timing chart for explaining an example of the operation of the PLL circuit and its activation storage circuit. While the PLL circuit is operating, the startup storage circuit performs AZD conversion operation using the internal clock INT.CLK generated thereby, and stores the divided voltage Vr r corresponding to the control voltage V CTL in the shift register. Is stored. Entering the data retention state (standby state)

The operation of the PLL circuit is stopped. When the memory access is started, the mode is set to the recovery mode, and the signal 0r r is set to the high level for a certain period. As a result, the PLL circuit is restarted, and the voltage Vr is applied to the PLL circuit via the voltage comparison circuit formed in a voltage-floor form by the switch MOS FET turned on by the signal ørr. r is output as the control voltage VCTL of the PLL circuit. As a result, the PLL circuit restarts from the same voltage Vrr as that in the stable state, so that the stable lock state can be entered in a very short time 內. That is, by setting a short recovery time, it is possible to enter an active mode in which the PLL circuit operates stably.

FIG. 19 is a characteristic diagram for explaining the pulse modulation mode according to the present invention. FIG. 3A is a characteristic diagram showing the relationship between the data rate and the clock frequency. As shown in the figure, in the pulse modulation mode, when multiplexing into 2N, the data terminal I0 can be equivalently multiplied by ^N by the pulse phase modulation PPM and the pulse width modulation PWMD. This allows higher data rates for the same clock frequency, in other words, faster memory access. For example, in the above-described embodiment, a memory access corresponding to the operation speed of the microprocessor can be realized only by speeding up the data transfer between the controller and the microprocessor in accordance with the above-mentioned data rate. .

FIG. 3B shows the relationship between the burst mode current and the clock frequency. If the data rate is the same, the clock frequency can be reduced accordingly, and the power can be significantly reduced. In addition, if a controller is provided on the microprocessor side, the actual number of IZO bits can be increased without increasing the number of data channels (bus width). it can.

FIG. 20 is a schematic diagram of a main part of a memory board as a memory storage unit in a computer system to which the DRAM of the present invention is applied. This memory board is a memory board composed of a plurality of memory modules. A plurality of packaged DRAMs of the present invention are mounted on the memory module, and the DRAMs of the present invention are connected to @ & ^ on the memory module.

Such a memory module is provided with the DRAM controller, and data transfer between the DRAM and the DRAM controller can be performed in the pulse modulation mode as described above. Through the DRAM controller, the address bus or data bus in the computer system is connected to the DRAM of the present invention by the connector on the memory module. This is performed by inserting the connector into the memory board slot of the memory unit in the memory storage unit in the computer system.

By doing so, the host system can access the memory in the same manner as a normal memory, and the number of DRAMs of the present invention that can be mounted on the memory board, that is, on the memory module, allows the storage of computer systems and the like. The information storage capacity of the device is determined.

FIG. 21 shows a configuration diagram of an embodiment of a personal computer system using a dynamic RAM to which the present invention is applied. Figure (a) shows a schematic diagram of the main part of the appearance, and Figure (b) shows a block diagram of the same.

In FIG. 1A, the system includes a floppy disk drive FDD, a main storage memory using DRAM to which the present invention is applied, and a battery-backed SRAM. And I / O device The floppy disk FD is inserted into the above-mentioned floppy disk drive FDD.

In the present embodiment, the present invention can be applied to a notebook-type personal computer or the like described in the example applied to a desktop type personal computer. A floppy disk is described as an example of the auxiliary function, but the present invention is not particularly limited.

Referring to FIG. 2B, the personal computer of this embodiment includes a central processing unit CPU as an information device, an I-bus built in the information processing system, a BUS Unit, a high-speed memory such as a main storage memory and an extended memory. Memory control unit for accessing memory, DRAM (or SDRAM) and extended RAM (DRAM or SDRAM according to the present invention) as a main storage memory, a basic control program, etc. It is composed of a ROM (flash EPROM) and a keyboard controller KBDC with a keyboard connected to the tip.

A display adapter as a display adapter is connected to the IZO bus, and a display is connected to the tip of the display adapter. Connected to the above IZO bus are a parallel boat Para 1 lei Port IZF, a serial boat such as a mouse Serial 1 Port IZF, a floppy disk drive FDD, and a buffer controller HDD bu ffer that converts to the HDD I from the above IZO bus. Is done. An extended RAM and a DRAM or SDRAM according to the present invention as a main memory are connected to a bus from the memory control unit Memory Controller 1 Unit. The extended RAM is not particularly limited, but is constituted by the DARM or SDRAM according to the present invention. Although not particularly limited, the above DRAM or SDRAM The body may be provided with the above controller, or the memory control unit may be provided with pulse modulation and demodulation functions.

An outline of the operation of the personal computer system will be described. When the power is turned on and the operation is started, first, the central processing unit CPU accesses the ROM through the 10 bus to perform initial diagnosis and initial settings. Then, the system program is loaded from the auxiliary storage device (floppy disk or hard disk) into the DRAM of the present invention as the main storage memory. The central processing unit CPU operates as accessing the HDD to the HDD controller through the IZO bus. When the loading of the system program ends, the processing proceeds according to the processing request of the user.

The user proceeds with the input and output of the process using the keyboard controller KBDC and the display adapter D ISP 1 ay adap ter on the IZO bus. Then, if necessary, an input / output device connected to the parallel boat Paria1PortI / F and the serial boat Serial1PortI / F is used. Further, in the case of the SDRAM according to the present invention as the main memory on the main body, if the main memory capacity is insufficient, the main memory is supplemented by the extended RAM. Although the figure shows the HDD as a hard disk drive, it can be replaced with a flash file using a flash memory FEPROM.

In such personal computers and workstations, high-throughput data transfer is possible due to the high performance of the microprocessor mounted on them. However, the current situation is that the memory side cannot cope with such a situation, and is coping with the above-mentioned multi-layered cache memory. In addition to the high throughput described above, There is also a need for highly flexible multi-bit 1-to-0 memory for expanding memory. However, with the conventional method of inputting and outputting binary data, the number of terminals increases, and there is a limit to increasing the number of bits.

In the DRAM or SDRAM according to the present invention, instead of shortening the access time itself in the memory as described above, multiple bits are accessed at the same time, and the data input / output portion is used. By using pulse modulation technology to increase the number of bits in the IZO equivalently, the above-mentioned high-throughput data transfer and multi-bit I / O with high flexibility for system expansion can be achieved. This is an excellent effect that can be realized simultaneously.

The operational effects obtained from the above embodiment are as follows.

(1) An address input circuit in which a row address signal is input in synchronization with a row address strobe signal and a column address signal is input in synchronization with a column address strobe signal, and a plurality of dynamic memory cells are arranged in a matrix. A memory array in which address selection is performed in units of a plurality of bits based on an address signal input through the address input circuit, and a column address strobe signal as a reference clock, or In a synchronous dynamic RAM, a clock signal is used as a reference clock, and a modulation circuit for pulse-modulating data read in units of a plurality of bits and a demodulation circuit for demodulating a pulse-modulated input write signal are provided. The existing dynamic RAM or synchronous die While using the input / output interface of the Mick RAM as it is, a large amount of data can be input / output by pulse modulation, which has the effect of substantially speeding up memory access. . (2) As a pulse modulation method for inputting / outputting data to / from dynamic multi-address type RAM, at least the first At this time, the terminal is reset to a low level, and the data to be transmitted is set based on the timing at which the data to be transmitted is prepared in the output section. The pulse signal at the data terminal is raised from a low level to a high level, and the pulse signal corresponding to data consisting of a plurality of bits to be transmitted is then changed from a high level to a low level, thereby obtaining a synchronous dynamic RAM. In this case, the data terminal is reset to a low level in synchronization with the low level of the clock signal, and the rising or falling timing of the pulse signal, or both the rising and falling timings, corresponding to the data to be transmitted, is set. By changing the existing dyna With the simple configuration, it is possible to input and output a large amount of data by pulse modulation while using the input / output interface of the Mick RAM or the Synchronous Dynamic RAM as it is.

(3) A plurality of modulation circuits provided with a modulation circuit for pulse-modulating data consisting of a plurality of bits read from a memory cell in units of a plurality of bits, and a demodulation circuit for demodulating a pulse-modulated input write signal. A semiconductor memory device, an address signal and a control signal required for the operation of the plurality of semiconductor memory devices, a demodulation circuit for demodulating a read modulation signal, a modulation circuit for forming a write modulation signal, and a microcontroller. By providing a memory controller including an interface circuit for inputting and outputting data to and from the processor, high-speed data transfer is performed between the memory controller and the semiconductor storage device by pulse-modulated data transfer. From above, adjust the above interface circuit to the corresponding micro It may be of an advantage of being permits faster operation while simplifying the entire system. (4) As described above, if the data transfer rate is the same, the operating frequency can be reduced correspondingly, and the effect that the operating current can be drastically reduced correspondingly can be obtained.

(5) When applied to dynamic RAM, stable by resetting the data pin to low level by disabling the capture of the column address by the first input signal / CAS while using the signal ZCAS as the reference clock. The effect that a modulated pulse modulation signal can be formed is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, various configurations can be adopted for the configuration of a DRAM or SDRAM memory array and the configuration of peripheral circuits corresponding to the configuration. The pulse modulation circuit may employ various embodiments such as those using pulse width modulation as described above and those using pulse phase modulation. Further, the controller may be built in or mounted on a system side such as a microphone processor. That is, the pulse modulation signal may be transmitted on the system bus. Industrial applicability

As described above, the present invention can be widely used for various semiconductor storage devices such as a static RAM, an EPROM, and a flash EEPROM in addition to the above-described DRAM and SDRAM. It is possible to construct a pulse modulation method for transferring data between the devices and a microcomputer system using the same. In other words, the comparative reading speed is slow, and However, by adopting the above-mentioned pulse modulation method without increasing the number of terminals, the number of bits of the IZO data can be equivalently increased, and the bus to which the data terminals are connected is provided. Since the width can be reduced, it will function effectively for simplification of microcomputer systems using it.

Claims

The scope of the claims

1. A modulation circuit that modulates data consisting of a plurality of bits read from a memory cell in units of a plurality of bits,

And a demodulation circuit for demodulating a pulse-modulated input write signal.

2. An address input circuit that receives a row address signal in synchronization with the row address strobe signal and a column address signal in synchronization with the column address strobe signal;

A memory array in which a plurality of dynamic memory cells are arranged in a matrix, and an address selection is performed in a unit of a plurality of bits based on an address signal input through the address input circuit;

A modulating circuit that modulates the data read from the memory array in units of the plurality of bits using the power ram address strobe signal as a reference clock;

A demodulation circuit for demodulating a pulse-modulated input write signal.

3. A mode setting register is provided.

2. The semiconductor memory device according to claim 1, wherein the operation of the modulation circuit or the demodulation circuit is enabled or disabled according to the mode information set in the mode setting register.

4. Mode setting Regis evening,

3. The semiconductor memory device according to claim 2, wherein the operation of the modulation circuit or the demodulation circuit is enabled or disabled according to the mode information set in the mode setting register.

5. When the modulation circuit is enabled by the mode setting register, In addition, the capture of the column address signal by the column address strobe signal input first is disabled,

At this timing, the modulation circuit resets the data terminal to the mouth level, and sets the pulse signal output from the data terminal to a low level based on the timing at which the read data is prepared in the output portion. 3. The semiconductor memory device according to claim 2, wherein said pulse signal is changed from a high level to a low level in response to said read data.

6. An input interface including an address input circuit corresponding to the synchronous dynamic RAM,

A plurality of dynamic memory cells are arranged in a matrix, and two memory banks for performing address selection in units of a plurality of bits based on an address signal input through the address input circuit, and the synchronous dynamic R A modulation circuit for pulse-modulating the data read from the memory bank in units of a plurality of bits using the clock signal at the input / output face of the AM as a reference clock;

And a demodulation circuit for demodulating a write signal that has been input after being subjected to Luth modulation.

7. When the modulation circuit is enabled by the mode setting register,

The modulation circuit resets the data terminal to a low level in synchronization with the low level of the clock signal, and sets the rising or falling timing of the pulse signal corresponding to the read data.

7. The semiconductor memory device according to claim 6, wherein both the rising timing and the falling timing are changed.

8. Data is output at the rising timing of the modulation output pulse. 8. The semiconductor memory according to claim 7, wherein at the fall timing, a parity bit for error correction added thereto is output.

9. An address input circuit that receives a row address signal in synchronization with the row address strobe signal and a column address signal in synchronization with the column address strobe signal;

A memory array in which a plurality of dynamic memory cells are arranged in a matrix, and a memory array in which an address is selected in units of a plurality of bits based on an address signal input through the address input circuit. As a pulse modulation method for input / output,

Disable the capture of the column address signal by the column address strobe signal input at least first,

At such a timing, the data terminal is reset to a low level, and the pulse signal of the data terminal is raised from a low level to a high level with reference to the timing at which the data to be transmitted is prepared in the output portion, and is composed of a plurality of bits to be transmitted. A pulse modulation method, wherein the pulse signal is changed from a high level to a low level according to data.

10. Pulse modulation method for inputting / outputting data to / from synchronous dynamic RAM

The data terminal is reset to the mouth level in synchronization with the low level of the clock signal in the input interface of the synchronous dynamic RAM,

The rising or falling timing of the pulse signal corresponding to the data to be transmitted, Alternatively, a pulse modulation method characterized by changing both the rising timing and the falling timing.

11. A modulation circuit for pulse-modulating data consisting of a plurality of bits read from a memory cell in units of a plurality of bits;

A plurality of semiconductor memory devices each including a demodulation circuit for demodulating a pulse-modulated input write signal;

An address signal and a control signal necessary for the operation of the plurality of semiconductor memory devices are generated, and a demodulation circuit for demodulating a read modulation signal, a modulation circuit for forming a write modulation signal, and a data circuit for a microprocessor are provided. A memory controller including an interface circuit for input and output

A system comprising: