US9406357B2 - Data capture system and method, and memory controllers and devices - Google Patents
Data capture system and method, and memory controllers and devices Download PDFInfo
- Publication number
- US9406357B2 US9406357B2 US14/148,488 US201414148488A US9406357B2 US 9406357 B2 US9406357 B2 US 9406357B2 US 201414148488 A US201414148488 A US 201414148488A US 9406357 B2 US9406357 B2 US 9406357B2
- Authority
- US
- United States
- Prior art keywords
- data
- signals
- bits
- capture
- phase signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 238000013481 data capture Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000000630 rising effect Effects 0.000 claims description 14
- 230000000737 periodic effect Effects 0.000 abstract description 7
- 239000000872 buffer Substances 0.000 description 12
- 230000007704 transition Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000013459 approach Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 3
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
Abstract
Description
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/148,488 US9406357B2 (en) | 2009-09-23 | 2014-01-06 | Data capture system and method, and memory controllers and devices |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/565,655 US8164975B2 (en) | 2009-09-23 | 2009-09-23 | Data capture system and method, and memory controllers and devices |
US13/438,634 US8625385B2 (en) | 2009-09-23 | 2012-04-03 | Data capture system and method, and memory controllers and devices |
US14/148,488 US9406357B2 (en) | 2009-09-23 | 2014-01-06 | Data capture system and method, and memory controllers and devices |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/438,634 Continuation US8625385B2 (en) | 2009-09-23 | 2012-04-03 | Data capture system and method, and memory controllers and devices |
Publications (2)
Publication Number | Publication Date |
---|---|
US20140126305A1 US20140126305A1 (en) | 2014-05-08 |
US9406357B2 true US9406357B2 (en) | 2016-08-02 |
Family
ID=43756510
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/565,655 Active 2030-11-05 US8164975B2 (en) | 2009-09-23 | 2009-09-23 | Data capture system and method, and memory controllers and devices |
US13/438,634 Active US8625385B2 (en) | 2009-09-23 | 2012-04-03 | Data capture system and method, and memory controllers and devices |
US14/148,488 Active 2029-12-24 US9406357B2 (en) | 2009-09-23 | 2014-01-06 | Data capture system and method, and memory controllers and devices |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/565,655 Active 2030-11-05 US8164975B2 (en) | 2009-09-23 | 2009-09-23 | Data capture system and method, and memory controllers and devices |
US13/438,634 Active US8625385B2 (en) | 2009-09-23 | 2012-04-03 | Data capture system and method, and memory controllers and devices |
Country Status (1)
Country | Link |
---|---|
US (3) | US8164975B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8164975B2 (en) | 2009-09-23 | 2012-04-24 | Micron Technology, Inc. | Data capture system and method, and memory controllers and devices |
KR102571176B1 (en) * | 2015-08-28 | 2023-08-28 | 에스케이하이닉스 주식회사 | Semiconductor apparatus and system using dual clock transmission |
US10339997B1 (en) | 2017-12-18 | 2019-07-02 | Micron Technology, Inc. | Multi-phase clock division |
US10366737B2 (en) | 2017-12-21 | 2019-07-30 | Micron Technology, Inc. | Management of strobe/clock phase tolerances during extended write preambles |
US10607671B2 (en) * | 2018-02-17 | 2020-03-31 | Micron Technology, Inc. | Timing circuit for command path in a memory device |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6671787B2 (en) | 1998-09-24 | 2003-12-30 | Fujitsu Limited | Semiconductor memory device and method of controlling the same |
US20080062788A1 (en) * | 2006-09-07 | 2008-03-13 | Kang Uk-Song | Parallel bit test circuit and method |
US7436904B2 (en) | 2003-02-20 | 2008-10-14 | Samsung Electronics Co., Ltd. | Data recovery apparatus and method for decreasing data recovery error in a high-speed serial link |
US7661010B2 (en) | 2006-05-31 | 2010-02-09 | Mosaid Technologies Incorporated | Apparatus and method for interfacing to a memory |
US7706195B2 (en) | 2007-12-28 | 2010-04-27 | Hynix Semiconductor Inc. | Strobe signal controlling circuit |
US7888991B2 (en) | 2009-03-23 | 2011-02-15 | Micron Technology, Inc. | Clock distribution network |
US20110069560A1 (en) | 2009-09-23 | 2011-03-24 | Micron Technology, Inc. | Data capture system and method, and memory controllers and devices |
US8023358B2 (en) | 2008-04-02 | 2011-09-20 | International Business Machines Corporation | System and method for providing a non-power-of-two burst length in a memory system |
US8049649B2 (en) | 2009-10-29 | 2011-11-01 | Hynix Semiconductor Inc. | Parallel-to-serial conversion circuit and method thereof |
US8055930B2 (en) | 2007-10-11 | 2011-11-08 | Samsung Electronics Co., Ltd. | Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices |
US20120218840A1 (en) * | 2011-02-28 | 2012-08-30 | Moon Jinyeong | Integrated circuit |
-
2009
- 2009-09-23 US US12/565,655 patent/US8164975B2/en active Active
-
2012
- 2012-04-03 US US13/438,634 patent/US8625385B2/en active Active
-
2014
- 2014-01-06 US US14/148,488 patent/US9406357B2/en active Active
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6671787B2 (en) | 1998-09-24 | 2003-12-30 | Fujitsu Limited | Semiconductor memory device and method of controlling the same |
US7436904B2 (en) | 2003-02-20 | 2008-10-14 | Samsung Electronics Co., Ltd. | Data recovery apparatus and method for decreasing data recovery error in a high-speed serial link |
US7661010B2 (en) | 2006-05-31 | 2010-02-09 | Mosaid Technologies Incorporated | Apparatus and method for interfacing to a memory |
US20080062788A1 (en) * | 2006-09-07 | 2008-03-13 | Kang Uk-Song | Parallel bit test circuit and method |
US8055930B2 (en) | 2007-10-11 | 2011-11-08 | Samsung Electronics Co., Ltd. | Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices |
US7706195B2 (en) | 2007-12-28 | 2010-04-27 | Hynix Semiconductor Inc. | Strobe signal controlling circuit |
US8023358B2 (en) | 2008-04-02 | 2011-09-20 | International Business Machines Corporation | System and method for providing a non-power-of-two burst length in a memory system |
US7888991B2 (en) | 2009-03-23 | 2011-02-15 | Micron Technology, Inc. | Clock distribution network |
US20110069560A1 (en) | 2009-09-23 | 2011-03-24 | Micron Technology, Inc. | Data capture system and method, and memory controllers and devices |
US8164975B2 (en) * | 2009-09-23 | 2012-04-24 | Micron Technology, Inc. | Data capture system and method, and memory controllers and devices |
US20120188828A1 (en) | 2009-09-23 | 2012-07-26 | Micron Technology, Inc. | Data capture system and method, and memory controllers and devices |
US8625385B2 (en) * | 2009-09-23 | 2014-01-07 | Micron Technology, Inc. | Data capture system and method, and memory controllers and devices |
US8049649B2 (en) | 2009-10-29 | 2011-11-01 | Hynix Semiconductor Inc. | Parallel-to-serial conversion circuit and method thereof |
US20120218840A1 (en) * | 2011-02-28 | 2012-08-30 | Moon Jinyeong | Integrated circuit |
Non-Patent Citations (1)
Title |
---|
Lee, Ki-Won et al., "A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL", IEEE Journal of Solid-State Circuits, vol. 42; No. 11, Nov. 2007, pp. 2369-2377. |
Also Published As
Publication number | Publication date |
---|---|
US20140126305A1 (en) | 2014-05-08 |
US20110069560A1 (en) | 2011-03-24 |
US8625385B2 (en) | 2014-01-07 |
US8164975B2 (en) | 2012-04-24 |
US20120188828A1 (en) | 2012-07-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110800056B (en) | System and method for refreshing a bank of memory while accessing another bank of memory using a shared address path | |
US10224091B1 (en) | Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path | |
US10482936B2 (en) | Signal training for prevention of metastability due to clocking indeterminacy | |
US6647523B2 (en) | Method for generating expect data from a captured bit pattern, and memory device using same | |
US6959016B1 (en) | Method and apparatus for adjusting the timing of signals over fine and coarse ranges | |
US20080126059A1 (en) | Method and apparatus for generating a sequence of clock signals | |
US20050180229A1 (en) | On die termination mode transfer circuit in semiconductor memory device and its method | |
US9406357B2 (en) | Data capture system and method, and memory controllers and devices | |
US20070028027A1 (en) | Memory device and method having separate write data and read data buses | |
KR20030069872A (en) | Semiconductor memory device and control method | |
US7519766B2 (en) | Method and device for transmission of adjustment information for data interface drivers for a RAM module | |
CN111108561B (en) | System and method for improving write preambles in DDR memory devices | |
US20230343383A1 (en) | Quadrature error correction circuit and semiconductor memory device including the same | |
US6971039B2 (en) | DDR to SDR conversion that decodes read and write accesses and forwards delayed commands to first and second memory modules | |
US6965532B2 (en) | Apparatus and method for controlling data output of a semiconductor memory device | |
US10832759B2 (en) | Half-width, double pumped data path | |
US6504767B1 (en) | Double data rate memory device having output data path with different number of latches | |
US8107315B2 (en) | Double data rate memory device having data selection circuit and data paths | |
US20150380070A1 (en) | Latch circuit and input/output device including the same | |
US20100278004A1 (en) | Address receiving circuit for a semiconductor apparatus | |
CN115762595A (en) | Apparatus including parallel pipeline control and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001 Effective date: 20190731 |
|
AS | Assignment |
Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |