WO1995027243B1 - Sound board emulation using digital signal processor - Google Patents
Sound board emulation using digital signal processorInfo
- Publication number
- WO1995027243B1 WO1995027243B1 PCT/US1995/003847 US9503847W WO9527243B1 WO 1995027243 B1 WO1995027243 B1 WO 1995027243B1 US 9503847 W US9503847 W US 9503847W WO 9527243 B1 WO9527243 B1 WO 9527243B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- audio
- output device
- bus
- communication area
- Prior art date
Links
- 230000015654 memory Effects 0.000 claims abstract 32
- 235000019800 disodium phosphate Nutrition 0.000 claims abstract 10
- 230000001808 coupling Effects 0.000 claims abstract 4
- 238000010168 coupling process Methods 0.000 claims abstract 4
- 238000005859 coupling reaction Methods 0.000 claims abstract 4
- 230000004044 response Effects 0.000 claims 3
- 241001562081 Ikeda Species 0.000 claims 2
- 230000000875 corresponding Effects 0.000 claims 1
Abstract
An improved audio-output device in which a DSP (202) operating under software control emulates a common command interface. The command interface has a set of registers that are made available to the CPU for reading and writing, even if there are no such physical registers available in the device. The audio-output device has a DSP (202) for interpreting and executing commands received from the CPU, a local memory (205) for storing data input to or output from the DSP (202), a bus-interface (BIF) (201) element for coupling the DSP (202) and memory (205) to a system bus (105), and a direct memory access (DMA) element for transferring data between the local memory (205) and the system bus (105). The local memory (205) has an emulation region for emulating a set of registers, and a communication region for transmitting messages between the local memory (205) and the system bus (105).
Claims
1. A computer system, comprising
a system bus, a processor coupled to said system bus, a system memory coupled to said system bus, and an audio-output device coupled to said system bus, said audio-output device comprising
a bus-interface element having means for coupling to said system bus, means for receiving a plurality of commands issued by said processor, and means for transmitting data to said processor;
a digital signal processor coupled to said bus-interface element, said digital signal processor having means for interpreting and executing instructions, means for receiving from said bus-interface element a signal indicative of receipt of at least one of said plurality of commands, and means for sending to said bus-interface element a signal indicative of completion of said at least one command;
a local memory coupled to said bus-interface element and to said digital signal processor, said local memory having a communication area; said bus-interface element having means for writing to said communication area upon receipt of a first subset of sad plurality of commands, and means for reading from said communication area upon receipt of a second subset of said plurality of commands; and said digital signal processor having means for reading from and writing to said communication area in response to said at least one command said communication area comprising a plurality of addressable registers pointed to by a base register, said base register comprising a dynamically allocable value indicative of an address of one of said plurality of addressable registers.
2 An audio-output device for coupling to a computer system, said system having a system bus, a processor coupled to said system bus, said audio-output device comprising
a bus-interface element having means for coupling to said system bus, means for receiving a plurality of commands issued by said processor, and means for transmitting data to said processor,
a digital signal processor coupled to said bus-interface element, said digital signal processor having means for interpreting and executing instructions, means for receiving from said bus- interface element a signal indicative of receipt of at least one of said plurality of commands, and means for sending to said bus-interface element a signal indicative of completion of said at least one command;
a memory coupled to said bus-interface element and to said digital signal processor, said memory having a communication area;
said bus-interface element having means for writing to said communication area upon receipt of a first subset of said plurality of commands, and means for reading from said communication area upon receipt of a second subset of said plurality of commands, and
said digital signal processor having means for reading from and writing to said communication area in response to said at least one command;
said communication area comprising a plurality of addressable registers pointed to by a base register, said base register comprising a dynamically allocable value indicative of an address of one of said plurality of addressable registers.
3. An audio-output device as in claim 2, wherein said communication area comprises a read communication area and a write communication area.
4. An audio-output device as in claim 3,
wherein said read communication area comprises a zeroth read communication area located in said memory at a zeroth offset from said address, and a first read communication area located in said memory at a first offset from said address; and
wherein said write communication area is located in said memory at a second offset from said address.
5. An audio-output device as in claim 4, comprising
a buffer located in said memory;
a system memory coupled to said system bus; and
a DMA transfer device coupled to said memory and to said system memory, said DMA transfer device being responsive to a command for transferring data between said memory and said system memory.
6. An audio-output device as in claim 2, wherein said means for receiving from said bus-interface element comprises a data communication word, said data communication word having a part indicating one of a set of registers for said digital signal processor to emulate and a part indicating data from said processor.
7. An audio-output device as in claim 6, wherein said data communication word comprises a part having a first state indicating said receipt of said at least one of said plurality of commands, and a second state indicating said completion of said at least one command.
8 An audio-output device as in claim 6, wherein said data communication word comprises a part indicating a read command or a write command, and a part indicating one of a plurality of said sets of registers for said digital signal processor to emulate
9. An audio-output device as in claim 2, wherein said memory comprises a program memory and a data memory.
10. An audio-output device as in claim 2, wherein said memory is coupled to said system bus.
11. An audio-output device as in claim 2, wherein said memory is not coupled to said system bus.
12 An audio-output device as in claim 2, wherein said signal indicative of receipt and said signal indicative of completion comprise signals in a polling configuration. 13. An audio-output device as in claim 2, wherein said signal indicative of receipt and said signal indicative of completion comprise interrupt signals STATEMENT UNDER ARTICLE 19
The invention provides a system in which a DSP, coupled to a system bus, can emulate a audio output device with a set of dedicated hardware registers for passing command parameters, but does not have to dedicate its time to watching for commands to that audio output device, and may devote time to other tasks besides emulating the audio output device. The hardware registers are emulated by separate readable and writable blocks of memory, dynamically allocated and pointed to by a base address register, and accessible to a main processor using a DMA device.
The cited patents are primarily directed to VO controllers which accept commands from a CPU and perform operations using I/O devices in response. Although some I/O controllers have memory and sometimes that memory might be readable or writable by the CPU, there is no provision therein for separate readable and writable blocks of memory for emulating dedicated hardware registers for passing command parameters, nor are they dynamically allocated and pointed to by a base address register.
US A 5,276,864 (Hernandez) has a DSP 51 coupled to a separate I/O bus 44, not the system bus 34, and which requires a separate audio controller 55. Hernandez thus teaches against emulating an audio output device using a DSP. The DSP 51 has instruction RAM 52 and data RAM 54, but there is no disclosure or suggestion that either such RAM should be used to emulate hardware registers for passing command parameters, nor are they dynamically allocated and pointed to by a base address register.
US A 4,901,232 (Harrington) and US A 5,276,684 (Pearson) show various I/O controllers which communicate with a CPU. Neither patent discloses or suggests emulating an audio output device using a DSP. Neither patent discloses or suggests readable and writable blocks of memory used to emulate hardware registers for passing command parameters, or which are dynamically allocated and pointed to by a base address register.
US A 4,663,730 (lkeda) shows a "sequence controller" which performs operations on behalf of a numerical controller. Ikeda also does not disclose or suggest emulating an audio output device using a DSP, or disclose or suggest readable and writable blocks of memory as claimed. Rather, Ikeda shows corresponding predetermined hardware registers for passing command parameters, and thus teaches against the claimed invention.
US A 5,283,883 (Mishler) merely shows DMA access to I/O device memories.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU21988/95A AU2198895A (en) | 1994-03-30 | 1995-03-29 | Sound board emulation using digital signal processor |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/219,841 US5598576A (en) | 1994-03-30 | 1994-03-30 | Audio output device having digital signal processor for responding to commands issued by processor by emulating designated functions according to common command interface |
| US08/219,841 | 1994-03-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1995027243A1 WO1995027243A1 (en) | 1995-10-12 |
| WO1995027243B1 true WO1995027243B1 (en) | 1995-11-23 |
Family
ID=22820994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1995/003847 WO1995027243A1 (en) | 1994-03-30 | 1995-03-29 | Sound board emulation using digital signal processor |
Country Status (3)
| Country | Link |
|---|---|
| US (3) | US5598576A (en) |
| AU (1) | AU2198895A (en) |
| WO (1) | WO1995027243A1 (en) |
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| US5528309A (en) | 1994-06-28 | 1996-06-18 | Sigma Designs, Incorporated | Analog video chromakey mixer |
-
1994
- 1994-03-30 US US08/219,841 patent/US5598576A/en not_active Expired - Lifetime
-
1995
- 1995-03-29 AU AU21988/95A patent/AU2198895A/en not_active Abandoned
- 1995-03-29 WO PCT/US1995/003847 patent/WO1995027243A1/en active Application Filing
-
1997
- 1997-01-22 US US08/786,295 patent/US5797029A/en not_active Expired - Lifetime
-
1998
- 1998-08-17 US US09/135,151 patent/US6175880B1/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9395953B2 (en) | 2006-12-05 | 2016-07-19 | Altera Corporation | Large multiplier for programmable logic device |
| US8886695B1 (en) | 2008-03-14 | 2014-11-11 | Altera Corporation | Normalization of floating point operations in a programmable integrated circuit device |
| US8886696B1 (en) | 2009-03-03 | 2014-11-11 | Altera Corporation | Digital signal processing circuitry with redundancy and ability to support larger multipliers |
| US8949298B1 (en) | 2011-09-16 | 2015-02-03 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
| US9098332B1 (en) | 2012-06-01 | 2015-08-04 | Altera Corporation | Specialized processing block with fixed- and floating-point structures |
| US8996600B1 (en) | 2012-08-03 | 2015-03-31 | Altera Corporation | Specialized processing block for implementing floating-point multiplier with subnormal operation support |
| US9189200B1 (en) | 2013-03-14 | 2015-11-17 | Altera Corporation | Multiple-precision processing block in a programmable integrated circuit device |
| US9379687B1 (en) | 2014-01-14 | 2016-06-28 | Altera Corporation | Pipelined systolic finite impulse response filter |
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