WO1991014320A1

WO1991014320A1 - Digital signal multiplexer

Info

Publication number: WO1991014320A1
Application number: PCT/CH1991/000036
Authority: WO
Inventors: Heinz Wiher
Original assignee: Siemens-Albis Ag; Siemens Aktiengesellschaft
Priority date: 1990-03-06
Filing date: 1991-02-08
Publication date: 1991-09-19
Also published as: CH679820A5; CA2054742A1; JPH05500893A; EP0471045A1; AU7227191A; IE910733A1; BR9104811A; PT96935A

Abstract

A digital signal multiplexer has a data bus (SH) with n lines which are accessed on the single-channel side by at least one interface sub-assembly (SSB-X) and on the multiple-channel side by at least one multiplexer (MXH-Z). Several single-channel interfaces (EKS-XY) on the interface sub-assemblies (SSB-X) receive and transmit the single-channel signals with bit rates of a lower hierarchical level. The multiplexer (MXH-Z) has at least one interface (EPIC-Z) which receives or transmits a data stream which has a bit rate of a higher hierarchical level and which is composed of different single-channel signals. All multiplexers (MXH-Z) and interface sub-assemblies are connected through a control bus (CB) to a programming and control station (CTRL). The digital signal multiplexer can be configured as desired according to various system arrangements. Several decentralized digital signal multiplexers can be configured in minimum time by the central station. Data communication between data lines on the same or different hierarchical levels and with the same or different bit rates is efficient and economical.

Description

Digital signal multiplexer

The present invention relates to a digital signal multiplexer according to the preamble of patent claim 1.

Digital voice signals and data with bit rates of a middle or lower hierarchy level, in particular of bit rates with 2400, 4800 and 9600 bit / s are preferably used over long distances in a time-multiplexed form at a higher hierarchy level, e.g. with bit rates of 64kbit / s or a few Mbit / s. A multiplexer used for this purpose and its use in a digital data network is known from St. Bürgin, P.A. Merz "MXB.2 data multiplexer 64kbit / s of the 2nd generation according to CCITT X.50" or P.A. Merz "Digital data network for the transmission of 2400, 4800 and 9600 bit / s on dedicated lines", Siemens Albis reports 3 (1987) p.9 ff. And p.4 ff. The described multiplexer MXB.2 makes it possible to multiplex five individual channels of 9600, ten individual channels of 4800 or twenty individual channels of 2400 bit / s and, with certain restrictions, combinations thereof to a total bit stream of 64 kbit / s. The data transfer takes place structured on the single and multiple channel side enveloping or frame. Figure 6 on page 12 shows a multiple system with four MXB.2 multiplexers, which are interconnected to form a multiple system and are operated by two multiplexer, clock central, interface and monitoring modules. Each MXB.2 multiplexer contains four interface modules, each of which can accommodate five individual channel interfaces and which are connected to two channel processor modules via a serial bus. The flexibility of such a multiple system is severely limited. The channel processor assemblies are not connected to one another via the serial bus and can only access a maximum of 4 X 5 single-channel interfaces. The options for the bit rates of the single channel interfaces are limited. A permissible readjustment of this multiple system to changed requirements of the user in each case requires a high level of development effort and manual access to mostly locally localized assemblies. The serial bus used in the system, which connects the individual channel interfaces with the channel processors, carries addresses as well as data and is consequently heavily loaded.

The present invention is therefore based on the object of specifying a digital signal multiplexer which can be freely configured as a function of various system constellations. The configuration of several decentrally localized digital signal multiplexers should be possible from a central location and within a very short time. The data traffic between data lines The same and different hierarchy levels and bit rates should be done efficiently and with little effort.

This object is achieved by the measures specified in the characterizing part of patent claim 1. Advantageous embodiments of the invention are given in further claims.

The digital signal multiplexer according to the invention has the following advantages: it can be configured quickly and as desired by an external control station. It also has optimal flexibility with regard to data transfer options, expandability and acceptance of any data transfer rates. It is therefore also universally applicable.

The invention is explained in more detail below with reference to drawings, for example. It shows:

Fig. 1 The block diagram of a digital signal multiplexer with various internal

Multiplexer and interface modules

Fig. 2 An internal multiplexer module

Fig. 3 An internal interface module

1 shows the block diagram of a digital signal multiplexer according to the invention, which has a data bus SH with n lines, on the single-channel side two interface modules SSB-1, SSB-2 and multiple-channel side two multiplexers MXH-1, MXH-2, which access via an EPIC-Z interface is connected to a parallel DH data bus. The data bus DH has high, preferably standardized data transmission rates such as 64 kbit / s, 2 Mbit / s, 8 Mbit / s etc. In addition to the multiplexer MXH-1 and the interface module SSB-1, which are provided as the minimum configuration of the digital signal multiplexer, further multiplexers MXH-Z can be used up to a maximum number, which corresponds to the number n lines of the data bus SH (Z = n). The interface modules SSB-1, SSB-2 have ten single-channel interfaces, interfaces EKS-11, ..., EKS-25, the data with lower or medium, preferably standardized data transmission rates such as 2400, 4800, 9600 bit / s receive or send via a subscriber line. Each MXH-Z multiplexer subsequently serves any number of individual channel interfaces EKS-XY located on any SSB-X interface module, which may have different data transmission rates. The resulting data stream, which is fed to the multiplexer MXH-Z, corresponds at most to the data transmission rate of the data bus DH.

The multiplexers MXH-Z and the interface modules SSB-X bitwise connect the data serially to one of the lines of the data bus SH or collect it from the latter. Such interconnection of all modules MXH-Z and SSB-X on a solid data bus SH results in maximum flexibility. Thus, in addition to SSB-X interface modules located on different interface modules EKS-XY with a multiplexer MXH-Z, different individual channel interfaces EKS-XY or multiplexer MXH-Z can also exchange data with one another. To increase the efficiency of the system, the data transfer on the lines of the data bus SH is provided bidirectionally. The complete process for dissolving and creating the frame structures of the incoming or outgoing data, as well as for the timely creation and removal on or from the lines of the data bus SH, is carried out by a management unit contained in each assembly MXH-Z, SSB-X preferably communicated parallel control bus CB depending on the existing module configuration. This gives the advantage that, after changes in the configuration of the modules, the digital signal multiplexer can be adapted to the new conditions from a central point with almost no delay. If e.g. If the individual channel interfaces EKS-13 and EKS-25 transmit data at the same transmission rate to the multiplexer MXH-2 and the operation of the first EKS-13 is stopped and the transmission rate of the second EKS-25 is doubled, the digital signal multiplexer can be changed accordingly Information can be quickly adapted to the administrative units of the affected modules MXH-2, SSB-1, SSB-2.

2 shows a multiplexer MXH-Z, a configuration and alarm controller KAC-Z and a cycle counter ZC, which are connected via the control bus CB to a programming and control station CTRL. It also contains a channel call memory KAR as well as a multiple channel controller VKC connected to the data bus DH via the EPIC-Z interface and a single channel controller EKC. The controllers EKC and VKC are connected to one another via a processor register memory PR controlled by the configuration and alarm controller KAC-Z. The channel call memory KAR is connected to the configuration and alarming controller KAC-Z, the single channel controller EKC, the cycle counter ZC and a demultiplexer DD and a multiplexer UM. The demultiplexer DD and the multiplexer UM are connected on the one hand to the single-channel controller EKC and on the other hand directly or via a buffer memory UR to the data bus SH. The circuit shown works as follows:

The multi-channel controller VKC synchronizes on frames of data that arrive via the data bus DH and the interface EPIC-Z. The data contained in each frame are subsequently broken down into individual channel data and stored in the processor register memory PR. Single channel data, which are available in the processor register memory PR for sending to the data bus DH, are taken by the multi-channel controller VKC, enclosed in a frame and output to the EPIC-Z interface. In the processor register memory PR, a memory area is assigned to each individual channel for each transmission direction, as well as to the multiple and single channel controllers for alarm messages to the configuration and alarm controller KAC-Z. A memory area for configuration data for the multiple and single channel controllers VKC, EKC is also provided in the processor register PR and in the channel call memory KAR. These configuration data are supplied to the configuration and alarming controller KAC-Z when the system is started up or when the system is changed, via the control bus CB, which subsequently writes them into the memories PR and KAR. The multiple and single-channel controllers VKC, EKC monitor the sequence of the data transfer and store any alarm messages in the processor register memory PR. These are removed by the configuration and alarm controller KAC-Z and passed on to the control station. The EKC single-channel controller has individual programs that can be called up for each transmission direction, which are used for bit-by-bit single-channel data transfer and for generating and checking the frame structure on the single-channel side. The configuration and alarm controller KAC-Z writes program configuration data units into the channel call memory KAR, which are cyclically cycled by the cycle counter ZC, read into the single channel controller EKC and by means of which an individual program is selected per cycle. A single channel data bit is fetched from one of the lines of the data bus SH and fed to the processor register memory PR via the multiplexer UM and the single channel controller EKC, or a single channel data bit provided by the multiple channel controller VKC is removed from the processor register memory PR and One of the lines of the data bus SH is fed via the single-channel controller EKC and the demultiplexer DD. For a data transmission rate of 64 kbit / s per transmission direction, an individual program in the single channel controller EKC runs at least 128,000 times per second. In order that the transfer of a single channel data bit carried out with the selected individual program can run correctly, control data belonging to the respective program configuration data units are simultaneously applied from the channel call memory KAR to the demultiplexer DD and to the multiplexer UM and the buffer memory UR, so that depending on the control data present the demultiplexer DD that Passes single channel data bit from the single channel controller EKC to the correct line of the data bus SH or that the single channel data bit is sent from the correct line of the data bus SH to the single channel controller EKC after being temporarily stored in the buffer memory UR by the multiplexer UM. Individual programs can also be used to check individual modules or the entire digital signal multiplexer.

The interface module SSB-X shown in FIG. 3 contains a configuration and alarm controller KAC-X and a cycle counter ZC which are with a channel call memory KAR and via the control bus CB with the programming and control station CTRL. The configuration and alarm controller KAC-X is also connected via a control line to all individual channel interfaces EKS-X1, ..., EKS-X5. The channel call memory KAR is connected via a further control line to the individual channel interfaces EKS-X1, ..., EKS-X5 as well as to a demultiplexer UD and a multiplexer DM. The demultiplexer UD and the multiplexer DM are also connected to the data bus SH and via a data line to the individual channel interfaces EKS-X1 EKS-X5.

The configuration and alarm controller KAC-X writes configuration data units into the channel call memory KAR, which are cyclically applied, clocked by the cycle counter, to the single-channel interfaces EKS-XY and to the multiplexers DM, UD. Single-channel data bits are subsequently picked up by one of the single-channel interfaces EKS-X1, ..., EKS-X5 and taken via the demultiplexer UD to the respective line of the data bus SH or vice versa from one of the lines of the data bus SH and via the multiplexer DM to one of the individual channel interfaces EKS-X1, ..., EKS-X5. The channel call memory controls the multiplexers DM and UD in such a way that the individual channel interfaces EKS-X1, ..., EKS_X5 for data transfer are each connected to the correct line of the data bus SH. The control unit, with which the configuration and alarm controller KAC-X is connected to all individual channel interfaces EKS-X1, ..., EKS-X5, serves to initialize these modules EKS-X1, ..., EKS-X5 , as well as for receiving status and alarm messages.

In order to ensure that the MXH-Z multiplexers and the SSB-X interface modules work together synchronously, their cycle counters ZC are started together. This ensures that the data bits are placed on the lines of the data bus SH in a timely and therefore collision-free manner or are removed from these lines again.

Claims

PAT E NTAN SPEECH

1. Programmable, flexible digital signal multiplexer with at least one subscriber-side single-channel interface (EKS-XY) for exchanging single-channel signals with bit rates of a lower hierarchical level and with at least one interface (EPIC-Z) that transmit a data stream with a bit rate of a higher one Hierarchy level, which is composed of different individual channel signals, receives or delivers, characterized in that at least one multiplexer (MXH-Z), which has an interface (EPIC-Z) connected to a data bus H) and at least one interface module ( SSB-X), which has at least one single channel interface (EKS-XY), are each connected to a data bus (SH) and each via a control bus (CB) to a programming and control station (CTRL).

2. Digital signal multiplexer according to claim 1, characterized in that the number of lines of the data bus (SH), which is preferably operated bidirectionally, corresponds to the maximum number of multiplexers (MXH-Z), the individual channel data via the data bus (SH) with replace the interface modules (SSB-X).

3. Digital signal multiplexer according to claim 1, characterized in that the multiplexer (MXH-Z) a configuration and alarm controller (KAC-Z) and a cycle counter (ZC), via the control bus (CB) with the programming and control station (CTRL) are connected, a multiple channel controller (VKC) connected to the interface (EPIC-Z) and a single channel controller (EKC), which are controlled via a processor register memory (PR) controlled by the configuration and alarm controller (KAC-Z). are connected to each other, and has a channel call memory (KAR), which is connected to the configuration and alarm controller (KAC-Z), the single channel controller (EKC), the cycle counter (ZC) as well as a demultiplexer (DD) and a multiplexer (UM) which are connected on the one hand to the single channel controller (EKC) and on the other hand directly or via a buffer memory (UR) to the data bus (SH).

4. Digital signal multiplexer according to claim 3, characterized in that the multi-channel controller (VKC) synchronizes data arriving on frames, breaks down the data contained in the frame into individual channel data and stores them in the processor register memory (PR) that the multi-channel controller (VKC) takes individual channel data from the processor register memory (PR), encloses it in a frame and outputs it to the interface (EPIC-Z) that in the processor register memory (PR) a memory area is allocated to each individual channel for each transmission direction. It is arranged that configuration data for the multi-channel and single-channel controllers (VKC, EKC) are stored in the processor register memory (PR) and in the channel call memory (KAR) by the configuration and alarm controller (KAC-Z), that the Multiple and single-channel controllers (VKC, EKC) alarm messages for the configuration and alarm controller (KAC-Z) store in these memory modules (PR) that the single-channel controller (EKC) can be called individual programs for the bitwise single-channel data transfer and for each transmission direction Generation and checking of the frame structure on the single-channel side contains that the configuration and alarm controller (KAC-Z) writes program configuration data units in the channel call memory (KAR), which are cyclically read into the single-channel controller (EKC) and by means of which a single program is selected, that simultaneously with the respective program configuration data units n associated control data from the channel call memory (KAR) to the demultiplexer (DD) as well as to the multiplexer (UM) and the buffer memory (UR) are applied so that, depending on the control data present, the demultiplexer (DD) single channel data bits from the single channel controller (EKC) to a line of the data bus (SH). transfers or that a single channel data bit is emitted from a line of the data bus (SH) directly or after buffering in the buffer memory (UR) by the multiplexer (UM) to the single channel controller (EKC).

5. Digital signal multiplexer according to claim 1, characterized in that the interface module (SSB-X) has a configuration and alarm controller (KAC-X) and a cycle counter (ZC), which with the programming and control station ( CTRL) and a channel call memory (KAR) are connected, that the configuration and alarm controller (KAC-X) is connected via a control bus to all individual channel interfaces (EKS-XY), that the channel call memory (KAR) is connected via a control line the single channel interfaces (EKS-XY) as well as a demultiplexer (UD) and a multiplexer (DM) is connected so that the demultiplexer (UD) and the multiplexer (DM) on the one hand with the data bus (SH) and on the other hand via a data line with the single channel interfaces (EKS-XY) are connected.

6. Digital signal multiplexer according to claim 5, characterized in that the configuration and alarm controller (KAC-X) writes configuration data units in the Kanalaufrufspei¬ cher (KAR), which cyclically to the individual channel interfaces (EKS-XY) and to the multi ¬ plexers (DM, UD) are created, and that individual channel data bits are consequently transmitted from the individual channel interfaces (EKS-XY) to the respective line of the data bus (SH) or vice versa.