USRE37611E1 - Non-volatile memory system having internal data verification test mode - Google Patents
Non-volatile memory system having internal data verification test mode Download PDFInfo
- Publication number
- USRE37611E1 USRE37611E1 US09/237,501 US23750199A USRE37611E US RE37611 E1 USRE37611 E1 US RE37611E1 US 23750199 A US23750199 A US 23750199A US RE37611 E USRE37611 E US RE37611E
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- United States
- Prior art keywords
- memory
- erase
- internal
- sub
- operations
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 title claims abstract description 514
- 238000012360 testing method Methods 0.000 title claims abstract description 119
- 238000013524 data verification Methods 0.000 title claims abstract description 52
- 238000012795 verification Methods 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims description 76
- 230000004044 response Effects 0.000 claims description 14
- 238000013500 data storage Methods 0.000 claims description 12
- 230000006870 function Effects 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 6
- 230000000977 initiatory effect Effects 0.000 claims 5
- 239000003607 modifier Substances 0.000 claims 3
- 230000008569 process Effects 0.000 description 18
- 238000009826 distribution Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 230000008859 change Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/81—Threshold
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
Abstract
Description
Claims (77)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/237,501 USRE37611E1 (en) | 1996-01-22 | 1999-01-26 | Non-volatile memory system having internal data verification test mode |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/589,823 US5675540A (en) | 1996-01-22 | 1996-01-22 | Non-volatile memory system having internal data verification test mode |
US09/237,501 USRE37611E1 (en) | 1996-01-22 | 1999-01-26 | Non-volatile memory system having internal data verification test mode |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/589,823 Reissue US5675540A (en) | 1996-01-22 | 1996-01-22 | Non-volatile memory system having internal data verification test mode |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE37611E1 true USRE37611E1 (en) | 2002-03-26 |
Family
ID=24359696
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/589,823 Ceased US5675540A (en) | 1996-01-22 | 1996-01-22 | Non-volatile memory system having internal data verification test mode |
US09/237,501 Expired - Lifetime USRE37611E1 (en) | 1996-01-22 | 1999-01-26 | Non-volatile memory system having internal data verification test mode |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/589,823 Ceased US5675540A (en) | 1996-01-22 | 1996-01-22 | Non-volatile memory system having internal data verification test mode |
Country Status (2)
Country | Link |
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US (2) | US5675540A (en) |
TW (1) | TW303465B (en) |
Cited By (19)
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US6639837B2 (en) * | 2000-12-11 | 2003-10-28 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
US20040019841A1 (en) * | 2002-07-25 | 2004-01-29 | Ong Adrian E. | Internally generating patterns for testing in an integrated circuit device |
US20040062123A1 (en) * | 2002-09-27 | 2004-04-01 | Oki Electric Industry Co., Ltd. | Nonvolatile semiconductor memory device able to detect test mode |
US6732304B1 (en) | 2000-09-21 | 2004-05-04 | Inapac Technology, Inc. | Chip testing within a multi-chip semiconductor package |
US6754866B1 (en) | 2001-09-28 | 2004-06-22 | Inapac Technology, Inc. | Testing of integrated circuit devices |
US6812726B1 (en) | 2002-11-27 | 2004-11-02 | Inapac Technology, Inc. | Entering test mode and accessing of a packaged semiconductor device |
US20050024977A1 (en) * | 2000-09-21 | 2005-02-03 | Ong Adrian E. | Multiple power levels for a chip within a multi-chip semiconductor package |
US20050162182A1 (en) * | 2002-07-25 | 2005-07-28 | Ong Adrian E. | Internally generating patterns for testing in an integrated circuit device |
US7061263B1 (en) | 2001-11-15 | 2006-06-13 | Inapac Technology, Inc. | Layout and use of bond pads and probe pads for testing of integrated circuits devices |
US7071771B2 (en) | 2000-12-11 | 2006-07-04 | Kabushiki Kaisha Toshiba | Current difference divider circuit |
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US7444575B2 (en) | 2000-09-21 | 2008-10-28 | Inapac Technology, Inc. | Architecture and method for testing of an integrated circuit device |
US20100306604A1 (en) * | 2009-05-28 | 2010-12-02 | Mcginty Stephen F | Method and circuit for brownout detection in a memory system |
US8001439B2 (en) | 2001-09-28 | 2011-08-16 | Rambus Inc. | Integrated circuit testing module including signal shaping interface |
US8063650B2 (en) | 2002-11-27 | 2011-11-22 | Rambus Inc. | Testing fuse configurations in semiconductor devices |
US20150022264A1 (en) * | 2013-07-22 | 2015-01-22 | Qualcomm Incorporated | Sense amplifier offset voltage reduction |
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1999
- 1999-01-26 US US09/237,501 patent/USRE37611E1/en not_active Expired - Lifetime
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