JP6748760B1 - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of accurately executing a power-down operation during a test operation while reducing power consumption. The flash memory of the present invention includes a low power voltage detection circuit 210 that detects that the supply voltage has dropped to a constant voltage, a high-precision voltage detection circuit 220 that detects that the supply voltage has dropped to a constant voltage, and an internal structure. Select the high-precision voltage detection circuit 220 when the circuit is in the test state, select the low-power detection circuit 210 when the internal circuit is not in the test state, and use the detection results of the low-power voltage detection circuit 210 or the high-precision voltage detection circuit 230. It has a controller 140 that responds and executes a power-down operation. [Selection diagram]

Description

The present invention relates to a semiconductor memory device such as a flash memory, and more particularly to power down detection during a test operation.

The NAND flash memory uses a fuse cell for storing voltage setting for reading, programming, erasing, etc., and setting information such as user options. The fuse cell is set, for example, in a storage area in the memory cell array that cannot be accessed by the user. When the power is turned on, the flash memory reads the setting information from the fuse cell and loads it into the internal register as a power-up operation. After the power-up operation is completed, the controller controls each operation based on the setting information held in the internal register (Patent Document 1).

Patent No. 6494139

A power-up detection operation when the power of the flash memory is turned on and a power-down detection operation when the power is dropped will be described with reference to FIG. FIG. 1 shows the relationship between the voltage supplied from the outside and the time.

For example, in a flash memory to which a voltage of 3.0V is supplied, the power-up detector is used as a voltage for starting a power-up operation when the power is turned on when the operation guarantee voltage is 2.7 to 3.3V. , Detect a power-up voltage level V_PU of about 2.2V. The power-up detection unit first detects that the supply voltage reaches a constant voltage by using a detection circuit that is relatively inaccurate, and then uses a detection circuit that is relatively accurate to detect that the supply voltage is Detecting that the up voltage level V_PU has been reached. The highly accurate detection circuit includes a reference voltage generation circuit and a comparison circuit that compares the reference voltage with the supply voltage. When the power-up voltage level V_PU is detected, the power-up sequence is executed, the internal circuit is initialized (reset), and the setting information read from the fuse cell of the memory cell array is set in the register. Done. After that, when the supply voltage rises to the operation guarantee voltage, normal operation is started.

FIG. 2 shows a conventional power down detector. When the power down detection unit 10 detects that the supply voltage Vcc has dropped to the power down voltage level V_PD, it outputs a reset signal to the internal circuit 20 such as the CPU or the logic circuit. For example, when the external power supply capacity is low or when a large peak current is generated by the operation of the internal circuit 20, the supply voltage Vcc drops to the power down voltage level V_PD. When the internal circuit 20 receives the reset signal from the power-down detection unit 10, the internal circuit 20 executes the power-down operation, stops the operation of the charge pump circuit of the internal circuit 20, and resets the CPU and the logic.

The power-down voltage level V_PD is lower than the power-up voltage level V_PU (otherwise, the power-down operation is performed after the power-up operation and the flash memory cannot operate), and the power-down voltage level V_PD And the power-up voltage level V_PU is set to be higher than the operating voltage Vt of the CMOS of the internal circuit (for example, the total of the threshold value of the PMOS and the threshold value of the NMOS) (otherwise, the power-up operation or the power-up operation). I can't get the down action to run properly).

In addition, when the flash memory is in the standby state, the consumption current allowed to be consumed in that state is defined in the specifications. Due to such restrictions, the power-down detection unit 10 is configured to minimize the operating current so as not to exceed the allowable current consumption in the standby state. For example, as shown in FIG. 3, the power down detection unit 10 is composed of a simple circuit using a resistance voltage divider and an inverter, and outputs a H level detection signal Vdet when detecting the power down voltage level V_PD.

Unlike the power-up detection unit, the power-down detection unit 10 does not include a reference voltage generation circuit and a comparison circuit, so that it is possible to reduce power consumption, but on the other hand, the detection accuracy is worse than that of the power-up detection unit. .. Therefore, as shown in FIG. 1, the variation of the detection range H2 of the power-down detection unit 10 is larger than the variation of the detection range H1 of the power-up detection unit.

When such a power down detection unit 10 is used, there is an essential problem that the power down voltage level V_PD cannot be detected correctly because the detection range H2 varies greatly. If the flash memory is in the standby state, even if there is some error in the detection range of the power down voltage level V_PD, there is no particular effect, but if the power down voltage level V_PD cannot be correctly detected during the test of the internal circuit, the flash memory Can cause serious problems. When testing a memory cell array or its peripheral circuits, multi-parallel measurement is often performed, and therefore, the environment is such that the supply voltage easily drops, and during the test, the supply voltage is lower than the power-down voltage level V_PD. If the power-down operation is not started even if the voltage drops, a high voltage is applied to an unexpected circuit due to a malfunction, causing the circuit to fail or the memory cell being programmed with incorrect test data, and the reliability of the test itself being lost. Will end up.

The present invention solves such a conventional problem, and an object of the present invention is to provide a semiconductor memory device capable of accurately performing a power-down operation during a test operation while reducing power consumption.

The semiconductor memory device according to the present invention has a first detection circuit that detects that the supply voltage has dropped to a constant voltage, and detection accuracy higher than that of the first detection circuit, and the supply voltage has dropped to a constant voltage. A second detection circuit that detects that the first detection circuit is selected when the internal circuit is in the test state, and a first detection circuit that is selected when the internal circuit is not in the test state; And a executing unit that executes a power-down operation in response to the detection result of the detection circuit or the second detection circuit.

In one embodiment, the second detection circuit includes a reference voltage generation circuit that generates a reference voltage and a comparison circuit that compares the reference voltage with a power supply voltage, and the first detection circuit has a reference voltage generation circuit. Does not include circuits. In one embodiment, the internal circuit includes a test circuit, and the selecting means selects the second detection circuit when the test circuit executes a test, and selects the first detection circuit when the test circuit does not execute the test. Select the detection circuit. In one embodiment, the selection means selects the first detection circuit or the second detection circuit based on the test signal output from the test circuit. In one embodiment, the selection means selects the second detection circuit when a command for starting the test is input from the outside. In one embodiment, the selection means selects the second detection circuit when a signal is input to the test pad. In one embodiment, the second detection circuit detects that the supply voltage has dropped to a constant voltage by using the reference voltage input from the test pad. In one embodiment, the test circuit performs a test on the memory cell array or a peripheral circuit of the memory cell array. In one embodiment, the voltage level detected by the first and second detection circuits is lower than the voltage level detected by the power-up detection circuit and higher than the operable voltage level of the CMOS.

According to the present invention, the second detection circuit is selected when the internal circuit is in the test state, and the first detection circuit is selected when the internal circuit is not in the test state, and the selected first detection circuit or the second detection circuit is selected. Since the power-down operation is executed in response to the detection result of the detection circuit, it is possible to accurately execute the power-down operation during the test operation while reducing the power consumption.

7 is a graph illustrating a power-up detection operation and a power-down detection operation of the flash memory. It is a figure which shows the conventional power down detection part. It is a figure which shows the structural example of the conventional power down detection part. It is a block diagram which shows the internal structure of the flash memory which concerns on the Example of this invention. It is a figure which shows the structure of the power down detection part which concerns on the Example of this invention. It is a figure which shows an example of the reference voltage generation circuit which concerns on the Example of this invention. It is a figure which shows an example of the high precision voltage detection circuit which concerns on the Example of this invention. FIG. 9 is a diagram for explaining variations in the detection range of the power-down detector in the test state according to the embodiment of the present invention. It is a figure which shows the structure of the power down detection part which concerns on another Example of this invention. It is a figure explaining the variation of the detection range of the power-down detection part in the test state by another Example of this invention.

Next, embodiments of the present invention will be described in detail with reference to the drawings. In a preferred mode, the semiconductor memory device of the present invention is a non-volatile memory such as a NAND type or NOR type flash memory, a resistance change type memory, or a magnetic change type memory. In the following description, a NAND flash memory will be exemplified.

FIG. 4 shows a schematic configuration of the flash memory according to the embodiment of the present invention. The flash memory 100 of the present embodiment has a memory cell array 110 in which a plurality of memory cells are arranged in a matrix, an input/output buffer 120 connected to an external input/output terminal I/O, and address data from the input/output buffer 120. The address register 130 receives the command data and the like from the input/output buffer 120, receives the row address information Ax from the controller 140 that controls each unit, and the address register 130, decodes the row address information Ax, and decodes the block based on the decoding result. A word line selection circuit 150 that performs selection and selection of word lines, and holds data read from a page selected by the word line selection circuit 150 and holds input data to be programmed in the selected page. A column selection circuit that receives the column address information Ay from the page buffer/sense circuit 160 and the address register 130, decodes the column address information Ay, and selects the data of the column address in the page buffer/sense circuit 160 based on the decoding result. 170, an internal voltage generation circuit 180 that generates various voltages (write voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, etc.) necessary for reading data, programming and erasing, and turning on the power. At times, the supply voltage Vcc supplied from the external terminal is monitored, the power-up voltage level V_PU is detected, the power-up detection unit 190 that outputs the power-up detection signal PWRDET, the supply voltage Vcc is monitored, and the power-down voltage level V_PD is detected. And a test control circuit 240 that executes a test of an internal circuit including the memory cell array and its peripheral circuits, and a power-down detection unit 200 that detects a power-down detection signal DET_H/DET_L.

The memory cell array 110 has m blocks BLK(0), BLK(1),..., BLK(m-1) arranged in the column direction. A plurality of NAND strings in which a plurality of memory cells are connected in series are formed in one block. The NAND string may be two-dimensionally formed on the substrate surface or may be three-dimensionally formed on the substrate surface. Further, the memory cell may be an SLC type that stores 1 bit (binary data) or an MLC type that stores multiple bits. One NAND string is configured by connecting a plurality of memory cells (for example, 64), a bit line side selection transistor, and a source line side selection transistor in series. The drain of the bit line side selection transistor is connected to one corresponding bit line GBL, and the source of the source line side selection transistor is connected to the common source line SL.

In the read operation, a certain positive voltage is applied to the bit line, a certain voltage (for example, 0V) is applied to the selected word line, and a pass voltage Vpass (for example, 4.5V) is applied to the non-selected word line. A positive voltage (for example, 4.5 V) is applied to the select gate lines SGD and SGS to turn on the bit line side selection transistor and the source line side selection transistor of the NAND string, and 0 V is applied to the common source line. In the program (write) operation, a high voltage program voltage Vpgm (15 to 20 V) is applied to the selected word line, an intermediate potential (for example, 10 V) is applied to the non-selected word line, and the bit line side selection transistor is set. The source line side select transistor is turned on and the potential corresponding to the data of "0" or "1" is supplied to the bit line. In the erase operation, 0 V is applied to the selected word line in the block, a high voltage (for example, 20 V) is applied to the P well, and electrons in the floating gate are extracted to the substrate, thereby erasing data in block units.

When detecting that the supply voltage Vcc supplied to the flash memory 100 reaches the power-up voltage level V_PU when the power is turned on, the power-up voltage detection unit 190 outputs the power-up detection signal PWRDET to the controller 140. The controller 140 includes, for example, a CPU, a ROM/RAM, and the like, and the ROM/RAM has codes such as instructions and data for executing a power-up operation, a power-down operation, a read operation, a program operation, and an erase operation. It is stored. When the controller 140 receives the power-up detection signal PWRDET, in response thereto, it executes the power-up operation according to the code read from the ROM/RAM. In the power-up operation, the internal circuit including the controller 140 is reset, the fuse cell of the memory cell array 110 is read, and the like.

When detecting that the supply voltage Vcc has dropped to the power-down detection level V_PD, the power-down detection unit 200 outputs the power-down detection signal DET_L or DET_H to the controller 140 according to the operating state of the flash memory 100. Upon receiving the power-down detection signal DET_L/DET_H, the controller 140 responds to this and executes the power-down operation according to the code read from the ROM/RAM. In the power-down operation, the internal circuit including the controller 140 is reset, the charge pump circuit is stopped, and the like.

The test control circuit 240 is not particularly limited in its configuration, but may be, for example, a built-in self-test circuit (hereinafter, BIST circuit (Built-In Self Test). The BIST circuit facilitates testing of a memory, a logic, and the like. It is one of the design technologies to be realized, and includes a function for self-testing the internal circuit including the memory cell array 110 and its peripheral circuits, and can test the internal circuit at the wafer level, the chip level or the package level. Further, the BIST circuit can include, for example, a circuit that generates a test pattern, a circuit that compares a test result with an expected value, a circuit that outputs pass or fail as a comparison result, and the like.

The test control circuit 240, for example, executes a test of the internal circuit in response to a test signal applied to the test terminal, or executes a test of the internal circuit in response to a test command input from the outside. .. When executing the test of the internal circuit, the test control circuit 240 outputs a test signal TEST_PD of, for example, H level indicating that the test is being performed.

FIG. 5 shows the internal configuration of the power down detection unit 200 of this embodiment. As shown in the figure, the power down detection unit 200 includes a low power voltage detection circuit 210, a high precision voltage detection circuit 220, and a selector 230. The low power voltage detection circuit 210 is a relatively simple circuit, and is composed of a circuit capable of further reducing power consumption, and is composed of, for example, the detection circuit 10 having a resistor and an inverter as shown in FIG. The detection circuit 10 constantly monitors the supply voltage Vcc, and when the detection node N drops to the power-down voltage level V_PD, the resistance value is selected so that the voltage of the detection node N becomes equal to or lower than the threshold value of the inverter. It Thus, when the low power voltage detection circuit 210 detects that the supply voltage Vcc has dropped to the power down voltage level V_PD, it outputs the H level detection signal DET_L representing the detection result to the selector 230 (the detection signal in FIG. 3). Vdet corresponds).

The high-accuracy voltage detection circuit 220 includes a reference voltage generator 222 that generates the reference voltage Vref, and a comparison circuit 224 that compares the reference voltage Vref generated by the reference voltage generator 222 with the supply voltage Vcc. The reference voltage Vref is set to the power-down voltage level V_PD, and when the supply voltage Vcc drops below the power-down voltage level V_PD, the comparison circuit 224 outputs an H-level detection signal DET_H indicating this to the selector 230.

The configuration of the reference voltage generation circuit 222 is not particularly limited, but for example, a bandgap reference circuit (BGR circuit) that is hardly dependent on fluctuations in power supply voltage or operating temperature is used. FIG. 6 shows a general BGR circuit. As shown in the figure, the BGR circuit includes first and second current paths between the power supply voltage Vcc and GND, and the PMOS transistor P1, the resistor R1, and the bipolar transistor Q1 which are connected in series to the first current path. Including a PMOS transistor P2, resistors R2 and R, and a bipolar transistor Q2 that are connected in series to the second current path, and a node VN commonly connecting the resistor R1 and the transistor Q1 to the inverting input terminal (-). It includes a differential amplifier circuit AMP which is connected to the node VP, which commonly connects the resistors R2 and R, to the non-inverting input terminal (+), and whose output terminal is commonly connected to the gates of the transistors P1 and P2. The differential amplifier circuit AMP adjusts the output voltage so that the forward voltage of the transistor Q1 is equal to the voltage obtained by adding the voltage generated in the resistor R to the forward voltage of the transistor Q2, and the reference voltage from the output node BGR is adjusted. The voltage Vref is output.

Although not particularly limited in its configuration, the comparison circuit 224 includes, for example, as shown in FIG. 7, a comparator CMP that compares the internal voltage VI generated from the supply voltage Vcc with the reference voltage Vref. Reference voltage Vref=power down voltage level V_PD. The comparator CMP outputs an L level detection signal DET_H when VI>Vref, and outputs an H level detection signal DET_H when Vref≧VI.

The reference voltage generator 222 and the comparison circuit 224 are activated or deactivated in response to the test signal TEST_PD from the test control circuit 240. For example, when the test signal TEST_PD is at H level, the reference voltage generator 222 and the comparison circuit 224 are enabled, and when the test signal TEST_PD is at L level, the reference voltage generator 222 and the comparison circuit 224 are disabled.

The selector 230 receives the detection signal DET_L from the low power voltage detection circuit 210 and the detection signal DET_H from the high precision voltage detection circuit 220, and selects one of the detection signals based on the test signal TEST_PD from the test control circuit 240. , And outputs the selected detection signal to the controller 140. For example, when the test signal TEST_PD is at H level, the detection signal DET_H of the high precision voltage detection circuit 220 is selected, and when the test signal TEST_PD is at L level, the detection signal DET_L of the low power voltage detection circuit 210 is selected. When the detection signal DET_L or DET_H indicates the detection of the power-down voltage level V_PD, the controller 140 resets the internal circuit in response to the detection signal DET_L or DET_H.

Next, the operation of the power down detection unit 200 of this embodiment will be described. When the test control circuit 240 tests the internal circuit (memory cell array or peripheral circuit), the high-accuracy voltage detection circuit 220 operates in response to the test signal TEST_PD, and the selector 230 causes the high-precision voltage detection circuit 220 to operate. The detection signal DET_H is output to the controller 140. That is, in the test state, both the low power voltage detection circuit 210 and the high-precision voltage detection circuit 220 are operating, but the selector 230 provides the detection signal DET_H of the high-precision voltage detection circuit 220 to the controller 140.

On the other hand, when the test control circuit 240 does not execute the test of the internal circuit, the high-accuracy voltage detection circuit 220 is deactivated in response to the test signal TEST_PD, and the selector 230 detects the low power voltage detection circuit 210. The signal DET_L is output to the controller 140. That is, at the time of non-test, only the low power voltage detection circuit 210 operates, and the selector 230 provides the detection signal DET_L of the low power voltage detection circuit 210 to the controller 140.

FIG. 8 shows the detection range H3 of the power-down voltage level V_PD in the test state according to this embodiment. As described above, during the test execution, the power-down voltage level V_PD is detected by using the high-accuracy voltage detection circuit 220. Therefore, the detection accuracy is higher than that when the low-power voltage detection circuit 210 is used, and the detection range H3 The variation can be reduced. In the test state, the internal circuit is operating, and the supply voltage becomes weak due to, for example, multiple parallel measurements. By correctly detecting the power-down voltage level V_PD during the test period, for example, it is possible to prevent the internal circuit from operating at a voltage lower than the power-down voltage level V_PD, and as a result, a circuit failure due to a malfunction or a test result It is possible to prevent a decrease in reliability. On the other hand, when the test of the internal circuit is not executed, the high-accuracy voltage detection circuit 220 is deactivated, and only the low power voltage detection circuit 210 is operated, so that the test is not executed or the standby state is allowed. Power consumption restrictions can be complied with.

Here, the power-up detection unit 190 is also required to have high accuracy in detecting the power-up voltage level V_PU. Therefore, the power-up detection unit 190 also uses a high-accuracy voltage detection circuit using a reference voltage generator and a comparison circuit. Therefore, the high-accuracy voltage detection circuit 220 of the power-down detection unit 200 may use the high-accuracy voltage detection circuit of the power-up detection unit 190. In this case, after the power-up sequence ends, the detection level of the high-accuracy voltage detection circuit is changed from the power-up voltage level V_PU to the power-down voltage level V_PD.

In the above embodiment, the high-accuracy voltage detection circuit 220 is enabled/disabled in response to the test signal TEST_PD from the test control circuit 240, but this is an example, and the point is that the test operation is executed. The high-accuracy voltage detection circuit 220 may be enabled/disabled in response to the information capable of identifying the fact. For example, the high-accuracy voltage detection unit 220 may be enabled/disabled in response to a test-related signal input to a test pad or a test external terminal, or in response to a test-related command input from the outside. The high-precision voltage detector 220 may be enabled/disabled. This also applies to the selection operation of the selector 230.

Next, another embodiment of the present invention will be described. In the above-described embodiment, the high-precision voltage detection circuit 220 uses the reference voltage Vref generated by the reference voltage generator 222. However, in this embodiment, the high-precision voltage detection circuit 220 is input from the test pad. The reference voltage Vref is used.

FIG. 9 is a diagram showing the configuration of the power-down detection unit 200A of this embodiment. As shown in the figure, the test pad 250 is, for example, a test-dedicated pad that is not bonded and connected to an external terminal, and a reference voltage Vref is applied via a probe pin during a wafer-level or chip-level test. The reference voltage Vref is, for example, the power-down voltage level V_PD. FIG. 10 shows the detection range of the power-down voltage level V_PD at the time of the test according to this embodiment, and the variation of the detection range can be virtually eliminated. In this way, the comparison circuit 224 can detect with high accuracy whether the supply voltage Vcc has dropped to the power-down voltage level V_PD using the reference voltage Vref input from the test pad 250.

In the above embodiment, the reference voltage Vref is input from the test pad 250, but this is an example, and the reference voltage Vref may be input from an external terminal electrically connected to the test pad 250. Good. The external terminal is, for example, a terminal that is not used during the test operation. Further, although the NAND flash memory is exemplified in the above embodiment, the present invention is not limited to this, and can be applied to the power down detection of other nonvolatile memories.

Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the invention described in the claims. Is possible.

100: Flash memory 110: Memory cell array 120: Input/output buffer 130: Address register 140: Controller 150: Word line selection circuit 160: Page buffer/sense circuit 170: Column selection circuit 180: Internal voltage generation circuit 190: Power-on detection unit 200: Power down detection unit 210: Low power voltage detection unit 220: High precision voltage detection circuit 230: Selector 240: Test control circuit

Claims (9)

A first detection circuit for detecting that the supply voltage has dropped to a constant voltage;
A second detection circuit that has a higher detection accuracy than the first detection circuit and that detects that the supply voltage has dropped to a constant voltage;
Selecting means for selecting the second detection circuit when the internal circuit is in the test state, and selecting the first detection circuit when the internal circuit is not in the test state;
Executing means for executing a power down operation in response to the detection result of the first detection circuit or the second detection circuit;
And a semiconductor memory device. The second detection circuit includes a reference voltage generation circuit that generates a reference voltage and a comparison circuit that compares the reference voltage with a power supply voltage, and the first detection circuit does not include a reference voltage generation circuit. The semiconductor memory device according to claim 1. The internal circuit includes a test circuit,
3. The semiconductor according to claim 1, wherein the selection unit selects the second detection circuit when the test circuit executes a test, and selects the first detection circuit when the test circuit does not execute the test. Storage device. 4. The semiconductor memory device according to claim 3, wherein the selection unit selects the first detection circuit or the second detection circuit based on a test signal output from the test circuit. 2. The semiconductor memory device according to claim 1, wherein the selection means selects the second detection circuit when a command for starting the test is input from the outside. 2. The semiconductor memory device according to claim 1, wherein the selection unit selects the second detection circuit when a signal is input to the test pad. The semiconductor memory device according to claim 1, wherein the second detection circuit detects that the supply voltage has dropped to a constant voltage by using a reference voltage input from the test pad. The semiconductor memory device according to claim 3, wherein the test circuit executes a test of a memory cell array or a peripheral circuit of the memory cell array. 9. The voltage level detected by the first and second detection circuits is lower than the voltage level detected by the power-up detection circuit and higher than the operable voltage level of the CMOS. The semiconductor memory device according to 1.

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