US8421193B2 - Integrated circuit device having through via and method for preparing the same - Google Patents
Integrated circuit device having through via and method for preparing the same Download PDFInfo
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- US8421193B2 US8421193B2 US12/949,058 US94905810A US8421193B2 US 8421193 B2 US8421193 B2 US 8421193B2 US 94905810 A US94905810 A US 94905810A US 8421193 B2 US8421193 B2 US 8421193B2
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Definitions
- the present invention relates to an integrated circuit device having stacking wafers with through silicon vias and a method for preparing the same. More particularly, the present invention relates to an integrated circuit device and method for preparing the same by bonding wafers before the formation of the through silicon via.
- Packaging technology for integrated circuit structures has been continuously developed to meet the demand for miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric and electronic products are required, various techniques have been disclosed in the art.
- a stack of at least two chips i.e., the so-called 3D package
- a stack package provides advantages not only of an increase in memory capacity but also in regards to mounting density and mounting area utilization efficiency. Due to such advantages, research and development of stack package technology has accelerated.
- a through-silicon via As an example of a stack package, a through-silicon via (TSV) has been disclosed in the art.
- the stack package using a TSV has a structure in which the TSV is disposed in a chip so that chips are physically and electrically connected with each other through the TSV.
- a TSV is formed by etching a vertical via through a substrate and filling the via with a conductive material, such as copper.
- a conductive material such as copper.
- U.S. Pat. No. 7,683,459 discloses a hybrid bonding method for through silicon via based wafer stacking, in which patterned adhesive layers are provided to join together adjacent wafers in the stack, while solder bonding is used to electrically connect the lower end of the via in the upper wafer to the bump pad on the upper end of the via in the lower wafer.
- solder bonding is used to electrically connect the lower end of the via in the upper wafer to the bump pad on the upper end of the via in the lower wafer.
- the formation of the bump pad on the upper end of the via requires seeding, electroplating, photolithography and etching processes; therefore, the formation of the bump pad on the upper end of the via is very complicated and expensive.
- An aspect of the present invention is to provide an integrated circuit device and method for preparing the same by bonding wafers prior to the formation of the through silicon via such that no bump pad is positioned between the stacking wafer and the bottom wafer; therefore, the issues of complicated processing and high cost can be resolved.
- One aspect of the present invention discloses an integrated circuit device comprising a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer.
- Another aspect of the present invention discloses a method for preparing an integrated circuit device comprising the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.
- the embodiment of the present invention forms the integrated circuit device by bonding wafers prior to the formation of the through silicon via that penetrates through the stacking wafer and not through the bottom wafer. Consequently, the embodiment of the present invention does not need to form the bump pad between the stacking wafer and the bottom wafer; therefore, the issues of complicated processing and high cost can be resolved.
- FIGS. 1 through 12 are cross-sectional views illustrating a method for forming an integrated circuit device in accordance with one embodiment of the present invention.
- FIG. 1 to FIG. 12 are cross-sectional views illustrating a method for forming an integrated circuit device 100 in accordance with one embodiment of the present invention.
- fabrication processes are performed to form an active element 13 such as a transistor in a silicon wafer 11 , with a dielectric layer 15 covering the active element 13 and a shallow trench isolation 17 next to the active element 13 in the wafer 11 .
- an etching process is performed to form a depression 19 in the shallow trench isolation 17 , as shown in FIG. 2 .
- the depression 19 penetrates through the shallow trench isolation 17 .
- the depression 19 is filled with dielectric material by deposition process to form a dielectric block 21 , and photolithographic and etching processes are then performed to remove a portion of the dielectric block 21 and the dielectric layer 15 to form at least one concavity 23 .
- photolithographic and etching processes are performed to remove a portion of the dielectric layer 15 to form at least one contact hole 25 , which exposes at least one terminal of the active element 13 , as shown in FIG. 4 .
- a deposition process is performed to form a contact plug 27 by filling the contact hole 25 and an interconnect 29 by filling the concavity 23 with the same conductive material such as tungsten.
- a conductive layer 31 is formed by deposition process to electrically connect the interconnect 29 to the active element 13 through the contact plug 27 , as shown in FIG. 6 .
- the interconnect 29 and the conductive layer 31 form a connecting structure 30 .
- a dielectric layer 33 is formed by deposition process to cover the conductive layer 31 and a passivation layer 35 is then formed by deposition process to cover the dielectric layer 33 to form a bottom wafer 10 A.
- the fabrication processes shown in FIG. 1 to FIG. 6 are performed again on another wafer 11 , a carrier 39 is adhered to the top side of the wafer 11 via an adhesive 37 , and a thinning process such as the backside grinding process or CMP process is then performed to remove a portion of the wafer 11 from the bottom side of the wafer 11 to form a stacking wafer 10 B, as shown in FIG. 8 .
- the stacking wafer 10 B is bonded to the bottom wafer 10 A by an intervening adhesive layer 41 without forming a bump pad between the bottom wafer 10 A and the stacking wafer 10 B.
- the intervening adhesive layer 41 is the only layer between the bottom wafer 10 A and the stacking wafer 10 B, i.e., the stacking wafer 10 B is bonded to the bottom wafer 11 A without using solder.
- the carrier 39 and the adhesive 37 are removed from the top side of the stacking wafer 10 B, and a dry etching process using fluorine-containing etching gas is then performed to form at least one via hole 43 penetrating through the stacking wafer 10 B and into the bottom wafer 10 A in a substantially linear manner, as shown in FIG. 10 .
- the at least one via hole 43 does not penetrate through the bottom wafer 10 A.
- a barrier layer and seed layer 45 is formed in the via hole 43 by physical vapor deposition, and an electroplating process is then performed to form a conductive via (TSV) 47 by filling the via hole 43 with conductive material such as copper.
- TSV conductive via
- the conductive via 47 penetrates through the dielectric block 21 of the stacking wafer 10 B, and does not penetrate through the bottom wafer 10 A. In particular, the conductive via 47 does not penetrate through the dielectric block 21 of the bottom wafer 10 A.
- a bump pad 49 is formed on the stacking wafer 10 B to complete the integrated circuit device 100 .
- the conductive via 47 is positioned in the shallow trench isolation 17 and connected to the bump pad 49 .
- the conductive via 47 is electrically connected to the interconnect 29 of the connecting structure 30 , and the conductive layer 31 of the connecting structure 30 electrically connects the active element 13 to the interconnect 29 ; therefore, the active element 13 is electrically connected to the conductive via 47 .
- the embodiment of the present invention forms the integrated circuit device 100 by bonding wafers 10 A and 10 B before the formation of the through silicon via 47 that penetrates through the stacking wafer 10 B and not through the bottom wafer 10 A. Consequently, the embodiment of the present invention does not need to form the bump pad 49 between the stacking wafer 10 B and the bottom wafer 10 A; therefore, the issues of complicated processing and high cost can be solved.
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Abstract
An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.
Description
The present invention relates to an integrated circuit device having stacking wafers with through silicon vias and a method for preparing the same. More particularly, the present invention relates to an integrated circuit device and method for preparing the same by bonding wafers before the formation of the through silicon via.
Packaging technology for integrated circuit structures has been continuously developed to meet the demand for miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric and electronic products are required, various techniques have been disclosed in the art.
By using a stack of at least two chips, i.e., the so-called 3D package, in the case of a memory device for example, it is possible to produce a product having a memory capacity which is twice as large as that obtainable through semiconductor integration processes. Also, a stack package provides advantages not only of an increase in memory capacity but also in regards to mounting density and mounting area utilization efficiency. Due to such advantages, research and development of stack package technology has accelerated.
As an example of a stack package, a through-silicon via (TSV) has been disclosed in the art. The stack package using a TSV has a structure in which the TSV is disposed in a chip so that chips are physically and electrically connected with each other through the TSV. Generally, a TSV is formed by etching a vertical via through a substrate and filling the via with a conductive material, such as copper. To increase the transmission speed and for high-density fabrication, the thickness of a semiconductor wafer comprising multiple integrated circuit structures each having the TSV should be reduced.
U.S. Pat. No. 7,683,459 discloses a hybrid bonding method for through silicon via based wafer stacking, in which patterned adhesive layers are provided to join together adjacent wafers in the stack, while solder bonding is used to electrically connect the lower end of the via in the upper wafer to the bump pad on the upper end of the via in the lower wafer. However, the formation of the bump pad on the upper end of the via requires seeding, electroplating, photolithography and etching processes; therefore, the formation of the bump pad on the upper end of the via is very complicated and expensive.
An aspect of the present invention is to provide an integrated circuit device and method for preparing the same by bonding wafers prior to the formation of the through silicon via such that no bump pad is positioned between the stacking wafer and the bottom wafer; therefore, the issues of complicated processing and high cost can be resolved.
One aspect of the present invention discloses an integrated circuit device comprising a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer.
Another aspect of the present invention discloses a method for preparing an integrated circuit device comprising the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.
Compared to the technique disclosed in U.S. Pat. No. 7,683,459 forming one bump pad for each wafer, the embodiment of the present invention forms the integrated circuit device by bonding wafers prior to the formation of the through silicon via that penetrates through the stacking wafer and not through the bottom wafer. Consequently, the embodiment of the present invention does not need to form the bump pad between the stacking wafer and the bottom wafer; therefore, the issues of complicated processing and high cost can be resolved.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, and form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes as those of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the invention.
Referring to FIG. 3 , the depression 19 is filled with dielectric material by deposition process to form a dielectric block 21, and photolithographic and etching processes are then performed to remove a portion of the dielectric block 21 and the dielectric layer 15 to form at least one concavity 23. Referring to FIG. 4 , photolithographic and etching processes are performed to remove a portion of the dielectric layer 15 to form at least one contact hole 25, which exposes at least one terminal of the active element 13, as shown in FIG. 4 .
Referring to FIG. 5 , a deposition process is performed to form a contact plug 27 by filling the contact hole 25 and an interconnect 29 by filling the concavity 23 with the same conductive material such as tungsten. Subsequently, a conductive layer 31 is formed by deposition process to electrically connect the interconnect 29 to the active element 13 through the contact plug 27, as shown in FIG. 6 . In one embodiment of the present invention, the interconnect 29 and the conductive layer 31 form a connecting structure 30.
Referring to FIG. 7 , a dielectric layer 33 is formed by deposition process to cover the conductive layer 31 and a passivation layer 35 is then formed by deposition process to cover the dielectric layer 33 to form a bottom wafer 10A. The fabrication processes shown in FIG. 1 to FIG. 6 are performed again on another wafer 11, a carrier 39 is adhered to the top side of the wafer 11 via an adhesive 37, and a thinning process such as the backside grinding process or CMP process is then performed to remove a portion of the wafer 11 from the bottom side of the wafer 11 to form a stacking wafer 10B, as shown in FIG. 8 .
Referring to FIG. 9 , the stacking wafer 10B is bonded to the bottom wafer 10A by an intervening adhesive layer 41 without forming a bump pad between the bottom wafer 10A and the stacking wafer 10B. In one embodiment of the present invention, the intervening adhesive layer 41 is the only layer between the bottom wafer 10A and the stacking wafer 10B, i.e., the stacking wafer 10B is bonded to the bottom wafer 11A without using solder. Subsequently, the carrier 39 and the adhesive 37 are removed from the top side of the stacking wafer 10B, and a dry etching process using fluorine-containing etching gas is then performed to form at least one via hole 43 penetrating through the stacking wafer 10B and into the bottom wafer 10A in a substantially linear manner, as shown in FIG. 10 . In one embodiment of the present invention, the at least one via hole 43 does not penetrate through the bottom wafer 10A.
Referring to FIG. 11 , a barrier layer and seed layer 45 is formed in the via hole 43 by physical vapor deposition, and an electroplating process is then performed to form a conductive via (TSV) 47 by filling the via hole 43 with conductive material such as copper. In one embodiment of the present invention, the conductive via 47 penetrates through the dielectric block 21 of the stacking wafer 10B, and does not penetrate through the bottom wafer 10A. In particular, the conductive via 47 does not penetrate through the dielectric block 21 of the bottom wafer 10A.
Referring to FIG. 12 , a bump pad 49 is formed on the stacking wafer 10B to complete the integrated circuit device 100. In one embodiment of the present invention, the conductive via 47 is positioned in the shallow trench isolation 17 and connected to the bump pad 49. In one embodiment of the present invention, the conductive via 47 is electrically connected to the interconnect 29 of the connecting structure 30, and the conductive layer 31 of the connecting structure 30 electrically connects the active element 13 to the interconnect 29; therefore, the active element 13 is electrically connected to the conductive via 47.
Compared to the technique disclosed in U.S. Pat. No. 7,683,459 forming one bump pad for each wafer, the embodiment of the present invention forms the integrated circuit device 100 by bonding wafers 10A and 10B before the formation of the through silicon via 47 that penetrates through the stacking wafer 10B and not through the bottom wafer 10A. Consequently, the embodiment of the present invention does not need to form the bump pad 49 between the stacking wafer 10B and the bottom wafer 10A; therefore, the issues of complicated processing and high cost can be solved.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (18)
1. An integrated circuit device, comprising:
a bottom wafer including:
a first active element;
a first trench isolation disposed next to the first active element;
a first dielectric block penetrating through the first trench isolation;
a first dielectric layer covering the first active element, the first trench isolation and the first dielectric block;
a first connecting structure disposed on the first dielectric block and the first trench isolation; and
at least one stacking wafer positioned on the bottom wafer and including:
a second active element;
a second trench isolation disposed next to the second active element;
a second dielectric block penetrating through the second trench isolation and bottom side of the second dielectric block is exposed by wafer thinning removing backside conduction active element;
a second dielectric layer covering the second active element, the second trench isolation and the second dielectric block;
a second connecting structure disposed on the second dielectric block and the second trench isolation; and
wherein the bottom wafer and the at least one stacking wafer are bonded by an intervening adhesive layer, no bump pad is positioned between the bottom wafer and the at least one stacking wafer, and
at least one conductive via penetrating through the at least one stacking wafer and into the bottom wafer in a substantially linear manner, wherein the at least one conductive via is surrounded by the first dielectric block and the second dielectric block.
2. The integrated circuit device of claim 1 , wherein the at least one conductive via penetrates through the second dielectric block.
3. The integrated circuit device of claim 1 , wherein the at least one conductive via does not penetrate through the bottom wafer.
4. The integrated circuit device of claim 1 , wherein a position of the first dielectric block vertically overlaps a position of the second dielectric block, the at least one conductive via penetrates through the second dielectric block, and the at least one conductive via does not penetrate through the first dielectric block.
5. The integrated circuit device of claim 1 , wherein the at least one stacking wafer comprises a top wafer having a bump pad, and the at least one conductive via is connected to the bump pad.
6. The integrated circuit device of claim 1 , wherein the first connecting structure electrically connects the at least one conductive via to first active element, the second connecting structure electrically connects the at least one conductive via to the second active element.
7. The integrated circuit device of claim 6 , wherein the first connecting structure comprises:
an interconnect electrically connected to the at least one conductive via; and
a conductive layer electrically connecting the first active element to the interconnect.
8. The integrated circuit device of claim 7 , wherein the at least one stacking wafer comprises a contact plug, and the interconnect and the contact plug are made of the same conductive material.
9. The integrated circuit device of claim 1 , wherein no solder is positioned between the bottom wafer and the at least one stacking wafer.
10. A method for preparing an integrated circuit device, comprising the steps of:
forming a bottom wafer;
forming at least one stacking wafer;
bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, without forming a bump pad between the bottom wafer and the at least one stacking wafer, wherein the at least one stacking wafer comprises at least one second active element, a second dielectric block and a second trench isolation next to the active element, the second dielectric block penetrates through the second trench isolation, the bottom wafer comprise a first active element, a first dielectric block and a first trench isolation, the first dielectric block penetrates through the first trench isolation; and
forming at least one conductive via penetrating through the at least one stacking wafer and into the bottom wafer in a substantially linear manner, wherein the at least one conductive via is surrounded by the first dielectric block and the second dielectric block.
11. The method for preparing an integrated circuit device of claim 10 , wherein the forming of the at least one stacking wafer comprises a step of forming the second dielectric block, and the at least one conductive via penetrates through the second dielectric block.
12. The method for preparing an integrated circuit device of claim 10 , wherein the at least one conductive via is formed without penetrating through the bottom wafer.
13. The method for preparing an integrated circuit device of claim 10 , wherein the forming of the bottom wafer comprises a step of forming the first dielectric block and the second dielectric block, a position of the first dielectric block vertically overlaps a position of the second dielectric block, the at least one conductive via penetrates through the second dielectric block, and the at least one conductive via does not penetrate through the first dielectric block.
14. The method for preparing an integrated circuit device of claim 10 , further comprising a step of forming a bump pad on the at least one stacking wafer, wherein the at least one conductive via is connected to the bump pad.
15. The method for preparing an integrated circuit device of claim 10 , wherein the forming of the at least one stacking wafer comprises steps of forming a first connecting structure electrically connected to the first active element.
16. The method for preparing an integrated circuit device of claim 15 , wherein the forming of the first connecting structure comprises the steps of:
forming an interconnect in a predetermined area of the at least one stacking wafer, wherein the at least one conductive via is positioned in the predetermined area;
forming a conductive contact between the predetermined interconnect and the at least one conductive via; and
forming a conductive layer electrically connecting the first active element to the interconnect.
17. The method for preparing an integrated circuit device of claim 16 , wherein the forming of the at least one stacking wafer comprises a step of forming a contact plug connected to the first active element, and the interconnect and the contact plug are made of the same conductive material.
18. The method for preparing an integrated circuit device of claim 10 , wherein the bonding of the at least one stacking wafer to the bottom wafer is performed without using solder between the bottom wafer and the at least one stacking wafer.
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TW100100435A TW201222773A (en) | 2010-11-18 | 2011-01-06 | Integrated circuit device and method of forming the same |
CN201110004086.1A CN102468279B (en) | 2010-11-18 | 2011-01-11 | Integrated circuit device and method for preparing same |
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US12/949,058 US8421193B2 (en) | 2010-11-18 | 2010-11-18 | Integrated circuit device having through via and method for preparing the same |
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US8421193B2 true US8421193B2 (en) | 2013-04-16 |
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US12/949,058 Active 2031-06-03 US8421193B2 (en) | 2010-11-18 | 2010-11-18 | Integrated circuit device having through via and method for preparing the same |
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US8704347B2 (en) | 2006-11-22 | 2014-04-22 | Tessera, Inc. | Packaged semiconductor chips |
US8735287B2 (en) | 2007-07-31 | 2014-05-27 | Invensas Corp. | Semiconductor packaging process using through silicon vias |
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US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8796828B2 (en) | 2010-12-08 | 2014-08-05 | Tessera, Inc. | Compliant interconnects in wafers |
US8809190B2 (en) | 2010-09-17 | 2014-08-19 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US20140264862A1 (en) * | 2013-03-12 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure and Method |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8860229B1 (en) * | 2013-07-16 | 2014-10-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US20140306261A1 (en) * | 2013-04-15 | 2014-10-16 | Samsung Electronics Co., Ltd. | Electronic device package and package substrate for the same |
US9070678B2 (en) | 2006-11-22 | 2015-06-30 | Tessera, Inc. | Packaged semiconductor chips with array |
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US9087821B2 (en) | 2013-07-16 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9099296B2 (en) | 2010-12-02 | 2015-08-04 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages with plural active chips |
US9269692B2 (en) | 2010-12-02 | 2016-02-23 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
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Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US11302608B2 (en) * | 2020-06-22 | 2022-04-12 | Nanya Technology Corporation | Semiconductor device with protection layers and method for fabricating the same |
US11462453B2 (en) * | 2020-07-10 | 2022-10-04 | Nanya Technology Corporation | Semiconductor device with protection layers and method for fabricating the same |
Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050092614A1 (en) * | 2003-10-29 | 2005-05-05 | Gallina Mark J. | Distributing forces for electrodeposition |
US6908785B2 (en) | 2001-12-06 | 2005-06-21 | Samsung Electronics Co., Ltd. | Multi-chip package (MCP) with a conductive bar and method for manufacturing the same |
US6943067B2 (en) * | 2002-01-08 | 2005-09-13 | Advanced Micro Devices, Inc. | Three-dimensional integrated semiconductor devices |
US7041576B2 (en) * | 2004-05-28 | 2006-05-09 | Freescale Semiconductor, Inc. | Separately strained N-channel and P-channel transistors |
US7371662B2 (en) * | 2006-03-21 | 2008-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a 3D interconnect and resulting structures |
US7453150B1 (en) * | 2004-04-01 | 2008-11-18 | Rensselaer Polytechnic Institute | Three-dimensional face-to-face integration assembly |
US20080290524A1 (en) * | 2007-05-25 | 2008-11-27 | International Business Machines Corporation | Through via in ultra high resistivity wafer and related methods |
US7507637B2 (en) * | 2006-03-17 | 2009-03-24 | Hynix Semiconductor Inc. | Method of manufacturing wafer level stack package |
US20090267194A1 (en) * | 2008-04-24 | 2009-10-29 | Powertech Technology Inc. | Semiconductor chip having tsv (through silicon via) and stacked assembly including the chips |
US20090283872A1 (en) | 2008-05-13 | 2009-11-19 | Lin Chun-Te | Package structure of three-dimensional stacking dice and method for manufacturing the same |
US20090325343A1 (en) * | 2003-06-24 | 2009-12-31 | Sang-Yun Lee | Bonded semiconductor structure and method of fabricating the same |
US7683459B2 (en) | 2008-06-02 | 2010-03-23 | Hong Kong Applied Science and Technology Research Institute Company, Ltd. | Bonding method for through-silicon-via based 3D wafer stacking |
US20100102453A1 (en) | 2008-10-28 | 2010-04-29 | Ming-Hong Tseng | Three-Dimensional Integrated Circuit Stacking-Joint Interface Structure |
US20100133697A1 (en) * | 2007-07-05 | 2010-06-03 | Aac Microtec Ab | Low resistance through-wafer via |
US20100224876A1 (en) * | 2009-03-05 | 2010-09-09 | International Business Machines Corporation | Two-Sided Semiconductor Structure |
US20100320575A9 (en) * | 2008-05-12 | 2010-12-23 | Satyendra Singh Chauhan | Thru silicon enabled die stacking scheme |
US20120061794A1 (en) * | 2010-09-10 | 2012-03-15 | S.O.I. Tec Silicon On Insulator Technologies | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods |
US8143712B2 (en) * | 2010-07-15 | 2012-03-27 | Nanya Technology Corp. | Die package structure |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7897431B2 (en) * | 2008-02-01 | 2011-03-01 | Promos Technologies, Inc. | Stacked semiconductor device and method |
CN101882598A (en) * | 2009-05-04 | 2010-11-10 | 南亚科技股份有限公司 | Electric through connection and forming method thereof |
-
2010
- 2010-11-18 US US12/949,058 patent/US8421193B2/en active Active
-
2011
- 2011-01-06 TW TW100100435A patent/TW201222773A/en unknown
- 2011-01-11 CN CN201110004086.1A patent/CN102468279B/en active Active
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6908785B2 (en) | 2001-12-06 | 2005-06-21 | Samsung Electronics Co., Ltd. | Multi-chip package (MCP) with a conductive bar and method for manufacturing the same |
US6943067B2 (en) * | 2002-01-08 | 2005-09-13 | Advanced Micro Devices, Inc. | Three-dimensional integrated semiconductor devices |
US20090325343A1 (en) * | 2003-06-24 | 2009-12-31 | Sang-Yun Lee | Bonded semiconductor structure and method of fabricating the same |
US20050092614A1 (en) * | 2003-10-29 | 2005-05-05 | Gallina Mark J. | Distributing forces for electrodeposition |
US7453150B1 (en) * | 2004-04-01 | 2008-11-18 | Rensselaer Polytechnic Institute | Three-dimensional face-to-face integration assembly |
US7041576B2 (en) * | 2004-05-28 | 2006-05-09 | Freescale Semiconductor, Inc. | Separately strained N-channel and P-channel transistors |
US7507637B2 (en) * | 2006-03-17 | 2009-03-24 | Hynix Semiconductor Inc. | Method of manufacturing wafer level stack package |
US7371662B2 (en) * | 2006-03-21 | 2008-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a 3D interconnect and resulting structures |
US20080290524A1 (en) * | 2007-05-25 | 2008-11-27 | International Business Machines Corporation | Through via in ultra high resistivity wafer and related methods |
US20100133697A1 (en) * | 2007-07-05 | 2010-06-03 | Aac Microtec Ab | Low resistance through-wafer via |
US20090267194A1 (en) * | 2008-04-24 | 2009-10-29 | Powertech Technology Inc. | Semiconductor chip having tsv (through silicon via) and stacked assembly including the chips |
US20100320575A9 (en) * | 2008-05-12 | 2010-12-23 | Satyendra Singh Chauhan | Thru silicon enabled die stacking scheme |
US20090283872A1 (en) | 2008-05-13 | 2009-11-19 | Lin Chun-Te | Package structure of three-dimensional stacking dice and method for manufacturing the same |
US7683459B2 (en) | 2008-06-02 | 2010-03-23 | Hong Kong Applied Science and Technology Research Institute Company, Ltd. | Bonding method for through-silicon-via based 3D wafer stacking |
US20100102453A1 (en) | 2008-10-28 | 2010-04-29 | Ming-Hong Tseng | Three-Dimensional Integrated Circuit Stacking-Joint Interface Structure |
US20100224876A1 (en) * | 2009-03-05 | 2010-09-09 | International Business Machines Corporation | Two-Sided Semiconductor Structure |
US8143712B2 (en) * | 2010-07-15 | 2012-03-27 | Nanya Technology Corp. | Die package structure |
US20120061794A1 (en) * | 2010-09-10 | 2012-03-15 | S.O.I. Tec Silicon On Insulator Technologies | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods |
Non-Patent Citations (1)
Title |
---|
Yoichiro Kurita,etc. A 3D Stack Memory Integrated on a Logic Using SMAFTI Technology. 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan 2007 Electronic Components and Technology Conference p. 821-829. |
Cited By (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9548254B2 (en) | 2006-11-22 | 2017-01-17 | Tessera, Inc. | Packaged semiconductor chips with array |
US8704347B2 (en) | 2006-11-22 | 2014-04-22 | Tessera, Inc. | Packaged semiconductor chips |
US9070678B2 (en) | 2006-11-22 | 2015-06-30 | Tessera, Inc. | Packaged semiconductor chips with array |
US8735287B2 (en) | 2007-07-31 | 2014-05-27 | Invensas Corp. | Semiconductor packaging process using through silicon vias |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US9847277B2 (en) | 2010-09-17 | 2017-12-19 | Tessera, Inc. | Staged via formation from both sides of chip |
US8809190B2 (en) | 2010-09-17 | 2014-08-19 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US10354942B2 (en) | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US9362203B2 (en) | 2010-09-17 | 2016-06-07 | Tessera, Inc. | Staged via formation from both sides of chip |
US9355948B2 (en) | 2010-09-17 | 2016-05-31 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US9099296B2 (en) | 2010-12-02 | 2015-08-04 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages with plural active chips |
US9620437B2 (en) | 2010-12-02 | 2017-04-11 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
US20120139094A1 (en) * | 2010-12-02 | 2012-06-07 | Tessera Research Llc | Stacked microelectronic assembly having interposer connecting active chips |
US9269692B2 (en) | 2010-12-02 | 2016-02-23 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
US8637968B2 (en) * | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US9368476B2 (en) | 2010-12-02 | 2016-06-14 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8796828B2 (en) | 2010-12-08 | 2014-08-05 | Tessera, Inc. | Compliant interconnects in wafers |
US9224649B2 (en) | 2010-12-08 | 2015-12-29 | Tessera, Inc. | Compliant interconnects in wafers |
US20140175598A1 (en) * | 2012-12-21 | 2014-06-26 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Silicon-on-insulator radio frequency device and silicon-on-insulator substrate |
US9780164B2 (en) * | 2012-12-21 | 2017-10-03 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Silicon-on-insulator radio frequency device and silicon-on-insulator substrate |
US9553020B2 (en) | 2013-03-12 | 2017-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for connecting dies and methods of forming the same |
US20140264862A1 (en) * | 2013-03-12 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure and Method |
US9406712B2 (en) | 2013-03-12 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for connecting dies and methods of forming the same |
US9041206B2 (en) * | 2013-03-12 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
US9076715B2 (en) | 2013-03-12 | 2015-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for connecting dies and methods of forming the same |
US9391250B2 (en) * | 2013-04-15 | 2016-07-12 | Samsung Electronics Co., Ltd. | Electronic device package and package substrate for the same |
US20140306261A1 (en) * | 2013-04-15 | 2014-10-16 | Samsung Electronics Co., Ltd. | Electronic device package and package substrate for the same |
US9087821B2 (en) | 2013-07-16 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9299640B2 (en) | 2013-07-16 | 2016-03-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (TSV) |
US9991244B2 (en) | 2013-07-16 | 2018-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming hybrid bonding with through substrate via (TSV) |
US10461069B2 (en) | 2013-07-16 | 2019-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US10847443B2 (en) | 2013-07-16 | 2020-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (TSV) |
US10340247B2 (en) | 2013-07-16 | 2019-07-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming hybrid bonding with through substrate via (TSV) |
US9768143B2 (en) | 2013-07-16 | 2017-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US11658172B2 (en) | 2013-07-16 | 2023-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with through substrate via (TSV) |
US11791241B2 (en) | 2013-07-16 | 2023-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Front-to-back bonding with through-substrate via (TSV) |
US9831156B2 (en) | 2013-07-16 | 2017-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (TSV) |
US8860229B1 (en) * | 2013-07-16 | 2014-10-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9929050B2 (en) | 2013-07-16 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure |
US10056353B2 (en) | 2013-12-19 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US10510729B2 (en) | 2013-12-19 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US11798916B2 (en) | 2013-12-19 | 2023-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US10157891B2 (en) | 2013-12-19 | 2018-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US9412719B2 (en) | 2013-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US9754925B2 (en) | 2013-12-19 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
US10304818B2 (en) | 2013-12-26 | 2019-05-28 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing semiconductor devices having conductive plugs with varying widths |
US11532661B2 (en) | 2014-01-09 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC seal ring structure and methods of forming same |
US10510792B2 (en) | 2014-01-09 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC seal ring structure and methods of forming same |
US9806119B2 (en) | 2014-01-09 | 2017-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC seal ring structure and methods of forming same |
US9425150B2 (en) | 2014-02-13 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-via interconnect structure and method of manufacture |
US9543257B2 (en) * | 2014-05-29 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
US9941249B2 (en) | 2014-05-30 | 2018-04-10 | Taiwan Semiconductor Manufacturing Company | Multi-wafer stacking by Ox-Ox bonding |
US9455158B2 (en) | 2014-05-30 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
US10629568B2 (en) | 2014-07-17 | 2020-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuits with redistribution lines |
US11923338B2 (en) | 2014-07-17 | 2024-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuits with redistribution lines |
US9449914B2 (en) | 2014-07-17 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuits with redistribution lines |
US10269768B2 (en) | 2014-07-17 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuits with redistribution lines |
US11594484B2 (en) * | 2015-10-16 | 2023-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming bonding structures by using template layer as templates |
US20200328153A1 (en) * | 2015-10-16 | 2020-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Forming Bonding Structures By Using Template Layer as Templates |
US11121127B2 (en) | 2019-01-18 | 2021-09-14 | Samsung Electronics Co., Ltd. | Integrated circuit chips, integrated circuit packages including the integrated circuit chips, and display apparatuses including the integrated circuit chips |
US20220293588A1 (en) * | 2021-02-23 | 2022-09-15 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Process for protecting an upper stage of electronic components of an integrated circuit against antenna effects |
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US20120126394A1 (en) | 2012-05-24 |
CN102468279B (en) | 2014-02-05 |
CN102468279A (en) | 2012-05-23 |
TW201222773A (en) | 2012-06-01 |
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