US4567604A - Biphase signal receiver - Google Patents
Biphase signal receiver Download PDFInfo
- Publication number
- US4567604A US4567604A US06/526,940 US52694083A US4567604A US 4567604 A US4567604 A US 4567604A US 52694083 A US52694083 A US 52694083A US 4567604 A US4567604 A US 4567604A
- Authority
- US
- United States
- Prior art keywords
- signal
- biphase
- generating
- receiver
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/06—Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
- H03M5/12—Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
Definitions
- a biphase signal may be conceptualized as including a series of cells each having clock and data information.
- One type of biphase signal is the biphase-L signal which has a mid-cell voltage level transition providing both clock and data information. The direction of the level transition corresponds to the data information stored in the cell. For example, a positive going transition represents a mark (high level data signal); and a negative going transition represents a space (low level data signal). Additionally, a level transition may be present at a cell boundary. Such a situation occurs whenever adjacent cells encode the same data information.
- Another scheme for biphase signal encoding is biphase-M. In this encoding scheme, a level transition occurs at each cell boundary; and either a positive or negative going mid-cell level transition occurs when the cell data is a mark.
- FIG. 2 is a timing diagram of selected signal levels of the circuit of FIG. 1.
- the biphase receiver illustrated in FIG. 1 accepts, at an input terminal 10, a biphase-L signal A (FIG. 2) having a preamble from t10 to t16 followed by a data message.
- the receiver provides a mark-space signal H corresponding to the data message of the incoming biphase-L signal A.
- a signal level transition As illustrated in FIG. 2, centered on each cell (each cell delimiting successive even numbered times) of the incoming biphase-L signal A, is a signal level transition. For example, the cell between t0 and t2 has a negative going transition; and the cell between t10 and t12 has a positive going transition. A positive going transition represents a mark, and a negative going transition a space.
- the voltage level, during the last half of a cell corresponds to the data encoded in the cell. That is, when a cell represents a mark, the voltage level during the last half of the cell is high. In the event two adjacent cells encode the same data information i.e. both a mark, there will be a level transition at the cell boundaries as at times t2, t4, t6 and t8. As will be subsequently described, the illustrated receiver decodes the data message of the biphase-L signal by sampling the cell voltage level immediately after the mid-cell transitior and providing this voltage level to external circuitry (not shown) for one clock period.
- a line-up detector 14 In response to the initial presence of the biphase-L signal A at the input terminal 10, a line-up detector 14 generates a line detect pulse which initializes the receiver circuitry.
- the line-up detector 14 sends this pulse to the direct set input of a type-D flip-flop 16 of a data sampling signal generator 17.
- the flip-flop 16 will remain in the set condition with Q high until a preamble sequence of cells of the biphase-L signal A has been recognized.
- the line detect signal also initializes a switch 18 forming part of a first control signal generating means 19.
- the switch 18 includes an R-S flip-flop 20, a pair of AND-gates 22, 24 and a two-input OR-gate 26.
- the flip-flop 20 controls the AND-gates 22, 24 so that either the signal from the sample signal generator 17 or the output of a positive edge detector 30 will appear at the output of the OR-gate 26.
- the two inputs of the OR-gate 26 are fed by the output of the AND-gates 22, 24.
- the input of the positive edge detector 30 receives the incoming biphase-L signal A from the terminal 10 and generates a positive pulse train B in response to each positive going level transition of the biphase-L signal A.
- the output of the OR-gate 26 is fed to the input of a delay line 34 which provides a time delay interval equal to three-quarters of the time period of the clock of the biphase-L signal A.
- the output of the delay line 34 designated signal C is a series of negative going pulses as illustrated in FIG. 2.
- the output of the delay line 34 is fed to an active low input of a dual input AND-gate 36 and to one input of a dual input NAND-gate 38 through an inverter 39.
- the NAND-gate 38 comprises a component of a preamble decoder 40.
- the output of the NAND-gate 38 is fed to the clock input of a type-D flip-flop 42 which transfers the signal at the D input to the direct output Q in response to a rising edge of the signal at the clock input.
- the compliment output of the flip-flop 42 is fed to the remaining input of the NAND-gate 38.
- the flip-flop 42 toggles enabling the sample signal generator 17 by placing a low level on the active low AND-gate 36 input 43.
- the compliment output of the flip-flop 42 will remain low until the next line detect pulse clears the flip-flop 42 disabling the AND-gate 36 and enabling the NAND-gate 38.
- the preamble sequence of the biphase-L signal A illustrated in FIG. 2 is a mark-space-mark (1-0-1) sequence from time t10 through t16. Slightly after time t12 negative going pulse C appears at the clock input of flip-flop 42. At this time, the D input to the flip-flop is high thus bringing the compliment output of the flip-flop 42 low. During prior occurrences of the negative going pulse C, the D input to the flip-flop 42 was low. The next pulse C from the delay line 34 occurs after time t16 and is generated by the biphase-L signal A transition at t15 passing through the delay line 34. The pulse passes through the AND-gate 36 resetting the flip-flop 20.
- the flip-flop 20 disables the AND-gate 24 and enables the AND-gate 22.
- the sampling signal generator 17 also includes the type-D flip-flop 16 which is reset by the output of the AND-gate 36 and clocked by the output E of a dual edge detector 50.
- the dual edge detector 50 generates a positive going pulse E, at the direct output, in response to each level transition of the biphase-L signal A.
- the compliment output of the flip-flop 16 is fed to one input of a dual input AND-gate 52, and the alternate input of the AND-gate 52 is fed with the signal E from the direct output of the dual edge detector 50.
- the output of the AND-gate 52 follows the output of the dual edge detector 50 when the signal F is high. This interval starts with the reset of the flip-flop 16 by the output of the delay line 34 and ends in response to the next level transition of the biphase-L signal A.
- the output pulse G from and AND-gate 52 clocks a type-D flip-flop 54. Each time the sampling flip-flop 54 is clocked, the voltage level of the biphase-L signal A appearing at the D input is transfered on the falling edge of the clock signal to the direct output Q producing signal H.
- the voltage level of the cell immediately following the mid-cell transition corresponds to the level data information encoded in that cell; and thus, the signal H provides a mark-space signal corresponding to the data encoded in the biphase-L signal A.
- the output G of the AND-gate 52 is a recovered clock signal having a frequency equal to that of the incoming biphase-L signal A.
- a feature of the illustrated receiver is that the circuitry may be modified to receive incoming biphase-M as well as biphase-L signals.
- the additional components necessary to decode a biphase-M signal are illustrated within the dotted area indicated by the numeral 62.
- the biphase-M decoding circuitry 62 include a type-D flip-flop 60.
- the D input of the flip-flop 60 is fed by the direct output of the first flip-flop 54.
- the direct outputs Q of both of the flip-flops 54 and 60 are fed to separate inputs of a dual input, exclusive NOR-gate 64.
- the output of the NOR-gate 64 is a mark-space data signal.
- the initial line signal is a series of marking cells having positive boundary transitions followed by a premable of three spacing cells. The data information is valid after the second recovered clock pulse.
- a biphase-L signal A appears at the input terminal 10 and line-up detector 14 responds by generating a line detect pulse which initializes selected components of the receiver.
- the positive going transitions of the incoming biphase-L signal A generate pulses which pass through the delay line 34 clocking the preamble flip-flop 42.
- the biphase-L signal A is fed to the D input of the flip-flop 42.
- the signal from the delay line 34 In response to the fist occurrence of a mark-space-mark sequence, the signal from the delay line 34 generates a pulse slightly after time t12 latching a low level at the compliment output of the flip-flop 42.
- the pulse train passing through the AND-gate 36 occurs three-quarters of a time period after the last mid-cell transition i.e. during the first quarter time interval of the next cell of the biphase-L signal A.
- the AND-gate 52 is enabled and remains in the enabled condition until the next mid-cell transition.
- Cell boundary transition pulses from the dual edge detector 50 will not pass through the AND-gate 52 since the AND-gate 52 opens after the first quarter of the following cell and is closed by the mid-cell level transition E from the dual edge detector 50.
- the pulse E generated by the dual edge detector 50 in response to this mid-cell transition, clocks a high level from the D input of the flip-flop 16 to the direct output thereof.
- the compliment output of the flip-flop 16 goes low thus blinding the AND-gate 52.
- the pulse G at the output of the AND-gate 52 also clocks the flip-flop 54, and the biphase-L signal A level following the mid-cell level transition is transfered to the direct output of the flip-flop 54.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
Claims (5)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/526,940 US4567604A (en) | 1983-08-29 | 1983-08-29 | Biphase signal receiver |
CA000459987A CA1215781A (en) | 1983-08-29 | 1984-07-30 | Biphase signal receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/526,940 US4567604A (en) | 1983-08-29 | 1983-08-29 | Biphase signal receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
US4567604A true US4567604A (en) | 1986-01-28 |
Family
ID=24099459
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/526,940 Expired - Lifetime US4567604A (en) | 1983-08-29 | 1983-08-29 | Biphase signal receiver |
Country Status (2)
Country | Link |
---|---|
US (1) | US4567604A (en) |
CA (1) | CA1215781A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2174754A (en) * | 1985-04-26 | 1986-11-12 | Webasto Werk Baier Kg W | Vehicle sliding roof |
US4862482A (en) * | 1988-06-16 | 1989-08-29 | National Semiconductor Corporation | Receiver for Manchester encoded data |
US5023891A (en) * | 1989-07-25 | 1991-06-11 | Sf2 Corporation | Method and circuit for decoding a Manchester code signal |
US5040193A (en) * | 1989-07-28 | 1991-08-13 | At&T Bell Laboratories | Receiver and digital phase-locked loop for burst mode data recovery |
US5185766A (en) * | 1990-04-24 | 1993-02-09 | Samsung Electronics Co., Ltd. | Apparatus and method for decoding biphase-coded data |
US5222107A (en) * | 1988-12-07 | 1993-06-22 | Automobiles Peugeot | Transmission and reception synchronization device for a communication network station particularly for automotive vehicles |
EP0551695A1 (en) * | 1992-01-14 | 1993-07-21 | Matsushita Electric Industrial Co., Ltd. | Synchronizer and receiver for bi-phase coded data |
US5311559A (en) * | 1991-09-03 | 1994-05-10 | Sony Corporation | Apparatus for correcting waveform distortion |
US5696800A (en) * | 1995-03-22 | 1997-12-09 | Intel Corporation | Dual tracking differential manchester decoder and clock recovery circuit |
US10228712B2 (en) | 2016-03-25 | 2019-03-12 | Semiconductor Components Industries, Llc | Signal receiving circuit and method, and signal detecting circuit |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3859631A (en) * | 1973-07-16 | 1975-01-07 | Comsci Data Inc | Method and apparatus for decoding binary digital signals |
US3938082A (en) * | 1974-09-19 | 1976-02-10 | General Electric Company | Receiver for bi-polar coded data with bit time interval detection used as the data validation discriminant |
US3949394A (en) * | 1974-04-08 | 1976-04-06 | C. J. Kennedy Company | Read amplifier having retriggerable, variable duty cycle inhibit pulse generator |
US3994014A (en) * | 1975-12-10 | 1976-11-23 | Corning Glass Works | Circuit for rewriting blocks of phase encoded data |
US4302845A (en) * | 1980-02-07 | 1981-11-24 | Motorola, Inc. | Phase-encoded data signal demodulator |
US4313206A (en) * | 1979-10-19 | 1982-01-26 | Burroughs Corporation | Clock derivation circuit for double frequency encoded serial digital data |
US4449119A (en) * | 1981-12-14 | 1984-05-15 | International Business Machines Corporation | Self-clocking serial decoder |
-
1983
- 1983-08-29 US US06/526,940 patent/US4567604A/en not_active Expired - Lifetime
-
1984
- 1984-07-30 CA CA000459987A patent/CA1215781A/en not_active Expired
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3859631A (en) * | 1973-07-16 | 1975-01-07 | Comsci Data Inc | Method and apparatus for decoding binary digital signals |
US3949394A (en) * | 1974-04-08 | 1976-04-06 | C. J. Kennedy Company | Read amplifier having retriggerable, variable duty cycle inhibit pulse generator |
US3938082A (en) * | 1974-09-19 | 1976-02-10 | General Electric Company | Receiver for bi-polar coded data with bit time interval detection used as the data validation discriminant |
US3994014A (en) * | 1975-12-10 | 1976-11-23 | Corning Glass Works | Circuit for rewriting blocks of phase encoded data |
US4313206A (en) * | 1979-10-19 | 1982-01-26 | Burroughs Corporation | Clock derivation circuit for double frequency encoded serial digital data |
US4302845A (en) * | 1980-02-07 | 1981-11-24 | Motorola, Inc. | Phase-encoded data signal demodulator |
US4449119A (en) * | 1981-12-14 | 1984-05-15 | International Business Machines Corporation | Self-clocking serial decoder |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2174754A (en) * | 1985-04-26 | 1986-11-12 | Webasto Werk Baier Kg W | Vehicle sliding roof |
US4862482A (en) * | 1988-06-16 | 1989-08-29 | National Semiconductor Corporation | Receiver for Manchester encoded data |
US5222107A (en) * | 1988-12-07 | 1993-06-22 | Automobiles Peugeot | Transmission and reception synchronization device for a communication network station particularly for automotive vehicles |
US5023891A (en) * | 1989-07-25 | 1991-06-11 | Sf2 Corporation | Method and circuit for decoding a Manchester code signal |
US5040193A (en) * | 1989-07-28 | 1991-08-13 | At&T Bell Laboratories | Receiver and digital phase-locked loop for burst mode data recovery |
US5185766A (en) * | 1990-04-24 | 1993-02-09 | Samsung Electronics Co., Ltd. | Apparatus and method for decoding biphase-coded data |
US5311559A (en) * | 1991-09-03 | 1994-05-10 | Sony Corporation | Apparatus for correcting waveform distortion |
EP0551695A1 (en) * | 1992-01-14 | 1993-07-21 | Matsushita Electric Industrial Co., Ltd. | Synchronizer and receiver for bi-phase coded data |
US5373534A (en) * | 1992-01-14 | 1994-12-13 | Matsushita Electric Industrial Co., Ltd. | Serial data receiving apparatus |
US5696800A (en) * | 1995-03-22 | 1997-12-09 | Intel Corporation | Dual tracking differential manchester decoder and clock recovery circuit |
US10228712B2 (en) | 2016-03-25 | 2019-03-12 | Semiconductor Components Industries, Llc | Signal receiving circuit and method, and signal detecting circuit |
US11132011B2 (en) | 2016-03-25 | 2021-09-28 | Semiconductor Components Industries, Llc | Signal receiving circuit and method, and signal detecting circuit |
Also Published As
Publication number | Publication date |
---|---|
CA1215781A (en) | 1986-12-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0773653B1 (en) | Method and apparatus for decoding Manchester-encoded data | |
EP0186462B1 (en) | A method for detection of manchester-encoded signals | |
US4146743A (en) | Adaptive sampling decoder-encoder apparatus and method | |
US4567604A (en) | Biphase signal receiver | |
US4317211A (en) | Manchester code decoding apparatus | |
US3602828A (en) | Self-clocking detection system | |
US4232388A (en) | Method and means for encoding and decoding digital data | |
EP0304799A3 (en) | Method and/or apparatus for demodulating a biphase signal | |
US4204199A (en) | Method and means for encoding and decoding digital data | |
US4292626A (en) | Manchester decoder | |
US4876697A (en) | Three-part decoder circuit | |
US4513329A (en) | Manchester decoder clock multiplier | |
US4809301A (en) | Detection apparatus for bi-phase signals | |
US5046073A (en) | Signal processing apparatus for recovering a clock signal and a data signal from an encoded information signal | |
KR0149720B1 (en) | Manchester decoder | |
US4352095A (en) | A/D Dynamic range enhancing technique | |
US3613015A (en) | Binary digital data detection system | |
JPH0137890B2 (en) | ||
KR100526937B1 (en) | Differential Code Generator | |
SU1350839A1 (en) | Phase triggering device | |
JPS58151753A (en) | Pulse communication system | |
JPH0562851B2 (en) | ||
JPH0338115A (en) | Data transmission equipment | |
JPS5869151A (en) | Decoding circuit | |
JPH06291753A (en) | Data transmitter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TELETYPE CORPORATION, 5555 TOUHY AVE., SKOKIE, ILL Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:JACKSIER, BARRY H.;REEL/FRAME:004168/0357 Effective date: 19830825 |
|
AS | Assignment |
Owner name: AT&T TELETYPE CORPORATION A CORP OF DE Free format text: CHANGE OF NAME;ASSIGNOR:TELETYPE CORPORATION;REEL/FRAME:004372/0404 Effective date: 19840817 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REFU | Refund |
Free format text: REFUND PROCESSED. MAINTENANCE FEE HAS ALREADY BEEN PAID (ORIGINAL EVENT CODE: R160); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 12 |